Re: [U-Boot] [PATCH v7] net/phy: Add support for CS4315/CS4340 PHY

2014-12-05 Thread York Sun 
On 11/10/2014 02:32 AM, Shengzhou Liu wrote:
 Add support for Cortina CS4315/CS4340 10G PHY.
 - This driver loads CS43xx firmware from NOR/NAND/SPI/SD device
   to initialize Cortina PHY.
 - Cortina PHY has non-standard offset of PHY ID registers, thus
   we define own get_phy_id() to override default get_phy_id().
 - To define macro CONFIG_PHY_CORTINA will enable this driver.
 
 Signed-off-by: Shengzhou Liu shengzhou@freescale.com
 ---
 v7: reorder it in alphabetical order in Makefile
 v6: polish it in phy.c and phy.h in alphabetical order 
 v5: fix unclaimed variable in case of nand boot.
 v4: add support for loading cortina phy ucode from NAND/SPI/SD
 v3: move devad as '0' in cortina.c instead of in phy.c
 v2: no change.
 
Applied to u-boot-mpc85xx, awaiting upstream.

York

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v7] net/phy: Add support for CS4315/CS4340 PHY

2014-12-05 Thread York Sun 
On 11/25/2014 02:33 PM, Joe Hershberger wrote:
 On Mon, Nov 10, 2014 at 4:32 AM, Shengzhou Liu shengzhou@freescale.com
 mailto:shengzhou@freescale.com wrote:

 Add support for Cortina CS4315/CS4340 10G PHY.
 - This driver loads CS43xx firmware from NOR/NAND/SPI/SD device
   to initialize Cortina PHY.
 - Cortina PHY has non-standard offset of PHY ID registers, thus
   we define own get_phy_id() to override default get_phy_id().
 - To define macro CONFIG_PHY_CORTINA will enable this driver.

 Signed-off-by: Shengzhou Liu shengzhou@freescale.com
 mailto:shengzhou@freescale.com
 ---
 v7: reorder it in alphabetical order in Makefile
 v6: polish it in phy.c and phy.h in alphabetical order
 v5: fix unclaimed variable in case of nand boot.
 v4: add support for loading cortina phy ucode from NAND/SPI/SD
 v3: move devad as '0' in cortina.c instead of in phy.c
 v2: no change.

  drivers/net/phy/Makefile  |   1 +
  drivers/net/phy/cortina.c | 333 
 ++
  drivers/net/phy/phy.c |   3 +
  include/cortina.h |  75 +++
  include/phy.h |   2 +
  5 files changed, 414 insertions(+)
  create mode 100644 drivers/net/phy/cortina.c
  create mode 100644 include/cortina.h

 diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
 index 9556536..f46bf00 100644
 --- a/drivers/net/phy/Makefile
 +++ b/drivers/net/phy/Makefile
 @@ -13,6 +13,7 @@ obj-$(CONFIG_PHYLIB) += phy.o
  obj-$(CONFIG_PHYLIB_10G) += generic_10g.o
  obj-$(CONFIG_PHY_ATHEROS) += atheros.o
  obj-$(CONFIG_PHY_BROADCOM) += broadcom.o
 +obj-$(CONFIG_PHY_CORTINA) += cortina.o
  obj-$(CONFIG_PHY_DAVICOM) += davicom.o
  obj-$(CONFIG_PHY_ET1011C) += et1011c.o
  obj-$(CONFIG_PHY_LXT) += lxt.o
 diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
 new file mode 100644
 index 000..254f056
 --- /dev/null
 +++ b/drivers/net/phy/cortina.c
 @@ -0,0 +1,333 @@
 +/*
 + * Cortina CS4315/CS4340 10G PHY drivers
 + *
 + * SPDX-License-Identifier: GPL-2.0+
 + *
 + * Copyright 2014 Freescale Semiconductor, Inc.
 + *
 + */
 +
 +#include config.h
 +#include common.h
 +#include malloc.h
 +#include linux/ctype.h
 +#include linux/string.h
 +#include linux/err.h
 +#include phy.h
 +#include cortina.h
 +#ifdef CONFIG_SYS_CORTINA_FW_IN_NAND
 +#include nand.h
 +#elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
 +#include spi_flash.h
 +#elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
 +#include mmc.h
 +#endif
 +
 +#ifndef CONFIG_PHYLIB_10G
 +#error The Cortina PHY needs 10G support
 +#endif
 +
 +struct cortina_reg_config cortina_reg_cfg[] = {
 +   /* CS4315_enable_sr_mode */
 +   {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
 +   {VILLA_MSEQ_OPTIONS, 0xf},
 +   {VILLA_MSEQ_PC, 0x0},
 +   {VILLA_MSEQ_BANKSELECT,0x4},
 +   {VILLA_LINE_SDS_COMMON_SRX0_RX_CPA, 0x55},
 +   {VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0x30},
 +   {VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0x1},
 +   {VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT, 0x2},
 +   {VILLA_LINE_SDS_COMMON_SRX0_RX_CPB, 0x2003},
 +   {VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0xF047},
 +   {VILLA_MSEQ_ENABLE_MSB, 0x},
 +   {VILLA_MSEQ_SPARE21_LSB, 0x6},
 +   {VILLA_MSEQ_RESET_COUNT_LSB, 0x0},
 +   {VILLA_MSEQ_SPARE12_MSB, 0x},
 +   /*
 +* to invert the receiver path, uncomment the next line
 +* write (VILLA_MSEQ_SPARE12_MSB, 0x4000)
 +*
 +* SPARE2_LSB is used to configure the device while in sr mode to
 +* enable power savings and to use the optical module LOS signal.
 +* in power savings mode, the internal prbs checker can not be used.
 +* if the optical module LOS signal is used as an input to the micro
 +* code, then the micro code will wait until the optical module
 +* LOS = 0 before turning on the adaptive equalizer.
 +* Setting SPARE2_LSB bit 0 to 1 places the devie in power savings 
 mode
 +* while setting bit 0 to 0 disables power savings mode.
 +* Setting SPARE2_LSB bit 2 to 0 configures the device to use the
 +* optical module LOS signal while setting bit 2 to 1 configures the
 +* device so that it will ignore the optical module LOS SPARE2_LSB =  0
 +*/
 +
 +   /* enable power savings, ignore optical module LOS */
 +   {VILLA_MSEQ_SPARE2_LSB, 0x5},
 +
 +   {VILLA_MSEQ_SPARE7_LSB, 0x1e},
 +   {VILLA_MSEQ_BANKSELECT, 0x4},
 +   {VILLA_MSEQ_SPARE9_LSB, 0x2},
 +   {VILLA_MSEQ_SPARE3_LSB, 0x0F53},
 +   {VILLA_MSEQ_SPARE3_MSB, 0x2006},
 +   {VILLA_MSEQ_SPARE8_LSB, 0x3FF7},
 +   {VILLA_MSEQ_SPARE8_MSB, 0x0A46},
 +   {VILLA_MSEQ_COEF8_FFE0_LSB, 0xD500},
 +   {VILLA_MSEQ_COEF8_FFE1_LSB, 0x0200},
 +   {VILLA_MSEQ_COEF8_FFE2_LSB, 0xBA00},
 +   {VILLA_MSEQ_COEF8_FFE3_LSB, 0x0100},
 +   {VILLA_MSEQ_COEF8_FFE4_LSB, 0x0300},
 +   {VILLA_MSEQ_COEF8_FFE5_LSB, 0x0300},
 +   {VILLA_MSEQ_COEF8_DFE0_LSB, 0x0700},
 +

Re: [U-Boot] [PATCH v7] net/phy: Add support for CS4315/CS4340 PHY

2014-12-05 Thread Joe Hershberger 
Hi York,

On Fri, Dec 5, 2014 at 10:27 AM, York Sun york...@freescale.com wrote:

 On 11/10/2014 02:32 AM, Shengzhou Liu wrote:
  Add support for Cortina CS4315/CS4340 10G PHY.
  - This driver loads CS43xx firmware from NOR/NAND/SPI/SD device
to initialize Cortina PHY.
  - Cortina PHY has non-standard offset of PHY ID registers, thus
we define own get_phy_id() to override default get_phy_id().
  - To define macro CONFIG_PHY_CORTINA will enable this driver.
 
  Signed-off-by: Shengzhou Liu shengzhou@freescale.com
  ---
  v7: reorder it in alphabetical order in Makefile
  v6: polish it in phy.c and phy.h in alphabetical order
  v5: fix unclaimed variable in case of nand boot.
  v4: add support for loading cortina phy ucode from NAND/SPI/SD
  v3: move devad as '0' in cortina.c instead of in phy.c
  v2: no change.
 
 Applied to u-boot-mpc85xx, awaiting upstream.

Were my concerns from Nov 25 addressed?

Thanks,
-Joe
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v7] net/phy: Add support for CS4315/CS4340 PHY

2014-12-05 Thread York Sun 
On 12/05/2014 08:29 AM, Joe Hershberger wrote:
 Hi York,
 
 On Fri, Dec 5, 2014 at 10:27 AM, York Sun york...@freescale.com
 mailto:york...@freescale.com wrote:

 On 11/10/2014 02:32 AM, Shengzhou Liu wrote:
  Add support for Cortina CS4315/CS4340 10G PHY.
  - This driver loads CS43xx firmware from NOR/NAND/SPI/SD device
to initialize Cortina PHY.
  - Cortina PHY has non-standard offset of PHY ID registers, thus
we define own get_phy_id() to override default get_phy_id().
  - To define macro CONFIG_PHY_CORTINA will enable this driver.
 
  Signed-off-by: Shengzhou Liu shengzhou@freescale.com
 mailto:shengzhou@freescale.com
  ---
  v7: reorder it in alphabetical order in Makefile
  v6: polish it in phy.c and phy.h in alphabetical order
  v5: fix unclaimed variable in case of nand boot.
  v4: add support for loading cortina phy ucode from NAND/SPI/SD
  v3: move devad as '0' in cortina.c instead of in phy.c
  v2: no change.
 
 Applied to u-boot-mpc85xx, awaiting upstream.
 
 Were my concerns from Nov 25 addressed?
 

No. Somehow I missed your comment. My apology.
Shengzhou, please follow up and address the comments. Please send additional
patch if needed.

York

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v7] net/phy: Add support for CS4315/CS4340 PHY

2014-11-25 Thread York Sun 
On 11/10/2014 03:32 AM, Liu Shengzhou-B36685 wrote:
 -Original Message-
 From: Shengzhou Liu [mailto:shengzhou@freescale.com]
 Sent: Monday, November 10, 2014 6:32 PM
 To: u-boot@lists.denx.de; Sun York-R58495; joe.hershber...@gmail.com
 Cc: Liu Shengzhou-B36685
 Subject: [PATCH v7] net/phy: Add support for CS4315/CS4340 PHY
  
 The link of previous version: http://patchwork.ozlabs.org/patch/350162/
 Joe, York please review and ACK this version.
 

Joe,

If you have OK with this patch, I can bring it in.

York

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v7] net/phy: Add support for CS4315/CS4340 PHY

2014-11-25 Thread Joe Hershberger 
On Mon, Nov 10, 2014 at 4:32 AM, Shengzhou Liu shengzhou@freescale.com
wrote:

 Add support for Cortina CS4315/CS4340 10G PHY.
 - This driver loads CS43xx firmware from NOR/NAND/SPI/SD device
   to initialize Cortina PHY.
 - Cortina PHY has non-standard offset of PHY ID registers, thus
   we define own get_phy_id() to override default get_phy_id().
 - To define macro CONFIG_PHY_CORTINA will enable this driver.

 Signed-off-by: Shengzhou Liu shengzhou@freescale.com
 ---
 v7: reorder it in alphabetical order in Makefile
 v6: polish it in phy.c and phy.h in alphabetical order
 v5: fix unclaimed variable in case of nand boot.
 v4: add support for loading cortina phy ucode from NAND/SPI/SD
 v3: move devad as '0' in cortina.c instead of in phy.c
 v2: no change.

  drivers/net/phy/Makefile  |   1 +
  drivers/net/phy/cortina.c | 333
++
  drivers/net/phy/phy.c |   3 +
  include/cortina.h |  75 +++
  include/phy.h |   2 +
  5 files changed, 414 insertions(+)
  create mode 100644 drivers/net/phy/cortina.c
  create mode 100644 include/cortina.h

 diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
 index 9556536..f46bf00 100644
 --- a/drivers/net/phy/Makefile
 +++ b/drivers/net/phy/Makefile
 @@ -13,6 +13,7 @@ obj-$(CONFIG_PHYLIB) += phy.o
  obj-$(CONFIG_PHYLIB_10G) += generic_10g.o
  obj-$(CONFIG_PHY_ATHEROS) += atheros.o
  obj-$(CONFIG_PHY_BROADCOM) += broadcom.o
 +obj-$(CONFIG_PHY_CORTINA) += cortina.o
  obj-$(CONFIG_PHY_DAVICOM) += davicom.o
  obj-$(CONFIG_PHY_ET1011C) += et1011c.o
  obj-$(CONFIG_PHY_LXT) += lxt.o
 diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
 new file mode 100644
 index 000..254f056
 --- /dev/null
 +++ b/drivers/net/phy/cortina.c
 @@ -0,0 +1,333 @@
 +/*
 + * Cortina CS4315/CS4340 10G PHY drivers
 + *
 + * SPDX-License-Identifier: GPL-2.0+
 + *
 + * Copyright 2014 Freescale Semiconductor, Inc.
 + *
 + */
 +
 +#include config.h
 +#include common.h
 +#include malloc.h
 +#include linux/ctype.h
 +#include linux/string.h
 +#include linux/err.h
 +#include phy.h
 +#include cortina.h
 +#ifdef CONFIG_SYS_CORTINA_FW_IN_NAND
 +#include nand.h
 +#elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
 +#include spi_flash.h
 +#elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
 +#include mmc.h
 +#endif
 +
 +#ifndef CONFIG_PHYLIB_10G
 +#error The Cortina PHY needs 10G support
 +#endif
 +
 +struct cortina_reg_config cortina_reg_cfg[] = {
 +   /* CS4315_enable_sr_mode */
 +   {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
 +   {VILLA_MSEQ_OPTIONS, 0xf},
 +   {VILLA_MSEQ_PC, 0x0},
 +   {VILLA_MSEQ_BANKSELECT,0x4},
 +   {VILLA_LINE_SDS_COMMON_SRX0_RX_CPA, 0x55},
 +   {VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0x30},
 +   {VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0x1},
 +   {VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT, 0x2},
 +   {VILLA_LINE_SDS_COMMON_SRX0_RX_CPB, 0x2003},
 +   {VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0xF047},
 +   {VILLA_MSEQ_ENABLE_MSB, 0x},
 +   {VILLA_MSEQ_SPARE21_LSB, 0x6},
 +   {VILLA_MSEQ_RESET_COUNT_LSB, 0x0},
 +   {VILLA_MSEQ_SPARE12_MSB, 0x},
 +   /*
 +* to invert the receiver path, uncomment the next line
 +* write (VILLA_MSEQ_SPARE12_MSB, 0x4000)
 +*
 +* SPARE2_LSB is used to configure the device while in sr mode to
 +* enable power savings and to use the optical module LOS signal.
 +* in power savings mode, the internal prbs checker can not be
used.
 +* if the optical module LOS signal is used as an input to the
micro
 +* code, then the micro code will wait until the optical module
 +* LOS = 0 before turning on the adaptive equalizer.
 +* Setting SPARE2_LSB bit 0 to 1 places the devie in power
savings mode
 +* while setting bit 0 to 0 disables power savings mode.
 +* Setting SPARE2_LSB bit 2 to 0 configures the device to use the
 +* optical module LOS signal while setting bit 2 to 1 configures
the
 +* device so that it will ignore the optical module LOS
SPARE2_LSB = 0
 +*/
 +
 +   /* enable power savings, ignore optical module LOS */
 +   {VILLA_MSEQ_SPARE2_LSB, 0x5},
 +
 +   {VILLA_MSEQ_SPARE7_LSB, 0x1e},
 +   {VILLA_MSEQ_BANKSELECT, 0x4},
 +   {VILLA_MSEQ_SPARE9_LSB, 0x2},
 +   {VILLA_MSEQ_SPARE3_LSB, 0x0F53},
 +   {VILLA_MSEQ_SPARE3_MSB, 0x2006},
 +   {VILLA_MSEQ_SPARE8_LSB, 0x3FF7},
 +   {VILLA_MSEQ_SPARE8_MSB, 0x0A46},
 +   {VILLA_MSEQ_COEF8_FFE0_LSB, 0xD500},
 +   {VILLA_MSEQ_COEF8_FFE1_LSB, 0x0200},
 +   {VILLA_MSEQ_COEF8_FFE2_LSB, 0xBA00},
 +   {VILLA_MSEQ_COEF8_FFE3_LSB, 0x0100},
 +   {VILLA_MSEQ_COEF8_FFE4_LSB, 0x0300},
 +   {VILLA_MSEQ_COEF8_FFE5_LSB, 0x0300},
 +   {VILLA_MSEQ_COEF8_DFE0_LSB, 0x0700},
 +   {VILLA_MSEQ_COEF8_DFE0N_LSB, 0x0E00},
 +   {VILLA_MSEQ_COEF8_DFE1_LSB, 0x0B00},
 +

Re: [U-Boot] [PATCH v7] net/phy: Add support for CS4315/CS4340 PHY

2014-11-10 Thread shengzhou....@freescale.com 
 -Original Message-
 From: Shengzhou Liu [mailto:shengzhou@freescale.com]
 Sent: Monday, November 10, 2014 6:32 PM
 To: u-boot@lists.denx.de; Sun York-R58495; joe.hershber...@gmail.com
 Cc: Liu Shengzhou-B36685
 Subject: [PATCH v7] net/phy: Add support for CS4315/CS4340 PHY
 
The link of previous version: http://patchwork.ozlabs.org/patch/350162/
Joe, York please review and ACK this version.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot