Re: [U-Boot] [PATCH] : add canyonlands RAM-boot target
On Sunday 06 March 2011 13:13:30 Fawaz wrote: >This patch adds another build target for the AMCC Canyonlands > PPC460Ex eval board. Using JTAG debugger(e.g. BDI2000/3000) configured > to setup the SDRAM. > here are TLB entries required by RAM-u-boot (for BDI2000/3000): > WTLB 0x0095 0x003F ;SDRAM 256MB @ 0x > WTLB 0xE075 0x4E3F > WTLB 0xE105 0x4E10001B > WTLB 0xE354 0x403F > keep SDRAM configuration part as it's. > > Signed-off-by: Fawaz Gaili > Cc: Stefan Roese > Cc: Wolfgang Denk > Cc: Felix Radensky Your patch is line wrapped and can't be applied. Please fix this in your mailer, or even better, use "git send-email" to send your patches. And did you check if this RAM-booting target also works when it is loaded/started via an already running U-Boot (instead of via the JTAG debugger)? Cheers, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Undelivered Mail Returned to Sender
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Re: [U-Boot] [PATCH 06/22] arm: new labels in the linker script file
Hi Aneesh,
On Mon, Feb 28, 2011 at 7:46 PM, Aneesh V wrote:
> _bss_start_ofs is used in start.S to indicate end of copied
> image. This may not be correct when we have a discontiguous
> memory map. For instance, .bss may be placed in SDRAM for
> some SPLS while rest of the image is placed in SRAM.
>
> Define a new label in linker script to indicate the end of the
> image copied during relocation and use it appropriately in
> start.S.
>
> Also, add a new label to indicate the end of flash image.
> This will be useful in identifying the size of flash image
>
> Signed-off-by: Aneesh V
> ---
> arch/arm/cpu/armv7/start.S | 6 +-
> arch/arm/cpu/armv7/u-boot.lds | 4
> 2 files changed, 9 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
> index 3618190..8215d26 100644
> --- a/arch/arm/cpu/armv7/start.S
> +++ b/arch/arm/cpu/armv7/start.S
> @@ -77,6 +77,10 @@ _TEXT_BASE:
> _bss_start_ofs:
> .word __bss_start - _start
>
> +.global _image_copy_end_ofs
> +_image_copy_end_ofs:
> + .word __image_copy_end - _start
> +
> .globl _bss_end_ofs
> _bss_end_ofs:
> .word _end - _start
> @@ -172,7 +176,7 @@ stack_setup:
> beq clear_bss /* skip relocation */
> #endif
> mov r1, r6 /* r1 <- scratch for copy_loop */
> - ldr r3, _bss_start_ofs
> + ldr r3, _image_copy_end_ofs
> add r2, r0, r3 /* r2 <- source end address */
>
> copy_loop:
> diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
> index 5725c30..c3ad587 100644
> --- a/arch/arm/cpu/armv7/u-boot.lds
> +++ b/arch/arm/cpu/armv7/u-boot.lds
> @@ -55,6 +55,8 @@ SECTIONS
>
> . = ALIGN(4);
>
> + __image_copy_end = .;
> +
> .rel.dyn : {
> __rel_dyn_start = .;
> *(.rel*)
> @@ -66,6 +68,8 @@ SECTIONS
> *(.dynsym)
> }
>
> + __flash_image_end = .;
> +
> .bss __rel_dyn_start (OVERLAY) : {
> __bss_start = .;
> *(.bss)
There is a patch series which makes _end as end of image and
has been applied to arm branch.
[U-Boot] [PATCH 1/2 v2] rename _end to __bss_end__
http://lists.denx.de/pipermail/u-boot/2011-March/088166.html
[U-Boot] [PATCH 2/2 v2] arm: fix incorrect monitor protection region in FLASH
http://lists.denx.de/pipermail/u-boot/2011-March/088139.html
You can use the newly added symbol _end_ofs to replace your
__flash_image_end here.
best regards,
Po-Yu Chuang
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Re: [U-Boot] [PATCH 06/22] arm: new labels in the linker script file
On Tuesday 08 March 2011 03:42 PM, Po-Yu Chuang wrote:
> Hi Aneesh,
>
[snip ..]
>> + __flash_image_end = .;
>> +
>> .bss __rel_dyn_start (OVERLAY) : {
>> __bss_start = .;
>> *(.bss)
>
> There is a patch series which makes _end as end of image and
> has been applied to arm branch.
>
> [U-Boot] [PATCH 1/2 v2] rename _end to __bss_end__
> http://lists.denx.de/pipermail/u-boot/2011-March/088166.html
>
> [U-Boot] [PATCH 2/2 v2] arm: fix incorrect monitor protection region in FLASH
> http://lists.denx.de/pipermail/u-boot/2011-March/088139.html
>
> You can use the newly added symbol _end_ofs to replace your
> __flash_image_end here.
Thanks for the pointer. I will do that in v2.
best regards,
Aneesh
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[U-Boot] [PATCH v2 01/10] arm: make default implementation of cache_flush() weakly linked
make default implementation of cache_flush() weakly linked so that
sub-architectures can override it
Signed-off-by: Aneesh V
---
arch/arm/lib/cache.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 30686fe..27123cd 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -25,7 +25,7 @@
#include
-void flush_cache (unsigned long dummy1, unsigned long dummy2)
+void __flush_cache(unsigned long start, unsigned long size)
{
#if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136)
void arm1136_cache_flush(void);
@@ -45,3 +45,5 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2)
#endif
return;
}
+void flush_cache(unsigned long start, unsigned long size)
+ __attribute__((weak, alias("__flush_cache")));
--
1.7.0.4
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[U-Boot] [PATCH v2 00/10] armv7: cache maintenance operations
With D-cache and MMU enabled for ARM in u-boot it becomes imperative to support a minimal set of cache maintenance operations and necessary initializations before enabling MMU. This series of patches attempt to do the following for armv7: * Necessary initialization sequence before enabling MMU that includes invalidation of TLB, data caches, branch predictor array etc. * Framework for supporting SOC specific outer caches in a generic manner (using a structure of function pointers - inspired by the Linux implementation) * Generic armv7 cache maintenance operations for caches known to the CPU * Support for ARM PL310 L2 cache controller used in OMAP4 * Cleanup of the cleanup_before_linux() function * Adapting all armv7 SOCs to use the new framework and removing duplicated code Testing: * Extensive testing on OMAP4430SDP and OMAP3430SDP by creating coherency issues and solving them using the maintenance routines - Eg: memfill a region of memory with a known pattern - Invalidate the region - Read back and compare the region with the original pattern - If match fails it means that invalidate is successful - Now add a flush call just before the invalidate - If match succeeds it means that flush was successful - Outer caches were tested with experiments involving making the function pointers NULL * Kernel booting on OMAP4430SDP and OMAP3430SDP Note: v2 has been tested only on OMAP4430SDP v2: * Pointer based callback mechanism for outer cache operations changed to a weakly linked functions. * Change -march=armv7-a back to armv5 * Moved utility macros out of armv7.h * Added documentation for new CONFIG options. * Changed implementation of log2n to not use CLZ instruction as armv4 doesn't support this instruction and newly added Tegra2 uses -march=armv4 * Blank line after local variable declarations - fixed globally * Explicitly added an empty flush_cache() under #ifdef CONFIG_SYS_NO_DCACHE * Removed the print inside the weakly linked stub function - __arm_init_before_mmu * Fixed signature of flush_cache in cache.c * More descriptive commit message for the PL310 support patch * C struct for PL310 register accesses * Fixed white space issues Aneesh V (10): arm: make default implementation of cache_flush() weakly linked armv7: add miscellaneous utility macros armv7: cache maintenance operations for armv7 armv7: replace CONFIG_L2_OFF with CONFIG_SYS_NO_L2CACHE armv7: integrate cache maintenance support arm: minor fixes for cache and mmu handling armv7: add PL310 support to u-boot armv7: adapt omap4 to the new cache maintenance framework armv7: adapt omap3 to the new cache maintenance framework armv7: adapt s5pc1xx to the new cache maintenance framework README| 11 + arch/arm/cpu/armv7/Makefile |2 +- arch/arm/cpu/armv7/cache_v7.c | 390 + arch/arm/cpu/armv7/cpu.c | 51 ++-- arch/arm/cpu/armv7/omap3/Makefile |1 - arch/arm/cpu/armv7/omap3/board.c | 138 -- arch/arm/cpu/armv7/omap3/cache.S | 263 - arch/arm/cpu/armv7/omap3/lowlevel_init.S | 32 ++ arch/arm/cpu/armv7/omap4/lowlevel_init.S | 18 ++ arch/arm/cpu/armv7/s5pc1xx/cache.S| 88 +- arch/arm/cpu/armv7/start.S| 18 +- arch/arm/include/asm/arch-omap3/omap3.h | 20 ++ arch/arm/include/asm/arch-omap3/sys_proto.h | 10 +- arch/arm/include/asm/arch-omap4/sys_proto.h |1 - arch/arm/include/asm/arch-s5pc1xx/sys_proto.h |3 - arch/arm/include/asm/armv7.h | 68 + arch/arm/include/asm/pl310.h | 74 + arch/arm/include/asm/utils.h | 80 + arch/arm/lib/Makefile |1 + arch/arm/lib/board.c |6 + arch/arm/lib/cache-cp15.c | 16 +- arch/arm/lib/cache-pl310.c| 116 arch/arm/lib/cache.c | 20 +- include/common.h |5 +- include/configs/ca9x4_ct_vxp.h|2 +- include/configs/efikamx.h |2 +- include/configs/mx51evk.h |2 +- include/configs/mx53evk.h |2 +- include/configs/omap4_panda.h |8 +- include/configs/omap4_sdp4430.h |8 +- include/configs/s5pc210_universal.h |2 +- include/configs/tegra2-common.h |2 +- include/configs/vision2.h |2 +- 33 files changed, 1037 insertions(+), 425 deletions(-) create mode 100644 arch/arm/cpu/armv7/cache_v7.c delete mode 100644 arch/arm/cpu/armv7/omap3/cache.S create mode 100644 arch/arm/include/asm/armv7.h create mode 100644 arch/arm/include/asm/pl310.h cr
[U-Boot] [PATCH v2 02/10] armv7: add miscellaneous utility macros
add utility macros for:
* bit field operations
* log2n functions
Signed-off-by: Aneesh V
---
arch/arm/include/asm/utils.h | 80 ++
1 files changed, 80 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/utils.h
diff --git a/arch/arm/include/asm/utils.h b/arch/arm/include/asm/utils.h
new file mode 100644
index 000..d581539
--- /dev/null
+++ b/arch/arm/include/asm/utils.h
@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments,
+ *
+ * Aneesh V
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef_UTILS_H_
+#define_UTILS_H_
+
+/* extract a bit field from a bit vector */
+#define get_bit_field(nr, start, mask)\
+ (((nr) & (mask)) >> (start))
+
+/* Set a field in a bit vector */
+#define set_bit_field(nr, start, mask, val)\
+ do { \
+ (nr) = ((nr) & ~(mask)) | (((val) << (start)) & (mask));\
+ } while (0);
+
+/*
+ * Utility macro for read-modify-write of a hardware register
+ * addr - address of the register
+ * shift - starting bit position of the field to be modified
+ * msk - mask for the field
+ * val - value to be shifted masked and written to the field
+ */
+#define modify_reg_32(addr, shift, msk, val) \
+ do {\
+ writel(((readl(addr) & ~(msk))|(((val) << (shift)) & (msk))),\
+ (addr));\
+ } while (0);
+
+static inline s32 log_2_n_round_up(u32 n)
+{
+ s32 log2n = -1;
+ u32 temp = n;
+
+ while (temp) {
+ log2n++;
+ temp >>= 1;
+ }
+
+ if (n & (n - 1))
+ return log2n + 1; /* not power of 2 - round up */
+ else
+ return log2n; /* power of 2 */
+}
+
+static inline s32 log_2_n_round_down(u32 n)
+{
+ s32 log2n = -1;
+ u32 temp = n;
+
+ while (temp) {
+ log2n++;
+ temp >>= 1;
+ }
+
+ return log2n;
+}
+
+#endif /* _OMAP_COMMON_H_ */
--
1.7.0.4
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[U-Boot] [PATCH v2 10/10] armv7: adapt s5pc1xx to the new cache maintenance framework
adapt s5pc1xx to the new layered cache maintenance framework
Signed-off-by: Aneesh V
---
arch/arm/cpu/armv7/s5pc1xx/cache.S| 88 ++---
arch/arm/include/asm/arch-s5pc1xx/sys_proto.h |3 -
2 files changed, 7 insertions(+), 84 deletions(-)
diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.S
b/arch/arm/cpu/armv7/s5pc1xx/cache.S
index 7734b32..726afe7 100644
--- a/arch/arm/cpu/armv7/s5pc1xx/cache.S
+++ b/arch/arm/cpu/armv7/s5pc1xx/cache.S
@@ -23,98 +23,24 @@
* MA 02111-1307 USA
*/
-#include
-
.align 5
-.global invalidate_dcache
-.global l2_cache_enable
-.global l2_cache_disable
-
-/*
- * invalidate_dcache()
- * Invalidate the whole D-cache.
- *
- * Corrupted registers: r0-r5, r7, r9-r11
- */
-invalidate_dcache:
- stmfd r13!, {r0 - r5, r7, r9 - r12, r14}
-
- cmp r0, #0xC100 @ check if the cpu is s5pc100
- beq finished_inval @ s5pc100 doesn't need this
- @ routine
- mrc p15, 1, r0, c0, c0, 1 @ read clidr
- andsr3, r0, #0x700 @ extract loc from clidr
- mov r3, r3, lsr #23 @ left align loc bit field
- beq finished_inval @ if loc is 0, then no need to
- @ clean
- mov r10, #0 @ start clean at cache level 0
-inval_loop1:
- add r2, r10, r10, lsr #1@ work out 3x current cache
- @ level
- mov r1, r0, lsr r2 @ extract cache type bits from
- @ clidr
- and r1, r1, #7 @ mask of the bits for current
- @ cache only
- cmp r1, #2 @ see what cache we have at
- @ this level
- blt skip_inval @ skip if no cache, or just
- @ i-cache
- mcr p15, 2, r10, c0, c0, 0 @ select current cache level
- @ in cssr
- mov r2, #0 @ operand for mcr SBZ
- mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to
- @ sych the new cssr&csidr,
- @ with armv7 this is 'isb',
- @ but we compile with armv5
- mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
- and r2, r1, #7 @ extract the length of the
- @ cache lines
- add r2, r2, #4 @ add 4 (line length offset)
- ldr r4, =0x3ff
- andsr4, r4, r1, lsr #3 @ find maximum number on the
- @ way size
- clz r5, r4 @ find bit position of way
- @ size increment
- ldr r7, =0x7fff
- andsr7, r7, r1, lsr #13 @ extract max number of the
- @ index size
-inval_loop2:
- mov r9, r4 @ create working copy of max
- @ way size
-inval_loop3:
- orr r11, r10, r9, lsl r5@ factor way and cache number
- @ into r11
- orr r11, r11, r7, lsl r2@ factor index number into r11
- mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
- subsr9, r9, #1 @ decrement the way
- bge inval_loop3
- subsr7, r7, #1 @ decrement the index
- bge inval_loop2
-skip_inval:
- add r10, r10, #2@ increment cache number
- cmp r3, r10
- bgt inval_loop1
-finished_inval:
- mov r10, #0 @ swith back to cache level 0
- mcr p15, 2, r10, c0, c0, 0 @ select current cache level
- @ in cssr
- mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
- @ with armv7 this is 'isb',
- @ but we compile with armv5
+#if !defined(CONFIG_SYS_NO_DCACHE) && !defined(CONFIG_SYS_NO_L2CACHE)
- ldmfd r13!, {r0 - r5, r7, r9 - r12, pc}
-
-l2_cache_enable:
+.global v7_outer_cache_enable
+v7_outer_cache_enable:
push{r0, r1, r2, lr}
mrc 15, 0, r3, cr1, cr0, 1
orr r3, r3, #2
mcr 15, 0, r3, cr1, cr0, 1
pop {r1,
[U-Boot] [PATCH v2 06/10] arm: minor fixes for cache and mmu handling
1. make sure that page table setup is not done multiple times
2. flush_dcache_all() is more appropriate while disabling cache
than a range flush on the entire memory(flush_cache())
Provide a default implementation for flush_dcache_all()
for backward compatibility and to avoid build issues.
Signed-off-by: Aneesh V
---
arch/arm/lib/cache-cp15.c |9 +++--
arch/arm/lib/cache.c | 11 +++
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index fd97c45..b1ccc3c 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -92,13 +92,18 @@ static inline void mmu_setup(void)
set_cr(reg | CR_M);
}
+static int mmu_enabled(void)
+{
+ return get_cr() & CR_M;
+}
+
/* cache_bit must be either CR_I or CR_C */
static void cache_enable(uint32_t cache_bit)
{
uint32_t reg;
/* The data cache is not active unless the mmu is enabled too */
- if (cache_bit == CR_C)
+ if ((cache_bit == CR_C) && !mmu_enabled())
mmu_setup();
reg = get_cr(); /* get control reg. */
cp_delay();
@@ -117,7 +122,7 @@ static void cache_disable(uint32_t cache_bit)
return;
/* if disabling data cache, disable mmu too */
cache_bit |= CR_M;
- flush_cache(0, ~0);
+ flush_dcache_all();
}
reg = get_cr();
cp_delay();
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index dc3242c..92b61a2 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -42,3 +42,14 @@ void __flush_cache(unsigned long start, unsigned long size)
}
void flush_cache(unsigned long start, unsigned long size)
__attribute__((weak, alias("__flush_cache")));
+
+/*
+ * Default implementation:
+ * do a range flush for the entire range
+ */
+void __flush_dcache_all(void)
+{
+ flush_cache(0, ~0);
+}
+void flush_dcache_all(void)
+ __attribute__((weak, alias("__flush_dcache_all")));
--
1.7.0.4
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[U-Boot] [PATCH v2 05/10] armv7: integrate cache maintenance support
- Enable I-cache on bootup
- Enable MMU and D-cache immediately after relocation
- Do necessary initialization before enabling d-cache and MMU
- Changes to cleanup_before_linux()
- Make changes according to the new framework
Signed-off-by: Aneesh V
---
arch/arm/cpu/armv7/cpu.c | 45 +++
arch/arm/cpu/armv7/start.S | 18 -
arch/arm/lib/board.c |6 +
arch/arm/lib/cache-cp15.c |7 ++
arch/arm/lib/cache.c |5
5 files changed, 50 insertions(+), 31 deletions(-)
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index 7f28d87..5c69d04 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -34,13 +34,10 @@
#include
#include
#include
-#include
#include
int cleanup_before_linux(void)
{
- unsigned int i;
-
/*
* this function is called just before we call linux
* it prepares the processor for linux
@@ -49,31 +46,29 @@ int cleanup_before_linux(void)
*/
disable_interrupts();
- /* turn off I/D-cache */
+ /*
+* Turn off I-cache and invalidate it
+*/
icache_disable();
- dcache_disable();
+ invalidate_icache_all();
- /* invalidate I-cache */
- cache_flush();
-
-#ifndef CONFIG_L2_OFF
- /* turn off L2 cache */
- l2_cache_disable();
- /* invalidate L2 cache also */
- invalidate_dcache(get_device_type());
-#endif
- i = 0;
- /* mem barrier to sync up things */
- asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
+ /*
+* turn off D-cache
+* dcache_disable() in turn flushes the d-cache and disables MMU
+*/
+ dcache_disable();
-#ifndef CONFIG_L2_OFF
- l2_cache_enable();
-#endif
+ /*
+* After D-cache is flushed and before it is disabled there may
+* be some new valid entries brought into the cache. We are sure
+* that these lines are not dirty and will not affect our execution.
+* (because unwinding the call-stack and setting a bit in CP15 SCTRL
+* is all we did during this. We have not pushed anything on to the
+* stack. Neither have we affected any static data)
+* So just invalidate the entire d-cache again to avoid coherency
+* problems for kernel
+*/
+ invalidate_dcache_all();
return 0;
}
-
-static void cache_flush(void)
-{
- asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
-}
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index cb4f92f..0b54397 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -239,6 +239,14 @@ clbss_l:strr2, [r0]/* clear
loop...*/
* initialization, now running from RAM.
*/
jump_2_ram:
+/*
+ * If I-cache is enabled invalidate it
+ */
+#ifndef CONFIG_SYS_NO_ICACHE
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
+ mcr p15, 0, r0, c7, c10, 4 @ DSB
+ mcr p15, 0, r0, c7, c5, 4 @ ISB
+#endif
ldr r0, _board_init_r_ofs
adr r1, _start
add lr, r0, r1
@@ -274,6 +282,9 @@ cpu_init_crit:
mov r0, #0 @ set up for MCR
mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
+ mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
+ mcr p15, 0, r0, c7, c10, 4 @ DSB
+ mcr p15, 0, r0, c7, c5, 4 @ ISB
/*
* disable MMU stuff and caches
@@ -282,7 +293,12 @@ cpu_init_crit:
bic r0, r0, #0x2000 @ clear bits 13 (--V-)
bic r0, r0, #0x0007 @ clear bits 2:0 (-CAM)
orr r0, r0, #0x0002 @ set bit 1 (--A-) Align
- orr r0, r0, #0x0800 @ set bit 12 (Z---) BTB
+ orr r0, r0, #0x0800 @ set bit 11 (Z---) BTB
+#ifdef CONFIG_SYS_NO_ICACHE
+ bic r0, r0, #0x1000 @ clear bit 12 (I) I-cache
+#else
+ orr r0, r0, #0x1000 @ set bit 12 (I) I-cache
+#endif
mcr p15, 0, r0, c1, c0, 0
/*
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index c620d2c..72ee108 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -459,6 +459,12 @@ void board_init_r (gd_t *id, ulong dest_addr)
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
+ /*
+* Enable D$:
+* I$, if needed, must be already enabled in start.S
+*/
+ dcache_enable();
+
monitor_flash_len = _bss_start_ofs;
debug ("monitor flash len: %08lX\n", monitor_flash_len);
board_init(); /* Setup chipselects */
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index d9175f0..fd97c45 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -34,6 +34,12 @@
DECLARE_GLOBAL_DATA_PTR;
+void __a
[U-Boot] [PATCH v2 04/10] armv7: replace CONFIG_L2_OFF with CONFIG_SYS_NO_L2CACHE
replace all occurences of CONFIG_L2_OFF with a more appropriate
CONFIG_SYS_NO_L2CACHE
CONFIG_SYS_NO_L2CACHE has been chosen to be in line with
CONFIG_SYS_NO_ICACHE and CONFIG_SYS_NO_DCACHE
Signed-off-by: Aneesh V
---
arch/arm/cpu/armv7/cpu.c|6 +-
include/configs/ca9x4_ct_vxp.h |2 +-
include/configs/efikamx.h |2 +-
include/configs/mx51evk.h |2 +-
include/configs/mx53evk.h |2 +-
include/configs/omap4_panda.h |2 +-
include/configs/omap4_sdp4430.h |2 +-
include/configs/s5pc210_universal.h |2 +-
include/configs/tegra2-common.h |2 +-
include/configs/vision2.h |2 +-
10 files changed, 10 insertions(+), 14 deletions(-)
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index a01e0d6..7f28d87 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -35,11 +35,7 @@
#include
#include
#include
-#ifndef CONFIG_L2_OFF
-#include
-#endif
-
-static void cache_flush(void);
+#include
int cleanup_before_linux(void)
{
diff --git a/include/configs/ca9x4_ct_vxp.h b/include/configs/ca9x4_ct_vxp.h
index 63f003d..bdd4e91 100644
--- a/include/configs/ca9x4_ct_vxp.h
+++ b/include/configs/ca9x4_ct_vxp.h
@@ -40,7 +40,7 @@
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_L2_OFF 1
+#define CONFIG_SYS_NO_L2CACHE 1
#define CONFIG_INITRD_TAG 1
/* Size of malloc() pool */
diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h
index 1424347..0b64f54 100644
--- a/include/configs/efikamx.h
+++ b/include/configs/efikamx.h
@@ -38,7 +38,7 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_L2_OFF
+#define CONFIG_SYS_NO_L2CACHE
/*
* Bootloader Components Configuration
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 591d6e1..20c299b 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -33,7 +33,7 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_L2_OFF
+#define CONFIG_SYS_NO_L2CACHE
#include
/*
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index f2a5752..244a1ae 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -29,7 +29,7 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_L2_OFF
+#define CONFIG_SYS_NO_L2CACHE
#include
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 2b03b0f..8684798 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -46,7 +46,7 @@
#define CONFIG_DISPLAY_BOARDINFO 1
/* Keep L2 Cache Disabled */
-#define CONFIG_L2_OFF 1
+#define CONFIG_SYS_NO_L2CACHE 1
/* Clock Defines */
#define V_OSCK 3840/* Clock output from T2 */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 9a8bb73..7cc0c13 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -47,7 +47,7 @@
#define CONFIG_DISPLAY_BOARDINFO 1
/* Keep L2 Cache Disabled */
-#define CONFIG_L2_OFF 1
+#define CONFIG_SYS_NO_L2CACHE 1
/* Clock Defines */
#define V_OSCK 3840/* Clock output from T2 */
diff --git a/include/configs/s5pc210_universal.h
b/include/configs/s5pc210_universal.h
index c033a8d..09f5cfc 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -43,7 +43,7 @@
#define CONFIG_DISPLAY_BOARDINFO
/* Keep L2 Cache Disabled */
-#define CONFIG_L2_OFF 1
+#define CONFIG_SYS_NO_L2CACHE 1
#define CONFIG_SYS_SDRAM_BASE 0x4000
#define CONFIG_SYS_TEXT_BASE 0x4480
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
index 4f4374a..27edf68 100644
--- a/include/configs/tegra2-common.h
+++ b/include/configs/tegra2-common.h
@@ -31,7 +31,7 @@
#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
#define CONFIG_TEGRA2 /* in a NVidia Tegra2 core */
#define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */
-#define CONFIG_L2_OFF /* No L2 cache */
+#define CONFIG_SYS_NO_L2CACHE /* No L2 cache */
#include/* get chip and board defs */
diff --git a/include/configs/vision2.h b/include/configs/vision2.h
index 4c8e7fa..d6c99de 100644
--- a/include/configs/vision2.h
+++ b/include/configs/vision2.h
@@ -26,7 +26,7 @@
#define CONFIG_MX51/* in a mx51 */
-#define CONFIG_L2_OFF
+#define CONFIG_SYS_NO_L2CACHE
#include
--
1.7.0.4
___
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U-Boot@lists.denx.de
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[U-Boot] [PATCH v2 09/10] armv7: adapt omap3 to the new cache maintenance framework
adapt omap3 to the new layered cache maintenance framework
Signed-off-by: Aneesh V
---
arch/arm/cpu/armv7/omap3/Makefile |1 -
arch/arm/cpu/armv7/omap3/board.c| 138 --
arch/arm/cpu/armv7/omap3/cache.S| 263 ---
arch/arm/cpu/armv7/omap3/lowlevel_init.S| 32
arch/arm/include/asm/arch-omap3/omap3.h | 20 ++
arch/arm/include/asm/arch-omap3/sys_proto.h | 10 +-
6 files changed, 178 insertions(+), 286 deletions(-)
delete mode 100644 arch/arm/cpu/armv7/omap3/cache.S
diff --git a/arch/arm/cpu/armv7/omap3/Makefile
b/arch/arm/cpu/armv7/omap3/Makefile
index 7164d50..522bcd2 100644
--- a/arch/arm/cpu/armv7/omap3/Makefile
+++ b/arch/arm/cpu/armv7/omap3/Makefile
@@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
-SOBJS += cache.o
COBJS += board.o
COBJS += clock.o
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 6c2a132..39866e0 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -37,8 +37,12 @@
#include
#include
#include
+#include
+/* Declarations */
extern omap3_sysinfo sysinfo;
+static void omap3_setup_aux_cr(void);
+static void omap3_invalidate_l2_cache_secure(void);
/**
* Routine: delay
@@ -166,27 +170,13 @@ void s_init(void)
try_unlock_memory();
- /*
-* Right now flushing at low MPU speed.
-* Need to move after clock init
-*/
- invalidate_dcache(get_device_type());
-#ifndef CONFIG_ICACHE_OFF
- icache_enable();
-#endif
+ /* Errata workarounds */
+ omap3_setup_aux_cr();
-#ifdef CONFIG_L2_OFF
- l2_cache_disable();
-#else
- l2_cache_enable();
+#ifndef CONFIG_SYS_NO_L2CACHE
+ /* Invalidate L2-cache from secure mode */
+ omap3_invalidate_l2_cache_secure();
#endif
- /*
-* Writing to AuxCR in U-boot using SMI for GP DEV
-* Currently SMI in Kernel on ES2 devices seems to have an issue
-* Once that is resolved, we can postpone this config to kernel
-*/
- if (get_device_type() == GP_DEVICE)
- setup_auxcr();
set_muxconf_regs();
delay(100);
@@ -292,3 +282,113 @@ int checkboard (void)
return 0;
}
#endif /* CONFIG_DISPLAY_BOARDINFO */
+
+static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
+{
+ u32 i, num_params = *parameters;
+ u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
+
+ /*
+* copy the parameters to an un-cached area to avoid coherency
+* issues
+*/
+ for (i = 0; i < num_params; i++) {
+ __raw_writel(*parameters, sram_scratch_space);
+ parameters++;
+ sram_scratch_space++;
+ }
+
+ /* Now make the PPA call */
+ do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
+}
+
+static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
+{
+ u32 acr;
+
+ /* Read ACR */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
+ acr &= ~clear_bits;
+ acr |= set_bits;
+
+ if (get_device_type() == GP_DEVICE) {
+ omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
+ acr);
+ } else {
+ struct emu_hal_params emu_romcode_params;
+ emu_romcode_params.num_params = 1;
+ emu_romcode_params.param1 = acr;
+ omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+ (u32 *)&emu_romcode_params);
+ }
+}
+
+static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
+{
+ u32 acr;
+
+ /* Read ACR */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
+ acr &= ~clear_bits;
+ acr |= set_bits;
+
+ /* Write ACR - affects non-secure banked bits */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
+}
+
+static void omap3_setup_aux_cr(void)
+{
+ /* Workaround for Cortex-A8 errata: #454179 #430973
+* Set "IBE" bit
+* Set "Disable Brach Size Mispredicts" bit
+* Workaround for erratum #621766
+* Enable L1NEON bit
+* ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
+*/
+ omap3_update_aux_cr_secure(0xE0, 0);
+}
+
+#if !defined(CONFIG_SYS_NO_DCACHE) && !defined(CONFIG_SYS_NO_L2CACHE)
+
+/* Invalidate the entire L2 cache from secure mode */
+static void omap3_invalidate_l2_cache_secure(void)
+{
+ if (get_device_type() == GP_DEVICE) {
+ omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
+ 0);
+ } else {
+ struct emu_hal_params emu_romcode_params;
+ emu_romcode_params.num_params = 1;
+
[U-Boot] [PATCH v2 03/10] armv7: cache maintenance operations for armv7
- Add a framework for layered cache maintenance
- separate out SOC specific outer cache maintenance from
maintenance of caches known to CPU
- Add generic ARMv7 cache maintenance operations that affect all
caches known to ARMv7 CPUs. For instance in Cortex-A8 these
opertions will affect both L1 and L2 caches. In Cortex-A9
these will affect only L1 cache
- D-cache operations supported:
- Invalidate entire D-cache
- Invalidate D-cache range
- Flush(clean & invalidate) entire D-cache
- Flush D-cache range
- I-cache operations supported:
- Invalidate entire I-cache
- Add maintenance functions for TLB, branch predictor array etc.
- Enable -march=armv7-a so that armv7 assembly instructions can be
used
Signed-off-by: Aneesh V
---
README|5 +
arch/arm/cpu/armv7/Makefile |2 +-
arch/arm/cpu/armv7/cache_v7.c | 390 +
arch/arm/include/asm/armv7.h | 68 +++
include/common.h |5 +-
5 files changed, 468 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv7/cache_v7.c
create mode 100644 arch/arm/include/asm/armv7.h
diff --git a/README b/README
index 21cd71b..ba01c52 100644
--- a/README
+++ b/README
@@ -448,6 +448,11 @@ The following options need to be configured:
Note: If a "bootargs" environment is defined, it will overwride
the defaults discussed just above.
+- Cache Configuration:
+ CONFIG_SYS_NO_ICACHE - Do not enable instruction cache in U-Boot
+ CONFIG_SYS_NO_DCACHE - Do not enable data cache in U-Boot
+ CONFIG_SYS_NO_L2CACHE- Do not enable L2 cache in U-Boot
+
- Serial Ports:
CONFIG_PL010_SERIAL
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 8c0e915..299792a 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(CPU).o
START := start.o
-COBJS := cpu.o
+COBJS := cpu.o cache_v7.o
COBJS += syslib.o
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
new file mode 100644
index 000..46d8e09
--- /dev/null
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -0,0 +1,390 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ * Aneesh V
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include
+#include
+#include
+#include
+
+#define ARMV7_DCACHE_INVAL_ALL 1
+#define ARMV7_DCACHE_CLEAN_INVAL_ALL 2
+#define ARMV7_DCACHE_INVAL_RANGE 3
+#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4
+
+#ifndef CONFIG_SYS_NO_DCACHE
+/*
+ * Write the level and type you want to Cache Size Selection Register(CSSELR)
+ * to get size details from Current Cache Size ID Register(CCSIDR)
+ */
+static void set_csselr(u32 level, u32 type)
+{ u32 csselr = level << 1 | type;
+
+ /* Write to Cache Size Selection Register(CSSELR) */
+ asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
+}
+
+static u32 get_ccsidr(void)
+{
+ u32 ccsidr;
+
+ /* Read current CP15 Cache Size ID Register */
+ asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
+ return ccsidr;
+}
+
+static u32 get_clidr(void)
+{
+ u32 clidr;
+
+ /* Read current CP15 Cache Level ID Register */
+ asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr));
+ return clidr;
+}
+
+static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
+u32 num_ways, u32 way_shift,
+u32 log2_line_len)
+{
+ int way, set, setway;
+
+ /*
+* For optimal assembly code:
+* a. count down
+* b. have bigger loop inside
+*/
+ for (way = num_ways - 1; way >= 0 ; way--)
+ for (set = num_sets - 1; set >= 0; set--) {
+ setway = (level << 1) | (set << log2_line_len) |
+(way << way_shift);
+ /* Invalidate data/unified cache line by set/way */
+
[U-Boot] [PATCH v2 08/10] armv7: adapt omap4 to the new cache maintenance framework
adapt omap4 to the new layered cache maintenance framework
Signed-off-by: Aneesh V
---
arch/arm/cpu/armv7/omap4/lowlevel_init.S| 18 ++
arch/arm/include/asm/arch-omap4/sys_proto.h |1 -
include/configs/omap4_panda.h |8 +---
include/configs/omap4_sdp4430.h |8 +---
4 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S
b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
index 026dfa4..5e6c16f 100644
--- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
@@ -45,3 +45,21 @@ lowlevel_init:
*/
bl s_init
pop {ip, pc}
+
+set_pl310_ctrl_reg:
+ PUSH{r4-r11, lr}@ save registers - ROM code may pollute
+ @ our registers
+ LDR r12, =0x102 @ Set PL310 control register - value in R0
+ .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5
+ @ call ROM Code API to set control register
+ POP {r4-r11, pc}
+
+.globl v7_outer_cache_enable
+v7_outer_cache_enable:
+ MOV r0, #1
+ B set_pl310_ctrl_reg
+
+.globl v7_outer_cache_disable
+v7_outer_cache_disable:
+ MOV r0, #0
+ B set_pl310_ctrl_reg
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h
b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 4813e9e..017f216 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -31,7 +31,6 @@ struct omap_sysinfo {
void gpmc_init(void);
void watchdog_init(void);
u32 get_device_type(void);
-void invalidate_dcache(u32);
void set_muxconf_regs(void);
void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 8684798..d7abf94 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -45,9 +45,6 @@
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
-/* Keep L2 Cache Disabled */
-#define CONFIG_SYS_NO_L2CACHE 1
-
/* Clock Defines */
#define V_OSCK 3840/* Clock output from T2 */
#define V_SCLK V_OSCK
@@ -234,4 +231,9 @@
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
+#ifndef CONFIG_SYS_NO_L2CACHE
+#define CONFIG_SYS_L2_PL3101
+#define CONFIG_SYS_PL310_BASE 0x48242000
+#endif
+
#endif /* __CONFIG_H */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 7cc0c13..3d5ffe5 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -46,9 +46,6 @@
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
-/* Keep L2 Cache Disabled */
-#define CONFIG_SYS_NO_L2CACHE 1
-
/* Clock Defines */
#define V_OSCK 3840/* Clock output from T2 */
#define V_SCLK V_OSCK
@@ -240,4 +237,9 @@
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
+#ifndef CONFIG_SYS_NO_L2CACHE
+#define CONFIG_SYS_L2_PL3101
+#define CONFIG_SYS_PL310_BASE 0x48242000
+#endif
+
#endif /* __CONFIG_H */
--
1.7.0.4
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[U-Boot] [PATCH v2 07/10] armv7: add PL310 support to u-boot
PL310 is the L2$ controller from ARM used in many SoCs
including the Cortex-A9 based OMAP4430
Add support for some of the key PL310 operations
- Invalidate all
- Invalidate range
- Flush(clean & invalidate) all
- Flush range
Signed-off-by: Aneesh V
---
README |6 ++
arch/arm/include/asm/pl310.h | 74 +++
arch/arm/lib/Makefile|1 +
arch/arm/lib/cache-pl310.c | 116 ++
4 files changed, 197 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/pl310.h
create mode 100644 arch/arm/lib/cache-pl310.c
diff --git a/README b/README
index ba01c52..f1547a4 100644
--- a/README
+++ b/README
@@ -453,6 +453,12 @@ The following options need to be configured:
CONFIG_SYS_NO_DCACHE - Do not enable data cache in U-Boot
CONFIG_SYS_NO_L2CACHE- Do not enable L2 cache in U-Boot
+- Cache Configuration for ARM:
+ CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
+ controller
+ CONFIG_SYS_PL310_BASE - Physical base address of PL310
+ controller register space
+
- Serial Ports:
CONFIG_PL010_SERIAL
diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
new file mode 100644
index 000..ffc58e9
--- /dev/null
+++ b/arch/arm/include/asm/pl310.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Aneesh V
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _PL310_H_
+#define _PL310_H_
+
+#include
+
+/* Register bit fields */
+#define PL310_AUX_CTRL_ASSOCIATIVITY_MASK (1 << 16)
+
+struct pl310_regs {
+ u32 pl310_cache_id;
+ u32 pl310_cache_type;
+ u32 pad1[62];
+ u32 pl310_ctrl;
+ u32 pl310_aux_ctrl;
+ u32 pl310_tag_latency_ctrl;
+ u32 pl310_data_latency_ctrl;
+ u32 pad2[60];
+ u32 pl310_event_cnt_ctrl;
+ u32 pl310_event_cnt1_cfg;
+ u32 pl310_event_cnt0_cfg;
+ u32 pl310_event_cnt1_val;
+ u32 pl310_event_cnt0_val;
+ u32 pl310_intr_mask;
+ u32 pl310_masked_intr_stat;
+ u32 pl310_raw_intr_stat;
+ u32 pl310_intr_clear;
+ u32 pad3[323];
+ u32 pl310_cache_sync;
+ u32 pad4[15];
+ u32 pl310_inv_line_pa;
+ u32 pad5[2];
+ u32 pl310_inv_way;
+ u32 pad6[12];
+ u32 pl310_clean_line_pa;
+ u32 pad7[1];
+ u32 pl310_clean_line_idx;
+ u32 pl310_clean_way;
+ u32 pad8[12];
+ u32 pl310_clean_inv_line_pa;
+ u32 pad9[1];
+ u32 pl310_clean_inv_line_idx;
+ u32 pl310_clean_inv_way;
+};
+
+void pl310_inval_all(void);
+void pl310_clean_inval_all(void);
+void pl310_inval_range(u32 start, u32 end);
+void pl310_clean_inval_range(u32 start, u32 end);
+
+#endif
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 454440c..98f32da 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -42,6 +42,7 @@ COBJS-y += cache.o
ifndef CONFIG_SYS_NO_CP15_CACHE
COBJS-y+= cache-cp15.o
endif
+COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
COBJS-y+= interrupts.o
COBJS-y+= reset.o
diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c
new file mode 100644
index 000..f55c63a
--- /dev/null
+++ b/arch/arm/lib/cache-pl310.c
@@ -0,0 +1,116 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Aneesh V
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a cop
[U-Boot] cfi: Problem with Intel Strata 28F320 flash
Hello, as I am actual trying to get the keymile boards in sync with actual mainline u-boot, I faced the following Problem with an Intel Strata Flash on the mgcoge (mpc8247 based board): I couldn;t unprotect/erase/write/protect some (not all!) Flash sectors. For Example, I could do this without errors on the sectors where u-boot sits (First three sectors), but not with the environment (next two sectors)! After some debugging, I found out, that, if I revert commit commit 54652991caedc39b2ec2e5b49e750669bfcd1e2e Author: Philippe De Muyter Date: Tue Aug 17 18:40:25 2010 +0200 Work around bug in Numonyx P33/P30 256-Mbit 65nm flash chips. I have "ported" U-boot to a in house made board with Numonyx Axcell P33/P30 256-Mbit 65nm flash chips. After some time :( searching for bugs in our board or soft, we have discovered that those chips have a small but annoying bug, documented in "Numonyx Axcell P33/P30 256-Mbit Specification Update" [...] It works again fine, and without problems ... did somebody faced similiar issues with the cfi driver? Some Ideas? bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 15/20] keymile boards: add CONFIG_PIGGY_MAC_ADRESS_OFFSET
Normaly the PIGGY_MAC_ADRESS can be read directly from the
IVM on keymile boards. On mgcoge3 it differs. Because there
are two piggy boards deployed the second MAC adress must be
calculated with the IVM mac adress and an offset. This patch
allows to set such a offset in the board config.
Signed-off-by: Holger Brunck
cc: Valentin Longchamp
cc: Heiko Schocher
---
board/keymile/common/common.c | 20
board/keymile/common/common.h |4
2 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index 03d63c1..6136884 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -228,8 +228,28 @@ static int ivm_analyze_block2 (unsigned char *buf, int len)
buf[5],
buf[6]);
ivm_set_value ("IVM_MacAddress", (char *)valbuf);
+ /* if an offset is defined, add it */
+#if defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET)
+ if(CONFIG_PIGGY_MAC_ADRESS_OFFSET > 0) {
+ unsigned long val = (buf[4] << 16) + (buf[5] << 8) + buf[6];
+
+ val += CONFIG_PIGGY_MAC_ADRESS_OFFSET;
+ buf[4] = (val >> 16) & 0xff;
+ buf[5] = (val >> 8) & 0xff;
+ buf[6] = val & 0xff;
+
+ sprintf ((char *)valbuf, "%02X:%02X:%02X:%02X:%02X:%02X",
+ buf[1],
+ buf[2],
+ buf[3],
+ buf[4],
+ buf[5],
+ buf[6]);
+ }
+#endif
if (getenv ("ethaddr") == NULL)
setenv ((char *)"ethaddr", (char *)valbuf);
+
/* IVM_MacCount */
count = (buf[10] << 24) +
(buf[11] << 16) +
diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h
index a38c727..8fd3125 100644
--- a/board/keymile/common/common.h
+++ b/board/keymile/common/common.h
@@ -11,6 +11,10 @@
#ifndef __KEYMILE_COMMON_H
#define __KEYMILE_COMMON_H
+#if !defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET)
+#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 0
+#endif
+
int ethernet_present (void);
int ivm_read_eeprom (void);
--
1.7.4
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[U-Boot] [PATCH 18/20] keymile boards: support of boardId / hwkey lists
From: Thomas Herzmann
In order to support boardId / hwkey lists, the u-boot default
environment has been updated: Added a script checkboardidlist
which checks the list of boardId / hwkey if the boadrId / hwkey
of the IVM is included in that list. This feature is used if you
got different HW variants but you only want to create one boot
package. E.g. supx5 board series.
Signed-off-by: Thomas Herzmann
Signed-off-by: Holger Brunck
cc: Valentin Longchamp
cc: Heiko Schocher
---
include/configs/keymile-common.h | 29 -
1 files changed, 28 insertions(+), 1 deletions(-)
diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h
index a04c39e..ed24072 100644
--- a/include/configs/keymile-common.h
+++ b/include/configs/keymile-common.h
@@ -243,6 +243,7 @@
"release=" \
"setenv actual_bank ${initial_boot_bank} && " \
"setenv subbootcmds \"" \
+ "checkboardidlist " \
"checkboardid " \
"ubiattach ubicopy "\
"cramfsloadfdt cramfsloadkernel " \
@@ -392,8 +393,34 @@
"default=" \
"setenv default \'run newenv; reset\' && " \
"run release && saveenv; reset\0" \
+ "checkboardidlist=" \
+ "if test \"x${boardIdListHex}\" != \"x\"; then "\
+ "IVMbidhwk=${IVM_BoardId}_${IVM_HWKey}; " \
+ "found=0; " \
+ "for bidhwk in \"${boardIdListHex}\"; do " \
+ "echo trying $bidhwk ...; " \
+ "if test \"x$bidhwk\" = \"x$IVMbidhwk\"; then " \
+ "found=1; " \
+ "echo match found for $bidhwk; "\
+ "if test \"x$bidhwk\" != \"x${boardId}_${hwKey}\";then "\
+ "setenv boardid ${IVM_BoardId}; " \
+ "setenv boardId ${IVM_BoardId}; " \
+ "setenv hwkey ${IVM_HWKey}; " \
+ "setenv hwKey ${IVM_HWKey}; " \
+ "echo \"boardId set to ${boardId}\"; " \
+ "echo \"hwKey set to ${hwKey}\"; "\
+ "saveenv; " \
+ "fi; " \
+ "fi; " \
+ "done; "\
+ "else " \
+ "echo \"boardIdListHex not set, not checked\"; "\
+ "found=1; " \
+ "fi; " \
+ "test \"$found\" = 1 \0"\
"checkboardid=" \
- "test \"x${boardId}\" = \"x${IVM_BoardId}\"\0" \
+ "test \"x${boardId}\" = \"x${IVM_BoardId}\" && "\
+ "test \"x${hwKey}\" = \"x${IVM_HWKey}\"\0" \
"printbootargs=print bootargs\0"\
"rootfsfile=" xstr(CONFIG_HOSTNAME) "/rootfsImage\0"\
""
--
1.7.4
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[U-Boot] [PATCH 05/20] arm: add support for kirkwood based mgcoge2un board
This board is similar to keymile suen3.
Signed-off-by: Clive Stubbings
Signed-off-by: Holger Brunck
Signed-off-by: Heiko Schocher
cc: Prafulla Wadaskar
---
MAINTAINERS |1 +
boards.cfg |1 +
include/configs/km_arm.h| 41 +
include/configs/mgcoge2un.h | 60 +++
include/configs/suen3.h | 41 -
5 files changed, 103 insertions(+), 41 deletions(-)
create mode 100644 include/configs/mgcoge2un.h
diff --git a/MAINTAINERS b/MAINTAINERS
index cbc34af..4e7a8f7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -428,6 +428,7 @@ Heiko Schocher
jupiter MPC5200
kmeter1 MPC8360
mgcoge MPC8247
+ mgcoge2un ARM926EJS (Kirkwood SoC)
mucmc52 MPC5200
muas3001MPC8270
municse MPC5200
diff --git a/boards.cfg b/boards.cfg
index b3a4e9e..1b45b5e 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -94,6 +94,7 @@ davinci_schmoogiearm arm926ejs
schmoogie davinci
davinci_sffsdr arm arm926ejs sffsdr
davincidavinci
davinci_sonata arm arm926ejs sonata
davincidavinci
suen3arm arm926ejs km_arm
keymilekirkwood
+mgcoge2unarm arm926ejs km_arm
keymilekirkwood
guruplug arm arm926ejs -
Marvellkirkwood
mv88f6281gtw_ge arm arm926ejs -
Marvellkirkwood
openrd_base arm arm926ejs -
Marvellkirkwood
diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h
index 04a187e..c1a0feb 100644
--- a/include/configs/km_arm.h
+++ b/include/configs/km_arm.h
@@ -197,6 +197,47 @@ int get_scl (void);
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_IN_EEPROM/* use EEPROM for environment
vars */
+#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50
+#define CONFIG_ENV_EEPROM_IS_ON_I2C1
+#define CONFIG_SYS_EEPROM_WREN 1
+#define CONFIG_ENV_OFFSET 0x0 /* no bracets! */
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE(0x2000 - CONFIG_ENV_OFFSET)
+#define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0"
+
+/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+#define CONFIG_CMD_SF
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_HARD_SPI
+#define CONFIG_KIRKWOOD_SPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 5000/* 50Mhz */
+
+#define FLASH_GPIO_PIN 0x0001
+
+#define MTDIDS_DEFAULT "nand0=orion_nand"
+/* test-only: partitioning needs some tuning, this is just for tests */
+#define MTDPARTS_DEFAULT "mtdparts=" \
+ "orion_nand:" \
+ "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
+
+#defineCONFIG_KM_DEF_ENV_UPDATE
\
+ "update=" \
+ "spi on;sf probe 0;sf erase 0 5;" \
+ "sf write ${u-boot_addr_r} 0 ${filesize};" \
+ "spi off\0"
+
#if defined(CONFIG_SYS_NO_FLASH)
#define CONFIG_KM_UBI_PARTITION_NAME "ubi0"
#undef CONFIG_FLASH_CFI_MTD
diff --git a/include/configs/mgcoge2un.h b/include/configs/mgcoge2un.h
new file mode 100644
index 000..1f2b23f
--- /dev/null
+++ b/include/configs/mgcoge2un.h
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor
+ * Prafulla Wadaskar
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, s...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if n
[U-Boot] [PATCH 09/20] powerpc, 83xx: add kmsupx5 board support
The Keymile SUPx5 board series is based on a PBEC8321 but contains an additional PBUS FPGA (LPXF) on local bus CS2. Signed-off-by: Thomas Reufer Signed-off-by: Heiko Schocher cc: Wolfgang Denk cc: Kim Phillips cc: Valentin Longchamp cc: Holger Brunck --- MAINTAINERS |1 + boards.cfg|1 + include/configs/kmsupx5.h | 89 + 3 files changed, 91 insertions(+), 0 deletions(-) create mode 100644 include/configs/kmsupx5.h diff --git a/MAINTAINERS b/MAINTAINERS index e4525e4..730e306 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -427,6 +427,7 @@ Heiko Schocher ids8247 MPC8247 jupiter MPC5200 kmeter1 MPC8360 + kmsupx5 MPC8321 mgcoge MPC8247 mgcoge2ne MPC8247 mgcoge2un ARM926EJS (Kirkwood SoC) diff --git a/boards.cfg b/boards.cfg index 3c45456..d1ec52e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -477,6 +477,7 @@ kmeter1 powerpc mpc83xx km83xx keymile MVBLM7 powerpc mpc83xx mvblm7 matrix_vision SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon- SIMPC8313:NAND_LP SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon- SIMPC8313:NAND_SP +kmsupx5 powerpc mpc83xx km83xx keymile suvd3powerpc mpc83xx km83xx keymile TQM834x powerpc mpc83xx tqm834x tqc tuda1powerpc mpc83xx km83xx keymile diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h new file mode 100644 index 000..ff9883e --- /dev/null +++ b/include/configs/kmsupx5.h @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + *Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + *Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + *Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, h...@denx.de. + * + * (C) Copyright 2010 + * Lukas Roggli, KEYMILE Ltd, lukas.rog...@keymile.com + * + * (C) Copyright 2010 + * Thomas Reufer, KEYMILE Ltd, thomas.reu...@keymile.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_KMSUPX5 1 /* Keymile PBEC8321 board specific */ +#define CONFIG_HOSTNAMEsupx5 +#define CONFIG_KM_BOARD_NAME "supx5" + +#defineCONFIG_SYS_TEXT_BASE0xF000 + +/* include common defines/options for all 8321 Keymile boards */ +#include "km8321-common.h" + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * --- --- -- - -- + * 2 Local GPCM8 bit 256MB LPXF + * 3 Local not used + * + */ + +/* + * LPXF on the local bus CS2 + * Window base at flash base + * Window size: 256 MB + */ + +#defineCONFIG_SYS_LPXF_BASE0xA000// LPXF +#defineCONFIG_SYS_LPXF_SIZE256 // Megabytes + +#define CONFIG_SYS_LBLAWBAR2_PRELIMCONFIG_SYS_LPXF_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM LBLAWAR_EN | LBLAWAR_256MB + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LPXF_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_2 | \ + (OR_GPCM_TRLX & \ + (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_EAD) + +/* LPXF: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +/* Bank 3 not used */ +#define CONFIG_SYS_IBAT6L (0) +#define CONFIG_SYS_IBAT6U (0) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#endif /* __CONFIG_H */ -- 1.7.4 _
[U-Boot] [PATCH 06/20] arm: add support of Kirkwood based board SUEN8
The Kirwood based SUEN8 board from Keymile is at this stage
the same than the suen3 board. This patch adds the board
support for the suen8.
Signed-off-by: Holger Brunck
Signed-off-by: Heiko Schocher
cc: Prafulla Wadaskar
---
MAINTAINERS |1 +
boards.cfg |1 +
include/configs/suen8.h | 59 +++
3 files changed, 61 insertions(+), 0 deletions(-)
create mode 100644 include/configs/suen8.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 4e7a8f7..9644d38 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -434,6 +434,7 @@ Heiko Schocher
municse MPC5200
sc3 PPC405GP
suen3 ARM926EJS (Kirkwood SoC)
+ suen8 ARM926EJS (Kirkwood SoC)
suvd3 MPC8321
tuda1 MPC8321
tuxa1 MPC8321
diff --git a/boards.cfg b/boards.cfg
index 1b45b5e..22cb509 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -94,6 +94,7 @@ davinci_schmoogiearm arm926ejs
schmoogie davinci
davinci_sffsdr arm arm926ejs sffsdr
davincidavinci
davinci_sonata arm arm926ejs sonata
davincidavinci
suen3arm arm926ejs km_arm
keymilekirkwood
+suen8arm arm926ejs km_arm
keymilekirkwood
mgcoge2unarm arm926ejs km_arm
keymilekirkwood
guruplug arm arm926ejs -
Marvellkirkwood
mv88f6281gtw_ge arm arm926ejs -
Marvellkirkwood
diff --git a/include/configs/suen8.h b/include/configs/suen8.h
new file mode 100644
index 000..2f25b74
--- /dev/null
+++ b/include/configs/suen8.h
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor
+ * Prafulla Wadaskar
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, s...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* for linking errors see
http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
+
+#ifndef _CONFIG_SUEN8_H
+#define _CONFIG_SUEN8_H
+
+/* include common defines/options for all arm based Keymile boards */
+#include "km_arm.h"
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING"\nKeymile SUEN8"
+
+#define CONFIG_HOSTNAMEsuen8
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_KM_DEF_ENV \
+ "memsize=0x800\0" \
+ "newenv=setenv addr 0x10 && " \
+ "i2c dev 1; mw.b ${addr} 0 4 && " \
+ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR)\
+ " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && "\
+ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR)\
+ " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \
+ "rootpath=/opt/eldk/arm\0" \
+ "EEprom_ivm=pca9544a:70:9\0"\
+ ""
+
+#endif /* _CONFIG_SUEN8_H */
--
1.7.4
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[U-Boot] [PATCH 11/20] km_arm: change some register values for SDRAM initialization
These new values were given by Clive Stubbings from Xentech. According to him they should be used on all bobcat designs. The changes are the following: - enables UART0 and UART1 pins in MPP - define some L2 cache settings - changes a SDRAM timing to better fit the hardware - removed three writes that were the same as the reset values Signed-off-by: Valentin Longchamp Signed-off-by: Heiko Schocher cc: Holger Brunck cc: Prafulla Wadaskar --- board/keymile/km_arm/kwbimage.cfg | 32 ++-- 1 files changed, 18 insertions(+), 14 deletions(-) diff --git a/board/keymile/km_arm/kwbimage.cfg b/board/keymile/km_arm/kwbimage.cfg index 26d6aa0..b2f5193 100644 --- a/board/keymile/km_arm/kwbimage.cfg +++ b/board/keymile/km_arm/kwbimage.cfg @@ -27,16 +27,18 @@ # Boot Media configurations BOOT_FROM spi # Boot from SPI flash -DATA 0xFFD1 0x0111 # MPP Control 0 Register -# bit 3-0: MPPSel0 1, NF_IO[2] -# bit 7-4: MPPSel1 1, NF_IO[3] -# bit 12-8: MPPSel2 1, NF_IO[4] -# bit 15-12: MPPSel3 1, NF_IO[5] +DATA 0xFFD1 0x0111 # MPP Control 0 Register +# bit 3-0: MPPSel0 2, NF_IO[2] +# bit 7-4: MPPSel1 2, NF_IO[3] +# bit 12-8: MPPSel2 2, NF_IO[4] +# bit 15-12: MPPSel3 2, NF_IO[5] # bit 19-16: MPPSel4 1, NF_IO[6] # bit 23-20: MPPSel5 1, NF_IO[7] # bit 27-24: MPPSel6 1, SYSRST_O # bit 31-28: MPPSel7 0, GPO[7] +DATA 0xFFD10004 0x03303300 + DATA 0xFFD10008 0x1100 # MPP Control 2 Register # bit 3-0: MPPSel16 0, GPIO[16] # bit 7-4: MPPSel17 0, GPIO[17] @@ -48,8 +50,8 @@ DATA 0xFFD10008 0x1100# MPP Control 2 Register # bit 31-28: MPPSel23 0, GPIO[23] DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register -DATA 0xFFD20134 0x # L2 RAM Timing 0 Register -DATA 0xFFD20138 0x00BB # L2 RAM Timing 1 Register +DATA 0xFFD20134 0x # L2 RAM Timing 0 Register +DATA 0xFFD20138 0x # L2 RAM Timing 1 Register DATA 0xFFD20154 0x0200 # CPU RAM Management Control3 Register DATA 0xFFD2014C 0x1C00 # CPU RAM Management Control1 Register DATA 0xFFD20148 0x0001 # CPU RAM Management Control0 Register @@ -63,7 +65,7 @@ DATA 0xFFD01400 0x43000400# SDRAM Configuration Register # bit29-26: zero # bit31-30: 01 -DATA 0xFFD01404 0x36343000 # DDR Controller Control Low +DATA 0xFFD01404 0x39543000 # DDR Controller Control Low # bit 3-0: 0 reserved # bit 4:0=addr/cmd in smame cycle # bit 5:0=clk is driven during self refresh, we don't care for APX @@ -75,7 +77,7 @@ DATA 0xFFD01404 0x36343000# DDR Controller Control Low # bit30-28: 3 required # bit31:0=no additional STARTBURST delay -DATA 0xFFD01408 0x2302544B # DDR Timing (Low) (active cycles value +1) +DATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1) # bit3-0: TRAS lsbs # bit7-4: TRCD # bit11- 8: TRP @@ -86,7 +88,7 @@ DATA 0xFFD01408 0x2302544B# DDR Timing (Low) (active cycles value +1) # bit27-24: TRRD # bit31-28: TRTP -DATA 0xFFD0140C 0x0032 # DDR Timing (High) +DATA 0xFFD0140C 0x0033 # DDR Timing (High) # bit6-0: TRFC # bit8-7: TR2R # bit10-9: TR2W @@ -116,8 +118,8 @@ DATA 0xFFD01418 0x # DDR Operation # bit3-0: 0x0, DDR cmd # bit31-4: 0 required -DATA 0xFFD0141C 0x0642 # DDR Mode -DATA 0xFFD01420 0x0040 # DDR Extended Mode +DATA 0xFFD0141C 0x0652 # DDR Mode +DATA 0xFFD01420 0x0044 # DDR Extended Mode # bit0:0, DDR DLL enabled # bit1:0, DDR drive strenght normal # bit2:1, DDR ODT control lsd disabled @@ -140,6 +142,8 @@ DATA 0xFFD01424 0xF07F # DDR Controller Control High # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh # bit15-12: required # bit31-16: 0required +DATA 0xFFD01428 0x00074510 +DATA 0xFFD0147c 0x7451 DATA 0xFFD01500 0x # CS[0]n Base address to 0x0 DATA 0xFFD01504 0x07F1 # CS[0]n Size @@ -153,7 +157,7 @@ DATA 0xFFD0150C 0x # CS[1]n Size, window disabled DATA 0xFFD01514 0x # CS[2]n Size, window disabled DATA 0xFFD0151C 0x # CS[3]n Size, window disabled -DATA 0xFFD01494 0x # DDR ODT Control (Low) +DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low) # bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0 # bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0 @@ -162,7 +166,7 @@ DATA 0xFFD01498 0x # DDR ODT Control (High) # bit3-2: 00, ODT1 controlled by register # bit31-4: zero, required -DATA 0xFFD0149C 0xE90F # CPU ODT Control +DATA 0xFFD0149C 0xFC11 # CPU ODT Control # bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0 # bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0 # bit9-8: 1, ODTEn, never active -- 1.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lis
[U-Boot] [PATCH 17/20] ppc, arm: rework and enhance keymile-common.h
From: Holger Brunck
Add:
- introduce "bootrunner" environment variable
This allows to execute consecutive different commands
specified in the list "subbootcmd". If one command fails
the command serie will stop.
- introduce environment variable "develop", "ramfs" and "release"
Each variable is one way to boot our linux. "develop" is for
development purpose and boots the SW via NFS. "release" is for
booting the linux image from flash, "ramfs" allows to load an SW
image via tftp into ram and executes from there
- introduce "addmem" variable, this command adds the used memory
for linux to the bootargs
- introduce "addvar" variable, this command adress for the /var
directory to the kernel command line
- introduce "setramfspram" and "setrootfsaddr" these calculation
were done if "ramfs" was used (only for debugging)
- introduce "tftpramfs" used for "ramfs" to load the image into
RAM (only for debugging)
Remove unneeded stuff:
- CONFIG_IO_MUXING is obsolete for keymile boards
- CONFIG_KM_DEF_ENV_PRIVATE is also obsolete
- define CONFIG_SYS_TEXT_BASE in board configs only
Signed-off-by: Holger Brunck
cc: Wolfgang Denk
cc: Prafulla Wadaskar
cc: Valentin Longchamp
cc: Heiko Schocher
---
include/configs/keymile-common.h | 163 +++--
include/configs/km_arm.h |2 +
2 files changed, 138 insertions(+), 27 deletions(-)
diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h
index 142a6a1..a04c39e 100644
--- a/include/configs/keymile-common.h
+++ b/include/configs/keymile-common.h
@@ -40,13 +40,6 @@
#endif /* CONFIG_SYS_KWD_CONFIG */
/*
- * CONFIG_SYS_TEXT_BASE can be defined in board specific header file, if needed
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#defineCONFIG_SYS_TEXT_BASE0x0040
-#endif /* CONFIG_SYS_TEXT_BASE */
-
-/*
* Command line configuration.
*/
#include
@@ -144,28 +137,16 @@
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_CONCAT
-/* define this to use the keymile's io muxing feature */
-/*#define CONFIG_IO_MUXING */
-
-#ifdef CONFIG_IO_MUXING
-#defineCONFIG_KM_DEF_ENV_IOMUX \
- "nc=setenv ethact HDLC \0" \
- "nce=setenv ethact SCC \0" \
- "stderr=serial,nc \0" \
- "stdin=serial,nc \0" \
- "stdout=serial,nc \0" \
- "tftpsrcp=69 \0" \
- "tftpdstp=69 \0"
-#else
#defineCONFIG_KM_DEF_ENV_IOMUX \
"stderr=serial \0" \
"stdin=serial \0"\
"stdout=serial \0"
-#endif
-#ifndef CONFIG_KM_DEF_ENV_PRIVATE
-#defineCONFIG_KM_DEF_ENV_PRIVATE \
- "kmprivate=empty\0"
+/* common powerpc specific env settings */
+#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS
+#define CONFIG_KM_DEF_ENV_BOOTPARAMS \
+ "bootparams=empty\0"\
+ "initial_boot_bank=0\0"
#endif
#ifndef CONFIG_KM_DEF_NETDEV
@@ -184,17 +165,116 @@
#define str(s) #s
/*
+ * bootrunner
+ * - run all commands in 'subbootcmds'
+ * - on error, stop running the remaing commands
+ */
+#define CONFIG_KM_DEF_ENV_BOOTRUNNER \
+ "bootrunner=" \
+ "break=0; " \
+ "for subbootcmd in ${subbootcmds}; do " \
+ "if test ${break} -eq 0; then; "\
+ "echo \"[INFO] running \\c\"; " \
+ "print ${subbootcmd}; " \
+ "run ${subbootcmd} || break=1; "\
+ "if test ${break} -eq 1; then; "\
+ "echo \"[ERR] failed \\c\"; " \
+ "print ${subbootcmd}; " \
+ "fi; " \
+ "fi; " \
+ "done\0"\
+ ""
+
+/*
+ * boottargets
+ * - set 'subbootcmds' for the bootrunner
+ * - set 'bootcmd' and 'altbootcmd'
+ * available targets:
+ * - 'release': for a standalone systemkernel/rootfs from flash
+ * - 'develop': for developmentkernel(tftp)/rootfs(NFS)
+ * - 'ramfs': rootfilesystem in RAMkernel(tftp)/rootfs(RAM)
+ *
+ * - 'commonargs': bootargs common to all targets
+ */
+#define CONFIG_KM_DEF_ENV_BOOTTARGETS \
+ "commonargs=" \
+ "addip "\
+ "addtty " \
+ "addmem " \
+ "addinit " \
+ "addvar "
[U-Boot] [PATCH 10/20] km-arm: i2c support for suenx based boards
This patch renames the suen3 defines and functions to suenx
which is more generic and more precise, because these values
and functions where used by all suenX boards and not only sune3.
Signed-off-by: Lukas Roggli
Signed-off-by: Valentin Longchamp
Signed-off-by: Holger Brunck
Signed-off-by: Heiko Schocher
cc: Prafulla Wadaskar
---
board/keymile/km_arm/km_arm.c | 20 ++--
include/configs/km_arm.h | 18 +-
2 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 5c1e822..48a10c5 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -96,7 +96,7 @@ u32 kwmpp_config[] = {
MPP41_GPIO, /* Piggy3 LED[4] */
MPP42_GPIO, /* Piggy3 LED[5] */
MPP43_GPIO, /* Piggy3 LED[6] */
- MPP44_GPIO, /* Piggy3 LED[7] */
+ MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
MPP45_GPIO, /* Piggy3 LED[8] */
MPP46_GPIO, /* Reserved */
MPP47_GPIO, /* Reserved */
@@ -162,14 +162,14 @@ int board_early_init_f(void)
#if defined(CONFIG_SOFT_I2C)
/* init the GPIO for I2C Bitbang driver */
- kw_gpio_set_valid(SUEN3_SDA_PIN, 1);
- kw_gpio_set_valid(SUEN3_SCL_PIN, 1);
- kw_gpio_direction_output(SUEN3_SDA_PIN, 0);
- kw_gpio_direction_output(SUEN3_SCL_PIN, 0);
+ kw_gpio_set_valid(SUENx_SDA_PIN, 1);
+ kw_gpio_set_valid(SUENx_SCL_PIN, 1);
+ kw_gpio_direction_output(SUENx_SDA_PIN, 0);
+ kw_gpio_direction_output(SUENx_SCL_PIN, 0);
#endif
#if defined(CONFIG_SYS_EEPROM_WREN)
- kw_gpio_set_valid(SUEN3_ENV_WP, 38);
- kw_gpio_direction_output(SUEN3_ENV_WP, 1);
+ kw_gpio_set_valid(SUENx_ENV_WP, 38);
+ kw_gpio_direction_output(SUENx_ENV_WP, 1);
#endif
return 0;
@@ -322,15 +322,15 @@ int get_sda (void)
int get_scl (void)
{
- return (kw_gpio_get_value(SUEN3_SCL_PIN) ? 1 : 0);
+ return (kw_gpio_get_value(SUENx_SCL_PIN) ? 1 : 0);
}
#endif
#if defined(CONFIG_SYS_EEPROM_WREN)
int eeprom_write_enable (unsigned dev_addr, int state)
{
- kw_gpio_set_value(SUEN3_ENV_WP, !state);
+ kw_gpio_set_value(SUENx_ENV_WP, !state);
- return !kw_gpio_get_value(SUEN3_ENV_WP);
+ return !kw_gpio_get_value(SUENx_ENV_WP);
}
#endif
diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h
index c1a0feb..2c13cae 100644
--- a/include/configs/km_arm.h
+++ b/include/configs/km_arm.h
@@ -176,15 +176,15 @@ void set_sda (int state);
void set_scl (int state);
int get_sda (void);
int get_scl (void);
-#define SUEN3_SDA_PIN 8
-#define SUEN3_SCL_PIN 9
-#define SUEN3_ENV_WP 38
-
-#define I2C_ACTIVE __set_direction(SUEN3_SDA_PIN, 0)
-#define I2C_TRISTATE __set_direction(SUEN3_SDA_PIN, 1)
-#define I2C_READ (kw_gpio_get_value(SUEN3_SDA_PIN) ? 1 : 0)
-#define I2C_SDA(bit) kw_gpio_set_value(SUEN3_SDA_PIN, bit);
-#define I2C_SCL(bit) kw_gpio_set_value(SUEN3_SCL_PIN, bit);
+#define SUENx_SDA_PIN 8
+#define SUENx_SCL_PIN 9
+#define SUENx_ENV_WP 38
+
+#define I2C_ACTIVE __set_direction(SUENx_SDA_PIN, 0)
+#define I2C_TRISTATE __set_direction(SUENx_SDA_PIN, 1)
+#define I2C_READ (kw_gpio_get_value(SUENx_SDA_PIN) ? 1 : 0)
+#define I2C_SDA(bit) kw_gpio_set_value(SUENx_SDA_PIN, bit);
+#define I2C_SCL(bit) kw_gpio_set_value(SUENx_SCL_PIN, bit);
#endif
#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */
--
1.7.4
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[U-Boot] [PATCH 0/20] keymile board update
The following patchset updates the support for the keymile
boards.
- heavy rework of the headerfiles, common board code
- add support for 4 new mpc83xx based boards
- add support for 1 82xx based board
- add support for 2 new kirkwood based boards
- fix i2c deblocking for this boards
Patch overview:
Heiko Schocher (15):
keymile: rework headerfiles for keymile boards
mpc832x: add support for the mpc8321 based suvd3 board
mpc832x: add support for mpc8321 based tuxa1 board
mpc832x: add support for mpc8321 based tuda1 board
arm: add support for kirkwood based mgcoge2un board
arm: add support of Kirkwood based board SUEN8
ppc: add support for ppc based board mgcoge2ne
powerpc, 83xx: add kmsupx5 board support
km-arm: i2c support for suenx based boards
km_arm: change some register values for SDRAM initialization
ppc, 8321: cleanup tuxa1, tuda1 and suvd3 support
keymile, common; fix i2c deblocking support
arm, keymile: updates for the arm based boards from keymile
keymile boards: add CONFIG_PIGGY_MAC_ADRESS_OFFSET
keymile, common: add setting of some environment variables
Holger Brunck (2):
ppc, arm: rework and enhance keymile-common.h
keymile-common.h: remove IO mux stuff
Huber, Andreas (1):
ppc, mgcoge, mgcoge2ne: add DIP switch detection
Thomas Herzmann (1):
keymile boards: support of boardId / hwkey lists
Thomas Reufer (1):
keymile, 8321 boards: move common definitions to km8321-common.h
MAINTAINERS|7 +
arch/powerpc/cpu/mpc83xx/fdt.c |3 +-
arch/powerpc/lib/bootcount.c |2 +-
board/keymile/common/common.c | 179 ++--
board/keymile/common/common.h |5 +
board/keymile/{kmeter1 => km83xx}/Makefile |0
.../keymile/{kmeter1/kmeter1.c => km83xx/km83xx.c} | 101 -
board/keymile/km_arm/km_arm.c | 70 +++-
board/keymile/km_arm/kwbimage.cfg | 32 +-
board/keymile/mgcoge/mgcoge.c | 34 ++-
boards.cfg |9 +-
include/configs/keymile-common.h | 465 ++--
include/configs/km-powerpc.h | 92
include/configs/km82xx-common.h| 321 ++
include/configs/km8321-common.h| 140 ++
include/configs/km83xx-common.h| 325 ++
include/configs/km_arm.h | 97 -
include/configs/kmeter1.h | 344 ++-
include/configs/kmsupx5.h | 89
include/configs/mgcoge.h | 296 +
include/configs/mgcoge2ne.h| 63 +++
include/configs/mgcoge2un.h| 62 +++
include/configs/suen3.h| 45 +--
include/configs/suen8.h| 61 +++
include/configs/suvd3.h| 104 +
include/configs/tuda1.h| 141 ++
include/configs/tuxa1.h| 124 ++
post/lib_powerpc/fpu/Makefile | 33 --
28 files changed, 2313 insertions(+), 931 deletions(-)
rename board/keymile/{kmeter1 => km83xx}/Makefile (100%)
rename board/keymile/{kmeter1/kmeter1.c => km83xx/km83xx.c} (64%)
create mode 100644 include/configs/km-powerpc.h
create mode 100644 include/configs/km82xx-common.h
create mode 100644 include/configs/km8321-common.h
create mode 100644 include/configs/km83xx-common.h
create mode 100644 include/configs/kmsupx5.h
create mode 100644 include/configs/mgcoge2ne.h
create mode 100644 include/configs/mgcoge2un.h
create mode 100644 include/configs/suen8.h
create mode 100644 include/configs/suvd3.h
create mode 100644 include/configs/tuda1.h
create mode 100644 include/configs/tuxa1.h
delete mode 100644 post/lib_powerpc/fpu/Makefile
cc: Holger Brunck
cc: Heiko Schocher
cc: Kim Phillips
cc: Wolfgang Denk
cc: Detlev Zundel
cc: Prafulla Wadaskar
cc: Valentin Longchamp
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[U-Boot] [PATCH 14/20] arm, keymile: updates for the arm based boards from keymile
define KM_IVM_BUS and KM_ENV_BUS macros
KM_IVM_BUS is used to define the EEprom_ivm environment variable.
These macros allow the reuse of these I2C addresses in other code
locations.
remove unneeded code
On first HW versions the BOCO FPGA was behind a MUX device. These
HW versions are not supported anymore. And therefore this code can
be removed.
added LED initialization for SUEN3
The bootstat LED required to be initialized so to have a green
colour after start-up.
define CONFIG_SYS_TEXT_BASE
This is needed by the relocation code and is not the same for
our ARM BEC and thus needs to be defined.
remove memsize variable
An environment variable for memsize is not needed.
this can be get via the board info struct.
remove unneeded double access to bi_dram[i].size field
Signed-off-by: Valentin Longchamp
Signed-off-by: Holger Brunck
Signed-off-by: Luca Haab
Signed-off-by: Heiko Schocher
cc: Prafulla Wadaskar
---
board/keymile/km_arm/km_arm.c | 37 +
include/configs/km_arm.h |1 +
include/configs/mgcoge2un.h |6 --
include/configs/suen3.h |6 --
include/configs/suen8.h |6 --
5 files changed, 42 insertions(+), 14 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 48a10c5..3dc63ea 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -41,9 +41,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static int io_dev;
-extern I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf);
-
/* Multi-Purpose Pins Functionality configuration */
u32 kwmpp_config[] = {
MPP0_NF_IO2,
@@ -120,15 +117,37 @@ int ethernet_present(void)
return ret;
}
+int initialize_unit_leds(void)
+{
+ /* init the unit LEDs */
+ /* per default they all are */
+ /* ok apart from bootstat */
+ /* LED connected through BOCO */
+ /* BOCO lies at the address 0x10 */
+ /* LEDs are in the block CTRL_H (addr 0x02) */
+ /* BOOTSTAT LED is the first 0x01 */
+ #define BOCO0x10
+ #define CTRL_H 0x02
+ #define APPLEDMASK 0x01
+ uchar buf;
+
+ if (i2c_read(BOCO, CTRL_H, 1, &buf, 1) != 0) {
+ printf("%s: Error reading Boco\n", __FUNCTION__);
+ return -1;
+ }
+ buf |= APPLEDMASK;
+ if (i2c_write(BOCO, CTRL_H, 1, &buf, 1) != 0) {
+ printf("%s: Error writing Boco\n", __FUNCTION__);
+ return -1;
+ }
+ return 0;
+}
+
int misc_init_r(void)
{
- I2C_MUX_DEVICE *i2cdev;
char *str;
int mach_type;
- /* add I2C Bus for I/O Expander */
- i2cdev = i2c_mux_ident_muxstring((uchar *)"pca9554a:70:a");
- io_dev = i2cdev->busid;
puts("Piggy:");
if (ethernet_present() == 0)
puts (" not");
@@ -140,6 +159,9 @@ int misc_init_r(void)
printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
gd->bd->bi_arch_number = mach_type;
}
+
+ initialize_unit_leds();
+
return 0;
}
@@ -246,7 +268,6 @@ void dram_init_banksize(void)
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = kw_sdram_bar(i);
- gd->bd->bi_dram[i].size = kw_sdram_bs(i);
gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
kw_sdram_bs(i));
}
diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h
index 2c13cae..578438e 100644
--- a/include/configs/km_arm.h
+++ b/include/configs/km_arm.h
@@ -46,6 +46,7 @@
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
+#define CONFIG_SYS_TEXT_BASE 0x0400 /* code address after reloc */
#define CONFIG_ENV_SIZE(128 << 10) /* NAND chip block size
*/
#define CONFIG_SYS_MEMTEST_START 0x0040/* 4M */
#define CONFIG_SYS_MEMTEST_END 0x007f /*(_8M -1) */
diff --git a/include/configs/mgcoge2un.h b/include/configs/mgcoge2un.h
index 1f2b23f..3dc4665 100644
--- a/include/configs/mgcoge2un.h
+++ b/include/configs/mgcoge2un.h
@@ -41,12 +41,14 @@
#define CONFIG_HOSTNAMEmgcoge2un
+#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/
+#define KM_ENV_BUS "pca9547:70:d" /* I2C2 (Mux-Port 5)*/
+
/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_DEF_ENV \
- "memsize=0x800\0" \
"newenv=setenv addr 0x10 && " \
"i2c dev 1; mw.b ${addr} 0 4 && " \
"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR)\
@@ -54,7 +56,7 @@
"eeprom write " xstr(CONFIG_SYS_DEF
[U-Boot] [PATCH 20/20] ppc, mgcoge, mgcoge2ne: add DIP switch detection
From: Huber, Andreas
This reads the DIP switch register in the BFTICU (0x4089). If 'Full reset'
or 'DB erase' is selected, 'actual_bank' is set to 0. This loads the Bootloader
application who does the erase stuff.
Signed-off-by: Andreas Huber
Signed-off-by: Holger Brunck
cc: Wolfgang Denk
cc: Valentin Longchamp
cc: Heiko Schocher
---
board/keymile/mgcoge/mgcoge.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c
index e932633..dabbec4 100644
--- a/board/keymile/mgcoge/mgcoge.c
+++ b/board/keymile/mgcoge/mgcoge.c
@@ -317,8 +317,21 @@ unsigned int arch_ram_size(void)
return gd->bd->bi_memsize;
}
+#define DIPSWITCH_OFFSET 0x89
+#define DIPSWITCH_MASK 0x0f
+
int last_stage_init(void)
{
+ u8 dip_switch;
+ /* Dip switch */
+ dip_switch = readb(CONFIG_SYS_FPGA_BASE + DIPSWITCH_OFFSET);
+ dip_switch &= DIPSWITCH_MASK;
+ /* dip switch 'full reset' or 'db erase' */
+ if (dip_switch & 0x1 || dip_switch & 0x2) {
+ /* start bootloader */
+ puts("DIP: Enabled\n");
+ setenv("actual_bank", "0");
+ }
set_km_env();
return 0;
}
--
1.7.4
___
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[U-Boot] [PATCH 04/20] mpc832x: add support for mpc8321 based tuda1 board
This board is similar to suvd3 board. So most initialisation topics are taken from suvd3 (UART1, Ethernet, piggy PHY, flash, ram) only the application specific chip selects differ. Signed-off-by: Lukas Roggli Signed-off-by: Holger Brunck Signed-off-by: Heiko Schocher cc: Kim Phillips cc: Valentin Longchamp --- MAINTAINERS |1 + boards.cfg |1 + include/configs/tuda1.h | 251 +++ 3 files changed, 253 insertions(+), 0 deletions(-) create mode 100644 include/configs/tuda1.h diff --git a/MAINTAINERS b/MAINTAINERS index 801e4dd..cbc34af 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -434,6 +434,7 @@ Heiko Schocher sc3 PPC405GP suen3 ARM926EJS (Kirkwood SoC) suvd3 MPC8321 + tuda1 MPC8321 tuxa1 MPC8321 uc101 MPC5200 ve8313 MPC8313 diff --git a/boards.cfg b/boards.cfg index ed5e0e7..b3a4e9e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -476,6 +476,7 @@ SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon- SIMPC8313:NAND_SP suvd3powerpc mpc83xx km83xx keymile TQM834x powerpc mpc83xx tqm834x tqc +tuda1powerpc mpc83xx km83xx keymile tuxa1powerpc mpc83xx km83xx keymile sbc8540 powerpc mpc85xx sbc8560 - - SBC8540 sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540 diff --git a/include/configs/tuda1.h b/include/configs/tuda1.h new file mode 100644 index 000..1583614 --- /dev/null +++ b/include/configs/tuda1.h @@ -0,0 +1,251 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + *Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + *Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + *Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, h...@denx.de. + * + * (C) Copyright 2010 + * Lukas Roggli, KEYMILE Ltd, lukas.rog...@keymile.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E3001 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC832x 1 /* MPC832x CPU specific */ +#define CONFIG_TUDA1 1 /* TUDA1 board specific */ +#define CONFIG_HOSTNAMEtuda1 +#define CONFIG_KM_BOARD_NAME "tuda1" + +#defineCONFIG_SYS_TEXT_BASE0xF000 +#define CONFIG_KM_DEF_NETDEV \ + "netdev=eth0\0" + +#define CONFIG_KM_DEF_ROOTPATH \ + "rootpath=/opt/eldk/ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +#define CONFIG_MISC_INIT_R 1 + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH 0x0006 +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X0100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDR_CS0_BNDS0x007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_2T_EN | \ + SDRAM_CFG_SREN) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ +(0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ +
[U-Boot] [PATCH 13/20] keymile, common; fix i2c deblocking support
This patch fix the i2c deblocking facility with the i2c HW-Controller.
The required delays for byte reading, the enhanced criteria for stop
the dummy read and required 5 start/stop sequences are added.
Add i2c deblocking before ivm eeprom read.
Improve i2c deblocking sequence by respecting stop hold time.
Cleaned function for deblocking. Have now one function i2c_make_abort()
available for bitbang, mpc82xx and mpc83xx harware controller.
Signed-off-by: Stefan Bigler
Signed-off-by: Holger Brunck
Signed-off-by: Heiko Schocher
cc: Valentin Longchamp
---
board/keymile/common/common.c | 109 ++---
1 files changed, 80 insertions(+), 29 deletions(-)
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index 5b54e35..03d63c1 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -41,6 +41,7 @@
#include
extern int i2c_soft_read_pin (void);
+extern int i2c_make_abort (void);
int ivm_calc_crc (unsigned char *buf, int len)
{
@@ -325,6 +326,9 @@ int ivm_read_eeprom (void)
if (buf != NULL)
dev_addr = simple_strtoul ((char *)buf, NULL, 16);
+ /* add deblocking here */
+ i2c_make_abort();
+
if (i2c_read(dev_addr, 0, 1, i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN)
!= 0) {
printf ("Error reading EEprom\n");
return -2;
@@ -334,7 +338,7 @@ int ivm_read_eeprom (void)
}
#if defined(CONFIG_SYS_I2C_INIT_BOARD)
-#define DELAY_ABORT_SEQ62
+#define DELAY_ABORT_SEQ62 /* @200kHz 9 clocks = 44us, 62us is
ok */
#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))
#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGCOGE2NE)
@@ -445,8 +449,21 @@ static void writeStartSeq (void)
This I2C Deblocking mechanism was developed by Keymile in association
with Anatech and Atmel in 1998.
*/
-static int i2c_make_abort (void)
+int i2c_make_abort (void)
{
+
+#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_MACH_SUEN3)
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
+ volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
+
+ /* disable I2C controller first, otherwhise it thinks we want to*/
+ /* talk to the slave port...*/
+ i2c->i2c_i2mod &= ~0x01;
+
+ /* Set the PortPins to GPIO */
+ setports (1);
+#endif
+
int scl_state = 0;
int sda_state = 0;
int i = 0;
@@ -473,54 +490,88 @@ static int i2c_make_abort (void)
writeStartSeq ();
}
}
+
+ /* respect stop setup time */
+ udelay (DELAY_ABORT_SEQ);
+ set_scl(1);
+ udelay (DELAY_ABORT_SEQ);
+ set_sda(1);
get_sda ();
+
+#if defined(CONFIG_HARD_I2C)
+ /* Set the PortPins back to use for I2C */
+ setports (0);
+#endif
return ret;
}
#endif
-/**
- * i2c_init_board - reset i2c bus. When the board is powercycled during a
- * bus transfer it might hang; for details see doc/I2C_Edge_Conditions.
- */
-void i2c_init_board(void)
-{
#if defined(CONFIG_MPC83xx)
+static void writeStartSeq (void)
+{
+ struct fsl_i2c *dev;
+ dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
+ udelay(DELAY_ABORT_SEQ);
+ out_8 (&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+ udelay(DELAY_ABORT_SEQ);
+ out_8 (&dev->cr, (I2C_CR_MEN));
+}
+
+int i2c_make_abort (void)
+{
struct fsl_i2c *dev;
dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
uchar dummy;
+ uchar last;
+ int nbr_read = 0;
+ int i = 0;
+ int ret = 0;
+ /* wait after each operation to finsh with a delay */
out_8 (&dev->cr, (I2C_CR_MSTA));
+ udelay(DELAY_ABORT_SEQ);
out_8 (&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+ udelay(DELAY_ABORT_SEQ);
dummy = in_8(&dev->dr);
- dummy = in_8(&dev->dr);
- if (dummy != 0xff) {
- dummy = in_8(&dev->dr);
+ udelay(DELAY_ABORT_SEQ);
+ last = in_8(&dev->dr);
+ nbr_read++;
+
+ /* do read until the last bit is 1, but stop if the full eeprom is read
*/
+ while (((last & 0x01) != 0x01) && (nbr_read <
CONFIG_SYS_IVM_EEPROM_MAX_LEN)) {
+ udelay(DELAY_ABORT_SEQ);
+ last = in_8(&dev->dr);
+ nbr_read++;
}
+ if ((last & 0x01) != 0x01)
+ ret = -2;
+ if ((last != 0xff) || (nbr_read > 1))
+ printf("[INFO] i2c abort after %d bytes (0x%02x)\n", nbr_read,
last);
+ udelay(DELAY_ABORT_SEQ);
out_8 (&dev->cr, (I2C_CR_MEN));
- out_8 (&dev->cr, 0x00);
- out_8 (&dev->cr, (I2C_CR_MEN));
+ udelay(DELAY_ABORT_SEQ);
+ /* clear status reg */
+ out_8 (&dev->sr, 0);
-#else
-#if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD)
-
[U-Boot] [PATCH 02/20] mpc832x: add support for the mpc8321 based suvd3 board
- serial console on UART1
- Ethernet RMII over UCC4
- PHY SMSC LAN8700
- 64MB Flash
- 128 MB DDR2 RAM
- I2C
- bootcount
This board is similiar to the kmeter1 (8360) board,
so common config options are extracted into the
include/configs/km83xx-common.h file.
Signed-off-by: Heiko Schocher
cc: Kim Phillips
cc: Holger Brunck
cc: Valentin Longchamp
---
MAINTAINERS |1 +
arch/powerpc/cpu/mpc83xx/fdt.c |3 +-
arch/powerpc/lib/bootcount.c|2 +-
board/keymile/common/common.c |9 +-
board/keymile/km83xx/Makefile | 53 +++
board/keymile/km83xx/km83xx.c | 271
board/keymile/kmeter1/Makefile | 53 ---
board/keymile/kmeter1/kmeter1.c | 217 --
boards.cfg |3 +-
include/configs/km83xx-common.h | 325 ++
include/configs/kmeter1.h | 326 +++
include/configs/suvd3.h | 217 ++
post/lib_powerpc/fpu/Makefile | 33
13 files changed, 896 insertions(+), 617 deletions(-)
create mode 100644 board/keymile/km83xx/Makefile
create mode 100644 board/keymile/km83xx/km83xx.c
delete mode 100644 board/keymile/kmeter1/Makefile
delete mode 100644 board/keymile/kmeter1/kmeter1.c
create mode 100644 include/configs/km83xx-common.h
create mode 100644 include/configs/suvd3.h
delete mode 100644 post/lib_powerpc/fpu/Makefile
diff --git a/MAINTAINERS b/MAINTAINERS
index 4756f14..75b7343 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -433,6 +433,7 @@ Heiko Schocher
municse MPC5200
sc3 PPC405GP
suen3 ARM926EJS (Kirkwood SoC)
+ suvd3 MPC8321
uc101 MPC5200
ve8313 MPC8313
diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c
index daf73a6..482aa7a 100644
--- a/arch/powerpc/cpu/mpc83xx/fdt.c
+++ b/arch/powerpc/cpu/mpc83xx/fdt.c
@@ -32,7 +32,8 @@ extern void ft_qe_setup(void *blob);
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_BOOTCOUNT_LIMIT) && defined(CONFIG_MPC8360)
+#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
+(defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x))
#include
void fdt_fixup_muram (void *blob)
diff --git a/arch/powerpc/lib/bootcount.c b/arch/powerpc/lib/bootcount.c
index 07ef28d..d833165 100644
--- a/arch/powerpc/lib/bootcount.c
+++ b/arch/powerpc/lib/bootcount.c
@@ -51,7 +51,7 @@
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR)
#endif /* defined(CONFIG_MPC8260) */
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
#include
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x11 + \
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index 86be9c2..f0b99ed 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
@@ -424,7 +425,7 @@ static int get_scl (void)
}
#endif
-#if !defined(CONFIG_KMETER1)
+#if !defined(CONFIG_MPC83xx)
static void writeStartSeq (void)
{
set_sda (1);
@@ -483,7 +484,7 @@ static int i2c_make_abort (void)
*/
void i2c_init_board(void)
{
-#if defined(CONFIG_KMETER1)
+#if defined(CONFIG_MPC83xx)
struct fsl_i2c *dev;
dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
uchar dummy;
@@ -591,7 +592,7 @@ int board_eth_init (bd_t *bis)
(void)keymile_hdlc_enet_initialize (bis);
#endif
if (ethernet_present ()) {
- return -1;
+ return cpu_eth_init(bis);
}
- return 0;
+ return -1;
}
diff --git a/board/keymile/km83xx/Makefile b/board/keymile/km83xx/Makefile
new file mode 100644
index 000..2fa84f3
--- /dev/null
+++ b/board/keymile/km83xx/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+
[U-Boot] [PATCH 01/20] keymile: rework headerfiles for keymile boards
- This patch reworks all headerfiles for keymile boards (coge, supx4,
eter1, suen3).
Furthermore, a refactoring on the whole environment variables has been
acomplished.
- Environment variables:
- grouped into logical blocks (#defines) based on the functionality/purpose
- short description for most of the variables
- as much as possible is moved into the common headerfiles
- keymile powerpc specific config settings are moved to km-powerpc.h
- Keep the kernel command line clean from KM 'specialities'.
The boardId and hwKey is no longer needed as kernel arguments.
They are stored in the U-Boot environment and read out from userspace
later with the help of fw_printenv or equivalent tools.
- km8xx: default environment partitioning corrected
- km_arm: MACH_TYPE changed to MACH_TYPE_KM_KIRKWOOD
Signed-off-by: Andreas Huber
Signed-off-by: Holger Brunck
Signed-off-by: Heiko Schocher
cc: Kim Phillips
cc: Wolfgang Denk
---
board/keymile/common/common.c|4 +-
board/keymile/km_arm/km_arm.c|2 +-
include/configs/keymile-common.h | 275 ++
include/configs/km-powerpc.h | 92 +
include/configs/km_arm.h | 30 -
include/configs/kmeter1.h| 40 +++---
include/configs/mgcoge.h | 38 +++---
7 files changed, 316 insertions(+), 165 deletions(-)
create mode 100644 include/configs/km-powerpc.h
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index 7b4eefd..86be9c2 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -500,7 +500,7 @@ void i2c_init_board(void)
out_8 (&dev->cr, (I2C_CR_MEN));
#else
-#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_MACH_SUEN3)
+#if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
@@ -578,7 +578,7 @@ int fdt_get_node_and_value (void *blob,
}
#endif
-#if !defined(CONFIG_MACH_SUEN3)
+#if !defined(MACH_TYPE_KM_KIRKWOOD)
int ethernet_present (void)
{
return (in_8((u8 *)CONFIG_SYS_PIGGY_BASE + CONFIG_SYS_SLOT_ID_OFF) &
0x80);
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 2e20644..5c1e822 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -180,7 +180,7 @@ int board_init(void)
/*
* arch number of board
*/
- gd->bd->bi_arch_number = MACH_TYPE_SUEN3;
+ gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
/* address of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h
index e3bd264..c6a1432 100644
--- a/include/configs/keymile-common.h
+++ b/include/configs/keymile-common.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2008
+ * (C) Copyright 2008-2010
* Heiko Schocher, DENX Software Engineering, h...@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -25,9 +25,7 @@
#define __CONFIG_KEYMILE_H
/* Do boardspecific init for all boards */
-#define CONFIG_BOARD_EARLY_INIT_R 1
-
-#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOARD_EARLY_INIT_R 1
/*
* By default kwbimage.cfg from board specific folder is used
@@ -56,16 +54,15 @@
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
-#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
-#define CONFIG_JFFS2_CMDLINE
#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_SETEXPR
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
/*
@@ -78,25 +75,21 @@
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */
#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE /* Boot
Argument Buffer Size */
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history
*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
+#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-
[U-Boot] [PATCH 19/20] keymile-common.h: remove IO mux stuff
From: Holger Brunck
Signed-off-by: Holger Brunck
cc: Wolfgang Denk
cc: Valentin Longchamp
cc: Heiko Schocher
---
include/configs/keymile-common.h |9 +++--
1 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h
index ed24072..93e3ddc 100644
--- a/include/configs/keymile-common.h
+++ b/include/configs/keymile-common.h
@@ -137,11 +137,6 @@
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_CONCAT
-#defineCONFIG_KM_DEF_ENV_IOMUX \
- "stderr=serial \0" \
- "stdin=serial \0"\
- "stdout=serial \0"
-
/* common powerpc specific env settings */
#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS
#define CONFIG_KM_DEF_ENV_BOOTPARAMS \
@@ -428,7 +423,6 @@
#ifndef CONFIG_KM_DEF_ENV
#define CONFIG_KM_DEF_ENV \
CONFIG_KM_DEF_ENV_BOOTPARAMS\
- CONFIG_KM_DEF_ENV_IOMUX \
CONFIG_KM_DEF_NETDEV\
CONFIG_KM_DEF_ENV_CPU \
CONFIG_KM_DEF_ENV_BOOTRUNNER\
@@ -448,6 +442,9 @@
"load=tftpboot ${u-boot_addr_r} ${u-boot}\0"\
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
+"stderr=serial \0" \
+"stdin=serial \0" \
+"stdout=serial \0" \
"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin \0"\
"u-boot_addr_r=" xstr(CONFIG_KM_KERNEL_ADDR) "\0" \
""
--
1.7.4
___
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[U-Boot] [PATCH 03/20] mpc832x: add support for mpc8321 based tuxa1 board
This board is similar to suvd3 board. So most initialisation topics are taken from suvd3 (UART1, Ethernet, piggy PHY, flash, ram) only the application specific chip selects differ. Signed-off-by: Lukas Roggli Signed-off-by: Holger Brunck Signed-off-by: Heiko Schocher cc: Kim Phillips cc: Valentin Longchamp --- MAINTAINERS |1 + boards.cfg |1 + include/configs/tuxa1.h | 236 +++ 3 files changed, 238 insertions(+), 0 deletions(-) create mode 100644 include/configs/tuxa1.h diff --git a/MAINTAINERS b/MAINTAINERS index 75b7343..801e4dd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -434,6 +434,7 @@ Heiko Schocher sc3 PPC405GP suen3 ARM926EJS (Kirkwood SoC) suvd3 MPC8321 + tuxa1 MPC8321 uc101 MPC5200 ve8313 MPC8313 diff --git a/boards.cfg b/boards.cfg index dc583ba..ed5e0e7 100644 --- a/boards.cfg +++ b/boards.cfg @@ -476,6 +476,7 @@ SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon- SIMPC8313:NAND_SP suvd3powerpc mpc83xx km83xx keymile TQM834x powerpc mpc83xx tqm834x tqc +tuxa1powerpc mpc83xx km83xx keymile sbc8540 powerpc mpc85xx sbc8560 - - SBC8540 sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540 sbc8540_66 powerpc mpc85xx sbc8560 - - SBC8540 diff --git a/include/configs/tuxa1.h b/include/configs/tuxa1.h new file mode 100644 index 000..44e12f3 --- /dev/null +++ b/include/configs/tuxa1.h @@ -0,0 +1,236 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + *Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + *Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + *Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, h...@denx.de. + * + * (C) Copyright 2010 + * Yan Bin, Lukas Roggli, KEYMILE Ltd, lukas.rog...@keymile.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E3001 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC832x 1 /* MPC832x CPU specific */ +#define CONFIG_TUXA1 1 /* TUXA1 board specific */ +#define CONFIG_HOSTNAMEtuxa1 +#define CONFIG_KM_BOARD_NAME "tuxa1" + +#defineCONFIG_SYS_TEXT_BASE0xF000 +#define CONFIG_KM_DEF_NETDEV \ + "netdev=eth0\0" + +#define CONFIG_KM_DEF_ROOTPATH \ + "rootpath=/opt/eldk/ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +#define CONFIG_MISC_INIT_R 1 + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH 0x0006 +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3 ) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X0100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL ) + +#define CONFIG_SYS_DDR_CS0_BNDS0x007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_2T_EN | \ + SDRAM_CFG_SREN) +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ +(0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ +
[U-Boot] [PATCH 16/20] keymile, common: add setting of some environment variables
This patch adds last_stage_init to all keymile boards. And
in the last stage init some environment variables for u-boot
were set. Currently these are pnvramaddr, pram and var address.
Signed-off-by: Holger Brunck
Signed-off-by: Heiko Schocher
cc: Valentin Longchamp
cc: Wolfgang Denk
cc: Kim Phillips
---
board/keymile/common/common.c| 35 +++
board/keymile/common/common.h|1 +
board/keymile/km83xx/km83xx.c| 13 +
board/keymile/km_arm/km_arm.c| 11 +++
board/keymile/mgcoge/mgcoge.c| 13 +
include/configs/keymile-common.h |3 +++
include/configs/km_arm.h |5 +
7 files changed, 81 insertions(+), 0 deletions(-)
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index 6136884..25c4539 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -42,6 +42,7 @@
extern int i2c_soft_read_pin (void);
extern int i2c_make_abort (void);
+extern unsigned int arch_ram_size(void);
int ivm_calc_crc (unsigned char *buf, int len)
{
@@ -73,6 +74,40 @@ int ivm_calc_crc (unsigned char *buf, int len)
return crc;
}
+/* Set Keymile specific environment variables
+ * Currently only some memory layout variables are calculated here
+ * ...
+ * ... |@rootfsaddr |@pnvramaddr |@varaddr |@reserved |@END_OF_RAM
+ * ... |<--- pram --->|
+ * ...
+ * @END_OF_RAM: denotes the RAM size
+ * @pnvramaddr: Startadress of pseudo non volatile RAM in hex
+ * @pram : preserved ram size in k
+ * @varaddr : startadress for /var mounted into RAM
+ */
+int set_km_env(void)
+{
+ uchar buf[32];
+ unsigned int pnvramaddr;
+ unsigned int pram;
+ unsigned int varaddr;
+
+ pnvramaddr = arch_ram_size() - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM
+ - CONFIG_KM_PNVRAM;
+ sprintf ((char *)buf, "0x%x", pnvramaddr);
+ setenv ("pnvramaddr", (char *)buf);
+
+ pram = (CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM + CONFIG_KM_PNVRAM) /
+ 0x400;
+ sprintf ((char *)buf, "0x%x", pram);
+ setenv ("pram", (char *)buf);
+
+ varaddr = arch_ram_size() - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM;
+ sprintf ((char *)buf, "0x%x", varaddr);
+ setenv ("varaddr", (char *)buf);
+ return 0;
+}
+
static int ivm_set_value (char *name, char *value)
{
char tempbuf[256];
diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h
index 8fd3125..acf19af 100644
--- a/board/keymile/common/common.h
+++ b/board/keymile/common/common.h
@@ -22,6 +22,7 @@ int ivm_read_eeprom (void);
int keymile_hdlc_enet_initialize (bd_t *bis);
#endif
+int set_km_env(void);
int fdt_set_node_and_value (void *blob,
char *nodename,
char *regname,
diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index c625b5d..1ee5ee0 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -30,6 +30,8 @@
#include "../common/common.h"
+DECLARE_GLOBAL_DATA_PTR;
+
extern void disable_addr_trans (void);
extern void enable_addr_trans (void);
const qe_iop_conf_t qe_iop_conf_tab[] = {
@@ -177,6 +179,17 @@ int misc_init_r (void)
return 0;
}
+unsigned int arch_ram_size(void)
+{
+ return gd->bd->bi_memsize;
+}
+
+int last_stage_init(void)
+{
+ set_km_env();
+ return 0;
+}
+
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 3dc63ea..1b5426a 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -210,6 +210,12 @@ int board_init(void)
return 0;
}
+int last_stage_init(void)
+{
+ set_km_env();
+ return 0;
+}
+
#if defined(CONFIG_CMD_SF)
int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@@ -273,6 +279,11 @@ void dram_init_banksize(void)
}
}
+unsigned int arch_ram_size(void)
+{
+ return gd->ram_size;
+}
+
/* Configure and enable MV88E1118 PHY */
void reset_phy(void)
{
diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c
index 44dc7a5..e932633 100644
--- a/board/keymile/mgcoge/mgcoge.c
+++ b/board/keymile/mgcoge/mgcoge.c
@@ -37,6 +37,8 @@
#include "../common/common.h"
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* I/O Port configuration table
*
@@ -310,6 +312,17 @@ int board_early_init_r (void)
return 0;
}
+unsigned int arch_ram_size(void)
+{
+ return gd->bd->bi_memsize;
+}
+
+int last_stage_init(void)
+{
+ set_km_env();
+ return 0;
+}
+
int hush_init_var (void)
{
ivm_read_eeprom ();
diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h
index 33f2af2..142a6a1 10
[U-Boot] [PATCH 08/20] keymile, 8321 boards: move common definitions to km8321-common.h
From: Thomas Reufer First step for a cleanup of all header files for km8321 boards. Signed-off-by: Thomas Reufer cc: Wolfgang Denk cc: Kim Phillips cc: Valentin Longchamp cc: Holger Brunck cc: Heiko Schocher --- include/configs/km8321-common.h | 143 +++ 1 files changed, 143 insertions(+), 0 deletions(-) create mode 100644 include/configs/km8321-common.h diff --git a/include/configs/km8321-common.h b/include/configs/km8321-common.h new file mode 100644 index 000..a60ee34 --- /dev/null +++ b/include/configs/km8321-common.h @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + *Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + *Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + *Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, h...@denx.de. + * + * (C) Copyright 2010 + * Lukas Roggli, KEYMILE Ltd, lukas.rog...@keymile.com + * + * (C) Copyright 2010 + * Thomas Reufer, KEYMILE Ltd, thomas.reu...@keymile.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_KM8321_COMMON_H +#define __CONFIG_KM8321_COMMON_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E3001 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC832x 1 /* MPC832x CPU specific */ +#define CONFIG_KM8321 1 /* Keymile PBEC8321 board specific */ + +#define CONFIG_KM_DEF_NETDEV \ + "netdev=eth0\0" + +#define CONFIG_KM_DEF_ROOTPATH \ + "rootpath=/opt/eldk/ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +#define CONFIG_MISC_INIT_R 1 + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH 0x0006 +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X0100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDR_CS0_BNDS0x007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ +(0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE0x47860252 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ +(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ +(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ +(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ +(0 << TIMING_CFG0_WWT_SHIFT) | \ +(0 << TIMING_CFG0_RRT_SHIFT) | \ +(0 << TIMING_CFG0_WRT_SHIFT) | \ +(0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1((TIMING_CFG1_CASLAT_50) | \ +(2 << TIMING_CFG1_WRTORD_SHIFT) | \ +(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ +(2 << TIMING_CFG1_WRREC_SHIFT) | \ +(6 << TIMING_CFG1_REFREC_SHIFT) | \ +(2 << TIMING_CFG1_ACTTORW_SHIFT) | \ +(6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ +(2 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ +(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ +
[U-Boot] [PATCH 07/20] ppc: add support for ppc based board mgcoge2ne
The mgcoge2 board from keymile deploys two different porcessors.
An ARM based Kirkwood for the "unit" part of the SW and a PPC for
the "ne" part of the SW. Therefore in Linux and U-Boot the names
for the board are mgcoge2un and mgcoge2ne. This patch adds the
mgcoge2ne part of the board. The ppc part of mgboge2 is quite
similar to mgcoge, therefore a generic header km82xx-common.h
was introduced to collect all similiarities. Currently the only
difference is that mgcoge2ne has a 64 MB numonyx NOR flash with
a single die. The mgcoge has a dual die flash 2*32MB from spansion.
Signed-off-by: Holger Brunck
Signed-off-by: Heiko Schocher
cc: Wolfgang Denk
cc: Valentin Longchamp
---
MAINTAINERS |1 +
board/keymile/common/common.c |4 +-
board/keymile/mgcoge/mgcoge.c |4 +
boards.cfg |1 +
include/configs/km82xx-common.h | 321 +++
include/configs/mgcoge.h| 292 +---
include/configs/mgcoge2ne.h | 63
7 files changed, 395 insertions(+), 291 deletions(-)
create mode 100644 include/configs/km82xx-common.h
create mode 100644 include/configs/mgcoge2ne.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 9644d38..e4525e4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -428,6 +428,7 @@ Heiko Schocher
jupiter MPC5200
kmeter1 MPC8360
mgcoge MPC8247
+ mgcoge2ne MPC8247
mgcoge2un ARM926EJS (Kirkwood SoC)
mucmc52 MPC5200
muas3001MPC8270
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index f0b99ed..f723cfa 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -22,7 +22,7 @@
*/
#include
-#if defined(CONFIG_MGCOGE)
+#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGCOGE2NE)
#include
#endif
#include
@@ -337,7 +337,7 @@ int ivm_read_eeprom (void)
#define DELAY_ABORT_SEQ62
#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))
-#if defined(CONFIG_MGCOGE)
+#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGCOGE2NE)
#define SDA_MASK 0x0001
#define SCL_MASK 0x0002
static void set_pin (int state, unsigned long mask)
diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c
index 5c9496c..d9b0380 100644
--- a/board/keymile/mgcoge/mgcoge.c
+++ b/board/keymile/mgcoge/mgcoge.c
@@ -286,7 +286,11 @@ phys_size_t initdram (int board_type)
int checkboard(void)
{
+#if defined(CONFIG_MGCOGE)
puts ("Board: Keymile mgcoge");
+#else
+ puts ("Board: Keymile mgcoge2ne");
+#endif
if (ethernet_present ())
puts (" with PIGGY.");
puts ("\n");
diff --git a/boards.cfg b/boards.cfg
index 22cb509..3c45456 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -424,6 +424,7 @@ PQ2FADS-ZU_66MHz_lowboot powerpc mpc8260
mpc8260ads freesca
PQ2FADS-ZU_lowboot powerpc mpc8260 mpc8260ads
freescale -
MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF80
VoVPN-GW_66MHz powerpc mpc8260 vovpn-gw
funkwerk - VoVPN-GW:CLKIN_66MHz
mgcoge powerpc mpc8260 -
keymile
+mgcoge2nepowerpc mpc8260 mgcoge
keymile
SCM powerpc mpc8260 -
siemens
TQM8255_AA powerpc mpc8260 tqm8260 tqc
- TQM8260:MPC8255,300MHz
TQM8260_AA powerpc mpc8260 tqm8260 tqc
- TQM8260:MPC8260,200MHz
diff --git a/include/configs/km82xx-common.h b/include/configs/km82xx-common.h
new file mode 100644
index 000..b28cc99
--- /dev/null
+++ b/include/configs/km82xx-common.h
@@ -0,0 +1,321 @@
+/*
+ * (C) Copyright 2007-2010
+ * Heiko Schocher, DENX Software Engineering, h...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __KM82XX_COMMON
+#define __KM82XX_COMMON
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+
[U-Boot] [PATCH 12/20] ppc, 8321: cleanup tuxa1, tuda1 and suvd3 support
For the kmsupx5 a new header file was introduced km8321-common.h.
Now the common stuff from tuxa1, tuda1 and suvd3 was removed and
the new header file included.
The defines CONFIG_SYS_PIGGY_BASE and CONFIG_SYS_PIGGY_SIZE are
confusing. Because they actually describe the KMBEC FPGA values.
The KMBEC FPGA can be PRIO on kmeter1 or upio on mgcoge. Therefore
all the defines were renamed.
remove unneeded variable CONFIG_KM_DEF_NETDEV, as it is
already declared in keymile-common.h
Signed-off-by: Holger Brunck
Signed-off-by: Heiko Schocher
cc: Kim Phillips
cc: Wolfgang Denk
cc: Valentin Longchamp
---
board/keymile/common/common.c|2 +-
board/keymile/km83xx/km83xx.c|4 +-
board/keymile/mgcoge/mgcoge.c|4 +-
include/configs/keymile-common.h |2 +-
include/configs/km82xx-common.h | 12 ++--
include/configs/km8321-common.h |7 +--
include/configs/km83xx-common.h | 18 +++---
include/configs/kmeter1.h|8 ++-
include/configs/suvd3.h | 117 +-
include/configs/tuda1.h | 114 +
include/configs/tuxa1.h | 116 +-
11 files changed, 34 insertions(+), 370 deletions(-)
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index f723cfa..5b54e35 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -582,7 +582,7 @@ int fdt_get_node_and_value (void *blob,
#if !defined(MACH_TYPE_KM_KIRKWOOD)
int ethernet_present (void)
{
- return (in_8((u8 *)CONFIG_SYS_PIGGY_BASE + CONFIG_SYS_SLOT_ID_OFF) &
0x80);
+ return (in_8((u8 *)CONFIG_SYS_KMBEC_FPGA_BASE + CONFIG_SYS_SLOT_ID_OFF)
& 0x80);
}
#endif
diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index ecd19c5..c625b5d 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -158,9 +158,9 @@ int board_early_init_r (void)
break;
}
/* enable the PHY on the PIGGY */
- setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01);
+ setbits (8, (void *)(CONFIG_SYS_KMBEC_FPGA_BASE + 0x10003), 0x01);
/* enable the Unit LED (green) */
- setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x2), 0x01);
+ setbits (8, (void *)(CONFIG_SYS_KMBEC_FPGA_BASE + 0x2), 0x01);
#if defined(CONFIG_SUVD3)
/* configure UPMA for APP1 */
diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c
index d9b0380..44dc7a5 100644
--- a/board/keymile/mgcoge/mgcoge.c
+++ b/board/keymile/mgcoge/mgcoge.c
@@ -304,9 +304,9 @@ int board_early_init_r (void)
{
/* setup the UPIOx */
/* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
- out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x02), 0xc2);
+ out_8((u8 *)(CONFIG_SYS_KMBEC_FPGA_BASE + 0x02), 0xc2);
/* SCC4 enable, halfduplex, FCC1 powerdown */
- out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x03), 0x15);
+ out_8((u8 *)(CONFIG_SYS_KMBEC_FPGA_BASE + 0x03), 0x15);
return 0;
}
diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h
index c6a1432..33f2af2 100644
--- a/include/configs/keymile-common.h
+++ b/include/configs/keymile-common.h
@@ -102,7 +102,7 @@
* driver to set the MAC.
*/
#define CONFIG_CHECK_ETHERNET_PRESENT 1
-#define CONFIG_SYS_SLOT_ID_BASECONFIG_SYS_PIGGY_BASE
+#define CONFIG_SYS_SLOT_ID_BASECONFIG_SYS_KMBEC_FPGA_BASE
#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */
#define CONFIG_SYS_SLOT_ID_MASK(0x3f) /* mask for slot ID
bits */
diff --git a/include/configs/km82xx-common.h b/include/configs/km82xx-common.h
index b28cc99..40a609d 100644
--- a/include/configs/km82xx-common.h
+++ b/include/configs/km82xx-common.h
@@ -274,19 +274,19 @@
PSDMR_WRC_1C |\
PSDMR_CL_2)
-/* GPIO/PIGGY on CS3 initialization values
+/* UPIO FPGA (GPIO/PIGGY) on CS3 initialization values
*/
-#define CONFIG_SYS_PIGGY_BASE 0x3000
-#define CONFIG_SYS_PIGGY_SIZE 128
+#define CONFIG_SYS_KMBEC_FPGA_BASE 0x3000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
-#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\
BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\
+#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\
ORxG_CSNT | ORxG_ACS_DIV2 |\
ORxG_SCY_3_CLK | ORxG_TRLX )
-/* Board FPGA on CS4 initialization values
+/* BFTICU board FPGA on CS4 initialization values
*/
#define CONFIG_SYS_FPGA_BASE 0x4000
#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/
diff --git a/include/configs/km8321-common.h b/include/configs/km8
[U-Boot] [PATCH] microblaze: Setup monitor_flash_len
Flash address on Microblaze systems could be on higher addresses then ram. This patch fixed this assumption and flash can be located on any address. Signed-off-by: Michal Simek --- arch/microblaze/lib/board.c |8 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c index c5f7ac4..75d3c86 100644 --- a/arch/microblaze/lib/board.c +++ b/arch/microblaze/lib/board.c @@ -54,6 +54,12 @@ extern int timer_init (void); extern void fsl_init2 (void); #endif +/* section symbols */ +extern char *__end; +extern char *__text_start; + +unsigned long monitor_flash_len; + /* * All attempts to come up with a "common" initialization sequence * that works for all boards and architectures failed: some of the @@ -107,6 +113,8 @@ void board_init (void) bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ + monitor_flash_len = __end - __text_start; + /* * The Malloc area is immediately below the monitor copy in DRAM * aka CONFIG_SYS_MONITOR_BASE - Note there is no need for reloc_off -- 1.5.5.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] net: axi_ethernet: Add driver to u-boot v2
Add the first axi_ethernet driver for little-endian Microblaze.
Signed-off-by: Michal Simek
---
v2:
- Fix return addreses
- Fix NULL pointer defer for priv structure
---
.../xilinx/microblaze-generic/microblaze-generic.c |4 +
drivers/net/Makefile |1 +
drivers/net/xilinx_axi_emac.c | 535
include/configs/microblaze-generic.h |3 +
4 files changed, 543 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/xilinx_axi_emac.c
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c
b/board/xilinx/microblaze-generic/microblaze-generic.c
index 5c07fdb..e711546 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -73,6 +73,10 @@ int board_eth_init(bd_t *bis)
{
int ret = 0;
+#ifdef CONFIG_XILINX_AXIEMAC
+ ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
+ XILINX_AXIDMA_BASEADDR);
+#endif
#ifdef CONFIG_XILINX_EMACLITE
ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR);
#endif
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index fd9d0b4..01752a5 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -83,6 +83,7 @@ COBJS-$(CONFIG_TSEC_ENET) += tsec.o
COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o
COBJS-$(CONFIG_ULI526X) += uli526x.o
COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
+COBJS-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
COBJS := $(sort $(COBJS-y))
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
new file mode 100644
index 000..53e25fa
--- /dev/null
+++ b/drivers/net/xilinx_axi_emac.c
@@ -0,0 +1,535 @@
+/*
+ * Copyright (C) 2011 Michal Simek
+ * Copyright (C) 2011 PetaLogix
+ * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+/* Axi Ethernet registers offset */
+#define XAE_IS_OFFSET 0x000C /* Interrupt status */
+#define XAE_IE_OFFSET 0x0014 /* Interrupt enable */
+#define XAE_RCW1_OFFSET0x0404 /* Rx Configuration Word 1 */
+#define XAE_TC_OFFSET 0x0408 /* Tx Configuration */
+#define XAE_EMMC_OFFSET0x0410 /* EMAC mode configuration */
+#define XAE_MDIO_MC_OFFSET 0x0500 /* MII Management Config */
+#define XAE_MDIO_MCR_OFFSET0x0504 /* MII Management Control */
+#define XAE_MDIO_MRD_OFFSET0x050C /* MII Management Read Data */
+
+/* Link setup */
+#define XAE_EMMC_LINKSPEED_MASK0xC000 /* Link speed */
+#define XAE_EMMC_LINKSPD_100x /* Link Speed mask for 10 Mbit */
+#define XAE_EMMC_LINKSPD_100 0x4000 /* Link Speed mask for 100 Mbit */
+#define XAE_EMMC_LINKSPD_1000 0x8000 /* Link Speed mask for 1000 Mbit */
+
+/* Interrupt Status/Enable/Mask Registers bit definitions */
+#define XAE_INT_RXRJECT_MASK 0x0008 /* Rx frame rejected */
+#define XAE_INT_MGTRDY_MASK0x0080 /* MGT clock Lock */
+
+/* Receive Configuration Word 1 (RCW1) Register bit definitions */
+#define XAE_RCW1_RX_MASK 0x1000 /* Receiver enable */
+
+/* Transmitter Configuration (TC) Register bit definitions */
+#define XAE_TC_TX_MASK 0x1000 /* Transmitter enable */
+
+/*
+ * Station address bits [47:32]
+ * Station address bits [31:0] are stored in register UAW0
+ */
+#define XAE_UAW0_OFFSET0x0700 /* Unicast address
word 0 */
+#define XAE_UAW1_OFFSET0x0704 /* Unicast address
word 1 */
+#define XAE_UAW1_UNICASTADDR_MASK 0x
+
+/* MDIO Management Configuration (MC) Register bit definitions */
+#define XAE_MDIO_MC_MDIOEN_MASK0x0040 /* MII management
enable*/
+
+/* MDIO Management Control Register (MCR) Register bit definitions */
+#define XAE_MDIO_MCR_PHYAD_MASK0x1F00 /* Phy Address Mask
*/
+#define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
+#define XAE_MDIO_MCR_REGAD_MASK
[U-Boot] [PATCH 2/2] net: xilinx emaclite: Fix return values
Fix return values for initialize/init/recv/send functions
Signed-off-by: Michal Simek
---
drivers/net/xilinx_emaclite.c | 14 +++---
1 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 76af939..3c7c250 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -226,7 +226,7 @@ static int emaclite_send (struct eth_device *dev, volatile
void *ptr, int len)
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET +
XEL_BUFFER_OFFSET, 0);
#endif
- return 0;
+ return -1;
}
/* Determine the expected TX buffer address */
@@ -252,7 +252,7 @@ static int emaclite_send (struct eth_device *dev, volatile
void *ptr, int len)
reg |= XEL_TSR_XMIT_ACTIVE_MASK;
}
out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
- return 1;
+ return 0;
}
#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
/* Switch to second buffer */
@@ -273,11 +273,11 @@ static int emaclite_send (struct eth_device *dev,
volatile void *ptr, int len)
reg |= XEL_TSR_XMIT_ACTIVE_MASK;
}
out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
- return 1;
+ return 0;
}
#endif
puts ("Error while sending frame\n");
- return 0;
+ return -1;
}
static int emaclite_recv(struct eth_device *dev)
@@ -337,7 +337,7 @@ static int emaclite_recv(struct eth_device *dev)
debug ("Packet receive from 0x%x, length %dB\n", baseaddress, length);
NetReceive ((uchar *) etherrxbuff, length);
- return 1;
+ return length;
}
@@ -347,7 +347,7 @@ int xilinx_emaclite_initialize (bd_t *bis, int base_addr)
dev = malloc(sizeof(*dev));
if (dev == NULL)
- hang();
+ return -1;
memset(dev, 0, sizeof(*dev));
sprintf(dev->name, "Xilinx_Emaclite");
@@ -361,5 +361,5 @@ int xilinx_emaclite_initialize (bd_t *bis, int base_addr)
eth_register(dev);
- return 0;
+ return 1;
}
--
1.5.5.6
___
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Re: [U-Boot] cfi: Problem with Intel Strata 28F320 flash
Hello Heiko, On Tue, Mar 08, 2011 at 02:08:26PM +0100, Heiko Schocher wrote: > Hello, > > as I am actual trying to get the keymile boards in sync with actual > mainline u-boot, I faced the following Problem with an Intel Strata > Flash on the mgcoge (mpc8247 based board): > > I couldn;t unprotect/erase/write/protect some (not all!) Flash sectors. > > For Example, I could do this without errors on the sectors where > u-boot sits (First three sectors), but not with the environment (next > two sectors)! That's exactly the problem I had, but triggered by another valid command sequence. So it is also a flash bug. Have you searched with google for your chip plus "errata" or "specification update" as they call that ? > > After some debugging, I found out, that, if I revert commit > > commit 54652991caedc39b2ec2e5b49e750669bfcd1e2e > Author: Philippe De Muyter > Date: Tue Aug 17 18:40:25 2010 +0200 > > Work around bug in Numonyx P33/P30 256-Mbit 65nm flash chips. > > I have "ported" U-boot to a in house made board with Numonyx Axcell > P33/P30 > 256-Mbit 65nm flash chips. > > After some time :( searching for bugs in our board or soft, we have > discovered that those chips have a small but annoying bug, documented in > "Numonyx Axcell P33/P30 256-Mbit Specification Update" > [...] > > It works again fine, and without problems ... did somebody faced > similiar issues with the cfi driver? Some Ideas? It seems like we'll need to check the flash chip type before issuing one command sequence or another. Philippe -- Philippe De Muyter +32 2 6101532 Macq SA rue de l'Aeronef 2 B-1140 Bruxelles ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 15/21] nios2: Generic system restart support
Hi Kyle, Kyle Moffett wrote: > The Nios-II port appears to use no generic hardware capability for > performing a CPU reset. Since all of the supported boards use the exact > same code to perform a jump-to-flash it goes into __arch_restart(). > > This means that Nios-II has a no-op __arch_emergency_restart() function. > If the CPU is in an invalid state then jump-to-FLASH probably won't > work. If the CPU state is stable enough to call __arch_emergency_restart(), a jump to the reset address should be fine. In many implementations the reset code is in on-chip ROM. If things get screwed up enough to affect the code in on-chip ROM, it probably won't matter what gets called. ;-) Thomas, any thoughts? Regards, --Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 15/21] nios2: Generic system restart support
Hi! On Mar 08, 2011, at 19:13, Scott McNutt wrote: > Hi Kyle, > > Kyle Moffett wrote: >> The Nios-II port appears to use no generic hardware capability for >> performing a CPU reset. Since all of the supported boards use the exact >> same code to perform a jump-to-flash it goes into __arch_restart(). >> >> This means that Nios-II has a no-op __arch_emergency_restart() function. >> If the CPU is in an invalid state then jump-to-FLASH probably won't >> work. > > If the CPU state is stable enough to call __arch_emergency_restart(), > a jump to the reset address should be fine. In many implementations > the reset code is in on-chip ROM. If things get screwed up enough > to affect the code in on-chip ROM, it probably won't matter what > gets called. ;-) I'm not at all familiar with the Nios-II hardware platform. Is the on-chip ROM really safe to be called in arbitrary system states? Using FLASH memory as an example, consider a FLASH driver in the middle of a programming cycle when an unexpected exception occurs: * FLASH programming in process * CPU takes an unexpected trap * CPU calls exception vector (possibly with interrupts disabled or enabled) * emergency_restart() * __arch_emergency_restart() * Boot ROM is called Until the FLASH memory is reset and put back into a defined state it will be unusable, and if your boot process depends on the FLASH then serious problems will result. In that case it would be better not to just hang than try to restart. Basically the emergency_restart() code should handle being called even in the following scenarios: * Unexpected CPU exception or interrupt occurs * Interrupts on or off, or *from* an interrupt or trap handler. * FLASH or other peripherals in an undefined state If that's the case for your onboard ROM then I will certainly remove the no-op emergency restart hook from this patch. Cheers, Kyle Moffett ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 15/21] nios2: Generic system restart support
Moffett, Kyle D wrote: > Hi! > > On Mar 08, 2011, at 19:13, Scott McNutt wrote: >> Hi Kyle, >> >> Kyle Moffett wrote: >>> The Nios-II port appears to use no generic hardware capability for >>> performing a CPU reset. Since all of the supported boards use the exact >>> same code to perform a jump-to-flash it goes into __arch_restart(). >>> >>> This means that Nios-II has a no-op __arch_emergency_restart() function. >>> If the CPU is in an invalid state then jump-to-FLASH probably won't >>> work. >> If the CPU state is stable enough to call __arch_emergency_restart(), >> a jump to the reset address should be fine. In many implementations >> the reset code is in on-chip ROM. If things get screwed up enough >> to affect the code in on-chip ROM, it probably won't matter what >> gets called. ;-) > ... ... > Basically the emergency_restart() code should handle being called even in the > following scenarios: > * Unexpected CPU exception or interrupt occurs > * Interrupts on or off, or *from* an interrupt or trap handler. > * FLASH or other peripherals in an undefined state > > If that's the case for your onboard ROM then I will certainly remove the > no-op emergency restart hook from this patch. From a practical perspective, in the case of on-chip ROM, it would be no different than a hard reset during any of the above activities. But please don't remove it. Your position is sound and conservative. I haven't had time to review the entire patch set yet. I'm assuming the __board_emergency_restart() routine is where a board can override the default arch-specific behavior? If so, you already provided the hooks for more daring developers. ;-) Regards, --Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] make fails for versatilepb_config
Using u-boot-marvell.git, doing a make all make[1]: Entering directory `/src/IConnect/src/U-boot/u-boot-marvell.git/arch/arm/lib' arm-gp2x-linux-gcc -g -Os -fno-common -ffixed-r8 -msoft-float -D__KERNEL__ -DCONFIG_SYS_TEXT_BASE=0x0100 -I/src/IConnect/src/U-boot/u-boot-marvell.git/include -fno-builtin -ffreestanding -nostdinc -isystem /usr/lib/gcc/arm-gp2x-linux/4.1.2/include -pipe -DCONFIG_ARM -D__ARM__ -marm -mabi=aapcs-linux -mno-thumb-interwork -march=armv5te -Wall -Wstrict-prototypes -fno-stack-protector -o board.o board.c -c board.c: In function '__dram_init_banksize': board.c:233: error: 'CONFIG_SYS_SDRAM_BASE' undeclared (first use in this function) board.c:233: error: (Each undeclared identifier is reported only once board.c:233: error: for each function it appears in.) board.c: In function 'board_init_f': board.c:279: error: 'CONFIG_SYS_INIT_SP_ADDR' undeclared (first use in this function) board.c:312: error: 'CONFIG_SYS_SDRAM_BASE' undeclared (first use in this function) make[1]: *** [board.o] Error 1 make[1]: Leaving directory `/src/IConnect/src/U-boot/u-boot-marvell.git/arch/arm/lib' make: *** [arch/arm/lib/libarm.o] Error 2 Has this been fixed yet?? -- William Estrada Mt Umunhum, CA, USA HTTP://64.124.13.3 ( Mt-Umunhum-Wireless.net ) Skype: MrUmunhum ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 17/22] omap4: calculate EMIF register values
On Mon, Feb 28, 2011 at 4:46 AM, Aneesh V wrote: > Calculate EMIF register values based on AC timing parameters > from the SDRAM datasheet and the DDR frequency rather than > using the hard-coded values. > > For a new board the user doen't have to go through the tedious > process of calculating the register values. Instead, just > provide the AC timings from the device data sheet as input > and the driver will automatically calculate the register values. > > Signed-off-by: Aneesh V > --- I get some warnings from arch/arm/cpu/armv7/omap4/emif.c: emif.c: In function ‘sdram_init’: emif.c:1164:43: warning: ‘section_map’ may be used uninitialized in this function emif.c:1166:27: warning: ‘lis_map_regs_calculated$dmm_lisa_map_3’ may be used uninitialized in this function emif.c: In function ‘sdram_init’: emif.c:1166:27: warning: ‘lis_map_regs_calculated$dmm_lisa_map_3’ may be used uninitialized in this function Looking at the code I see that these are initialized but the compiler can't firgure that out. John ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 17/22] omap4: calculate EMIF register values
On Wednesday 09 March 2011 10:16 AM, John Rigby wrote: > On Mon, Feb 28, 2011 at 4:46 AM, Aneesh V wrote: >> Calculate EMIF register values based on AC timing parameters >> from the SDRAM datasheet and the DDR frequency rather than >> using the hard-coded values. >> >> For a new board the user doen't have to go through the tedious >> process of calculating the register values. Instead, just >> provide the AC timings from the device data sheet as input >> and the driver will automatically calculate the register values. >> >> Signed-off-by: Aneesh V >> --- > > > I get some warnings from arch/arm/cpu/armv7/omap4/emif.c: > emif.c: In function ‘sdram_init’: > emif.c:1164:43: warning: ‘section_map’ may be used uninitialized in > this function > emif.c:1166:27: warning: ‘lis_map_regs_calculated$dmm_lisa_map_3’ may > be used uninitialized in this function > emif.c: In function ‘sdram_init’: > emif.c:1166:27: warning: ‘lis_map_regs_calculated$dmm_lisa_map_3’ may > be used uninitialized in this function > > Looking at the code I see that these are initialized but the compiler > can't firgure that out. I don't see the warnings with my tool-chain ((Sourcery G++ Lite 2010q1-202) GCC 4.4.1) I tried immediately after this patch and also after applying all the patches. Which compiler are you using? best regards, Aneesh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] problem with crossmaking
i m making crossmake on my host machine linux (x486/4.4.4) when i m in process of u boot compilation i found error given as bellow. root@hamid:/home/u-boot-1.1.6# crossmake for dir in tools examples post post/cpu ; do make -C $dir _depend ; done make[1]: Entering directory `/home/u-boot-1.1.6/tools' make[1]: Nothing to be done for `_depend'. make[1]: Leaving directory `/home/u-boot-1.1.6/tools' make[1]: Entering directory `/home/u-boot-1.1.6/examples' make[1]: Nothing to be done for `_depend'. make[1]: Leaving directory `/home/u-boot-1.1.6/examples' make[1]: Entering directory `/home/u-boot-1.1.6/post' make[1]: Nothing to be done for `_depend'. make[1]: Leaving directory `/home/u-boot-1.1.6/post' make[1]: Entering directory `/home/u-boot-1.1.6/post/cpu' make[1]: Nothing to be done for `_depend'. make[1]: Leaving directory `/home/u-boot-1.1.6/post/cpu' make -C tools all make[1]: Entering directory `/home/u-boot-1.1.6/tools' make[1]: *** No rule to make target `/usr/lib/gcc/i386-redhat-linux/4.1.2/include/stddef.h', needed by `img2srec.o'. Stop. make[1]: Leaving directory `/home/u-boot-1.1.6/tools' make: *** [tools] Error 2 -- MOHD HAMID KHAN NPL INDIA B TECH EC ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 17/22] omap4: calculate EMIF register values
On Tue, Mar 8, 2011 at 10:08 PM, Aneesh V wrote: > On Wednesday 09 March 2011 10:16 AM, John Rigby wrote: >> >> On Mon, Feb 28, 2011 at 4:46 AM, Aneesh V wrote: >>> >>> Calculate EMIF register values based on AC timing parameters >>> from the SDRAM datasheet and the DDR frequency rather than >>> using the hard-coded values. >>> >>> For a new board the user doen't have to go through the tedious >>> process of calculating the register values. Instead, just >>> provide the AC timings from the device data sheet as input >>> and the driver will automatically calculate the register values. >>> >>> Signed-off-by: Aneesh V >>> --- >> >> >> I get some warnings from arch/arm/cpu/armv7/omap4/emif.c: >> emif.c: In function ‘sdram_init’: >> emif.c:1164:43: warning: ‘section_map’ may be used uninitialized in >> this function >> emif.c:1166:27: warning: ‘lis_map_regs_calculated$dmm_lisa_map_3’ may >> be used uninitialized in this function >> emif.c: In function ‘sdram_init’: >> emif.c:1166:27: warning: ‘lis_map_regs_calculated$dmm_lisa_map_3’ may >> be used uninitialized in this function >> >> Looking at the code I see that these are initialized but the compiler >> can't firgure that out. > > I don't see the warnings with my tool-chain ((Sourcery G++ Lite > 2010q1-202) GCC 4.4.1) > > I tried immediately after this patch and also after applying all the > patches. Which compiler are you using? The latest Linaro cross toolchain: $ arm-linux-gnueabi-gcc --version arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.5.2-1ubuntu3ppa1) 4.5.2 > > best regards, > Aneesh > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] problem with crossmaking
i m making crossmake on my host machine linux (x486/4.4.4) when i m in process of u boot compilation i found error given as bellow. root@hamid:/home/u-boot-1.1.6# crossmake for dir in tools examples post post/cpu ; do make -C $dir _depend ; done make[1]: Entering directory `/home/u-boot-1.1.6/tools' make[1]: Nothing to be done for `_depend'. make[1]: Leaving directory `/home/u-boot-1.1.6/tools' make[1]: Entering directory `/home/u-boot-1.1.6/examples' make[1]: Nothing to be done for `_depend'. make[1]: Leaving directory `/home/u-boot-1.1.6/examples' make[1]: Entering directory `/home/u-boot-1.1.6/post' make[1]: Nothing to be done for `_depend'. make[1]: Leaving directory `/home/u-boot-1.1.6/post' make[1]: Entering directory `/home/u-boot-1.1.6/post/cpu' make[1]: Nothing to be done for `_depend'. make[1]: Leaving directory `/home/u-boot-1.1.6/post/cpu' make -C tools all make[1]: Entering directory `/home/u-boot-1.1.6/tools' make[1]: *** No rule to make target `/usr/lib/gcc/i386-redhat-linux/4.1.2/include/stddef.h', needed by `img2srec.o'. Stop. make[1]: Leaving directory `/home/u-boot-1.1.6/tools' make: *** [tools] Error 2 -- Open WebMail Project (http://openwebmail.org) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/5] powerpc/85xx: Read board switch settings on p1_p2_rdb
On Sun, Mar 6, 2011 at 10:17 PM, Kumar Gala wrote:
> + if (i2c_data & 0x1) {
> + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
> + puts("SD/MMC : 8-bit Mode\n");
> + puts("eSPI : Disabled\n");
> + } else {
> + puts("SD/MMC : 4-bit Mode\n");
> + puts("eSPI : Enabled\n");
I think this bit is actually important for the p1_p2_rdb_pc boards
also? Is this handled by the CPLD somehow or do we need to do the same
thing?
'IO0 - "read-only" CFG_SDWIDTH SW2[1].
-M
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Re: [U-Boot] cfi: Problem with Intel Strata 28F320 flash
Hello Philippe,
Philippe De Muyter wrote:
> On Tue, Mar 08, 2011 at 02:08:26PM +0100, Heiko Schocher wrote:
>> Hello,
>>
>> as I am actual trying to get the keymile boards in sync with actual
>> mainline u-boot, I faced the following Problem with an Intel Strata
>> Flash on the mgcoge (mpc8247 based board):
>>
>> I couldn;t unprotect/erase/write/protect some (not all!) Flash sectors.
>>
>> For Example, I could do this without errors on the sectors where
>> u-boot sits (First three sectors), but not with the environment (next
>> two sectors)!
>
> That's exactly the problem I had, but triggered by another valid command
> sequence.
>
> So it is also a flash bug.
Hmm.. I wouldn;t call it bug, because the sequence which is
run without 54652991caedc39b2ec2e5b49e750669bfcd1e2e, is exactly
the sequence, which is described in the datasheet for the 29Fxxx
chips ...
> Have you searched with google for your chip plus "errata" or "specification
> update" as they call that ?
No, see above comment.
>> After some debugging, I found out, that, if I revert commit
>>
>> commit 54652991caedc39b2ec2e5b49e750669bfcd1e2e
>> Author: Philippe De Muyter
>> Date: Tue Aug 17 18:40:25 2010 +0200
>>
>> Work around bug in Numonyx P33/P30 256-Mbit 65nm flash chips.
>>
>> I have "ported" U-boot to a in house made board with Numonyx Axcell
>> P33/P30
>> 256-Mbit 65nm flash chips.
>>
>> After some time :( searching for bugs in our board or soft, we have
>> discovered that those chips have a small but annoying bug, documented in
>> "Numonyx Axcell P33/P30 256-Mbit Specification Update"
>> [...]
>>
>> It works again fine, and without problems ... did somebody faced
>> similiar issues with the cfi driver? Some Ideas?
>
> It seems like we'll need to check the flash chip type before issuing one
> command
> sequence or another.
Maybe a way to go ... more comments?
Below a patch, which introduces a function, which checks for
"protection bugfixes", and if no bugfix is found the old code is
executed. Just a fast RFC patch.
bye,
Heiko
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index dd394a8..9d3fdcc 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -1376,6 +1376,38 @@ int write_buff (flash_info_t * info, uchar * src, ulong
addr, ulong cnt)
*/
#ifdef CONFIG_SYS_FLASH_PROTECTION
+static int cfi_protect_bugfix(flash_info_t * info, long sector, int prot)
+{
+ if ((info->manufacturer_id == 0x89) && (info->device_id == 0x8922)) {
+ /*
+* see errata called
+* "Numonyx Axcell P33/P30 Specification Update" :)
+*/
+ flash_write_cmd (info, sector, 0, FLASH_CMD_READ_ID);
+ if (!flash_isequal (info, sector, FLASH_OFFSET_PROTECT,
+ prot)) {
+ /*
+* cmd must come before FLASH_CMD_PROTECT + 20us
+* Disable interrupts which might cause a timeout here.
+*/
+ int flag = disable_interrupts ();
+ unsigned short cmd;
+ if (prot)
+ cmd = FLASH_CMD_PROTECT_SET;
+ else
+ cmd = FLASH_CMD_PROTECT_CLEAR;
+ flash_write_cmd (info, sector, 0,
+ FLASH_CMD_PROTECT);
+ flash_write_cmd (info, sector, 0, cmd);
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts ();
+ }
+ return 1;
+ }
+ return 0;
+}
+
int flash_real_protect (flash_info_t * info, long sector, int prot)
{
int retcode = 0;
@@ -1384,31 +1416,18 @@ int flash_real_protect (flash_info_t * info, long
sector, int prot)
case CFI_CMDSET_INTEL_PROG_REGIONS:
case CFI_CMDSET_INTEL_STANDARD:
case CFI_CMDSET_INTEL_EXTENDED:
- /*
-* see errata called
-* "Numonyx Axcell P33/P30 Specification Update" :)
-*/
- flash_write_cmd (info, sector, 0, FLASH_CMD_READ_ID);
- if (!flash_isequal (info, sector, FLASH_OFFSET_PROTECT,
- prot)) {
- /*
-* cmd must come before FLASH_CMD_PROTECT + 20us
-* Disable interrupts which might cause a
timeout here.
-*/
- int flag = disable_interrupts ();
- unsigned short cmd;
-
+ if (!cfi_protect_bugfix(info, sector, prot)) {
+ flash_write_cmd (info, sector, 0,
+
Re: [U-Boot] problem with crossmaking
On Wednesday, March 09, 2011 00:58:23 mohd hamid khan wrote: > root@hamid:/home/u-boot-1.1.6# crossmake two things: - you're using u-boot-1.1.6 which is not supported. upgrade. - crossmake has nothing to do with u-boot. ask whoever wrote it. -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] net: axi_ethernet: Add driver to u-boot
On Friday, March 04, 2011 05:09:53 Michal Simek wrote: > Mike Frysinger wrote: > >> 3. dev->init > >> return -1 - if init failed > >> return 0 - on success > > > > ok > > > >> (here you are saying should be return # of devices) > > > > no, i think you confused "initialize" with "init" in my feedback > > ok. From my point of view is better do initialize only for one device > and not to registered all device in the driver. IMHO this functionality > should be done by board specific net function in board_eth_init. > Not sure if this covers all cases which can happen. But anyway if the > driver initialize several drivers with the same type then you are losing > flexibility. no, that isnt what i meant. the initialize function is allowed to return more than one because a single part might support more than one interface. think of MAC switches or multiple PHYs hooked up to a single MAC. in neither of these cases should the board_eth_init func need to call a driver's initialize function multiple times imo. -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/2] net: axi_ethernet: Add driver to u-boot v2
On Tuesday, March 08, 2011 09:25:52 Michal Simek wrote:
> +int xilinx_axiemac_initialize(bd_t *bis, int base_addr, int dma_addr)
> +{
> + struct eth_device *dev;
> + struct axidma_priv *dma;
> +
> + dev = calloc(1, sizeof(struct eth_device));
> + if (dev == NULL)
> + return -1;
> +
> + dev->priv = calloc(1, sizeof(struct axidma_priv));
> + if (dev->priv == NULL)
> + return -1;
this 2nd error checker should call free(dev). the rest is copacetic.
-mike
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Re: [U-Boot] [PATCH] net: axi_ethernet: Add driver to u-boot
On Friday, March 04, 2011 05:09:53 Michal Simek wrote: > To finish this discuss - here is what you think that it is correct. > ad 2) > return -1 - if initialize failed > return 0 - never return > return >0 - # of devices oh, and to clarify on the "return 0", i think it's conceivable that if a device might not exist, the initialize function may return 0. whether any driver currently utilizes this is a different issue. -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
