Re: [U-Boot] [PATCH V2 4/4] cmd_part: add partition-related command
Hi Stephen, Tom, Rob's series depends on Wolfgang(?)'s u-boot/ext4 branch at present. I'm not sure what the status of that branch is right now - is it something that's ready to be submitted, or is more work there needed, so the branch won't be pulled into u-boot/master in the near future? I'm mainly asking so Rob and I know if Rob's patches should be rebased first onto something else, before I rebase my patches on his. Thanks. I'd also like to know if those patches will be accepted soon. I'm working on a GPT restoration support and those patches might be a pre-requisite for my development (if were pulled into u-boot/master). -- Best regards, Lukasz Majewski Samsung Poland RD Center | Linux Platform Group ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/2] i2c:soft:multi: Support for multiple soft I2C buses at Samsung boards
Hi Minkyu,
Support for multiple soft I2C buses.
Multibus I2C support is achieved by defining get_multi_{sda|scl}_pin
functions to switch between multiple soft I2C buses.
Common definition of I2C_X I2C buses is provided at i2c.h.
TEST HW:
Samsung's Exynos4210 evt.0.1 - Trats development board
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Heiko Schocher h...@denx.de
Cc: Minkyu Kang mk7.k...@samsung.com
---
Changes for v2:
- Common Samsung code has been put to
board/samsung/common/multi_i2c.c file
- I2C_{4|5} have been renamed to I2C_{0|1}
- *soft_i2c_name[] table has been removed
Changes for v3:
- None
Changes for v4:
- Common definitions of available I2C buses are now defined at i2c.h
- Compatibility layer (I2C_0) has been added temporarily to not break
the Trats I2C communication with PMIC. It will be removed when
redesigned PMIC will be posted
---
Can you evaluate those patches.
Those were acked-by Heiko already.
--
Best regards,
Lukasz Majewski
Samsung Poland RD Center | Linux Platform Group
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[U-Boot] Help Required [imx35pdk_u-boot]
I am adding support of imx35pdk in yocto. I have done with my bsp. But the u-boot that build in response of my bsp only runs over NOR and not on NAND. I spend 2 days on it but failed to do so. I read some where that mx35pdk required some external 4-pins bla bla something like that and page size is 2k... something like such, so therefore, NAND is not working. Also the u-boot running on NOR is not configuring uImage. I am using tftp but when it comes on loading, it keeps on showing T T T T T... (time-out response). I'm stuck here. Can you please help me :( I am using u-boot from this repo: git://git.denx.de/u-boot.git Here they give the u-boot-nand.bin but for imx31pdk and not for imx35pdk :( What to do ??? Regards, Usman ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/2] i2c:soft:multi: Support for multiple soft I2C buses at Samsung boards
Dear Lukasz,
On 12 September 2012 16:06, Lukasz Majewski l.majew...@samsung.com wrote:
Hi Minkyu,
Support for multiple soft I2C buses.
Multibus I2C support is achieved by defining get_multi_{sda|scl}_pin
functions to switch between multiple soft I2C buses.
Common definition of I2C_X I2C buses is provided at i2c.h.
TEST HW:
Samsung's Exynos4210 evt.0.1 - Trats development board
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Heiko Schocher h...@denx.de
Cc: Minkyu Kang mk7.k...@samsung.com
---
Changes for v2:
- Common Samsung code has been put to
board/samsung/common/multi_i2c.c file
- I2C_{4|5} have been renamed to I2C_{0|1}
- *soft_i2c_name[] table has been removed
Changes for v3:
- None
Changes for v4:
- Common definitions of available I2C buses are now defined at i2c.h
- Compatibility layer (I2C_0) has been added temporarily to not break
the Trats I2C communication with PMIC. It will be removed when
redesigned PMIC will be posted
---
Can you evaluate those patches.
Those were acked-by Heiko already.
OK.
please wait few days.
I will check pending patches soon.
Thanks.
Minkyu Kang.
--
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Re: [U-Boot] [PATCH 1/2] bfin: Disable -fstack-usage
Dear Mike Frysinger, On Tue, Sep 11, 2012 at 3:08 PM, Marek Vasut wrote: The GCC does not support this on blackfin, disable it. err, no, you're probably using gcc-4.5.x which didn't support -fstack-usage. that is not specific to Blackfin as gcc didn't add it until 4.6.x. I actually used gentoo here, so it's really possible there is some crap going on. $ bfin-unknown-elf-gcc --version bfin-unknown-elf-gcc (crosstool-NG hg+default-ff167977b163) 4.6.3 Copyright (C) 2011 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. why doesn't the cc-option check work ? I dunno man, probably because it's supported but broken, see (there's lot more to this, I cut it down): $ ARCH=blackfin CROSS_COMPILE=bfin-unknown-elf- ./MAKEALL -a blackfin Configuring for bct-brettl2 board... textdata bss dec hex filename 1682284070 61768 234066 39252 ./u-boot lib/asm-offsets.c: In function 'main': lib/asm-offsets.c:32:1: warning: -fstack-usage not supported for this target [enabled by default] initcode.c: In function 'initcode': initcode.c:691:1: warning: -fstack-usage not supported for this target [enabled by default] bootrom-asm-offsets.c: In function 'main': bootrom-asm-offsets.c:62:1: warning: -fstack-usage not supported for this target [enabled by default] cpu.c: In function 'cpu_init_f': cpu.c:76:1: warning: -fstack-usage not supported for this target [enabled by default] part.c: In function 'get_dev': part.c:103:1: warning: -fstack-usage not supported for this target [enabled by default] gpio.c: In function 'port_setup': gpio.c:220:1: warning: -fstack-usage not supported for this target [enabled by default] In file included from /home/marex/U-Boot/u-boot- marex/include/asm/blackfin.h:13:0, from /home/marex/U-Boot/u-boot-marex/include/common.h:109, from interrupts.c:21: /home/marex/U-Boot/u-boot-marex/include/asm/blackfin_local.h: In function 'CSYNC': /home/marex/U-Boot/u-boot-marex/include/asm/blackfin_local.h:200:1: warning: - fstack-usage not supported for this target [enabled by default] jtag-console.c: In function 'jtag_getc': jtag-console.c:177:1: warning: -fstack-usage not supported for this target [enabled by default] os_log.c: In function 'bfin_os_log_check': os_log.c:21:1: warning: -fstack-usage not supported for this target [enabled by default] -mike Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/9] i2c: sh_i2c.c: support iccl and icch extension
R-mobile SoC (at least SH73A0) has extension bits to store 8th bit of iccl and
icch.
This patch add support for the extentin bits.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
Changes for v2:
- define CONFIG_SH_I2C_8BIT at board config file and replace HAS_ICIC67.
drivers/i2c/sh_i2c.c| 30 ++
include/configs/kzm9g.h |1 +
2 files changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index fd8cb92..b98fce5 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -48,7 +48,13 @@ static struct sh_i2c *base;
#define SH_IC_WAIT (1 1)
#define SH_IC_DTE (1 0)
-static u8 iccl, icch;
+#ifdef CONFIG_SH_I2C_8BIT
+/* store 8th bit of iccl and icch in ICIC register */
+#define SH_I2C_ICIC_ICCLB8 (1 7)
+#define SH_I2C_ICIC_ICCHB8 (1 6)
+#endif
+
+static u16 iccl, icch;
#define IRQ_WAIT 1000
@@ -92,12 +98,20 @@ static void irq_busy(struct sh_i2c *base)
static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
{
+ u8 icic = 0;
+
writeb(readb(base-iccr) ~SH_I2C_ICCR_ICE, base-iccr);
writeb(readb(base-iccr) | SH_I2C_ICCR_ICE, base-iccr);
- writeb(iccl, base-iccl);
- writeb(icch, base-icch);
- writeb(0, base-icic);
+ writeb(iccl 0xff, base-iccl);
+ writeb(icch 0xff, base-icch);
+#ifdef CONFIG_SH_I2C_8BIT
+ if (iccl 0xff)
+ icic |= SH_I2C_ICIC_ICCLB8;
+ if (icch 0xff)
+ icic |= SH_I2C_ICIC_ICCHB8;
+#endif
+ writeb(icic, base-icic);
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), base-iccr);
irq_dte(base);
@@ -222,18 +236,18 @@ void i2c_init(int speed, int slaveaddr)
denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
tmp = num * 10 / denom;
if (tmp % 10 = 5)
- iccl = (u8)((num/denom) + 1);
+ iccl = (u16)((num/denom) + 1);
else
- iccl = (u8)(num/denom);
+ iccl = (u16)(num/denom);
/* Calculate the value for icch. From the data sheet:
icch = (p clock / transfer rate) * (H / (L + H)) */
num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
tmp = num * 10 / denom;
if (tmp % 10 = 5)
- icch = (u8)((num/denom) + 1);
+ icch = (u16)((num/denom) + 1);
else
- icch = (u8)(num/denom);
+ icch = (u16)(num/denom);
}
/*
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
index a1ae718..8877516 100644
--- a/include/configs/kzm9g.h
+++ b/include/configs/kzm9g.h
@@ -155,6 +155,7 @@
/* I2C */
#define CONFIG_CMD_I2C
#define CONFIG_SH_I2C 1
+#define CONFIG_SH_I2C_8BIT
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS (2)
--
1.7.9.5
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[U-Boot] [PATCH v2 7/9] i2c: sh_i2c.c: remove unused function
irq_wait() was not used. So removed it to elminate compiler warnings.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
Changes for v2:
- new
drivers/i2c/sh_i2c.c | 16
1 file changed, 16 deletions(-)
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index e3ee804..60bad52 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -58,22 +58,6 @@ static u16 iccl, icch;
#define IRQ_WAIT 1000
-static void irq_wait(struct sh_i2c *base)
-{
- int i;
- u8 status;
-
- for (i = 0 ; i IRQ_WAIT ; i++) {
- status = readb(base-icsr);
- if (SH_IC_WAIT status)
- break;
-
- udelay(10);
- }
-
- writeb(status ~SH_IC_WAIT, base-icsr);
-}
-
static void irq_dte(struct sh_i2c *base)
{
int i;
--
1.7.9.5
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[U-Boot] [PATCH v2 9/9] arm: rmobile: kzm9g: enable I2C2
Set gpio config for I2C2. Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp --- Changes for v2: - new board/kmc/kzm9g/kzm9g.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c index 93ca9d7..22f581a 100644 --- a/board/kmc/kzm9g/kzm9g.c +++ b/board/kmc/kzm9g/kzm9g.c @@ -370,6 +370,8 @@ int board_init(void) gpio_direction_output(GPIO_PORT15, 1); /* I2C */ + gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL); + gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL); gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL); gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL); -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 4/9] i2c: sh_i2c.c: support I2C2, I2C3 and I2C4
sh_i2c.c support I2C0 and I2C1. This patch extends it to I2C4. Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp --- Changes for v2: - new drivers/i2c/sh_i2c.c| 15 +++ include/configs/kzm9g.h |5 - 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index 6c6a141..d524619 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -200,6 +200,21 @@ int i2c_set_bus_num(unsigned int bus) case 1: base = (void *)CONFIG_SH_I2C_BASE1; break; +#ifdef CONFIG_SH_I2C_BASE2 + case 2: + base = (void *)CONFIG_SH_I2C_BASE2; + break; +#endif +#ifdef CONFIG_SH_I2C_BASE3 + case 3: + base = (void *)CONFIG_SH_I2C_BASE3; + break; +#endif +#ifdef CONFIG_SH_I2C_BASE4 + case 4: + base = (void *)CONFIG_SH_I2C_BASE4; + break; +#endif default: return -1; } diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index abeab69..6a0b6c5 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -158,7 +158,7 @@ #define CONFIG_SH_I2C_8BIT #define CONFIG_HARD_I2C #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_MAX_I2C_BUS (2) +#define CONFIG_SYS_MAX_I2C_BUS (5) #define CONFIG_SYS_I2C_MODULE #define CONFIG_SYS_I2C_SPEED(10) /* 100 kHz */ #define CONFIG_SYS_I2C_SLAVE(0x7F) @@ -167,5 +167,8 @@ #define CONFIG_SH_I2C_CLOCK (10400) /* 104 MHz */ #define CONFIG_SH_I2C_BASE0 (0xE682) #define CONFIG_SH_I2C_BASE1 (0xE6822000) +#define CONFIG_SH_I2C_BASE2 (0xE6824000) +#define CONFIG_SH_I2C_BASE3 (0xE6826000) +#define CONFIG_SH_I2C_BASE4 (0xE6828000) #endif /* __KZM9G_H */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 0/9] i2c for R-mobile
Hi, Iwamatsu-san Hello, Heiko Iwamatu-san, thank you for review. This is v2 patch for sh_i2c. Now i2c dev and i2c probe also work properly on KZM-A9-GT board. I think this modification is common for R-mobile, but I have SH73A0 document only. Iwamatu-san, please review this. This patch set is based on arm/rmobile branch of u-boot-sh.git. Tetsuyuki Kobayashi (9): i2c: sh_i2c.c: support iccl and icch extension i2c: sh_i2c.c: correct BUSY bit define in ICSR i2c: sh_i2c.c: adjust for SH73A0 i2c: sh_i2c.c: support I2C2, I2C3 and I2C4 i2c: sh_i2c: enable i2c_probe i2c: sh_i2c.c: check error in i2c_read and i2c_write i2c: sh_i2c.c: remove unused function arm: rmobile: kzm9g: enable I2C1 arm: rmobile: kzm9g: enable I2C2 board/kmc/kzm9g/kzm9g.c |7 ++- drivers/i2c/sh_i2c.c| 120 +-- include/configs/kzm9g.h |8 +++- 3 files changed, 95 insertions(+), 40 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 6/9] i2c: sh_i2c.c: check error in i2c_read and i2c_write
Before this patch, i2c_{read,write} always returned 0.
Check TACK in i2c_raw_{read,write} so that i2c_{read,write} return non-zero
when error.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
Changes for v2:
- new
drivers/i2c/sh_i2c.c | 44
1 file changed, 28 insertions(+), 16 deletions(-)
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index 25dbc43..e3ee804 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -151,29 +151,35 @@ static void i2c_finish(struct sh_i2c *base)
writeb(readb(base-iccr) ~SH_I2C_ICCR_ICE, base-iccr);
}
-static void i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val)
+static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val)
{
- i2c_set_addr(base, id, reg, 0);
+ if (i2c_set_addr(base, id, reg, 0) != 0)
+ return -1;
udelay(10);
writeb(val, base-icdr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), base-iccr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
irq_busy(base);
i2c_finish(base);
+ return 0;
}
-static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
+static int i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
{
- u8 ret;
+ int ret;
#if defined(CONFIG_SH73A0)
- i2c_set_addr(base, id, reg, 0);
+ if (i2c_set_addr(base, id, reg, 0) != 0)
+ return -1;
#else
- i2c_set_addr(base, id, reg, 1);
+ if (i2c_set_addr(base, id, reg, 1) != 0)
+ return -1;
udelay(100);
#endif
@@ -181,12 +187,14 @@ static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
irq_dte(base);
writeb(id 1 | 0x01, base-icdr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), base-iccr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
- ret = readb(base-icdr);
+ ret = readb(base-icdr) 0xff;
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), base-iccr);
readb(base-icdr); /* Dummy read */
@@ -303,10 +311,14 @@ void i2c_init(int speed, int slaveaddr)
*/
int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
{
+ int ret;
int i = 0;
- for (i = 0 ; i len ; i++)
- buffer[i] = i2c_raw_read(base, chip, addr + i);
-
+ for (i = 0 ; i len ; i++) {
+ ret = i2c_raw_read(base, chip, addr + i);
+ if (ret 0)
+ return -1;
+ buffer[i] = ret 0xff;
+ }
return 0;
}
@@ -327,8 +339,8 @@ int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int
len)
{
int i = 0;
for (i = 0; i len ; i++)
- i2c_raw_write(base, chip, addr + i, buffer[i]);
-
+ if (i2c_raw_write(base, chip, addr + i, buffer[i]) != 0)
+ return -1;
return 0;
}
--
1.7.9.5
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[U-Boot] [PATCH v2 8/9] arm: rmobile: kzm9g: enable I2C1
Supply clock to I2C1 and release resetting. Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp --- Changes for v2: - new board/kmc/kzm9g/kzm9g.c |5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c index 0679be6..93ca9d7 100644 --- a/board/kmc/kzm9g/kzm9g.c +++ b/board/kmc/kzm9g/kzm9g.c @@ -43,6 +43,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SMSTPCR1_CMT0 (1 24) #define SMSTPCR1_I2C0 (1 16) #define SMSTPCR3_USB (1 22) +#define SMSTPCR3_I2C1 (1 23) #define PORT32CR (0xE6051020) #define PORT33CR (0xE6051021) @@ -300,8 +301,8 @@ int board_early_init_f(void) clrbits_le32(cpg-smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); clrbits_le32(cpg_srcr-srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); - clrbits_le32(cpg-smstpcr3, SMSTPCR3_USB); - clrbits_le32(cpg_srcr-srcr3, SMSTPCR3_USB); + clrbits_le32(cpg-smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); + clrbits_le32(cpg_srcr-srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); writel(VCLKCR1_D, cpg-vclkcr1); /* Setup SCIF4 / workaround */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 3/9] i2c: sh_i2c.c: adjust for SH73A0
Adjust i2c_raw_read() in sh_i2c.c to work for SH73A0.
After this patch, i2c md and i2c mw command on U-Boot work properly on
KZM-A9-GT board.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
Changes for v2:
- none
drivers/i2c/sh_i2c.c|4
include/configs/kzm9g.h |2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index 03dfa7a..6c6a141 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -151,8 +151,12 @@ static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
{
u8 ret;
+#if defined(CONFIG_SH73A0)
+ i2c_set_addr(base, id, reg, 0);
+#else
i2c_set_addr(base, id, reg, 1);
udelay(100);
+#endif
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), base-iccr);
irq_dte(base);
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
index 8877516..abeab69 100644
--- a/include/configs/kzm9g.h
+++ b/include/configs/kzm9g.h
@@ -164,7 +164,7 @@
#define CONFIG_SYS_I2C_SLAVE(0x7F)
#define CONFIG_SH_I2C_DATA_HIGH (4)
#define CONFIG_SH_I2C_DATA_LOW (5)
-#define CONFIG_SH_I2C_CLOCK (4166)
+#define CONFIG_SH_I2C_CLOCK (10400) /* 104 MHz */
#define CONFIG_SH_I2C_BASE0 (0xE682)
#define CONFIG_SH_I2C_BASE1 (0xE6822000)
--
1.7.9.5
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[U-Boot] [PATCH v2 2/9] i2c: sh_i2c.c: correct BUSY bit define in ICSR
Correct BUSY bit define in ICSR from (13) to (14). Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp --- Changes for v2: - none drivers/i2c/sh_i2c.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index b98fce5..03dfa7a 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -43,7 +43,7 @@ static struct sh_i2c *base; #define SH_I2C_ICCR_SCP(1 0) /* ICSR / ICIC */ -#define SH_IC_BUSY (1 3) +#define SH_IC_BUSY (1 4) #define SH_IC_TACK (1 2) #define SH_IC_WAIT (1 1) #define SH_IC_DTE (1 0) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 5/9] i2c: sh_i2c: enable i2c_probe
Before this patch i2c_probe() always returned 0 and i2c probe command did not
work properly.
Modify i2c_set_addr() to check TACK when waiting DTE and make i2c_probe() call
this function.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
Changes for v2:
- new
drivers/i2c/sh_i2c.c | 29 -
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index d524619..25dbc43 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -85,6 +85,21 @@ static void irq_dte(struct sh_i2c *base)
}
}
+static int irq_dte_with_tack(struct sh_i2c *base)
+{
+ int i;
+ int ret = 0;
+
+ for (i = 0 ; i IRQ_WAIT ; i++) {
+ if (SH_IC_DTE readb(base-icsr))
+ break;
+ if (SH_IC_TACK readb(base-icsr))
+ return -1;
+ udelay(10);
+ }
+ return ret;
+}
+
static void irq_busy(struct sh_i2c *base)
{
int i;
@@ -96,9 +111,9 @@ static void irq_busy(struct sh_i2c *base)
}
}
-static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
+static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
{
- u8 icic = 0;
+ u8 icic = SH_IC_TACK;
writeb(readb(base-iccr) ~SH_I2C_ICCR_ICE, base-iccr);
writeb(readb(base-iccr) | SH_I2C_ICCR_ICE, base-iccr);
@@ -116,14 +131,18 @@ static void i2c_set_addr(struct sh_i2c *base, u8 id, u8
reg, int stop)
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), base-iccr);
irq_dte(base);
+ writeb(readb(base-icsr) ~SH_IC_TACK, base-icsr);
writeb(id 1, base-icdr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
writeb(reg, base-icdr);
if (stop)
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), base-iccr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
+ return 0;
}
static void i2c_finish(struct sh_i2c *base)
@@ -321,5 +340,5 @@ int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int
len)
*/
int i2c_probe(u8 chip)
{
- return 0;
+ return i2c_set_addr(base, chip, 0, 1);
}
--
1.7.9.5
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Re: [U-Boot] [PATCH 1/2] mx6q: Factor out common DDR3 init code
Am 12/09/2012 04:42, schrieb Liu Hui-R64343: -Original Message- From: Fabio Estevam [mailto:feste...@gmail.com] Sent: Wednesday, September 12, 2012 10:33 AM To: Liu Hui-R64343 Cc: Estevam Fabio-R49496; sba...@denx.de; u-boot@lists.denx.de Subject: Re: [U-Boot] [PATCH 1/2] mx6q: Factor out common DDR3 init code On Tue, Sep 11, 2012 at 11:26 PM, Liu Hui-R64343 r64...@freescale.com wrote: -Original Message- From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Fabio Estevam Sent: Wednesday, September 12, 2012 2:33 AM To: sba...@denx.de Cc: Estevam Fabio-R49496; u-boot@lists.denx.de Subject: [U-Boot] [PATCH 1/2] mx6q: Factor out common DDR3 init code Factor out common DDR3 initialization code, allowing easier maintainance of such scripts. Are you sure that we can use on DDR3 script to cover 3 kind of boards: ARM2/Sabrelite/SabreSD? Did you do the DDR stress test? Yes, mtest runs fine. mtest is not enough, you need run FSL DDR stress test tool. Then you are saying the *current* configuration in u-boot is already buggy. Fabio has only moved the setup but the boards use now the same configuration. Can you tell us which problem you have found with the current code ? Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RESEND PATCH v2 0/9] i2c for R-mobile
Some mails seems to be missing. I am sending again.. Hi, Iwamatsu-san Hello, Heiko Iwamatu-san, thank you for review. This is v2 patch for sh_i2c. Now i2c dev and i2c probe also work properly on KZM-A9-GT board. I think this modification is common for R-mobile, but I have SH73A0 document only. Iwamatu-san, please review this. This patch set is based on arm/rmobile branch of u-boot-sh.git. Tetsuyuki Kobayashi (9): i2c: sh_i2c.c: support iccl and icch extension i2c: sh_i2c.c: correct BUSY bit define in ICSR i2c: sh_i2c.c: adjust for SH73A0 i2c: sh_i2c.c: support I2C2, I2C3 and I2C4 i2c: sh_i2c: enable i2c_probe i2c: sh_i2c.c: check error in i2c_read and i2c_write i2c: sh_i2c.c: remove unused function arm: rmobile: kzm9g: enable I2C1 arm: rmobile: kzm9g: enable I2C2 board/kmc/kzm9g/kzm9g.c |7 ++- drivers/i2c/sh_i2c.c| 120 +-- include/configs/kzm9g.h |8 +++- 3 files changed, 95 insertions(+), 40 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/9] i2c: sh_i2c.c: support iccl and icch extension
R-mobile SoC (at least SH73A0) has extension bits to store 8th bit of iccl and
icch.
This patch add support for the extentin bits.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
Changes for v2:
- define CONFIG_SH_I2C_8BIT at board config file and replace HAS_ICIC67.
drivers/i2c/sh_i2c.c| 30 ++
include/configs/kzm9g.h |1 +
2 files changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index fd8cb92..b98fce5 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -48,7 +48,13 @@ static struct sh_i2c *base;
#define SH_IC_WAIT (1 1)
#define SH_IC_DTE (1 0)
-static u8 iccl, icch;
+#ifdef CONFIG_SH_I2C_8BIT
+/* store 8th bit of iccl and icch in ICIC register */
+#define SH_I2C_ICIC_ICCLB8 (1 7)
+#define SH_I2C_ICIC_ICCHB8 (1 6)
+#endif
+
+static u16 iccl, icch;
#define IRQ_WAIT 1000
@@ -92,12 +98,20 @@ static void irq_busy(struct sh_i2c *base)
static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
{
+ u8 icic = 0;
+
writeb(readb(base-iccr) ~SH_I2C_ICCR_ICE, base-iccr);
writeb(readb(base-iccr) | SH_I2C_ICCR_ICE, base-iccr);
- writeb(iccl, base-iccl);
- writeb(icch, base-icch);
- writeb(0, base-icic);
+ writeb(iccl 0xff, base-iccl);
+ writeb(icch 0xff, base-icch);
+#ifdef CONFIG_SH_I2C_8BIT
+ if (iccl 0xff)
+ icic |= SH_I2C_ICIC_ICCLB8;
+ if (icch 0xff)
+ icic |= SH_I2C_ICIC_ICCHB8;
+#endif
+ writeb(icic, base-icic);
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), base-iccr);
irq_dte(base);
@@ -222,18 +236,18 @@ void i2c_init(int speed, int slaveaddr)
denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
tmp = num * 10 / denom;
if (tmp % 10 = 5)
- iccl = (u8)((num/denom) + 1);
+ iccl = (u16)((num/denom) + 1);
else
- iccl = (u8)(num/denom);
+ iccl = (u16)(num/denom);
/* Calculate the value for icch. From the data sheet:
icch = (p clock / transfer rate) * (H / (L + H)) */
num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
tmp = num * 10 / denom;
if (tmp % 10 = 5)
- icch = (u8)((num/denom) + 1);
+ icch = (u16)((num/denom) + 1);
else
- icch = (u8)(num/denom);
+ icch = (u16)(num/denom);
}
/*
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
index a1ae718..8877516 100644
--- a/include/configs/kzm9g.h
+++ b/include/configs/kzm9g.h
@@ -155,6 +155,7 @@
/* I2C */
#define CONFIG_CMD_I2C
#define CONFIG_SH_I2C 1
+#define CONFIG_SH_I2C_8BIT
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS (2)
--
1.7.9.5
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[U-Boot] [PATCH v2 2/9] i2c: sh_i2c.c: correct BUSY bit define in ICSR
Correct BUSY bit define in ICSR from (13) to (14). Acked-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp --- Changes for v2: - none drivers/i2c/sh_i2c.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index b98fce5..03dfa7a 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -43,7 +43,7 @@ static struct sh_i2c *base; #define SH_I2C_ICCR_SCP(1 0) /* ICSR / ICIC */ -#define SH_IC_BUSY (1 3) +#define SH_IC_BUSY (1 4) #define SH_IC_TACK (1 2) #define SH_IC_WAIT (1 1) #define SH_IC_DTE (1 0) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 3/9] i2c: sh_i2c.c: adjust for SH73A0
Adjust i2c_raw_read() in sh_i2c.c to work for SH73A0.
After this patch, i2c md and i2c mw command on U-Boot work properly on
KZM-A9-GT board.
Acked-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
Changes for v2:
- none
drivers/i2c/sh_i2c.c|4
include/configs/kzm9g.h |2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index 03dfa7a..6c6a141 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -151,8 +151,12 @@ static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
{
u8 ret;
+#if defined(CONFIG_SH73A0)
+ i2c_set_addr(base, id, reg, 0);
+#else
i2c_set_addr(base, id, reg, 1);
udelay(100);
+#endif
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), base-iccr);
irq_dte(base);
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
index 8877516..abeab69 100644
--- a/include/configs/kzm9g.h
+++ b/include/configs/kzm9g.h
@@ -164,7 +164,7 @@
#define CONFIG_SYS_I2C_SLAVE(0x7F)
#define CONFIG_SH_I2C_DATA_HIGH (4)
#define CONFIG_SH_I2C_DATA_LOW (5)
-#define CONFIG_SH_I2C_CLOCK (4166)
+#define CONFIG_SH_I2C_CLOCK (10400) /* 104 MHz */
#define CONFIG_SH_I2C_BASE0 (0xE682)
#define CONFIG_SH_I2C_BASE1 (0xE6822000)
--
1.7.9.5
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[U-Boot] [PATCH v2 4/9] i2c: sh_i2c.c: support I2C2, I2C3 and I2C4
sh_i2c.c support I2C0 and I2C1. This patch extends it to I2C4. Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp --- Changes for v2: - new drivers/i2c/sh_i2c.c| 15 +++ include/configs/kzm9g.h |5 - 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index 6c6a141..d524619 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -200,6 +200,21 @@ int i2c_set_bus_num(unsigned int bus) case 1: base = (void *)CONFIG_SH_I2C_BASE1; break; +#ifdef CONFIG_SH_I2C_BASE2 + case 2: + base = (void *)CONFIG_SH_I2C_BASE2; + break; +#endif +#ifdef CONFIG_SH_I2C_BASE3 + case 3: + base = (void *)CONFIG_SH_I2C_BASE3; + break; +#endif +#ifdef CONFIG_SH_I2C_BASE4 + case 4: + base = (void *)CONFIG_SH_I2C_BASE4; + break; +#endif default: return -1; } diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index abeab69..6a0b6c5 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -158,7 +158,7 @@ #define CONFIG_SH_I2C_8BIT #define CONFIG_HARD_I2C #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_MAX_I2C_BUS (2) +#define CONFIG_SYS_MAX_I2C_BUS (5) #define CONFIG_SYS_I2C_MODULE #define CONFIG_SYS_I2C_SPEED(10) /* 100 kHz */ #define CONFIG_SYS_I2C_SLAVE(0x7F) @@ -167,5 +167,8 @@ #define CONFIG_SH_I2C_CLOCK (10400) /* 104 MHz */ #define CONFIG_SH_I2C_BASE0 (0xE682) #define CONFIG_SH_I2C_BASE1 (0xE6822000) +#define CONFIG_SH_I2C_BASE2 (0xE6824000) +#define CONFIG_SH_I2C_BASE3 (0xE6826000) +#define CONFIG_SH_I2C_BASE4 (0xE6828000) #endif /* __KZM9G_H */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 5/9] i2c: sh_i2c: enable i2c_probe
Before this patch i2c_probe() always returned 0 and i2c probe command did not
work properly.
Modify i2c_set_addr() to check TACK when waiting DTE and make i2c_probe() call
this function.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
Changes for v2:
- new
drivers/i2c/sh_i2c.c | 29 -
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index d524619..25dbc43 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -85,6 +85,21 @@ static void irq_dte(struct sh_i2c *base)
}
}
+static int irq_dte_with_tack(struct sh_i2c *base)
+{
+ int i;
+ int ret = 0;
+
+ for (i = 0 ; i IRQ_WAIT ; i++) {
+ if (SH_IC_DTE readb(base-icsr))
+ break;
+ if (SH_IC_TACK readb(base-icsr))
+ return -1;
+ udelay(10);
+ }
+ return ret;
+}
+
static void irq_busy(struct sh_i2c *base)
{
int i;
@@ -96,9 +111,9 @@ static void irq_busy(struct sh_i2c *base)
}
}
-static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
+static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
{
- u8 icic = 0;
+ u8 icic = SH_IC_TACK;
writeb(readb(base-iccr) ~SH_I2C_ICCR_ICE, base-iccr);
writeb(readb(base-iccr) | SH_I2C_ICCR_ICE, base-iccr);
@@ -116,14 +131,18 @@ static void i2c_set_addr(struct sh_i2c *base, u8 id, u8
reg, int stop)
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), base-iccr);
irq_dte(base);
+ writeb(readb(base-icsr) ~SH_IC_TACK, base-icsr);
writeb(id 1, base-icdr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
writeb(reg, base-icdr);
if (stop)
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), base-iccr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
+ return 0;
}
static void i2c_finish(struct sh_i2c *base)
@@ -321,5 +340,5 @@ int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int
len)
*/
int i2c_probe(u8 chip)
{
- return 0;
+ return i2c_set_addr(base, chip, 0, 1);
}
--
1.7.9.5
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[U-Boot] [PATCH v2 6/9] i2c: sh_i2c.c: check error in i2c_read and i2c_write
Before this patch, i2c_{read,write} always returned 0.
Check TACK in i2c_raw_{read,write} so that i2c_{read,write} return non-zero
when error.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
Changes for v2:
- new
drivers/i2c/sh_i2c.c | 44
1 file changed, 28 insertions(+), 16 deletions(-)
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index 25dbc43..e3ee804 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -151,29 +151,35 @@ static void i2c_finish(struct sh_i2c *base)
writeb(readb(base-iccr) ~SH_I2C_ICCR_ICE, base-iccr);
}
-static void i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val)
+static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val)
{
- i2c_set_addr(base, id, reg, 0);
+ if (i2c_set_addr(base, id, reg, 0) != 0)
+ return -1;
udelay(10);
writeb(val, base-icdr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), base-iccr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
irq_busy(base);
i2c_finish(base);
+ return 0;
}
-static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
+static int i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
{
- u8 ret;
+ int ret;
#if defined(CONFIG_SH73A0)
- i2c_set_addr(base, id, reg, 0);
+ if (i2c_set_addr(base, id, reg, 0) != 0)
+ return -1;
#else
- i2c_set_addr(base, id, reg, 1);
+ if (i2c_set_addr(base, id, reg, 1) != 0)
+ return -1;
udelay(100);
#endif
@@ -181,12 +187,14 @@ static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
irq_dte(base);
writeb(id 1 | 0x01, base-icdr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), base-iccr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
- ret = readb(base-icdr);
+ ret = readb(base-icdr) 0xff;
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), base-iccr);
readb(base-icdr); /* Dummy read */
@@ -303,10 +311,14 @@ void i2c_init(int speed, int slaveaddr)
*/
int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
{
+ int ret;
int i = 0;
- for (i = 0 ; i len ; i++)
- buffer[i] = i2c_raw_read(base, chip, addr + i);
-
+ for (i = 0 ; i len ; i++) {
+ ret = i2c_raw_read(base, chip, addr + i);
+ if (ret 0)
+ return -1;
+ buffer[i] = ret 0xff;
+ }
return 0;
}
@@ -327,8 +339,8 @@ int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int
len)
{
int i = 0;
for (i = 0; i len ; i++)
- i2c_raw_write(base, chip, addr + i, buffer[i]);
-
+ if (i2c_raw_write(base, chip, addr + i, buffer[i]) != 0)
+ return -1;
return 0;
}
--
1.7.9.5
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[U-Boot] [PATCH v2 7/9] i2c: sh_i2c.c: remove unused function
irq_wait() was not used. So removed it to elminate compiler warnings.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
Changes for v2:
- new
drivers/i2c/sh_i2c.c | 16
1 file changed, 16 deletions(-)
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index e3ee804..60bad52 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -58,22 +58,6 @@ static u16 iccl, icch;
#define IRQ_WAIT 1000
-static void irq_wait(struct sh_i2c *base)
-{
- int i;
- u8 status;
-
- for (i = 0 ; i IRQ_WAIT ; i++) {
- status = readb(base-icsr);
- if (SH_IC_WAIT status)
- break;
-
- udelay(10);
- }
-
- writeb(status ~SH_IC_WAIT, base-icsr);
-}
-
static void irq_dte(struct sh_i2c *base)
{
int i;
--
1.7.9.5
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[U-Boot] [PATCH v2 8/9] arm: rmobile: kzm9g: enable I2C1
Supply clock to I2C1 and release resetting. Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp --- Changes for v2: - new board/kmc/kzm9g/kzm9g.c |5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c index 0679be6..93ca9d7 100644 --- a/board/kmc/kzm9g/kzm9g.c +++ b/board/kmc/kzm9g/kzm9g.c @@ -43,6 +43,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SMSTPCR1_CMT0 (1 24) #define SMSTPCR1_I2C0 (1 16) #define SMSTPCR3_USB (1 22) +#define SMSTPCR3_I2C1 (1 23) #define PORT32CR (0xE6051020) #define PORT33CR (0xE6051021) @@ -300,8 +301,8 @@ int board_early_init_f(void) clrbits_le32(cpg-smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); clrbits_le32(cpg_srcr-srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); - clrbits_le32(cpg-smstpcr3, SMSTPCR3_USB); - clrbits_le32(cpg_srcr-srcr3, SMSTPCR3_USB); + clrbits_le32(cpg-smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); + clrbits_le32(cpg_srcr-srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); writel(VCLKCR1_D, cpg-vclkcr1); /* Setup SCIF4 / workaround */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 9/9] arm: rmobile: kzm9g: enable I2C2
Set gpio config for I2C2. Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp --- Changes for v2: - new board/kmc/kzm9g/kzm9g.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c index 93ca9d7..22f581a 100644 --- a/board/kmc/kzm9g/kzm9g.c +++ b/board/kmc/kzm9g/kzm9g.c @@ -370,6 +370,8 @@ int board_init(void) gpio_direction_output(GPIO_PORT15, 1); /* I2C */ + gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL); + gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL); gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL); gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL); -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch] make reset_cpu nonreturn.
Hi! From: Dinh Nguyen dingu...@altera.com Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Applied on top of trini/WIP/spl-improvements v6 [...] __noreturn attribute to reset_cpu() is still missing, but that's a minor thing. Hmm, I thought about it, but I guess the right solution is below. You sure it's propagated through to the function (aka. that it's not ignored) ? If so, WFM. I think so. It is actually when optimizing the caller when nonreturn is important... Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2] ARM: Add Altera SOCFPGA Cyclone5
Hi! On 09/11/2012 02:21 AM, Pavel Machek wrote: From: Dinh Nguyen dingu...@altera.com Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Applied on top of trini/WIP/spl-improvements v6 [...] __noreturn attribute to reset_cpu() is still missing, but that's a minor thing. Plus, I guess these should be deleted. We already have prototype in common arch/arm/include/asm/arch-kirkwood/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-orion5x/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-socfpga/reset_manager.h:void reset_cpu(ulong addr); Yes, good catch. What needs to be done to get the socfpga patches merged? As the patches are based upon the SPL framework patches from Tom Rini, Tom's patches need to get included first. AFAICT, this SPL framework will not go into mainline for the upcoming release, but will be pushed into next, once it opens. Would it make sense to push the changes without SPL, then? SPL is minority... Pavel diff --git a/MAINTAINERS b/MAINTAINERS index c5a6f2f..df48dea 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -765,6 +765,11 @@ Nagendra T S nagen...@mistralsolutions.com am3517_craneARM ARMV7 (AM35x SoC) +Dinh Nguyen dingu...@altera.com +Chin Liang See cl...@altera.com + + socfpga socfpga_cyclone5 + Kyungmin Park kyungmin.p...@samsung.com apollon ARM1136EJS diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile new file mode 100644 index 000..376a4bd --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# Copyright (C) 2012 Altera Corporation www.altera.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(SOC).o + +SOBJS := lowlevel_init.o +COBJS-y:= misc.o timer.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +all:$(obj).depend $(LIB) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/arm/cpu/armv7/socfpga/config.mk b/arch/arm/cpu/armv7/socfpga/config.mk new file mode 100644 index 000..b72ed1e --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/config.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed as is WITHOUT ANY WARRANTY of any +# kind, whether express or implied; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +ifndef CONFIG_SPL_BUILD +ALL-y += $(obj)u-boot.img +endif diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S new file mode 100644 index 000..001b37d --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2012 Altera Corporation www.altera.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public
Re: [U-Boot] [PATCH 2/2] bfin: Fix warning in bfin_mac
Dear Marek Vasut,
The buf variable in bfin_mac.c is not used and produces warning,
fix it.
bfin_mac.c: In function 'bfin_EMAC_send':
bfin_mac.c:125:16: warning: variable 'buf' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Mike Frysinger vap...@gentoo.org
Guess I should have Cced Joe too ...
---
drivers/net/bfin_mac.c |2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c
index c63398e..0ffd59d 100644
--- a/drivers/net/bfin_mac.c
+++ b/drivers/net/bfin_mac.c
@@ -122,8 +122,6 @@ static int bfin_EMAC_send(struct eth_device *dev, void
*packet, int length) {
int i;
int result = 0;
- unsigned int *buf;
- buf = (unsigned int *)packet;
if (length = 0) {
printf(Ethernet: bad packet size: %d\n, length);
Best regards,
Marek Vasut
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[U-Boot] Pull request - microblaze
Dear Wolfgang, please pull the following changes to your tree. Thanks, Michal The following changes since commit a6f0c4faa4c65a7b7048b12c9d180d7e1aad1721: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-avr32 are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git master Michal Simek (10): block: systemace: Simplify base and width initialization serial: Support serial multi for Microblaze serial: uartlite: Init all uartlites for serial multi microblaze: Add support for device tree driven board configuration microblaze: board: Remove compilation warning microblaze: intc: Registering interrupt should return value microblaze: intc: Coding style cleanup microblaze: timer: Prepare for device-tree initialization microblaze: Clean microblaze initialization microblaze: board: Use bi_flashstart instead of CONFIG_SYS_FLASH_BASE Stephan Linz (1): spi: xilinx: Remove unused variable arch/microblaze/config.mk |2 + arch/microblaze/cpu/interrupts.c | 42 ++-- arch/microblaze/cpu/start.S|2 +- arch/microblaze/cpu/timer.c| 69 ++- arch/microblaze/cpu/u-boot.lds |1 + arch/microblaze/include/asm/global_data.h |1 + arch/microblaze/include/asm/microblaze_intc.h | 11 +++- arch/microblaze/include/asm/microblaze_timer.h |3 + arch/microblaze/include/asm/processor.h|3 + arch/microblaze/lib/board.c| 59 ++--- .../xilinx/microblaze-generic/microblaze-generic.c |9 +++ drivers/block/systemace.c | 38 +++ drivers/serial/serial_xuartlite.c | 34 ++ drivers/spi/xilinx_spi.c |1 - include/configs/microblaze-generic.h | 12 +--- include/serial.h |3 +- 16 files changed, 171 insertions(+), 119 deletions(-) -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4 v2] net: Add driver for Zynq Gem IP
On 08/16/2012 08:30 AM, Michal Simek wrote: Device driver for Zynq Gem IP. Signed-off-by: Michal Simek mon...@monstr.eu CC: Joe Hershberger joe.hershber...@gmail.com --- v2: Remove phylib protection Rename driver file name xilinx_gem to zynq_gem Rename XEMACPSS to ZYNQ_GEM Rename gemac_priv to zynq_gem_priv Rename gem_regs to zynq_gem_regs Add zynq_ prefix to several functions Remove phy detection Rename driver name XGem to Gem Change setup_mac function to reflect u-boot style --- drivers/net/Makefile |1 + drivers/net/zynq_gem.c | 453 include/netdev.h |2 +- 3 files changed, 455 insertions(+), 1 deletions(-) create mode 100644 drivers/net/zynq_gem.c Joe: I am not sure if you have seen this patch. Can you please review it and comment it. If is ok, I would like to ask you to add this patch to your net custodian tree or sending me your ACK. Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4 v2] serial: Add Zynq serial driver
On 08/16/2012 08:30 AM, Michal Simek wrote: The driver is used on Xilinx Zynq platform. Signed-off-by: Michal Simek mon...@monstr.eu --- v2: Use Zynq name instead of Dragonfire and XPSS/XDFUART Rename driver name Remove driver description --- drivers/serial/Makefile |1 + drivers/serial/serial_zynq.c | 200 ++ 2 files changed, 201 insertions(+), 0 deletions(-) create mode 100644 drivers/serial/serial_zynq.c Joe: you have reviewed the first version of this patch. Can you comment it? Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] ARM: at91sam9x5: enable MCI0 support for 9x5ek board.
Hi, Voice
On 9/10/2012 4:07 PM, Bo Shen wrote:
Hi Josh,
On 9/7/2012 18:39, Josh Wu wrote:
Signed-off-by: Josh Wu josh...@atmel.com
---
arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c | 13 +
board/atmel/at91sam9x5ek/at91sam9x5ek.c | 16
include/configs/at91sam9x5ek.h |8
3 files changed, 37 insertions(+)
I think add MCI1 support at the same time will be better. Otherwise,
Acked-by: voice.s...@atmel.com
Tested-by: voice.s...@atmel.com
Thanks for the testing. If this patch will be accepted. then I will add
MCI1 support in later patch.
Best Regards,
Josh Wu
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
index 6d77219..3608e7c 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
@@ -230,3 +230,16 @@ void at91_macb_hw_init(void)
#endif
}
#endif
+
+#if defined(CONFIG_GENERIC_ATMEL_MCI)
+void at91_mci_hw_init(void)
+{
+/* Initialize the MCI0 */
+at91_set_a_periph(AT91_PIO_PORTA, 17, 1);/* MCCK */
+at91_set_a_periph(AT91_PIO_PORTA, 16, 1);/* MCCDA */
+at91_set_a_periph(AT91_PIO_PORTA, 15, 1);/* MCDA0 */
+at91_set_a_periph(AT91_PIO_PORTA, 18, 1);/* MCDA1 */
+at91_set_a_periph(AT91_PIO_PORTA, 19, 1);/* MCDA2 */
+at91_set_a_periph(AT91_PIO_PORTA, 20, 1);/* MCDA3 */
+}
+#endif
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index 06028aa..d1f05ef 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -42,6 +42,9 @@
#ifdef CONFIG_ATMEL_SPI
#include spi.h
#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+#include mmc.h
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -258,6 +261,19 @@ void spi_cs_deactivate(struct spi_slave *slave)
}
#endif /* CONFIG_ATMEL_SPI */
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+/* Enable clock */
+struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+writel(1 ATMEL_ID_HSMCI0, pmc-pcer);
+
+at91_mci_hw_init();
+
+return atmel_mci_init((void *)ATMEL_BASE_HSMCI0);
+}
+#endif
+
int board_early_init_f(void)
{
at91_seriald_hw_init();
diff --git a/include/configs/at91sam9x5ek.h
b/include/configs/at91sam9x5ek.h
index 1ceb31a..974e08f 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -136,6 +136,14 @@
#define CONFIG_CMD_UBIFS
#endif
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_DOS_PARTITION
+
/* Ethernet */
#define CONFIG_MACB
#define CONFIG_RMII
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Re: [U-Boot] [PATCH 3/4 v2] arm: Support new Xilinx Zynq platform
On 08/16/2012 08:30 AM, Michal Simek wrote: Add timer driver. Signed-off-by: Michal Simek mon...@monstr.eu --- v2: Move lowlevel_init.S from board to cpu folder Remove XPSS prefix Rename XSCUTIMER - SCUTIMER Keep timer in zynq folder till ARM custodian comments it. --- arch/arm/cpu/armv7/zynq/Makefile| 52 +++ arch/arm/cpu/armv7/zynq/lowlevel_init.S | 27 ++ arch/arm/cpu/armv7/zynq/timer.c | 151 +++ 3 files changed, 230 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/armv7/zynq/Makefile create mode 100644 arch/arm/cpu/armv7/zynq/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/zynq/timer.c We haven't got any reaction for Albert. Marek and Joe: Can you review this? And give me your ACK or NACK. Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4 v3] xilinx: Add new Zynq board
On 08/16/2012 08:30 AM, Michal Simek wrote: Add support for Xilinx Zynq board. Signed-off-by: Michal Simek mon...@monstr.eu --- v2: Forget to also add config file v3: Change name for serial driver Remove lowlevel_init from board folder Remove XPSS part from timer baseaddr Change name for Zynq gem driver Clean coding style Remove mac + ip addresses from config file Remove additional PHYs --- board/xilinx/zynq/Makefile | 54 + board/xilinx/zynq/board.c | 64 + boards.cfg |1 + include/configs/zynq.h | 110 4 files changed, 229 insertions(+), 0 deletions(-) create mode 100644 board/xilinx/zynq/Makefile create mode 100644 board/xilinx/zynq/board.c create mode 100644 include/configs/zynq.h The same for this one. Marek and Joe: Can you please review this? Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/7] S3C24XX: Add RTC driver
RTC driver for the S3C24XX SoCs.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
drivers/rtc/Makefile |1 +
drivers/rtc/s3c24xx_rtc.c | 166 +
2 files changed, 167 insertions(+)
create mode 100644 drivers/rtc/s3c24xx_rtc.c
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 8316e8f..bd8b1eb 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -69,6 +69,7 @@ COBJS-$(CONFIG_RTC_RTC4543) += rtc4543.o
COBJS-$(CONFIG_RTC_RV3029) += rv3029.o
COBJS-$(CONFIG_RTC_RX8025) += rx8025.o
COBJS-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o
+COBJS-$(CONFIG_RTC_S3C24XX) += s3c24xx_rtc.o
COBJS-$(CONFIG_RTC_S3C44B0) += s3c44b0_rtc.o
COBJS-$(CONFIG_RTC_X1205) += x1205.o
diff --git a/drivers/rtc/s3c24xx_rtc.c b/drivers/rtc/s3c24xx_rtc.c
new file mode 100644
index 000..3844e44
--- /dev/null
+++ b/drivers/rtc/s3c24xx_rtc.c
@@ -0,0 +1,166 @@
+/*
+ * (C) Copyright 2012 INOV - INESC Inovacao
+ * Jose Goncalves jose.goncal...@inov.pt
+ *
+ * Based on drivers/rtc/s3c24x0_rtc.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+
+#if defined(CONFIG_CMD_DATE)
+
+#include rtc.h
+#include asm/io.h
+#include asm/arch/s3c24xx_cpu.h
+
+static inline void rtc_access_enable(void)
+{
+ s3c24xx_rtc *const rtc = s3c24xx_get_base_rtc();
+ uchar rtccon;
+
+ rtccon = readb(rtc-rtccon);
+ rtccon |= 0x01;
+ writeb(rtccon, rtc-rtccon);
+}
+
+static inline void rtc_access_disable(void)
+{
+ s3c24xx_rtc *const rtc = s3c24xx_get_base_rtc();
+ uchar rtccon;
+
+ rtccon = readb(rtc-rtccon);
+ rtccon = ~0x01;
+ writeb(rtccon, rtc-rtccon);
+}
+
+/* - */
+
+int rtc_get(struct rtc_time *tmp)
+{
+ s3c24xx_rtc *const rtc = s3c24xx_get_base_rtc();
+ uchar sec, min, hour, mday, wday, mon, year;
+ int have_retried = 0;
+
+ rtc_access_enable();
+
+ /* Read RTC registers */
+retry_get_time:
+ min = readb(rtc-bcdmin);
+ hour = readb(rtc-bcdhour);
+ mday = readb(rtc-bcddate);
+ wday = readb(rtc-bcdday);
+ mon = readb(rtc-bcdmon);
+ year = readb(rtc-bcdyear);
+ sec = readb(rtc-bcdsec);
+
+ /* The only way to work out whether the RTC was mid-update
+* when we read it is to check the seconds counter.
+* If it's zero, then we re-try the entire read.
+*/
+ if (rtc-bcdsec == 0 !have_retried) {
+ have_retried = 1;
+ goto retry_get_time;
+ }
+
+ rtc_access_disable();
+
+ debug(Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x
+ hr: %02x min: %02x sec: %02x\n,
+ year, mon, mday, wday, hour, min, sec);
+
+ tmp-tm_sec = bcd2bin(sec 0x7F);
+ tmp-tm_min = bcd2bin(min 0x7F);
+ tmp-tm_hour = bcd2bin(hour 0x3F);
+ tmp-tm_mday = bcd2bin(mday 0x3F);
+ tmp-tm_wday = bcd2bin(wday 0x07);
+ tmp-tm_mon = bcd2bin(mon 0x1F);
+ tmp-tm_year = bcd2bin(year);
+ if (tmp-tm_year 70)
+ tmp-tm_year += 2000;
+ else
+ tmp-tm_year += 1900;
+ tmp-tm_yday = 0;
+ tmp-tm_isdst = 0;
+
+ debug(Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n,
+ tmp-tm_year, tmp-tm_mon, tmp-tm_mday, tmp-tm_wday,
+ tmp-tm_hour, tmp-tm_min, tmp-tm_sec);
+
+ return 0;
+}
+
+int rtc_set(struct rtc_time *tmp)
+{
+ s3c24xx_rtc *const rtc = s3c24xx_get_base_rtc();
+ uchar sec, min, hour, mday, wday, mon, year;
+
+ debug(Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n,
+ tmp-tm_year, tmp-tm_mon, tmp-tm_mday, tmp-tm_wday,
+ tmp-tm_hour, tmp-tm_min, tmp-tm_sec);
+
+ if (tmp-tm_year 1970 || tmp-tm_year 2069) {
+ puts(ERROR: year should be between 1970 and 2069!\n);
+ return -1;
+ }
+
+ year = bin2bcd(tmp-tm_year % 100);
+ mon = bin2bcd(tmp-tm_mon);
+ wday = bin2bcd(tmp-tm_wday);
+ mday = bin2bcd(tmp-tm_mday);
+ hour = bin2bcd(tmp-tm_hour);
+ min = bin2bcd(tmp-tm_min);
+ sec =
[U-Boot] [PATCH 6/7] Add u-boot-ubl.bin target to the Makefile
Samsung's S3C24XX SoCs need this in order to generate a binary image with the
SPL and U-Boot concatenated.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Makefile |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/Makefile b/Makefile
index 058fb53..595b5f6 100644
--- a/Makefile
+++ b/Makefile
@@ -442,13 +442,14 @@ $(obj)u-boot.sha1:$(obj)u-boot.bin
$(obj)u-boot.dis: $(obj)u-boot
$(OBJDUMP) -d $ $@
-$(obj)u-boot.ubl: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+$(obj)u-boot-ubl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary
$(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin
$(obj)u-boot-ubl.bin
+ rm $(obj)spl/u-boot-spl-pad.bin
+
+$(obj)u-boot.ubl: $(obj)u-boot-ubl.bin
$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
-e $(CONFIG_SYS_TEXT_BASE) -d $(obj)u-boot-ubl.bin
$(obj)u-boot.ubl
- rm $(obj)u-boot-ubl.bin
- rm $(obj)spl/u-boot-spl-pad.bin
$(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(obj)tools/mkimage -s -n $(if
$(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),/dev/null) \
--
1.7.9.5
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/7] ARM: fix relocation on ARM926EJS
Jumping to board_init_r is not performed due to a bug on address computation. Relocation offsets are not needed when building SPL. Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt --- arch/arm/cpu/arm926ejs/start.S |4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 6f05f1a..2da5342 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -325,7 +325,7 @@ _nand_boot_ofs: .word nand_boot #else ldr r0, _board_init_r_ofs - ldr r1, _TEXT_BASE + adr r1, _start add lr, r0, r1 add lr, lr, r9 /* setup parameters for board_init_r */ @@ -338,12 +338,14 @@ _board_init_r_ofs: .word board_init_r - _start #endif +#ifndef CONFIG_SPL_BUILD _rel_dyn_start_ofs: .word __rel_dyn_start - _start _rel_dyn_end_ofs: .word __rel_dyn_end - _start _dynsym_start_ofs: .word __dynsym_start - _start +#endif /* * -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/7] S3C24XX: Add serial driver
Serial driver for the S3C24XX SoCs.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
drivers/serial/Makefile |1 +
drivers/serial/s3c24xx_serial.c | 146 +++
2 files changed, 147 insertions(+)
create mode 100644 drivers/serial/s3c24xx_serial.c
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 65d0f23..2cbdaac 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -52,6 +52,7 @@ COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
COBJS-$(CONFIG_PXA_SERIAL) += serial_pxa.o
COBJS-$(CONFIG_SA1100_SERIAL) += serial_sa1100.o
COBJS-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
+COBJS-$(CONFIG_S3C24XX_SERIAL) += s3c24xx_serial.o
COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
diff --git a/drivers/serial/s3c24xx_serial.c b/drivers/serial/s3c24xx_serial.c
new file mode 100644
index 000..11f13a5
--- /dev/null
+++ b/drivers/serial/s3c24xx_serial.c
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2012 INOV - INESC Inovacao
+ * Jose Goncalves jose.goncal...@inov.pt
+ *
+ * Based on drivers/serial/s3c64xx.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/arch/s3c24xx_cpu.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SERIAL0
+#define UART_NRS3C24XX_UART0
+
+#elif defined(CONFIG_SERIAL1)
+#define UART_NRS3C24XX_UART1
+
+#elif defined(CONFIG_SERIAL2)
+#define UART_NRS3C24XX_UART2
+
+#elif defined(CONFIG_SERIAL3)
+#define UART_NRS3C24XX_UART3
+
+#else
+#error Bad: you didn't configure serial ...
+#endif
+
+#define barrier() asm volatile( ::: memory)
+
+/*
+ * The coefficient, used to calculate the baudrate on S3C24XX UARTs is
+ * calculated as C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
+ * however, section 2.1.10 of the S3C2416 User's Manual doesn't recommend
+ * using 1 for 1, 3 for 2, ... (2^n - 1) for n, instead, they suggest using
+ * these constants:
+ */
+static const int udivslot[] = {
+ 0x, 0x0080, 0x0808, 0x0888, 0x, 0x4924, 0x4A52, 0x54AA,
+ 0x, 0xD555, 0xD5D5, 0xDDD5, 0x, 0xDFDD, 0xDFDF, 0xFFDF,
+};
+
+void serial_setbrg(void)
+{
+ s3c24xx_uart *const uart = s3c24xx_get_base_uart(UART_NR);
+ u32 pclk;
+ u32 baudrate;
+ int i;
+
+ pclk = get_PCLK();
+ baudrate = gd-baudrate;
+
+ uart-ubrdiv = (pclk / baudrate / 16) - 1;
+ uart-udivslot = udivslot[(pclk / baudrate) % 16];
+
+ for (i = 0; i 100; i++)
+ barrier();
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+int serial_init(void)
+{
+ s3c24xx_uart *const uart = s3c24xx_get_base_uart(UART_NR);
+
+ /* FIFO enable, Tx/Rx FIFO clear */
+ uart-ufcon = 0x07;
+ uart-umcon = 0x00;
+ /* Normal mode, No parity, 1 stop bit, 8 data bits */
+ uart-ulcon = 0x03;
+ /* Polling mode */
+ uart-ucon = 0x005;
+
+ serial_setbrg();
+
+ return 0;
+}
+
+/*
+ * Read a single byte from the serial port.
+ */
+int serial_getc(void)
+{
+ s3c24xx_uart *const uart = s3c24xx_get_base_uart(UART_NR);
+
+ /* Wait for character to arrive */
+ while (!(uart-utrstat 0x1)) ;
+
+ return uart-urxh 0xff;
+}
+
+/*
+ * Output a single byte to the serial port.
+ */
+void serial_putc(const char c)
+{
+ s3c24xx_uart *const uart = s3c24xx_get_base_uart(UART_NR);
+
+ /* Wait for room in the TX FIFO */
+ while (!(uart-utrstat 0x2)) ;
+
+ uart-utxh = c;
+
+ /* If \n, also do \r */
+ if (c == '\n')
+ serial_putc('\r');
+}
+
+/*
+ * Test whether a character is in the RX buffer.
+ */
+int serial_tstc(void)
+{
+ s3c24xx_uart *const uart = s3c24xx_get_base_uart(UART_NR);
+
+ return uart-utrstat 0x1;
+}
+
+/*
+ * Output a string to the serial port.
+ */
+void serial_puts(const char *s)
+{
+ while (*s)
+ serial_putc(*s++);
+}
--
1.7.9.5
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[U-Boot] [PATCH 5/7] S3C24XX: Add NAND Flash driver
NAND Flash driver with HW ECC for the S3C24XX SoCs.
Currently it only supports SLC NAND chips.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/s3c24xx_nand.c | 269 +++
2 files changed, 270 insertions(+)
create mode 100644 drivers/mtd/nand/s3c24xx_nand.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 29dc20e..791ec44 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -60,6 +60,7 @@ COBJS-$(CONFIG_NAND_MXS) += mxs_nand.o
COBJS-$(CONFIG_NAND_NDFC) += ndfc.o
COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
+COBJS-$(CONFIG_NAND_S3C24XX) += s3c24xx_nand.o
COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
diff --git a/drivers/mtd/nand/s3c24xx_nand.c b/drivers/mtd/nand/s3c24xx_nand.c
new file mode 100644
index 000..eed72d5
--- /dev/null
+++ b/drivers/mtd/nand/s3c24xx_nand.c
@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2012 INOV - INESC Inovacao
+ * Jose Goncalves jose.goncal...@inov.pt
+ *
+ * Based on drivers/mtd/nand/s3c64xx.c and U-Boot 1.3.4 from Samsung.
+ * Supports only SLC NAND Flash chips.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include nand.h
+#include asm/io.h
+#include asm/arch/s3c24xx_cpu.h
+#include asm/errno.h
+
+#define NFCONT_ECC_ENC (118)
+#define NFCONT_WP (116)
+#define NFCONT_MECCLOCK(17)
+#define NFCONT_SECCLOCK(16)
+#define NFCONT_INITMECC(15)
+#define NFCONT_INITSECC(14)
+#define NFCONT_NCE1(12)
+#define NFCONT_NCE0(11)
+#define NFCONT_ENABLE (10)
+
+#define NFSTAT_RNB (10)
+
+#define MAX_CHIPS 2
+static int nand_cs[MAX_CHIPS] = { 0, 1 };
+
+#ifdef CONFIG_SPL_BUILD
+#define printf(arg...) do {} while (0)
+#endif
+
+static void s3c_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+ s3c24xx_nand *const nand = s3c24xx_get_base_nand();
+ u_long nfcont;
+
+ nfcont = readl(nand-nfcont);
+
+ switch (chip) {
+ case -1:
+ nfcont |= NFCONT_NCE1 | NFCONT_NCE0;
+ break;
+ case 0:
+ nfcont = ~NFCONT_NCE0;
+ break;
+ case 1:
+ nfcont = ~NFCONT_NCE1;
+ break;
+ default:
+ return;
+ }
+
+ writel(nfcont, nand-nfcont);
+}
+
+/*
+ * Hardware specific access to control-lines function
+ */
+static void s3c_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int
ctrl)
+{
+ s3c24xx_nand *const nand = s3c24xx_get_base_nand();
+ struct nand_chip *this = mtd-priv;
+
+ if (ctrl NAND_CTRL_CHANGE) {
+ if (ctrl NAND_CLE)
+ this-IO_ADDR_W = (void __iomem *)nand-nfcmmd;
+ else if (ctrl NAND_ALE)
+ this-IO_ADDR_W = (void __iomem *)nand-nfaddr;
+ else
+ this-IO_ADDR_W = (void __iomem *)nand-nfdata;
+ if (ctrl NAND_NCE)
+ s3c_nand_select_chip(mtd, *(int *)this-priv);
+ else
+ s3c_nand_select_chip(mtd, -1);
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this-IO_ADDR_W);
+}
+
+/*
+ * Function for checking device ready pin
+ */
+static int s3c_nand_device_ready(struct mtd_info *mtdinfo)
+{
+ s3c24xx_nand *const nand = s3c24xx_get_base_nand();
+
+ return readl(nand-nfstat) NFSTAT_RNB;
+}
+
+#ifdef CONFIG_S3C24XX_NAND_HWECC
+/*
+ * This function is called before encoding ECC codes to ready ECC engine.
+ */
+static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+ s3c24xx_nand *const nand = s3c24xx_get_base_nand();
+ u_long nfcont, nfconf;
+
+ /* Set 1-bit ECC */
+ nfconf = readl(nand-nfconf);
+#if defined(CONFIG_S3C2412) || defined(CONFIG_S3C2413)
+ nfconf = ~(0x1 24);
+#else
+ nfconf = ~(0x3 23);
+#endif
+ writel(nfconf, nand-nfconf);
+
+ /* Initialize unlock ECC */
+ nfcont = readl(nand-nfcont);
+ nfcont |= NFCONT_INITMECC;
+
[U-Boot] [PATCH 7/7] S3C24XX: Add support to MINI2416 board
The MINI2416 board is based on a Samsung's S3C2416 SoC and has 64MB DDR2 SDRAM,
256MB NAND Flash, a LAN9220 Ethernet Controller and a WM8731 Audio CODEC.
This U-Boot port was implemented and tested on a unit bought to Boardcon
(http://www.armdesigner.com/) but there are some other chinese providers
that can supply it with a selectable NAND chip from 128MB to 1GB.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
MAINTAINERS|4 +
board/boardcon/mini2416/Makefile | 47 +++
board/boardcon/mini2416/config.mk |4 +
board/boardcon/mini2416/mini2416.c | 100 +++
board/boardcon/mini2416/mini2416_spl.c | 213
board/boardcon/mini2416/u-boot-spl.lds | 63 ++
boards.cfg |1 +
include/configs/mini2416.h | 200 ++
8 files changed, 632 insertions(+)
create mode 100644 board/boardcon/mini2416/Makefile
create mode 100644 board/boardcon/mini2416/config.mk
create mode 100644 board/boardcon/mini2416/mini2416.c
create mode 100644 board/boardcon/mini2416/mini2416_spl.c
create mode 100644 board/boardcon/mini2416/u-boot-spl.lds
create mode 100644 include/configs/mini2416.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 4aabcff..593baa0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -655,6 +655,10 @@ Fabio Estevam fabio.este...@freescale.com
mx53ard i.MX53
mx53smd i.MX53
+José Gonçalves jose.goncal...@inov.pt
+
+ mini2416ARM926EJS (S3C2416 SoC)
+
Daniel Gorsulowski daniel.gorsulow...@esd.eu
meesc ARM926EJS (AT91SAM9263 SoC)
diff --git a/board/boardcon/mini2416/Makefile b/board/boardcon/mini2416/Makefile
new file mode 100644
index 000..bf92ba1
--- /dev/null
+++ b/board/boardcon/mini2416/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2012 INOV - INESC Inovacao
+# Jose Goncalves jose.goncal...@inov.pt
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS += mini2416_spl.o
+else
+COBJS += mini2416.o
+endif
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB):$(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/boardcon/mini2416/config.mk
b/board/boardcon/mini2416/config.mk
new file mode 100644
index 000..f1230d0
--- /dev/null
+++ b/board/boardcon/mini2416/config.mk
@@ -0,0 +1,4 @@
+PAD_TO := 0x2000
+ifndef CONFIG_SPL_BUILD
+ALL-y += $(obj)u-boot-ubl.bin
+endif
diff --git a/board/boardcon/mini2416/mini2416.c
b/board/boardcon/mini2416/mini2416.c
new file mode 100644
index 000..f4ed34d
--- /dev/null
+++ b/board/boardcon/mini2416/mini2416.c
@@ -0,0 +1,100 @@
+/*
+ * (C) Copyright 2012 INOV - INESC Inovacao
+ * Jose Goncalves jose.goncal...@inov.pt
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include netdev.h
+#include asm/io.h
+#include asm/arch/s3c24xx_cpu.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void ether_if_init(void)
+{
+ /* Ethernet chip is on memory bank 1 */
+ s3c24xx_smc *const smc = s3c24xx_get_base_smc(S3C24XX_SMC1);
+
[U-Boot] [PATCH 0/7] Add support to MINI2416 board
Support for the MINI2416 board based on a Samsung's S3C2416 SoC with 64MB DDR2 SDRAM, 256MB NAND Flash, a LAN9220 Ethernet Controller and a WM8731 Audio CODEC. José Miguel Gonçalves (7): ARM: fix relocation on ARM926EJS S3C24XX: Add core support for Samsung's S3C24XX SoCs S3C24XX: Add serial driver S3C24XX: Add RTC driver S3C24XX: Add NAND Flash driver Add u-boot-ubl.bin target to the Makefile S3C24XX: Add support to MINI2416 board MAINTAINERS |4 + Makefile|7 +- arch/arm/cpu/arm926ejs/s3c24xx/Makefile | 52 +++ arch/arm/cpu/arm926ejs/s3c24xx/cpu.c| 56 +++ arch/arm/cpu/arm926ejs/s3c24xx/cpu_info.c | 56 +++ arch/arm/cpu/arm926ejs/s3c24xx/s3c2412_speed.c | 114 + arch/arm/cpu/arm926ejs/s3c24xx/s3c2416_speed.c | 113 + arch/arm/cpu/arm926ejs/s3c24xx/timer.c | 159 +++ arch/arm/cpu/arm926ejs/start.S |4 +- arch/arm/include/asm/arch-s3c24xx/s3c2412.h | 120 ++ arch/arm/include/asm/arch-s3c24xx/s3c2416.h | 149 +++ arch/arm/include/asm/arch-s3c24xx/s3c24xx.h | 503 +++ arch/arm/include/asm/arch-s3c24xx/s3c24xx_cpu.h | 30 ++ board/boardcon/mini2416/Makefile| 47 +++ board/boardcon/mini2416/config.mk |4 + board/boardcon/mini2416/mini2416.c | 100 + board/boardcon/mini2416/mini2416_spl.c | 213 ++ board/boardcon/mini2416/u-boot-spl.lds | 63 +++ boards.cfg |1 + drivers/mtd/nand/Makefile |1 + drivers/mtd/nand/s3c24xx_nand.c | 269 drivers/rtc/Makefile|1 + drivers/rtc/s3c24xx_rtc.c | 166 drivers/serial/Makefile |1 + drivers/serial/s3c24xx_serial.c | 146 +++ include/common.h|1 + include/configs/mini2416.h | 200 + 27 files changed, 2576 insertions(+), 4 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/s3c24xx/Makefile create mode 100644 arch/arm/cpu/arm926ejs/s3c24xx/cpu.c create mode 100644 arch/arm/cpu/arm926ejs/s3c24xx/cpu_info.c create mode 100644 arch/arm/cpu/arm926ejs/s3c24xx/s3c2412_speed.c create mode 100644 arch/arm/cpu/arm926ejs/s3c24xx/s3c2416_speed.c create mode 100644 arch/arm/cpu/arm926ejs/s3c24xx/timer.c create mode 100644 arch/arm/include/asm/arch-s3c24xx/s3c2412.h create mode 100644 arch/arm/include/asm/arch-s3c24xx/s3c2416.h create mode 100644 arch/arm/include/asm/arch-s3c24xx/s3c24xx.h create mode 100644 arch/arm/include/asm/arch-s3c24xx/s3c24xx_cpu.h create mode 100644 board/boardcon/mini2416/Makefile create mode 100644 board/boardcon/mini2416/config.mk create mode 100644 board/boardcon/mini2416/mini2416.c create mode 100644 board/boardcon/mini2416/mini2416_spl.c create mode 100644 board/boardcon/mini2416/u-boot-spl.lds create mode 100644 drivers/mtd/nand/s3c24xx_nand.c create mode 100644 drivers/rtc/s3c24xx_rtc.c create mode 100644 drivers/serial/s3c24xx_serial.c create mode 100644 include/configs/mini2416.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/7] S3C24XX: Add core support for Samsung's S3C24XX SoCs
This patch adds the support for Samsung's S3C24XX SoCs that have an ARM926EJS
core.
Currently it supports S3C2412, S3C2413, S3C2416 and S3C2450.
Tested on an S3C2416 platform.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
arch/arm/cpu/arm926ejs/s3c24xx/Makefile | 52 +++
arch/arm/cpu/arm926ejs/s3c24xx/cpu.c| 56 +++
arch/arm/cpu/arm926ejs/s3c24xx/cpu_info.c | 56 +++
arch/arm/cpu/arm926ejs/s3c24xx/s3c2412_speed.c | 114 +
arch/arm/cpu/arm926ejs/s3c24xx/s3c2416_speed.c | 113 +
arch/arm/cpu/arm926ejs/s3c24xx/timer.c | 159 +++
arch/arm/include/asm/arch-s3c24xx/s3c2412.h | 120 ++
arch/arm/include/asm/arch-s3c24xx/s3c2416.h | 149 +++
arch/arm/include/asm/arch-s3c24xx/s3c24xx.h | 503 +++
arch/arm/include/asm/arch-s3c24xx/s3c24xx_cpu.h | 30 ++
include/common.h|1 +
11 files changed, 1353 insertions(+)
create mode 100644 arch/arm/cpu/arm926ejs/s3c24xx/Makefile
create mode 100644 arch/arm/cpu/arm926ejs/s3c24xx/cpu.c
create mode 100644 arch/arm/cpu/arm926ejs/s3c24xx/cpu_info.c
create mode 100644 arch/arm/cpu/arm926ejs/s3c24xx/s3c2412_speed.c
create mode 100644 arch/arm/cpu/arm926ejs/s3c24xx/s3c2416_speed.c
create mode 100644 arch/arm/cpu/arm926ejs/s3c24xx/timer.c
create mode 100644 arch/arm/include/asm/arch-s3c24xx/s3c2412.h
create mode 100644 arch/arm/include/asm/arch-s3c24xx/s3c2416.h
create mode 100644 arch/arm/include/asm/arch-s3c24xx/s3c24xx.h
create mode 100644 arch/arm/include/asm/arch-s3c24xx/s3c24xx_cpu.h
diff --git a/arch/arm/cpu/arm926ejs/s3c24xx/Makefile
b/arch/arm/cpu/arm926ejs/s3c24xx/Makefile
new file mode 100644
index 000..62b8378
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/s3c24xx/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2012 INOV - INESC Inovacao
+# Jose Goncalves jose.goncal...@inov.pt
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(SOC).o
+
+COBJS-$(CONFIG_DISPLAY_CPUINFO)+= cpu_info.o
+ifeq ($(filter y,$(CONFIG_S3C2412) $(CONFIG_S3C2413)),y)
+COBJS-y+= s3c2412_speed.o
+else
+COBJS-y+= s3c2416_speed.o
+endif
+COBJS-y+= cpu.o
+COBJS-y+= timer.o
+
+SRCS := $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB):$(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/arch/arm/cpu/arm926ejs/s3c24xx/cpu.c
b/arch/arm/cpu/arm926ejs/s3c24xx/cpu.c
new file mode 100644
index 000..326748c
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/s3c24xx/cpu.c
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2012 INOV - INESC Inovacao
+ * Jose Goncalves jose.goncal...@inov.pt
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/s3c24xx_cpu.h
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+ icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+ dcache_enable();
+#endif
+}
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let him time out.
+ */
+void reset_cpu(ulong addr)
+{
+ s3c24xx_watchdog *const watchdog = s3c24xx_get_base_watchdog();
+
+ /* Disable
Re: [U-Boot] [PATCH 2/2] bfin: Fix warning in bfin_mac
On Wed, Sep 12, 2012 at 4:51 AM, Marek Vasut ma...@denx.de wrote: Dear Marek Vasut, The buf variable in bfin_mac.c is not used and produces warning, fix it. bfin_mac.c: In function 'bfin_EMAC_send': bfin_mac.c:125:16: warning: variable 'buf' set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut ma...@denx.de Cc: Mike Frysinger vap...@gentoo.org Guess I should have Cced Joe too ... Acked-by: Joe Hershberger joe.hershber...@ni.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/6] gpt: Replace the leXX_to_int() calls with ones defined at compiler.h
Hi Chang Hyun, Hello Lukasz, Stephen, I see there has been quite a few mails going back and forth on the mailing list on the gpt: Replace the leXX_to_int() calls with ones defined at compiler.hI haven't been receiving the e-mails because my samsung e-mail account has expired.(Internship expired)(I just happened to run into the mails from a google search) Is there anything I should catch up on? Anything I should be doing?And on which fork is this commit being pushed onto? Thank you. I've changed you as an author of the commit. I will also add your private e-mail to CC when I send gpt v2, so stay tunned :-) -- Best regards, Lukasz Majewski Samsung Poland RD Center | Linux Platform Group ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 0/7] gpt: GUID Partition Table (GPT) restoration
This patch series provides a new command - gpt for eMMC partition table (in the GPT format) restoration. As a pre-work, some cleanup at the part_efi.c file was performed to remove custom macros and make GPT related structures more readable. Moreover the part_efi.h file has been moved to ./include directory to be easily available from other subsystems. The GPT detailed description has been written to README.gpt file. Tested at: - Exynos4210 rev.1 - TRATS Samsung development board Chang Hyun Park (1): gpt: The leXX_to_int() calls replaced with ones defined at compiler.h Lukasz Majewski (6): vsprintf:fix: Change type returned by ustrtoul part:efi: Move part_efi.h file to ./include gpt:doc: GPT (GUID Partition Table) documentation gpt: Support for GPT (GUID Partition Table) restoration gpt: Support for new gpt command gpt: Enable support for GPT partition table restoration at Samsung's Trats common/Makefile |1 + common/cmd_gpt.c| 405 +++ disk/part_efi.c | 210 disk/part_efi.h | 139 doc/README.gpt | 207 include/configs/trats.h | 23 +++- include/exports.h |2 +- include/part.h |3 + include/part_efi.h | 143 + lib/vsprintf.c |2 +- 10 files changed, 923 insertions(+), 212 deletions(-) create mode 100644 common/cmd_gpt.c delete mode 100644 disk/part_efi.h create mode 100644 doc/README.gpt create mode 100644 include/part_efi.h -- 1.7.2.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/7] vsprintf:fix: Change type returned by ustrtoul
The ustrtoul shall convert string defined size (e.g. 1GiB) to unsigned
long type (as its name implies).
Up till now it had returned int, which might cause problems with large
numbers (GiB range), when interpreted as U2 signed numbers.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
include/exports.h |2 +-
lib/vsprintf.c|2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/exports.h b/include/exports.h
index 63aa4b2..6cf31aa 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -23,7 +23,7 @@ char *getenv (const char *name);
int setenv (const char *varname, const char *varvalue);
long simple_strtol(const char *cp,char **endp,unsigned int base);
int strcmp(const char * cs,const char * ct);
-int ustrtoul(const char *cp, char **endp, unsigned int base);
+unsigned long ustrtoul(const char *cp, char **endp, unsigned int base);
#if defined(CONFIG_CMD_I2C)
int i2c_write (uchar, uint, int , uchar* , int);
int i2c_read (uchar, uint, int , uchar* , int);
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index e38a4b7..27cb836 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -98,7 +98,7 @@ long simple_strtol(const char *cp,char **endp,unsigned int
base)
return simple_strtoul(cp,endp,base);
}
-int ustrtoul(const char *cp, char **endp, unsigned int base)
+unsigned long ustrtoul(const char *cp, char **endp, unsigned int base)
{
unsigned long result = simple_strtoul(cp, endp, base);
switch (**endp) {
--
1.7.2.3
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[U-Boot] [PATCH v2 3/7] gpt:doc: GPT (GUID Partition Table) documentation
Documentation of the GPT format.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Changes for v2:
- Typos correction.
- Adding guidlines about GPT restoration.
- Adding information about GUID generator
---
doc/README.gpt | 207
1 files changed, 207 insertions(+), 0 deletions(-)
create mode 100644 doc/README.gpt
diff --git a/doc/README.gpt b/doc/README.gpt
new file mode 100644
index 000..ec56005
--- /dev/null
+++ b/doc/README.gpt
@@ -0,0 +1,207 @@
+#
+# Copyright (C) 2012 Samsung Electronics
+#
+# Lukasz Majewski l.majew...@samsung.com
+#
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+
+Glossary:
+
+- UUID -(Universally Unique Identifier)
+- GUID - (Globally Unique ID)
+- EFI - (Extensible Firmware Interface)
+- UEFI - (Unified EFI) - EFI evolution
+- GPT (GUID Partition Table) - it is the EFI standard part
+- partitions - lists of available partitions (defined at u-boot):
+ ./include/configs/{target}.h
+
+Introduction:
+=
+This document describes the GPT partition table format when used with u-boot.
+
+
+UUID introduction:
+
+
+GPT for marking disks/partitions is using the UUID. It is supposed to be a
+globally unique value. A UUID is a 16-byte (128-bit) number. The number of
+theoretically possible UUIDs is therefore about 3 × 10^38.
+More often UUID is stored as 32 hexadecimal digits, displayed in 5 groups
+separated by hyphens, in the form 8-4-4-4-12 for a total of 36 characters
+(32 digits and 4 hyphens)
+
+For instance, GUID of Linux data partition:
EBD0A0A2-B9E5-4433-87C0-68B6B72699C7
+
+Historically there are 5 methods to generate this number. The oldest one is
+combining machine's MAC address and timer (epoch) value.
+
+Successive versions are using MD5 hash, random numbers and SHA-1 hash. All
major
+OSes and programming languages are providing libraries to compute UUID (e.g.
+uuid command line tool).
+
+GPT brief explanation:
+==
+
+ Layout:
+ ---
+
+ --
+ LBA 0 |Protective MBR |
+ --
+ LBA 1 |Primary GPT Header | Primary
+ -- GPT
+ LBA 2 |Entry 1|Entry 2| Entry 3| Entry 4|
+ --
+ LBA 3 |Entries 5 - 128 |
+ | |
+ | |
+ --
+ LBA 34 |Partition 1 |
+ | |
+ ---
+ |Partition 2 |
+ | |
+ ---
+ |Partition n |
+ | |
+ --
+ LBA -34|Entry 1|Entry 2| Entry 3| Entry 4| Secondary
+ -- (bkp)
+ LBA -33|Entries 5 - 128 | GPT
+ | |
+ | |
+ LBA -2 | |
+ --
+ LBA -1 |Secondary GPT Header |
+ --
+
+
+For a legacy reasons, GPT's LBA 0 sector has a MBR structure. It is called
+protective MBR.
+Its first partition entry ID has 0xEE value, and disk software, which is not
+handling the GPT sees it as a storage device without free space.
+
+It is possible to define 128 linearly placed partition entries.
+
+LBA -1 means the last addressable block (in the mmc
[U-Boot] [PATCH v2 5/7] gpt: Support for GPT (GUID Partition Table) restoration
The restoration of GPT table (both primary and secondary) is now possible.
Simple GUID generation is supported.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Changes for v2:
- Move GPT Header and Page Table Entries generation code to cmd_gpt.c
- Provide clean API to use set_gpt_table function for GPT restoration on
a block device
---
disk/part_efi.c | 99 +++
include/part.h |3 ++
2 files changed, 102 insertions(+), 0 deletions(-)
diff --git a/disk/part_efi.c b/disk/part_efi.c
index d4c61d2..531c7ad 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -403,4 +403,103 @@ static int is_pte_valid(gpt_entry * pte)
return 1;
}
}
+
+/**
+ * set_protective_mbr(): Set the EFI protective MBR
+ * @param dev_desc - block device descriptor
+ *
+ * @return - zero on success, otherwise error
+ */
+static int set_protective_mbr(block_dev_desc_t *dev_desc)
+{
+ legacy_mbr p_mbr;
+
+ /* Setup the Protective MBR */
+ memset((u32 *) p_mbr, 0x00, sizeof(p_mbr));
+ /* Append signature */
+ p_mbr.signature = MSDOS_MBR_SIGNATURE;
+ p_mbr.partition_record[0].sys_ind = EFI_PMBR_OSTYPE_EFI_GPT;
+ p_mbr.partition_record[0].start_sect = 1;
+ p_mbr.partition_record[0].nr_sects = (u32) dev_desc-lba;
+
+ /* Write MBR sector to the MMC device */
+ if (dev_desc-block_write(dev_desc-dev, 0, 1, p_mbr) != 1) {
+ printf(** Can't write to device %d **\n,
+ dev_desc-dev);
+ return -1;
+ }
+
+ return 0;
+}
+
+/**
+ * set_gpt_table() - Restore the GUID Partition Table
+ *
+ * @param dev_desc - block device descriptor
+ * @param parts - number of partitions
+ * @param size - pointer to array with each partition size
+ * @param name - pointer to array with each partition name
+ *
+ * @return - zero on success, otherwise error
+ */
+int set_gpt_table(block_dev_desc_t *dev_desc,
+ gpt_header *gpt_h, gpt_entry *gpt_e)
+{
+ const int pte_blk_num = (GPT_ENTRY_NUMBERS * sizeof(gpt_entry)) /
+ dev_desc-blksz;
+ u32 calc_crc32;
+ u64 val;
+
+ debug(max lba: %x\n, (u32) dev_desc-lba);
+
+ /* Setup the Protective MBR */
+ if (set_protective_mbr(dev_desc) 0)
+ goto err;
+
+ /* Generate CRC for the Primary GPT Header */
+ calc_crc32 = efi_crc32((const unsigned char *)gpt_e,
+ le32_to_cpu(gpt_h-num_partition_entries) *
+ le32_to_cpu(gpt_h-sizeof_partition_entry));
+ gpt_h-partition_entry_array_crc32 = cpu_to_le32(calc_crc32);
+
+ calc_crc32 = efi_crc32((const unsigned char *)gpt_h,
+ le32_to_cpu(gpt_h-header_size));
+ gpt_h-header_crc32 = cpu_to_le32(calc_crc32);
+
+ /* Write the First GPT to the block right after the Legacy MBR */
+ if (dev_desc-block_write(dev_desc-dev, 1, 1, gpt_h) != 1)
+ goto err;
+
+ if (dev_desc-block_write(dev_desc-dev, 2, pte_blk_num, gpt_e)
+ != pte_blk_num)
+ goto err;
+
+ /* recalculate the values for the Second GPT Header*/
+ val = le64_to_cpu(gpt_h-my_lba);
+ gpt_h-my_lba = gpt_h-alternate_lba;
+ gpt_h-alternate_lba = cpu_to_le64(val);
+ gpt_h-header_crc32 = 0;
+
+ calc_crc32 = efi_crc32((const unsigned char *)gpt_h,
+ le32_to_cpu(gpt_h-header_size));
+ gpt_h-header_crc32 = cpu_to_le32(calc_crc32);
+
+ /* Write the Second GPT that is located at the end of the disk */
+ if (dev_desc-block_write(dev_desc-dev,
+ le32_to_cpu(gpt_h-last_usable_lba + 1),
+ pte_blk_num, gpt_e) != pte_blk_num)
+ goto err;
+
+ if (dev_desc-block_write(dev_desc-dev,
+ le32_to_cpu(gpt_h-my_lba), 1, gpt_h) != 1)
+ goto err;
+
+ printf(GPT successfully written to block device!\n);
+ return 0;
+
+ err:
+ printf(** Can't write to device %d **\n,
+ dev_desc-dev);
+ return -1;
+}
#endif
diff --git a/include/part.h b/include/part.h
index e1478f4..fc34ed2 100644
--- a/include/part.h
+++ b/include/part.h
@@ -157,10 +157,13 @@ int test_part_amiga (block_dev_desc_t *dev_desc);
#endif
#ifdef CONFIG_EFI_PARTITION
+#include part_efi.h
/* disk/part_efi.c */
int get_partition_info_efi (block_dev_desc_t * dev_desc, int part,
disk_partition_t *info);
void print_part_efi (block_dev_desc_t *dev_desc);
int test_part_efi (block_dev_desc_t *dev_desc);
+int set_gpt_table(block_dev_desc_t *dev_desc,
+ gpt_header *gpt_h, gpt_entry *gpt_e);
#endif
#endif /* _PART_H */
--
1.7.2.3
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[U-Boot] [PATCH v2 2/7] part:efi: Move part_efi.h file to ./include
This move is necessary to export gpt header and GPT partition entries to be
used with other commands or subsystems (like DFU in the future)
Additionally the part_efi.h file has been cleaned-up to supress checkpatch's
warnings.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
disk/part_efi.c|2 +-
disk/part_efi.h| 139 ---
include/part_efi.h | 140
3 files changed, 141 insertions(+), 140 deletions(-)
delete mode 100644 disk/part_efi.h
create mode 100644 include/part_efi.h
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 02927a0..b2233da 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -34,7 +34,7 @@
#include command.h
#include ide.h
#include malloc.h
-#include part_efi.h
+#include part_efi.h
#include linux/ctype.h
#if defined(CONFIG_CMD_IDE) || \
diff --git a/disk/part_efi.h b/disk/part_efi.h
deleted file mode 100644
index 5903e7c..000
--- a/disk/part_efi.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Copyright (C) 2008 RuggedCom, Inc.
- * Richard Retanubun richardretanu...@ruggedcom.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * See also linux/fs/partitions/efi.h
- *
- * EFI GUID Partition Table
- * Per Intel EFI Specification v1.02
- * http://developer.intel.com/technology/efi/efi.htm
-*/
-
-#ifndef _DISK_PART_EFI_H
-#define _DISK_PART_EFI_H
-
-#define MSDOS_MBR_SIGNATURE 0xAA55
-#define EFI_PMBR_OSTYPE_EFI 0xEF
-#define EFI_PMBR_OSTYPE_EFI_GPT 0xEE
-
-#define GPT_BLOCK_SIZE 512
-#define GPT_HEADER_SIGNATURE 0x5452415020494645ULL
-#define GPT_HEADER_REVISION_V1 0x0001
-#define GPT_PRIMARY_PARTITION_TABLE_LBA 1ULL
-#define GPT_ENTRY_NAME gpt
-
-#define EFI_GUID(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7) \
- ((efi_guid_t) \
- {{ (a) 0xff, ((a) 8) 0xff, ((a) 16) 0xff, ((a) 24)
0xff, \
- (b) 0xff, ((b) 8) 0xff, \
- (c) 0xff, ((c) 8) 0xff, \
- (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
-
-#define PARTITION_SYSTEM_GUID \
- EFI_GUID( 0xC12A7328, 0xF81F, 0x11d2, \
- 0xBA, 0x4B, 0x00, 0xA0, 0xC9, 0x3E, 0xC9, 0x3B)
-#define LEGACY_MBR_PARTITION_GUID \
- EFI_GUID( 0x024DEE41, 0x33E7, 0x11d3, \
- 0x9D, 0x69, 0x00, 0x08, 0xC7, 0x81, 0xF3, 0x9F)
-#define PARTITION_MSFT_RESERVED_GUID \
- EFI_GUID( 0xE3C9E316, 0x0B5C, 0x4DB8, \
- 0x81, 0x7D, 0xF9, 0x2D, 0xF0, 0x02, 0x15, 0xAE)
-#define PARTITION_BASIC_DATA_GUID \
- EFI_GUID( 0xEBD0A0A2, 0xB9E5, 0x4433, \
- 0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7)
-#define PARTITION_LINUX_RAID_GUID \
- EFI_GUID( 0xa19d880f, 0x05fc, 0x4d3b, \
- 0xa0, 0x06, 0x74, 0x3f, 0x0f, 0x84, 0x91, 0x1e)
-#define PARTITION_LINUX_SWAP_GUID \
- EFI_GUID( 0x0657fd6d, 0xa4ab, 0x43c4, \
- 0x84, 0xe5, 0x09, 0x33, 0xc8, 0x4b, 0x4f, 0x4f)
-#define PARTITION_LINUX_LVM_GUID \
- EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
- 0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
-
-/* linux/include/efi.h */
-typedef unsigned short efi_char16_t;
-
-typedef struct {
- unsigned char b[16];
-} efi_guid_t;
-
-/* based on linux/include/genhd.h */
-struct partition {
- unsigned char boot_ind; /* 0x80 - active */
- unsigned char head; /* starting head */
- unsigned char sector; /* starting sector */
- unsigned char cyl; /* starting cylinder */
- unsigned char sys_ind; /* What partition type */
- unsigned char end_head; /* end head */
- unsigned char end_sector; /* end sector */
- unsigned char end_cyl; /* end cylinder */
- unsigned char start_sect[4];/* starting sector counting from 0 */
- unsigned char nr_sects[4]; /* nr of sectors in partition */
-} __attribute__ ((packed));
-
-/* based on linux/fs/partitions/efi.h */
-typedef struct _gpt_header {
- unsigned char signature[8];
- unsigned char revision[4];
- unsigned char header_size[4];
- unsigned char header_crc32[4];
-
[U-Boot] [PATCH v2 4/7] gpt: The leXX_to_int() calls replaced with ones defined at compiler.h
From: Chang Hyun Park chchch.p...@samsung.com
Custom definitions of le_XX_to_int functions have been replaced with
standard ones, defined at compiler.h
Replacement of several GPT related structures members with ones
indicating its endianness and proper size.
Signed-off-by: Chang Hyun Park chchch.p...@samsung.com
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Changes for v2:
- Combining two commits regarding part_efi.{h|c}
---
disk/part_efi.c| 109 +++-
include/part_efi.h | 85 +---
2 files changed, 84 insertions(+), 110 deletions(-)
diff --git a/disk/part_efi.c b/disk/part_efi.c
index b2233da..d4c61d2 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -44,34 +44,6 @@
defined(CONFIG_MMC) || \
defined(CONFIG_SYSTEMACE)
-/* Convert char[2] in little endian format to the host format integer
- */
-static inline unsigned short le16_to_int(unsigned char *le16)
-{
- return ((le16[1] 8) + le16[0]);
-}
-
-/* Convert char[4] in little endian format to the host format integer
- */
-static inline unsigned long le32_to_int(unsigned char *le32)
-{
- return ((le32[3] 24) + (le32[2] 16) + (le32[1] 8) + le32[0]);
-}
-
-/* Convert char[8] in little endian format to the host format integer
- */
-static inline unsigned long long le64_to_int(unsigned char *le64)
-{
- return (((unsigned long long)le64[7] 56) +
- ((unsigned long long)le64[6] 48) +
- ((unsigned long long)le64[5] 40) +
- ((unsigned long long)le64[4] 32) +
- ((unsigned long long)le64[3] 24) +
- ((unsigned long long)le64[2] 16) +
- ((unsigned long long)le64[1] 8) +
- (unsigned long long)le64[0]);
-}
-
/**
* efi_crc32() - EFI version of crc32 function
* @buf: buffer to calculate crc32 of
@@ -79,7 +51,7 @@ static inline unsigned long long le64_to_int(unsigned char
*le64)
*
* Description: Returns EFI-style CRC32 value for @buf
*/
-static inline unsigned long efi_crc32(const void *buf, unsigned long len)
+static inline u32 efi_crc32(const void *buf, u32 len)
{
return crc32(0, buf, len);
}
@@ -137,13 +109,13 @@ void print_part_efi(block_dev_desc_t * dev_desc)
debug(%s: gpt-entry at %p\n, __func__, gpt_pte);
printf(Part\tName\t\t\tStart LBA\tEnd LBA\n);
- for (i = 0; i le32_to_int(gpt_head-num_partition_entries); i++) {
+ for (i = 0; i le32_to_cpu(gpt_head-num_partition_entries); i++) {
if (is_pte_valid(gpt_pte[i])) {
printf(%3d\t%-18s\t0x%08llX\t0x%08llX\n, (i + 1),
print_efiname(gpt_pte[i]),
- le64_to_int(gpt_pte[i].starting_lba),
- le64_to_int(gpt_pte[i].ending_lba));
+ (u64) le64_to_cpu(gpt_pte[i].starting_lba),
+ (u64) le64_to_cpu(gpt_pte[i].ending_lba));
} else {
break; /* Stop at the first non valid PTE */
}
@@ -174,9 +146,9 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc, int
part,
}
/* The ulong casting limits the maximum disk size to 2 TB */
- info-start = (ulong) le64_to_int(gpt_pte[part - 1].starting_lba);
+ info-start = (u64) le64_to_cpu(gpt_pte[part - 1].starting_lba);
/* The ending LBA is inclusive, to calculate size, add 1 to it */
- info-size = ((ulong)le64_to_int(gpt_pte[part - 1].ending_lba) + 1)
+ info-size = ((u64)le64_to_cpu(gpt_pte[part - 1].ending_lba) + 1)
- info-start;
info-blksz = GPT_BLOCK_SIZE;
@@ -215,7 +187,7 @@ int test_part_efi(block_dev_desc_t * dev_desc)
static int pmbr_part_valid(struct partition *part)
{
if (part-sys_ind == EFI_PMBR_OSTYPE_EFI_GPT
- le32_to_int(part-start_sect) == 1UL) {
+ le32_to_cpu(part-start_sect) == 1UL) {
return 1;
}
@@ -234,9 +206,8 @@ static int is_pmbr_valid(legacy_mbr * mbr)
{
int i = 0;
- if (!mbr || le16_to_int(mbr-signature) != MSDOS_MBR_SIGNATURE) {
+ if (!mbr || le16_to_cpu(mbr-signature) != MSDOS_MBR_SIGNATURE)
return 0;
- }
for (i = 0; i 4; i++) {
if (pmbr_part_valid(mbr-partition_record[i])) {
@@ -259,8 +230,8 @@ static int is_pmbr_valid(legacy_mbr * mbr)
static int is_gpt_valid(block_dev_desc_t * dev_desc, unsigned long long lba,
gpt_header * pgpt_head, gpt_entry ** pgpt_pte)
{
- unsigned char crc32_backup[4] = { 0 };
- unsigned long calc_crc32;
+ u32 crc32_backup = 0;
+ u32 calc_crc32;
unsigned long long lastlba;
if (!dev_desc || !pgpt_head) {
@@ -275,54 +246,54 @@ static int is_gpt_valid(block_dev_desc_t *
[U-Boot] [PATCH v2 6/7] gpt: Support for new gpt command
New command - gpt is supported. It restores the GPT partition table.
It looks into the partitions environment variable for partitions definition.
It can be enabled at target configuration file with CONFIG_CMD_GPT.
Simple UUID generator has been implemented. It uses the the gd-start_addr_sp
for entrophy pool. Moreover the pool address is used as crc32 seed.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Changes for v2:
- gpt command now accepts device medium and its number (e.g. gpt mmc 0)
- UUIDs can be passed via u-boot prompt when used with gpt command
- Format of restored GPT has been changed - now key=value pairs are used
'name=PARTS_CSA,size=8MiB;\ '
'name=PARTS_BOOTLOADER,size=60MiB; \'
- guid_gen now accepts pool pointer and guid pointer
- gd-start_addr_sp is used as a primary source of entrophy
- static buffers definitions have been removed
- remove memsize_to_blocks function with call to standard ustrtoul
- doxygen comments for functions added
---
common/Makefile |1 +
common/cmd_gpt.c | 405 ++
2 files changed, 406 insertions(+), 0 deletions(-)
create mode 100644 common/cmd_gpt.c
diff --git a/common/Makefile b/common/Makefile
index 49df751..438d36c 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -185,6 +185,7 @@ COBJS-$(CONFIG_MODEM_SUPPORT) += modem.o
COBJS-$(CONFIG_UPDATE_TFTP) += update.o
COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
COBJS-$(CONFIG_CMD_DFU) += cmd_dfu.o
+COBJS-$(CONFIG_CMD_GPT) += cmd_gpt.o
endif
ifdef CONFIG_SPL_BUILD
diff --git a/common/cmd_gpt.c b/common/cmd_gpt.c
new file mode 100644
index 000..bb62b05
--- /dev/null
+++ b/common/cmd_gpt.c
@@ -0,0 +1,405 @@
+/*
+ * cmd_gpt.c -- GPT (GUID Partition Table) handling command
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ * author: Lukasz Majewski l.majew...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include common.h
+#include malloc.h
+#include command.h
+#include mmc.h
+#include part_efi.h
+#include exports.h
+
+gpt_entry *gpt_e;
+gpt_header *gpt_h;
+DECLARE_GLOBAL_DATA_PTR;
+static unsigned int gpt_parts;
+
+#ifdef DEBUG
+/**
+ * guid_dump(): Dump guid content
+ *
+ * @param guid - pinter to guid
+ * @param i - number of bytes to dump
+ */
+static void guid_dump(u8 *guid, int i)
+{
+ int k;
+
+ debug(GUID: );
+ for (k = 0; k i; k++, guid++)
+ debug( %x , *guid);
+ debug(\n);
+}
+#else
+static void guid_dump(u8 *guid, int i) {}
+#endif
+
+/**
+ * guid_gen(): Generate UUID
+ *
+ * @param pool - pointer to pseudo random data (e.g. SP)
+ * @param guid - pointer to guid table
+ *
+ * @return - generated UUID table
+ *
+ * NOTE: The entrophy of this function is small
+ */
+static void guid_gen(const u32 *pool, u8 *guid)
+{
+ int k = 0;
+ u32 *ptr = (u32 *) guid;
+
+ debug(%s: pool: 0x%p guid: 0x%p\n, __func__, pool, guid);
+ for (k = 0; k 4; k++)
+ *(ptr + k) = crc32((u32) pool, (const void *) (pool - k), 512);
+
+ guid_dump(guid, sizeof(efi_guid_t));
+}
+
+/**
+ * convert_uuid(); Convert UUID stored as string to bytes
+ *
+ * @param uuid - UUID represented as string
+ * @param dst - GUID buffer
+ *
+ * @return
+ */
+static int convert_uuid(char *uuid, u8 *dst)
+{
+ efi_guid_t guid;
+ u16 b, c, d;
+ char *t;
+ u64 e;
+ u32 a;
+ u8 *p;
+
+ debug(%s: uuid: %s\n, __func__, uuid);
+ t = strsep(uuid, -);
+ a = (u32)simple_strtoul(t, NULL, 16);
+ t = strsep(uuid, -);
+ b = (u16)simple_strtoul(t, NULL, 16);
+ t = strsep(uuid, -);
+ c = (u16)simple_strtoul(t, NULL, 16);
+ t = strsep(uuid, -);
+ d = (u16)simple_strtoul(t, NULL, 16);
+ e = (u64)simple_strtoull(uuid, NULL, 16);
+
+ p = (u8 *) e;
+ guid = EFI_GUID(a, b, c, d 8, d 0xFF,
+ *(p + 5), *(p + 4), *(p + 3),
+ *(p + 2), *(p + 1) , *p);
+
+ guid_dump(guid.b, sizeof(efi_guid_t));
+ memcpy(dst, guid.b, sizeof(efi_guid_t));
+
+ return 0;
+}
+
+/**
+ * fill_pte(): Fill the GPT partition table entry
+ *
+ * @param dev_desc - block device descriptor
+ * @param gpt_h - GPT header representation
+ *
[U-Boot] [PATCH v2 7/7] gpt: Enable support for GPT partition table restoration at Samsung's Trats
Enable support for GPT partition table restoration at Samsung's Trats
development board.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Changes for v2:
- New format for default GPT partitions (key=value pairs)
- replace size definitions with more readable description(1GiB instead of 1G)
---
include/configs/trats.h | 23 ++-
1 files changed, 22 insertions(+), 1 deletions(-)
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 08aa65b..f1ba9e7 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -98,6 +98,7 @@
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_MMC
#define CONFIG_CMD_DFU
+#define CONFIG_CMD_GPT
/* FAT */
#define CONFIG_CMD_FAT
@@ -122,6 +123,24 @@
#define CONFIG_BOOTBLOCK 10
#define CONFIG_ENV_COMMON_BOOT ${console} ${meminfo}
+/* Tizen - partitions definitions */
+#define PARTS_CSA csa-mmc
+#define PARTS_BOOTLOADER u-boot
+#define PARTS_KERNEL kernel
+#define PARTS_ROOT platform
+#define PARTS_DATA data
+#define PARTS_CSC csc
+#define PARTS_UMS ums
+
+#define PARTS_DEFAULT name=PARTS_CSA,size=8MiB;\
+ name=PARTS_BOOTLOADER,size=60MiB;\
+ name=PARTS_KERNEL,size=60MiB;\
+ name=PARTS_ROOT,size=1GiB;\
+ name=PARTS_DATA,size=3GiB;\
+ name=PARTS_CSC,size=150MiB;\
+ name=PARTS_UMS,size=-\0
+#define GPT_PARTS_NUM 7
+
#define CONFIG_DFU_ALT \
dfu_alt_info= \
u-boot mmc 80 400; \
@@ -171,7 +190,8 @@
mmcbootpart=2\0 \
mmcrootpart=3\0 \
opts=always_resume=1\0 \
- CONFIG_DFU_ALT
+ partitions= PARTS_DEFAULT \
+ CONFIG_DFU_ALT \
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP/* undef to save memory */
@@ -210,6 +230,7 @@
#define CONFIG_ENV_OFFSET ((32 - 4) 10) /* 32KiB - 4KiB */
#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_LOAD_ADDR -
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_CACHELINE_SIZE 32
--
1.7.2.3
___
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[U-Boot] Next steps
Hey all, I know some of you have known me for ages, and some of you only as long as my jaunt back into U-Boot over the last year. Rather than talk myself up, I'd like to go with actions to let everyone know you're in good hands. I'd like to ask a few things of the community right now. If you're a custodian and have an outstanding pull request (I see a few on the mailing list right now even), please assign it to me in patchwork and shoot me a private email with a link too. If you aren't in patchwork please sign up. I know it's imperfect and we've talked about how to make something better, but it's the tool we have today. If you're a developer, and you have outstanding patches without an obvious custodian, please assign it to me in patchwork after making sure it applies to top of tree mainline still and shoot me a private email with the links and perhaps a few lines about what your patch(s) do. Finally, I'd like to ask for your patience as I come up to speed on everything that's outstanding still. I'd like to do -rc1 on the 21st of this month, -rc2 on the 28th, -rc3 on Oct 5th and release on Oct 15th. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 5/6] da850/omap-l138: davinci_emac: Suppress auto negotiation if needed
On 09/10/2012 10:32 PM, bastian.rupp...@sewerin.de wrote: Hello, Prabhakar, hello Tom On Monday 10 September 2012 09:38 PM, Tom Rini wrote: On Sun, Sep 9, 2012 at 11:01 PM, bastian.rupp...@sewerin.de wrote: Hello, Re: [U-Boot] [PATCH v3 5/6] da850/omap-l138: davinci_emac: Suppress auto negotiation if needed On Fri, Sep 7, 2012 at 1:08 AM, Prabhakar Lad prabhakar.cse...@gmail.com wrote: Hi Bastian, Thanks for the patch. On Thu, Sep 6, 2012 at 11:37 AM, Bastian Ruppert bastian.rupp...@sewerin.de wrote: From this commit id: b78375a806ed04eb22b963255cfdef8df702de47 auto negotiation is enabled in RMII mode. Some boards based on da850 need to suppress this procedure. CC: Rajashekhara, Sudhakar sudhakar@ti.com CC: Lad, Prabhakar prabhakar@ti.com CC: Hadli, Manjunath manjunath.ha...@ti.com CC: sba...@denx.de Acked-by: Stefano Babic sba...@denx.de CC: Tom Rini tr...@ti.com Signed-off-by: Bastian Ruppert bastian.rupp...@sewerin.de --- drivers/net/davinci_emac.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index b2516d1..fe988d7 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -897,7 +897,8 @@ int davinci_emac_initialize(void) } #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) \ - defined(CONFIG_MACH_DAVINCI_DA850_EVM) + defined(CONFIG_MACH_DAVINCI_DA850_EVM) \ + !defined(CONFIG_DRIVER_TI_EMAC_RMII_NONEG) instead of CONFIG_DRIVER_TI_EMAC_RMII_NONEG why not have CONFIG_DRIVER_TI_EMAC_RMII_AUTO_NEGOTIATE ? Good idea, opt-in is better than opt-out, please make it so. i can see what you mean! But in this case i would like to answer back. Normally, one almost certainly use the auto negotiation. On the ea20 board there is a seldom case where auto negotiation is counterproductive. In my opinion the feature disable it is opt-in. So i would like to leave it as it is. I will defer to Prabhakar for a final answer on this. Ok. 'NONEG' doesn't sound good can you make it NO_NEGOTIATE ? Ok, i will use CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE. It is not too long, isn´t it? Tom, would you like to receive a complete v4 patch series for this? Or should i post version 4 for the affected patches only? Whichever is easier for you to post, thanks. -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] bfin: Fix warning in bfin_mac
On Wed, Sep 12, 2012 at 10:32 AM, Joe Hershberger wrote: On Wed, Sep 12, 2012 at 4:51 AM, Marek Vasut wrote: Dear Marek Vasut, The buf variable in bfin_mac.c is not used and produces warning, fix it. bfin_mac.c: In function 'bfin_EMAC_send': bfin_mac.c:125:16: warning: variable 'buf' set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut ma...@denx.de Cc: Mike Frysinger vap...@gentoo.org Guess I should have Cced Joe too ... Acked-by: Joe Hershberger joe.hershber...@ni.com i can pick this up, or you can. it'll be another week before i'm back home working on u-boot though. -mike ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Cache alignment warnings on Tegra (ARM)
Folks,
Stephen Warren has posted an internal bug regarding the cache
alignment 'warnings' seen on Tegra20 boards when accessing MMC. Here's
the gist:
Executing mmc dev 0 still yields cache warnings:
Tegra20 (Harmony) # mmc dev 0
ERROR: v7_dcache_inval_range- stop address is not aligned- 0x3fb69908
mmc0 is current device
I carry the patch below to turn these off, but I'd like to drop it.
commit 37bccb3c67897a8944c458d511dac06389ea8f1e
Author: Stephen Warren swar...@nvidia.com
Date: Mon Apr 30 11:39:27 2012 -0600
HACK: Disable cache alignment warnings
They are very annoying and noisy
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 1b4e808..9031ea1 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -185,8 +185,10 @@ static void v7_dcache_inval_range(u32 start, u32
stop, u32 line_len)
* invalidate the first cache-line
*/
if (start (line_len- 1)) {
+#if 0
printf(ERROR: %s- start address is not aligned- 0x%08x\n,
__func__, start);
+#endif
/* move to next cache line */
start = (start + line_len- 1) ~(line_len- 1);
}
@@ -196,8 +198,10 @@ static void v7_dcache_inval_range(u32 start, u32
stop, u32 line_len)
* invalidate the last cache-line
*/
if (stop (line_len- 1)) {
+#if 0
printf(ERROR: %s- stop address is not aligned- 0x%08x\n,
__func__, stop);
+#endif
/* align to the beginning of this cache line */
stop = ~(line_len- 1);
}
diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c
index 21d13f7..d8a343c 100644
--- a/arch/arm/lib/cache-pl310.c
+++ b/arch/arm/lib/cache-pl310.c
@@ -94,8 +94,10 @@ void v7_outer_cache_inval_range(u32 start, u32 stop)
* invalidate the first cache-line
*/
if (start (line_size- 1)) {
+#if 0
printf(ERROR: %s- start address is not aligned- 0x%08x\n,
__func__, start);
+#endif
/* move to next cache line */
start = (start + line_size- 1) ~(line_size- 1);
}
@@ -105,8 +107,10 @@ void v7_outer_cache_inval_range(u32 start, u32 stop)
* invalidate the last cache-line
*/
if (stop (line_size- 1)) {
+#if 0
printf(ERROR: %s- stop address is not aligned- 0x%08x\n,
__func__, stop);
+#endif
/* align to the beginning of this cache line */
stop = ~(line_size- 1);
}
There have been patches in the past (IIRC) that have tried to ensure
all callers (FS, MMC driver, USB driver, etc.) force their buffers to
the appropriate alignment, but I don't know that we can ever correct
every instance, now or in the future.
Can we start a discussion about what we can do about this warning?
Adding an appropriate #ifdef (CONFIG_SYS_NO_CACHE_ALIGNMENT_WARNINGS,
etc.) where Stephen put his #if 0's would be one approach, or changing
the printf() to a debug(), perhaps. As far as I can tell, these
alignment 'errors' don't seem to produce bad data in the transfer.
Thanks,
Tom
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Re: [U-Boot] [PATCH v4] PXE: FDT: Add support for fdt in PXE
On Fri, Sep 07, 2012 at 11:06:31AM +0530, Chander Kashyap wrote: Now DT support is becoming common for all new SoC's. Hence it is better to have option for getting specific FDT from the remote server. This patch adds support for new label i.e. 'fdt'. This will allow to retrieve 'fdt blob' from the remote server. This patch take care for the following scenarios. The usage of fdt is optional. The 'fdt blob' can be retrieved from tftp or can be available locally or can be absent. If 'fdt_addr_r' environment variable is set and 'fdt' label is defined retrieve 'fdt blob' from tftp. 'fdt_addr_r' is then passed along bootm command. If 'fdt_addr' is set and 'fdt blob' is not retrieved from the tftp pass 'fdt_addr' to bootm command. In this case 'fdt blob' will be available at 'fdt_addr'. If 'fdt_addr' is not set and 'fdt blob' is not retrieve from tftp pass NULL to boot command. In this case 'fdt blob' is not required and absent. Signed-off-by: Chander Kashyap chander.kash...@linaro.org --- Changes in v2: - Removed the duplicate code. changes in v3: - Added documentation for fdt lable in doc/README.pxe changes in v4: - Added New environment variable 'fdt_addr_r' for 'fdt blob' - Add more descriptive documentation for the 'fdt' retrieval. common/cmd_pxe.c | 39 --- doc/README.pxe | 14 -- 2 files changed, 48 insertions(+), 5 deletions(-) Looks good to me, Joe can you please pick this up if you're good with it? Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 4/4] cmd_part: add partition-related command
On 09/11/2012 03:52 PM, Stephen Warren wrote:
On 09/05/2012 05:58 PM, Tom Rini wrote:
On Wed, Sep 05, 2012 at 06:51:58PM -0500, Rob Herring wrote:
On 09/05/2012 05:03 PM, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
This implements the following:
part uuid mmc 0:1
- print partition UUID
part uuid mmc 0:1 uuid
- set environment variable to partition UUID
What's the reason to not always both print out and set the uuid env var?
Perhaps the env name should be partuuid or part_uuid as you could have
uuid's for other purposes?
This can be useful when writing a bootcmd which searches all known
devices for something bootable, and then wants the kernel to use the
same partition as the root device, e.g.:
part uuid ${devtype} ${devnum}:${rootpart} uuid
setenv bootargs root=PARTUUID=${uuid} ...
It is expected that further part sub-commands will be added later, e.g.
to find which partition on a disk is marked bootable, to write new
partition tables to disk, etc.
A list command would be useful and would be better located here than
under scsi or other interface commands. Perhaps instead of printing a
single part uuid, you should make a list command that prints all
partitions and their UUIDs. That would address my first question.
Sounds like a good idea to me as well.
[snip]
Signed-off-by: Stephen Warren swar...@nvidia.com
---
v2: validate that CONFIG_PARTITION_UUID is defined when CONFIG_CMD_PART is
Note: If Rob Herring's proposed patch disk/part: introduce
get_device_and_partition is applied, the body of do_partuuid() should
be reworked to use Rob's new function get_device_and_partition().
I think the best idea here would be to make the next version just depend
on Rob's series.
Tom,
Rob's series depends on Wolfgang(?)'s u-boot/ext4 branch at present. I'm
not sure what the status of that branch is right now - is it something
that's ready to be submitted, or is more work there needed, so the
branch won't be pulled into u-boot/master in the near future? I'm mainly
asking so Rob and I know if Rob's patches should be rebased first onto
something else, before I rebase my patches on his.
So, I want the ext4 work to make it into the next release. At this
point I am aware there is an issue with large volumes but I need to
research a little more and make sure it's localized to ext4 only. If
so, my feeling is that it's good enough to start with and then yes, it
will get merged to master, around -rc1 time.
--
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Re: [U-Boot] [PATCH V2 4/4] cmd_part: add partition-related command
On 09/12/2012 12:00 AM, Lukasz Majewski wrote: Hi Stephen, Tom, Rob's series depends on Wolfgang(?)'s u-boot/ext4 branch at present. I'm not sure what the status of that branch is right now - is it something that's ready to be submitted, or is more work there needed, so the branch won't be pulled into u-boot/master in the near future? I'm mainly asking so Rob and I know if Rob's patches should be rebased first onto something else, before I rebase my patches on his. Thanks. I'd also like to know if those patches will be accepted soon. I'm working on a GPT restoration support and those patches might be a pre-requisite for my development (if were pulled into u-boot/master). In short, yes, merged to master. In longer form, please see the other email I just sent in this thread. -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Cache alignment warnings on Tegra (ARM)
On 09/12/2012 10:19 AM, Tom Warren wrote: Folks, Stephen Warren has posted an internal bug regarding the cache alignment 'warnings' seen on Tegra20 boards when accessing MMC. Here's the gist: Executing mmc dev 0 still yields cache warnings: Tegra20 (Harmony) # mmc dev 0 ERROR: v7_dcache_inval_range- stop address is not aligned- 0x3fb69908 mmc0 is current device ... There have been patches in the past (IIRC) that have tried to ensure all callers (FS, MMC driver, USB driver, etc.) force their buffers to the appropriate alignment, but I don't know that we can ever correct every instance, now or in the future. Can we start a discussion about what we can do about this warning? Adding an appropriate #ifdef (CONFIG_SYS_NO_CACHE_ALIGNMENT_WARNINGS, etc.) where Stephen put his #if 0's would be one approach, or changing the printf() to a debug(), perhaps. As far as I can tell, these alignment 'errors' don't seem to produce bad data in the transfer. I don't think simply turning off the warning is the correct approach; I believe they represent real problems that can in fact cause data corruption. I don't believe we have any choice other than to fully solve the root-cause. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2] ARM: Add Altera SOCFPGA Cyclone5
On Tue, Sep 11, 2012 at 07:53:17AM +0200, Stefan Roese wrote: Hi Pavel, On 09/11/2012 02:21 AM, Pavel Machek wrote: From: Dinh Nguyen dingu...@altera.com Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Applied on top of trini/WIP/spl-improvements v6 [...] __noreturn attribute to reset_cpu() is still missing, but that's a minor thing. Plus, I guess these should be deleted. We already have prototype in common arch/arm/include/asm/arch-kirkwood/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-orion5x/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-socfpga/reset_manager.h:void reset_cpu(ulong addr); Yes, good catch. What needs to be done to get the socfpga patches merged? As the patches are based upon the SPL framework patches from Tom Rini, Tom's patches need to get included first. AFAICT, this SPL framework will not go into mainline for the upcoming release, but will be pushed into next, once it opens. I posted the first series by the end of the merge window with the intention of getting it into this release. So long as there are no objections (I haven't seen any further comments), I plan to merge it soon (after working over the backlog of pull request). -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2] ARM: Add Altera SOCFPGA Cyclone5
On 09/10/2012 05:21 PM, Pavel Machek wrote: Hi! From: Dinh Nguyen dingu...@altera.com Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Applied on top of trini/WIP/spl-improvements v6 [...] __noreturn attribute to reset_cpu() is still missing, but that's a minor thing. Plus, I guess these should be deleted. We already have prototype in common arch/arm/include/asm/arch-kirkwood/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-orion5x/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-socfpga/reset_manager.h:void reset_cpu(ulong addr); What needs to be done to get the socfpga patches merged? Please do a v2 of the common.h patch that removes these SoC declarations and confirm that MAKEALL -s kirkwood -s orion5x compiles without new warnings. Thanks! -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] bfin: Disable -fstack-usage
On Wed, Sep 12, 2012 at 09:59:30AM +0200, Marek Vasut wrote: Dear Mike Frysinger, On Tue, Sep 11, 2012 at 3:08 PM, Marek Vasut wrote: The GCC does not support this on blackfin, disable it. err, no, you're probably using gcc-4.5.x which didn't support -fstack-usage. that is not specific to Blackfin as gcc didn't add it until 4.6.x. I actually used gentoo here, so it's really possible there is some crap going on. $ bfin-unknown-elf-gcc --version bfin-unknown-elf-gcc (crosstool-NG hg+default-ff167977b163) 4.6.3 Copyright (C) 2011 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. why doesn't the cc-option check work ? I dunno man, probably because it's supported but broken, see (there's lot more to this, I cut it down): I believe it's a gcc feature not a bug. -fstack-usage emits a warning on targets where it's not supported and cc-option doesn't catch that. How about if you make cc-option call -Werror ? -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 6/7] gpt: Support for new gpt command
On 09/12/2012 07:50 AM, Lukasz Majewski wrote:
New command - gpt is supported. It restores the GPT partition table.
It looks into the partitions environment variable for partitions definition.
It can be enabled at target configuration file with CONFIG_CMD_GPT.
Simple UUID generator has been implemented. It uses the the gd-start_addr_sp
for entrophy pool. Moreover the pool address is used as crc32 seed.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
[snip]
+ /* allocate remaining memory in last partition */
+ if (i != parts - 1) {
+ gpt_e[i].ending_lba =
+ cpu_to_le64(offset + size[i] - 1);
+ } else {
+ gpt_e[i].ending_lba = gpt_h-last_usable_lba;
+ }
Extra curly braces. That's all I've seen in this patch however, so
getting close :)
--
Tom
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Re: [U-Boot] [PATCH v2 5/7] gpt: Support for GPT (GUID Partition Table) restoration
On 09/12/2012 07:50 AM, Lukasz Majewski wrote: The restoration of GPT table (both primary and secondary) is now possible. Simple GUID generation is supported. Signed-off-by: Lukasz Majewski l.majew...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com [sinp] + + printf(GPT successfully written to block device!\n); puts() please. Thanks! -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/7] gpt: GUID Partition Table (GPT) restoration
On 09/12/2012 07:50 AM, Lukasz Majewski wrote: This patch series provides a new command - gpt for eMMC partition table (in the GPT format) restoration. As a pre-work, some cleanup at the part_efi.c file was performed to remove custom macros and make GPT related structures more readable. Moreover the part_efi.h file has been moved to ./include directory to be easily available from other subsystems. The GPT detailed description has been written to README.gpt file. Tested at: - Exynos4210 rev.1 - TRATS Samsung development board I had two very minor comments. Aside from that, please make sure the series is checkpatch clean (I haven't checked). Thanks! -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] mx6: Add basic support for mx6qsabresd board.
On 9/12/2012 12:02 AM, Fabio Estevam wrote:
mx6qsabresd is a board based on mx6q SoC with the following features:
- 1GB of DDR3
- 1 USB OTG port
- 1 HDMI output port
- SPI NOR
- LVDS panel
- Gigabit Ethernet
- Camera Connector
- eMMC and SD card slot
- Audio
Add very basic support for it.
Signed-off-by: Fabio Estevamfabio.este...@freescale.com
snip
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
According to this commit,
CONFIG_SYS_BAUDRATE_TABLE: Add config_fallbacks.h, place there
(26750c8aee2383a026e0cf89e9310628d3a5a6a0), the above line isn't
required anymore. Right?
Regards,
Vikram
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Re: [U-Boot] [PATCH 2/2] mx6: Add basic support for mx6qsabresd board.
Hi Vikram, On Wed, Sep 12, 2012 at 2:30 PM, Vikram Narayanan vikram...@gmail.com wrote: According to this commit, CONFIG_SYS_BAUDRATE_TABLE: Add config_fallbacks.h, place there (26750c8aee2383a026e0cf89e9310628d3a5a6a0), the above line isn't required anymore. Right? Yes, you are right. Will remove it in v2. Thanks, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] A little introduction
ons 2012-09-12 klockan 11:26 +1000 skrev Graeme Russ: I must make an apology - I had committed to assisting you and Tom in bringing this port into mainline U-Boot (including investigating the SPL breakage et. al.). No need to apology. We all have life (to various degrees) outside computers. AW A1X SPL seems to be under control. And currently massaging support for the two CPUs (AW A10 and A13) into a shared (and fully up to date) tree. The two CPUs are mostly the same for u-boot with only some tiny differences in DRAM and clocking. That's great news. When you say 'little brother', does that imply that the A13 is a lower-powered/featured device when compared against the A10? A13 is a very stripped down device compared to A10, aimed solely at dirt cheap 7 tablets where A10 is a general multi-purpose flexible beast. Good to hear that there are individuals committed to supporting this hardware. My perception is that we are seeing explosive growth in the 'cheap but feature-full' ARM SoC market. But the consequence of the amount of competition in the market is that vendor margins are dropping and, as a consequence, vendors are devoting very little time to support us. I just wish they would at least produce datasheets that were more than an over-rated product brochure ;) There is a restricted circulation AW A10 datasheet which is not the product brochure, but the Linux kernel sources is the authorative source of information in any interesting areas. Regards Henrik ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] mx6q: Factor out common DDR3 init code
Jason, On Tue, Sep 11, 2012 at 11:26 PM, Liu Hui-R64343 r64...@freescale.com wrote: Are you sure that we can use on DDR3 script to cover 3 kind of boards: ARM2/Sabrelite/SabreSD? Did you do the DDR stress test? Ok, looking more closely at this I will keep the ARM2 DDR3 init as is in my v2 series. sabrelite and sabresd does have the same DDR3 init as per the FSL U-boot source. arm2 has a different DDR3 density, so I will not touch this file. Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Help Required [imx35pdk]
I am adding support of imx35pdk in yocto. I have done with my bsp. But the u-boot that build in response of my bsp only runs over NOR and not on NAND. I spend 2 days on it but failed to do so. I read some where that mx35pdk required some external 4-pins bla bla something like that. Also the u-boot running on NOR is not configuring uImage. I am using tftp but when it comes on loading, it keeps on showing T T T T T... (time-out response). I'm stuck here. Need help :( I am using u-boot from this repo: git://git.denx.de/u-boot.git One thing more, in the above mentioned repository, there is a directory like spl_nand in which they have already add mx31pdk for u-boot-nand.bin support but not mx35pdk. What should i do to overcome all this ??? Regards, Usman ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Code Structure and API functionality of U-Boot
Hi,  I am a new member to u-boot mail list.  I have the source code of u-boot downloaded.I am aware that /boot,/board,/driver,include/config are the directory of imprtance.  I am trying to read the code.  1.I see that there are lots of other files and lots of APIs in the above direcories.Can some one describe/explain which API,which file does what operation say for ARM boards.  Any document/book suggestion on U-BOOT will be also helpfull on understanding the API functionality.  2.Suppose I want to debug the U-Boot code.Should I use Abatron BDI2000 hardware debugger ? OR is there any other method available?(I suppose I can not use gdb/kgdb)  Regards Chandan___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/7] S3C24XX: Add serial driver
Dear José Miguel Gonçalves,
Serial driver for the S3C24XX SoCs.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
drivers/serial/Makefile |1 +
drivers/serial/s3c24xx_serial.c | 146
+++ 2 files changed, 147 insertions(+)
create mode 100644 drivers/serial/s3c24xx_serial.c
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 65d0f23..2cbdaac 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -52,6 +52,7 @@ COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
COBJS-$(CONFIG_PXA_SERIAL) += serial_pxa.o
COBJS-$(CONFIG_SA1100_SERIAL) += serial_sa1100.o
COBJS-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
+COBJS-$(CONFIG_S3C24XX_SERIAL) += s3c24xx_serial.o
What's the difference between those two drivers ?!
COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
diff --git a/drivers/serial/s3c24xx_serial.c
b/drivers/serial/s3c24xx_serial.c new file mode 100644
index 000..11f13a5
--- /dev/null
+++ b/drivers/serial/s3c24xx_serial.c
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2012 INOV - INESC Inovacao
+ * Jose Goncalves jose.goncal...@inov.pt
+ *
+ * Based on drivers/serial/s3c64xx.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/arch/s3c24xx_cpu.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SERIAL0
+#define UART_NR S3C24XX_UART0
+
+#elif defined(CONFIG_SERIAL1)
+#define UART_NR S3C24XX_UART1
+
+#elif defined(CONFIG_SERIAL2)
+#define UART_NR S3C24XX_UART2
+
+#elif defined(CONFIG_SERIAL3)
+#define UART_NR S3C24XX_UART3
+
+#else
+#error Bad: you didn't configure serial ...
Error itself is Bad: so remove it
+#endif
+
+#define barrier() asm volatile( ::: memory)
Is that even used ?
+/*
+ * The coefficient, used to calculate the baudrate on S3C24XX UARTs is
+ * calculated as C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
+ * however, section 2.1.10 of the S3C2416 User's Manual doesn't recommend
+ * using 1 for 1, 3 for 2, ... (2^n - 1) for n, instead, they suggest
using + * these constants:
+ */
+static const int udivslot[] = {
const int const ... const array const members
+ 0x, 0x0080, 0x0808, 0x0888, 0x, 0x4924, 0x4A52, 0x54AA,
+ 0x, 0xD555, 0xD5D5, 0xDDD5, 0x, 0xDFDD, 0xDFDF, 0xFFDF,
+};
+
+void serial_setbrg(void)
+{
+ s3c24xx_uart *const uart = s3c24xx_get_base_uart(UART_NR);
+ u32 pclk;
+ u32 baudrate;
+ int i;
+
+ pclk = get_PCLK();
+ baudrate = gd-baudrate;
+
+ uart-ubrdiv = (pclk / baudrate / 16) - 1;
+ uart-udivslot = udivslot[(pclk / baudrate) % 16];
+
+ for (i = 0; i 100; i++)
+ barrier();
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+int serial_init(void)
+{
+ s3c24xx_uart *const uart = s3c24xx_get_base_uart(UART_NR);
+
+ /* FIFO enable, Tx/Rx FIFO clear */
+ uart-ufcon = 0x07;
+ uart-umcon = 0x00;
Magic numbers, fix
+ /* Normal mode, No parity, 1 stop bit, 8 data bits */
+ uart-ulcon = 0x03;
+ /* Polling mode */
+ uart-ucon = 0x005;
+
+ serial_setbrg();
+
+ return 0;
+}
+
+/*
+ * Read a single byte from the serial port.
+ */
+int serial_getc(void)
+{
+ s3c24xx_uart *const uart = s3c24xx_get_base_uart(UART_NR);
+
+ /* Wait for character to arrive */
+ while (!(uart-utrstat 0x1)) ;
+
+ return uart-urxh 0xff;
+}
+
+/*
+ * Output a single byte to the serial port.
+ */
+void serial_putc(const char c)
+{
+ s3c24xx_uart *const uart = s3c24xx_get_base_uart(UART_NR);
+
+ /* Wait for room in the TX FIFO */
+ while (!(uart-utrstat 0x2)) ;
+
+ uart-utxh = c;
+
+ /* If \n, also do \r */
+ if (c == '\n')
+ serial_putc('\r');
+}
+
+/*
+ * Test whether a character is in the RX buffer.
+ */
+int serial_tstc(void)
+{
+ s3c24xx_uart *const uart = s3c24xx_get_base_uart(UART_NR);
+
+
Re: [U-Boot] [PATCH 4/7] S3C24XX: Add RTC driver
Dear José Miguel Gonçalves,
RTC driver for the S3C24XX SoCs.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
drivers/rtc/Makefile |1 +
drivers/rtc/s3c24xx_rtc.c | 166
+ 2 files changed, 167
insertions(+)
create mode 100644 drivers/rtc/s3c24xx_rtc.c
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 8316e8f..bd8b1eb 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -69,6 +69,7 @@ COBJS-$(CONFIG_RTC_RTC4543) += rtc4543.o
COBJS-$(CONFIG_RTC_RV3029) += rv3029.o
COBJS-$(CONFIG_RTC_RX8025) += rx8025.o
COBJS-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o
+COBJS-$(CONFIG_RTC_S3C24XX) += s3c24xx_rtc.o
COBJS-$(CONFIG_RTC_S3C44B0) += s3c44b0_rtc.o
COBJS-$(CONFIG_RTC_X1205) += x1205.o
diff --git a/drivers/rtc/s3c24xx_rtc.c b/drivers/rtc/s3c24xx_rtc.c
new file mode 100644
index 000..3844e44
--- /dev/null
+++ b/drivers/rtc/s3c24xx_rtc.c
@@ -0,0 +1,166 @@
+/*
+ * (C) Copyright 2012 INOV - INESC Inovacao
+ * Jose Goncalves jose.goncal...@inov.pt
+ *
+ * Based on drivers/rtc/s3c24x0_rtc.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+
+#if defined(CONFIG_CMD_DATE)
+
+#include rtc.h
+#include asm/io.h
+#include asm/arch/s3c24xx_cpu.h
+
+static inline void rtc_access_enable(void)
+{
+ s3c24xx_rtc *const rtc = s3c24xx_get_base_rtc();
+ uchar rtccon;
+
+ rtccon = readb(rtc-rtccon);
+ rtccon |= 0x01;
+ writeb(rtccon, rtc-rtccon);
+}
+
+static inline void rtc_access_disable(void)
+{
+ s3c24xx_rtc *const rtc = s3c24xx_get_base_rtc();
+ uchar rtccon;
+
+ rtccon = readb(rtc-rtccon);
+ rtccon = ~0x01;
Magic numbers, fix globally in the patchset
+ writeb(rtccon, rtc-rtccon);
+}
+
+/*
-
*/ +
+int rtc_get(struct rtc_time *tmp)
+{
+ s3c24xx_rtc *const rtc = s3c24xx_get_base_rtc();
+ uchar sec, min, hour, mday, wday, mon, year;
+ int have_retried = 0;
+
+ rtc_access_enable();
+
+ /* Read RTC registers */
+retry_get_time:
+ min = readb(rtc-bcdmin);
+ hour = readb(rtc-bcdhour);
+ mday = readb(rtc-bcddate);
+ wday = readb(rtc-bcdday);
+ mon = readb(rtc-bcdmon);
+ year = readb(rtc-bcdyear);
+ sec = readb(rtc-bcdsec);
+
+ /* The only way to work out whether the RTC was mid-update
+ * when we read it is to check the seconds counter.
+ * If it's zero, then we re-try the entire read.
+ */
Wrong multiline comment style ... use ./tools/checkpatch.pl before resending
+ if (rtc-bcdsec == 0 !have_retried) {
I'm sure you can avoid the goto here ...besides, this rtc-bcdsec doesn't make
much sense
+ have_retried = 1;
+ goto retry_get_time;
+ }
+
+ rtc_access_disable();
+
+ debug(Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x
+ hr: %02x min: %02x sec: %02x\n,
+ year, mon, mday, wday, hour, min, sec);
+
+ tmp-tm_sec = bcd2bin(sec 0x7F);
+ tmp-tm_min = bcd2bin(min 0x7F);
+ tmp-tm_hour = bcd2bin(hour 0x3F);
+ tmp-tm_mday = bcd2bin(mday 0x3F);
+ tmp-tm_wday = bcd2bin(wday 0x07);
+ tmp-tm_mon = bcd2bin(mon 0x1F);
+ tmp-tm_year = bcd2bin(year);
+ if (tmp-tm_year 70)
+ tmp-tm_year += 2000;
+ else
+ tmp-tm_year += 1900;
+ tmp-tm_yday = 0;
+ tmp-tm_isdst = 0;
+
+ debug(Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n,
+ tmp-tm_year, tmp-tm_mon, tmp-tm_mday, tmp-tm_wday,
+ tmp-tm_hour, tmp-tm_min, tmp-tm_sec);
+
+ return 0;
+}
+
+int rtc_set(struct rtc_time *tmp)
+{
+ s3c24xx_rtc *const rtc = s3c24xx_get_base_rtc();
+ uchar sec, min, hour, mday, wday, mon, year;
+
+ debug(Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n,
+ tmp-tm_year, tmp-tm_mon, tmp-tm_mday, tmp-tm_wday,
+ tmp-tm_hour, tmp-tm_min, tmp-tm_sec);
+
+ if (tmp-tm_year 1970 || tmp-tm_year 2069) {
+ puts(ERROR: year should be between 1970 and 2069!\n);
+
Re: [U-Boot] Code Structure and API functionality of U-Boot
Dear chandan mohanty, Hi, I am a new member to u-boot mail list. I have the source code of u-boot downloaded.I am aware that /boot,/board,/driver,include/config are the directory of imprtance. I am trying to read the code. 1.I see that there are lots of other files and lots of APIs in the above direcories.Can some one describe/explain which API,which file does what operation say for ARM boards. Any document/book suggestion on U-BOOT will be also helpfull on understanding the API functionality. See doc/ and the denx u-boot wiki. 2.Suppose I want to debug the U-Boot code.Should I use Abatron BDI2000 hardware debugger ? OR is there any other method available?(I suppose I can not use gdb/kgdb) Either bdi2000 or openocd works just fine. Regards Chandan Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Help Required [imx35pdk]
Dear Muhammad Usman, Ccing Stefano. I am adding support of imx35pdk in yocto. I have done with my bsp. But the u-boot that build in response of my bsp only runs over NOR and not on NAND. I spend 2 days on it but failed to do so. I read some where that mx35pdk required some external 4-pins bla bla something like that. Also the u-boot running on NOR is not configuring uImage. I am using tftp but when it comes on loading, it keeps on showing T T T T T... (time-out response). I'm stuck here. Need help :( I am using u-boot from this repo: git://git.denx.de/u-boot.git One thing more, in the above mentioned repository, there is a directory like spl_nand in which they have already add mx31pdk for u-boot-nand.bin support but not mx35pdk. What should i do to overcome all this ??? Regards, Usman Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/7] S3C24XX: Add NAND Flash driver
Dear José Miguel Gonçalves,
NAND Flash driver with HW ECC for the S3C24XX SoCs.
Currently it only supports SLC NAND chips.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/s3c24xx_nand.c | 269
+++ 2 files changed, 270 insertions(+)
create mode 100644 drivers/mtd/nand/s3c24xx_nand.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 29dc20e..791ec44 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -60,6 +60,7 @@ COBJS-$(CONFIG_NAND_MXS) += mxs_nand.o
COBJS-$(CONFIG_NAND_NDFC) += ndfc.o
COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
+COBJS-$(CONFIG_NAND_S3C24XX) += s3c24xx_nand.o
COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
diff --git a/drivers/mtd/nand/s3c24xx_nand.c
b/drivers/mtd/nand/s3c24xx_nand.c new file mode 100644
index 000..eed72d5
--- /dev/null
+++ b/drivers/mtd/nand/s3c24xx_nand.c
@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2012 INOV - INESC Inovacao
+ * Jose Goncalves jose.goncal...@inov.pt
+ *
+ * Based on drivers/mtd/nand/s3c64xx.c and U-Boot 1.3.4 from Samsung.
+ * Supports only SLC NAND Flash chips.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include nand.h
+#include asm/io.h
+#include asm/arch/s3c24xx_cpu.h
+#include asm/errno.h
+
+#define NFCONT_ECC_ENC (118)
+#define NFCONT_WP(116)
+#define NFCONT_MECCLOCK (17)
+#define NFCONT_SECCLOCK (16)
+#define NFCONT_INITMECC (15)
+#define NFCONT_INITSECC (14)
+#define NFCONT_NCE1 (12)
+#define NFCONT_NCE0 (11)
+#define NFCONT_ENABLE(10)
+
+#define NFSTAT_RNB (10)
+
+#define MAX_CHIPS2
+static int nand_cs[MAX_CHIPS] = { 0, 1 };
+
+#ifdef CONFIG_SPL_BUILD
+#define printf(arg...) do {} while (0)
+#endif
+
+static void s3c_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+ s3c24xx_nand *const nand = s3c24xx_get_base_nand();
+ u_long nfcont;
+
+ nfcont = readl(nand-nfcont);
+
+ switch (chip) {
+ case -1:
+ nfcont |= NFCONT_NCE1 | NFCONT_NCE0;
+ break;
+ case 0:
+ nfcont = ~NFCONT_NCE0;
+ break;
+ case 1:
+ nfcont = ~NFCONT_NCE1;
+ break;
+ default:
+ return;
+ }
+
+ writel(nfcont, nand-nfcont);
+}
+
+/*
+ * Hardware specific access to control-lines function
+ */
+static void s3c_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int
ctrl) +{
+ s3c24xx_nand *const nand = s3c24xx_get_base_nand();
+ struct nand_chip *this = mtd-priv;
+
+ if (ctrl NAND_CTRL_CHANGE) {
+ if (ctrl NAND_CLE)
+ this-IO_ADDR_W = (void __iomem *)nand-nfcmmd;
+ else if (ctrl NAND_ALE)
+ this-IO_ADDR_W = (void __iomem *)nand-nfaddr;
+ else
+ this-IO_ADDR_W = (void __iomem *)nand-nfdata;
Do you need this cast ?
+ if (ctrl NAND_NCE)
+ s3c_nand_select_chip(mtd, *(int *)this-priv);
+ else
+ s3c_nand_select_chip(mtd, -1);
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this-IO_ADDR_W);
+}
+
+/*
+ * Function for checking device ready pin
+ */
+static int s3c_nand_device_ready(struct mtd_info *mtdinfo)
+{
+ s3c24xx_nand *const nand = s3c24xx_get_base_nand();
+
+ return readl(nand-nfstat) NFSTAT_RNB;
+}
+
+#ifdef CONFIG_S3C24XX_NAND_HWECC
+/*
+ * This function is called before encoding ECC codes to ready ECC engine.
+ */
+static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+ s3c24xx_nand *const nand = s3c24xx_get_base_nand();
+ u_long nfcont, nfconf;
+
+ /* Set 1-bit ECC */
+ nfconf = readl(nand-nfconf);
+#if defined(CONFIG_S3C2412) || defined(CONFIG_S3C2413)
+ nfconf = ~(0x1 24);
+#else
+ nfconf = ~(0x3 23);
+#endif
Magic
+ writel(nfconf,
[U-Boot] [PATCH 0/5] mpc8308rdb: improved hardware support
From: Ira W. Snyder i...@ovro.caltech.edu This series improves the hardware support for the Freescale MPC8308RDB board. Optional support for the SPI pins routed to header J8 is added for testing SPI flash chips. This was tested with a Spansion S25FL256S1. This is not enabled by default, because it breaks TSEC2 due to a pinmux conflict. Support for the onboard eSDHC MMC/SD controller is added. The SPI controller driver is fixed so that it works with MPC8308RDB (probably all 83xx boards are broken before this fix). Without the fix, the waveforms generated by the driver are incorrect (confirmed with an oscilloscope). Ira W. Snyder (5): mpc8xxx_spi: fix SPI support on MPC8308RDB mpc8308rdb: add support for Spansion SPI flash on header J8 spansion: add support for S25FL256S1 mpc8308rdb: add support for FIT images mpc8308rdb: add support for eSDHC MMC controller board/freescale/mpc8308rdb/mpc8308rdb.c | 57 +++ drivers/mtd/spi/spansion.c |8 drivers/spi/mpc8xxx_spi.c |4 ++ include/configs/MPC8308RDB.h| 31 + 4 files changed, 100 insertions(+), 0 deletions(-) -- 1.7.8.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/5] spansion: add support for S25FL256S1
From: Ira W. Snyder i...@ovro.caltech.edu
Add support for the S25FL256S1 flash chip. It is a 256Mb (32MB) flash
comprised of 64KB pages.
Signed-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
drivers/mtd/spi/spansion.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
index 457cc06..76eebf8 100644
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -78,6 +78,14 @@ static const struct spansion_spi_flash_params
spansion_spi_flash_table[] = {
.name = S25FL064A,
},
{
+ .idcode1 = 0x0219,
+ .idcode2 = 0x4d01,
+ .page_size = 256,
+ .pages_per_sector = 256,
+ .nr_sectors = 512,
+ .name = S25FL256S1,
+ },
+ {
.idcode1 = 0x2018,
.idcode2 = 0x0301,
.page_size = 256,
--
1.7.8.6
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[U-Boot] [PATCH 4/5] mpc8308rdb: add support for FIT images
From: Ira W. Snyder i...@ovro.caltech.edu This is very useful on a modern system. Signed-off-by: Ira W. Snyder i...@ovro.caltech.edu --- include/configs/MPC8308RDB.h |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index a24538a..c65635f 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -37,6 +37,10 @@ #define CONFIG_MISC_INIT_R +/* new uImage format support */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 + /* * On-board devices * -- 1.7.8.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/5] mpc8308rdb: add support for eSDHC MMC controller
From: Ira W. Snyder i...@ovro.caltech.edu
Add support for the onboard eSDHC MMC controller. The hardware on the
MPC8308RDB has the following errata:
- ESDHC111: manual asynchronous CMD12 is broken
- DMA is broken (PIO works)
Signed-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
board/freescale/mpc8308rdb/mpc8308rdb.c |8
include/configs/MPC8308RDB.h| 14 ++
2 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c
b/board/freescale/mpc8308rdb/mpc8308rdb.c
index b97cdc1..7fa3066 100644
--- a/board/freescale/mpc8308rdb/mpc8308rdb.c
+++ b/board/freescale/mpc8308rdb/mpc8308rdb.c
@@ -66,6 +66,13 @@ void spi_cs_deactivate(struct spi_slave *slave)
}
#endif /* CONFIG_MPC8XXX_SPI */
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+ return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
static u8 read_board_info(void)
{
u8 val8;
@@ -173,6 +180,7 @@ void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
fdt_fixup_dr_usb(blob, bd);
+ fdt_fixup_esdhc(blob, bd);
}
#endif
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index c65635f..2d48dde 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -41,6 +41,20 @@
#define CONFIG_FIT 1
#define CONFIG_FIT_VERBOSE 1
+#define CONFIG_MMC 1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ESDHC_USE_PIO
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
/*
* On-board devices
*
--
1.7.8.6
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[U-Boot] [PATCH 1/5] mpc8xxx_spi: fix SPI support on MPC8308RDB
From: Ira W. Snyder i...@ovro.caltech.edu
The MPC8308RDB Reference Manual states that no bits in the SPMODE
register are allowed to change while the enable (EN) bit is set.
This driver changes the character length bits (LEN) while the enable
(EN) bit is set. Clearing the EN bit while changing the LEN bits makes
the driver work correctly on MPC8308RDB.
Signed-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
drivers/spi/mpc8xxx_spi.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c
index 44ab39d..4e46041 100644
--- a/drivers/spi/mpc8xxx_spi.c
+++ b/drivers/spi/mpc8xxx_spi.c
@@ -124,6 +124,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout,
* len 16 0
*/
+ spi-mode = ~SPI_MODE_EN;
+
if (bitlen = 16) {
if (bitlen = 4)
spi-mode = (spi-mode 0xff0f) |
@@ -138,6 +140,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout,
dout += 4;
}
+ spi-mode |= SPI_MODE_EN;
+
spi-tx = tmpdout; /* Write the data out */
debug(*** spi_xfer: ... %08x written\n, tmpdout);
--
1.7.8.6
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[U-Boot] [PATCH 2/5] mpc8308rdb: add support for Spansion SPI flash on header J8
From: Ira W. Snyder i...@ovro.caltech.edu
The SPI pins are routed to header J8 for testing SPI functionality. A
Spansion flash has been wired up and tested on this header.
This patch breaks support for the second TSEC interface, since the GPIO
pin used as a chip select is pinmuxed with some of the TSEC pins.
Signed-off-by: Ira W. Snyder i...@ovro.caltech.edu
---
board/freescale/mpc8308rdb/mpc8308rdb.c | 49 +++
include/configs/MPC8308RDB.h| 13
2 files changed, 62 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c
b/board/freescale/mpc8308rdb/mpc8308rdb.c
index 5c54357..b97cdc1 100644
--- a/board/freescale/mpc8308rdb/mpc8308rdb.c
+++ b/board/freescale/mpc8308rdb/mpc8308rdb.c
@@ -24,6 +24,7 @@
#include common.h
#include hwconfig.h
#include i2c.h
+#include spi.h
#include libfdt.h
#include fdt_support.h
#include pci.h
@@ -36,6 +37,35 @@
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * The following are used to control the SPI chip selects for the SPI command.
+ */
+#ifdef CONFIG_MPC8XXX_SPI
+
+#define SPI_CS_MASK0x0040
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ /* active low */
+ clrbits_be32(immr-gpio[0].dat, SPI_CS_MASK);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ /* inactive high */
+ setbits_be32(immr-gpio[0].dat, SPI_CS_MASK);
+}
+#endif /* CONFIG_MPC8XXX_SPI */
+
static u8 read_board_info(void)
{
u8 val8;
@@ -109,6 +139,25 @@ void pci_init_board(void)
*/
int misc_init_r(void)
{
+#ifdef CONFIG_MPC8XXX_SPI
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ sysconf83xx_t *sysconf = immr-sysconf;
+
+ /*
+* Set proper bits in SICRH to allow SPI on header J8
+*
+* NOTE: this breaks the TSEC2 interface, attached to the Vitesse
+* switch. The pinmux configuration does not have a fine enough
+* granularity to support both simultaneously.
+*/
+ clrsetbits_be32(sysconf-sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
+ puts(WARNING: SPI enabled, TSEC2 support is broken\n);
+
+ /* Set header J8 SPI chip select output, disabled */
+ setbits_be32(immr-gpio[0].dir, SPI_CS_MASK);
+ setbits_be32(immr-gpio[0].dat, SPI_CS_MASK);
+#endif
+
#ifdef CONFIG_VSC7385_IMAGE
if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
CONFIG_VSC7385_IMAGE_SIZE)) {
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 7f2761c..a24538a 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -340,6 +340,19 @@
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
+/*
+ * SPI on header J8
+ *
+ * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
+ * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
+ */
+#ifdef CONFIG_MPC8XXX_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_USE_SPIFLASH
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#endif
/*
* Board info - revision and where boot from
--
1.7.8.6
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Re: [U-Boot] Help Required [imx35pdk]
Am 12/09/2012 23:07, schrieb Marek Vasut: Dear Muhammad Usman, Hi Muhammad, Ccing Stefano. I am adding support of imx35pdk in yocto. I have done with my bsp. But the u-boot that build in response of my bsp only runs over NOR and not on NAND. I spend 2 days on it but failed to do so. U-Boot for mx35pdk runs from NOR and not from NAND. There is no support to run from NAND. Even if I can convince the board to boot from NAND, this was not pushed to mainline. I explain why. You have found nand_spl with support for mx31pdk. This was the method we have previously to boot from NAND. We have now a generic framework for SPL, and all new boards (or added support for booting from NAND) must use it. A board using the old nand_spl will not be merged into mainline. The mx35pdk was not ported to this generic SPL. We are really merging this framework now to make it available for all SOC, because it was common only for TI processor. I read some where that mx35pdk required some external 4-pins bla bla something like that. It does not require external pins. You have to configure the dip switches on the mx35pdk. Also the u-boot running on NOR is not configuring uImage. I am using tftp but when it comes on loading, it keeps on showing T T T T T... (time-out response). I think I have tested it recently, and it worked - which of the two interfaces have you used in u-boot ? Both (FEC and SMC) are supported in the mx35pdk u-boot, and both should work, as far as I know. One thing more, in the above mentioned repository, there is a directory like spl_nand in which they have already add mx31pdk for u-boot-nand.bin support but not mx35pdk. What should i do to overcome all this ??? This is what I talked about before. All boards using spl_nand were added a lot of time ago. spl_nand requires a separate driver for SPL, and this is highly inefficient. The way we decided to go is to use a generic SPL, valid for all SOC. And there is not yet a port for mx35pdk to boot directly from NAND. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] mx6q: Factor out common DDR3 init code
Am 12/09/2012 20:22, schrieb Fabio Estevam: Jason, Hi Fabio, On Tue, Sep 11, 2012 at 11:26 PM, Liu Hui-R64343 r64...@freescale.com wrote: Are you sure that we can use on DDR3 script to cover 3 kind of boards: ARM2/Sabrelite/SabreSD? Did you do the DDR stress test? Ok, looking more closely at this I will keep the ARM2 DDR3 init as is in my v2 series. sabrelite and sabresd does have the same DDR3 init as per the FSL U-boot source. arm2 has a different DDR3 density, so I will not touch this file. Ok - before you put your next version, is imx-common the right place fir it ? I mean, in imx-common we should put code that can be shared among different Freescale's SOCs. The imximage you want to share is common to some boards, not SOCs. Should we put it into a freescale's directory, let see something into boards/freescale ? There is already a boards/freescale/common, but it is PowerPC specific, so maybe it is not the right place, but we could add a new one. What do you think ? Best regards, Stefano -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/9] Add basic Tegra30 (T30) support
This patch series adds basic (boot to cmd prompt) support for Tegra30.
This is based on the Tegra20 SPL, which initializes the AVP (ARM7TDMI
boot proc) first, then control is transferred to the CPU (A9 quad cluster).
It is based on current u-boot-tegra/next.
Future patches will add support/drivers for MMC, USB, I2C, SPI, NAND,
and other peripherals. The Cardhu T30 board is supported initially.
Tom Warren (9):
Tegra: T30: Add include files
Tegra: T30: Add AVP (arm720t) files
Tegra: T30: Add CPU (armv7) files
Tegra: T30: Add common Tegra30 CPU files
Tegra: DT: Add preliminary device tree files for T30 Cardhu
Tegra30: Add Cardhu board files
Tegra30: Add config files (common and Cardhu)
Tegra30: Add common pinmux config in board_early_init_f
Tegra30: Enable Cardhu build (SPL)
Makefile | 23 +
arch/arm/cpu/{armv7 = arm720t/tegra30}/Makefile | 27 +-
arch/arm/cpu/arm720t/tegra30/board.h | 25 +
arch/arm/cpu/arm720t/tegra30/config.mk | 26 +
arch/arm/cpu/arm720t/tegra30/cpu.c | 570 +++
arch/arm/cpu/arm720t/tegra30/cpu.h | 65 ++
arch/arm/cpu/arm720t/tegra30/spl.c | 132 +++
arch/arm/cpu/armv7/Makefile |2 +-
arch/arm/cpu/armv7/start.S |4 +-
arch/arm/cpu/armv7/{ = tegra30}/Makefile| 23 +-
arch/arm/cpu/armv7/tegra30/cmd_enterrcm.c| 65 ++
arch/arm/cpu/armv7/tegra30/config.mk | 26 +
arch/arm/cpu/{armv7 = tegra30-common}/Makefile | 28 +-
arch/arm/cpu/tegra30-common/ap30.c | 98 ++
arch/arm/cpu/tegra30-common/board.c | 141 +++
arch/arm/cpu/tegra30-common/clock.c | 1099 ++
arch/arm/cpu/tegra30-common/funcmux.c| 74 ++
arch/arm/cpu/tegra30-common/lowlevel_init.S | 42 +
arch/arm/cpu/tegra30-common/pinmux.c | 507 ++
arch/arm/cpu/tegra30-common/sys_info.c | 35 +
arch/arm/cpu/tegra30-common/timer.c | 111 +++
arch/arm/dts/tegra30.dtsi| 280 ++
arch/arm/include/asm/arch-tegra30/ap30.h | 99 ++
arch/arm/include/asm/arch-tegra30/board.h| 30 +
arch/arm/include/asm/arch-tegra30/clk_rst.h | 277 ++
arch/arm/include/asm/arch-tegra30/clock.h| 602
arch/arm/include/asm/arch-tegra30/emc.h | 113 +++
arch/arm/include/asm/arch-tegra30/flow.h | 42 +
arch/arm/include/asm/arch-tegra30/funcmux.h | 77 ++
arch/arm/include/asm/arch-tegra30/fuse.h | 39 +
arch/arm/include/asm/arch-tegra30/gp_padctrl.h | 73 ++
arch/arm/include/asm/arch-tegra30/gpio.h | 322 +++
arch/arm/include/asm/arch-tegra30/hardware.h | 29 +
arch/arm/include/asm/arch-tegra30/mmc.h | 28 +
arch/arm/include/asm/arch-tegra30/pinmux.h | 610
arch/arm/include/asm/arch-tegra30/pmc.h | 132 +++
arch/arm/include/asm/arch-tegra30/pmu.h | 30 +
arch/arm/include/asm/arch-tegra30/scu.h | 43 +
arch/arm/include/asm/arch-tegra30/sys_proto.h| 35 +
arch/arm/include/asm/arch-tegra30/tegra30.h | 109 +++
arch/arm/include/asm/arch-tegra30/tegra_i2c.h| 164
arch/arm/include/asm/arch-tegra30/timer.h| 31 +
arch/arm/include/asm/arch-tegra30/uart.h | 47 +
arch/arm/include/asm/arch-tegra30/usb.h | 253 +
arch/arm/include/asm/arch-tegra30/warmboot.h | 150 +++
board/nvidia/cardhu/Makefile | 48 +
board/nvidia/cardhu/cardhu.c | 87 ++
board/nvidia/cardhu/pinmux-config-common.h | 346 +++
board/nvidia/common/board.c | 27 +-
board/nvidia/dts/tegra30-cardhu.dts | 92 ++
boards.cfg |1 +
drivers/gpio/tegra_gpio.c|4 +
include/configs/cardhu.h | 52 +
include/configs/tegra30-common.h | 188
include/serial.h |3 +-
spl/Makefile |3 +
56 files changed, 7536 insertions(+), 53 deletions(-)
copy arch/arm/cpu/{armv7 = arm720t/tegra30}/Makefile (70%)
create mode 100644 arch/arm/cpu/arm720t/tegra30/board.h
create mode 100644 arch/arm/cpu/arm720t/tegra30/config.mk
create mode 100644 arch/arm/cpu/arm720t/tegra30/cpu.c
create mode 100644 arch/arm/cpu/arm720t/tegra30/cpu.h
create mode 100644 arch/arm/cpu/arm720t/tegra30/spl.c
copy arch/arm/cpu/armv7/{ = tegra30}/Makefile (76%)
create mode 100644 arch/arm/cpu/armv7/tegra30/cmd_enterrcm.c
create mode 100644 arch/arm/cpu/armv7/tegra30/config.mk
copy arch/arm/cpu/{armv7 = tegra30-common}/Makefile (69%)
create mode 100644 arch/arm/cpu/tegra30-common/ap30.c
create mode 100644 arch/arm/cpu/tegra30-common/board.c
create mode 100644
[U-Boot] [PATCH 2/9] Tegra: T30: Add AVP (arm720t) files
Signed-off-by: Tom Warren twar...@nvidia.com --- arch/arm/cpu/arm720t/tegra30/Makefile | 48 +++ arch/arm/cpu/arm720t/tegra30/board.h | 25 ++ arch/arm/cpu/arm720t/tegra30/config.mk | 26 ++ arch/arm/cpu/arm720t/tegra30/cpu.c | 570 arch/arm/cpu/arm720t/tegra30/cpu.h | 65 arch/arm/cpu/arm720t/tegra30/spl.c | 132 6 files changed, 866 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm720t/tegra30/Makefile create mode 100644 arch/arm/cpu/arm720t/tegra30/board.h create mode 100644 arch/arm/cpu/arm720t/tegra30/config.mk create mode 100644 arch/arm/cpu/arm720t/tegra30/cpu.c create mode 100644 arch/arm/cpu/arm720t/tegra30/cpu.h create mode 100644 arch/arm/cpu/arm720t/tegra30/spl.c diff --git a/arch/arm/cpu/arm720t/tegra30/Makefile b/arch/arm/cpu/arm720t/tegra30/Makefile new file mode 100644 index 000..96e722c --- /dev/null +++ b/arch/arm/cpu/arm720t/tegra30/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2010-2012 Nvidia Corporation. +# +# (C) Copyright 2000-2008 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(SOC).o + +COBJS-y+= cpu.o +COBJS-$(CONFIG_SPL_BUILD) += spl.o + +SRCS := $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/arm/cpu/arm720t/tegra30/board.h b/arch/arm/cpu/arm720t/tegra30/board.h new file mode 100644 index 000..fc11a7b --- /dev/null +++ b/arch/arm/cpu/arm720t/tegra30/board.h @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation www.nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +void board_init_uart_f(void); +void gpio_config_uart(void); diff --git a/arch/arm/cpu/arm720t/tegra30/config.mk b/arch/arm/cpu/arm720t/tegra30/config.mk new file mode 100644 index 000..ca9c6ea --- /dev/null +++ b/arch/arm/cpu/arm720t/tegra30/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation www.nvidia.com +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, ga...@denx.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +USE_PRIVATE_LIBGCC = yes diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c new file mode 100644 index 000..f7d9b87 --- /dev/null +++
[U-Boot] [PATCH 3/9] Tegra: T30: Add CPU (armv7) files
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/cpu/armv7/tegra30/Makefile | 48 +
arch/arm/cpu/armv7/tegra30/cmd_enterrcm.c | 65 +
arch/arm/cpu/armv7/tegra30/config.mk | 26 +++
3 files changed, 139 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/armv7/tegra30/Makefile
create mode 100644 arch/arm/cpu/armv7/tegra30/cmd_enterrcm.c
create mode 100644 arch/arm/cpu/armv7/tegra30/config.mk
diff --git a/arch/arm/cpu/armv7/tegra30/Makefile
b/arch/arm/cpu/armv7/tegra30/Makefile
new file mode 100644
index 000..3b98e23
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra30/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 20102012 Nvidia Corporation.
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(SOC).o
+
+COBJS-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
+
+COBJS := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all:$(obj).depend $(LIB)
+
+$(LIB):$(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/arch/arm/cpu/armv7/tegra30/cmd_enterrcm.c
b/arch/arm/cpu/armv7/tegra30/cmd_enterrcm.c
new file mode 100644
index 000..e146938
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra30/cmd_enterrcm.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Derived from code (arch/arm/lib/reset.c) that is:
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH www.elinos.com
+ * Marius Groeger mgroe...@sysgo.de
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH www.elinos.com
+ * Alex Zuepke a...@sysgo.de
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, ga...@denx.de
+ *
+ * (C) Copyright 2004
+ * DAVE Srl
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:i...@wawnet.biz
+ *
+ * (C) Copyright 2004 Texas Insturments
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see http://www.gnu.org/licenses/.
+ */
+
+#include common.h
+#include asm/arch/tegra30.h
+#include asm/arch/pmc.h
+
+static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ puts(Entering RCM...\n);
+ udelay(5);
+
+ pmc-pmc_scratch0 = 2;
+ disable_interrupts();
+ reset_cpu(0);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ enterrcm, 1, 0, do_enterrcm,
+ reset Tegra and enter USB Recovery Mode,
+
+);
diff --git a/arch/arm/cpu/armv7/tegra30/config.mk
b/arch/arm/cpu/armv7/tegra30/config.mk
new file mode 100644
index 000..fad9efa
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra30/config.mk
@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2010-2012
+# NVIDIA Corporation www.nvidia.com
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, ga...@denx.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is
[U-Boot] [PATCH 5/9] Tegra: DT: Add preliminary device tree files for T30 Cardhu
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/dts/tegra30.dtsi | 280 +++
board/nvidia/dts/tegra30-cardhu.dts | 92
2 files changed, 372 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/dts/tegra30.dtsi
create mode 100644 board/nvidia/dts/tegra30-cardhu.dts
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
new file mode 100644
index 000..a889705
--- /dev/null
+++ b/arch/arm/dts/tegra30.dtsi
@@ -0,0 +1,280 @@
+/include/ skeleton.dtsi
+
+/ {
+ model = NVIDIA Tegra30;
+ compatible = nvidia,tegra30;
+ interrupt-parent = intc;
+
+ tegra_car: clock@60006000 {
+ compatible = nvidia,tegra30-car;
+ reg = 0x60006000 0x1000;
+ #clock-cells = 1;
+ };
+
+ clocks {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ osc: clock {
+ compatible = fixed-clock;
+ #clock-cells = 0;
+ };
+ };
+
+ intc: interrupt-controller@50041000 {
+ compatible = nvidia,tegra30-gic;
+ interrupt-controller;
+ #interrupt-cells = 1;
+ reg = 0x50041000 0x1000 ,
+ 0x50040100 0x0100 ;
+ };
+
+ i2c@7000c000 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = nvidia,tegra30-i2c;
+ reg = 0x7000C000 0x100;
+ interrupts = 70 ;
+ /* PERIPH_ID_I2C1, PLL_P_OUT3 */
+ clocks = tegra_car 12, tegra_car 124;
+ };
+
+ i2c@7000c400 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = nvidia,tegra30-i2c;
+ reg = 0x7000C400 0x100;
+ interrupts = 116 ;
+ /* PERIPH_ID_I2C2, PLL_P_OUT3 */
+ clocks = tegra_car 54, tegra_car 124;
+ };
+
+ i2c@7000c500 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = nvidia,tegra30-i2c;
+ reg = 0x7000C500 0x100;
+ interrupts = 124 ;
+ /* PERIPH_ID_I2C3, PLL_P_OUT3 */
+ clocks = tegra_car 67, tegra_car 124;
+ };
+
+ i2c@7000d000 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = nvidia,tegra30-i2c-dvc;
+ reg = 0x7000D000 0x200;
+ interrupts = 85 ;
+ /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
+ clocks = tegra_car 47, tegra_car 124;
+ };
+
+ i2s@70002800 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = nvidia,tegra30-i2s;
+ reg = 0x70002800 0x200;
+ interrupts = 45 ;
+ dma-channel = 2 ;
+ };
+
+ i2s@70002a00 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = nvidia,tegra30-i2s;
+ reg = 0x70002a00 0x200;
+ interrupts = 35 ;
+ dma-channel = 1 ;
+ };
+
+ das@7c00 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = nvidia,tegra30-das;
+ reg = 0x7c00 0x80;
+ };
+
+ gpio: gpio@6000d000 {
+ compatible = nvidia,tegra30-gpio;
+ reg = 0x6000d000 0x1000 ;
+ interrupts = 64 65 66 67 87 119 121 ;
+ #gpio-cells = 2;
+ gpio-controller;
+ };
+
+ pinmux: pinmux@7000 {
+ compatible = nvidia,tegra30-pinmux;
+ reg = 0x7014 0x10/* Tri-state registers */
+ 0x7080 0x20/* Mux registers */
+ 0x70a0 0x14/* Pull-up/down registers */
+ 0x7868 0xa8 ; /* Pad control registers */
+ };
+
+ serial@70006000 {
+ compatible = nvidia,tegra30-uart;
+ reg = 0x70006000 0x40;
+ id = 0;
+ reg-shift = 2;
+ interrupts = 68 ;
+ status = disabled;
+ };
+
+ serial@70006040 {
+ compatible = nvidia,tegra30-uart;
+ reg = 0x70006040 0x40;
+ id = 1;
+ reg-shift = 2;
+ interrupts = 69 ;
+ status = disabled;
+ };
+
+ serial@70006200 {
+ compatible = nvidia,tegra30-uart;
+ reg = 0x70006200 0x100;
+ id = 2;
+ reg-shift = 2;
+ interrupts = 78 ;
+ status = disabled;
+ };
+
+ serial@70006300 {
+ compatible = nvidia,tegra30-uart;
+ reg = 0x70006300 0x100;
+ id = 3;
+ reg-shift = 2;
+ interrupts = 122 ;
+
[U-Boot] [PATCH 6/9] Tegra30: Add Cardhu board files
Signed-off-by: Tom Warren twar...@nvidia.com
---
board/nvidia/cardhu/Makefile | 48
board/nvidia/cardhu/cardhu.c | 87 +++
board/nvidia/cardhu/pinmux-config-common.h | 346
3 files changed, 481 insertions(+), 0 deletions(-)
create mode 100644 board/nvidia/cardhu/Makefile
create mode 100644 board/nvidia/cardhu/cardhu.c
create mode 100644 board/nvidia/cardhu/pinmux-config-common.h
diff --git a/board/nvidia/cardhu/Makefile b/board/nvidia/cardhu/Makefile
new file mode 100644
index 000..a910577
--- /dev/null
+++ b/board/nvidia/cardhu/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2010-2012
+# NVIDIA Corporation www.nvidia.com
+#
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB):$(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c
new file mode 100644
index 000..f907906
--- /dev/null
+++ b/board/nvidia/cardhu/cardhu.c
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation www.nvidia.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/tegra30.h
+#include asm/arch/clock.h
+#include asm/arch/funcmux.h
+#include asm/arch/pinmux.h
+#include asm/arch/mmc.h
+#include asm/gpio.h
+#ifdef CONFIG_TEGRA_MMC
+#include mmc.h
+#endif
+
+/*
+ * Routine: gpio_config_uart
+ * Description: Does nothing on Cardhu - no conflict w/SPI.
+ */
+void gpio_config_uart(void)
+{
+}
+
+#ifdef CONFIG_TEGRA_MMC
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+static void pin_mux_mmc(void)
+{
+ funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
+ funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT);
+
+ /* For power GPIO PI6 */
+ pinmux_tristate_disable(PINGRP_ATA);
+ /* For CD GPIO PI5 */
+ pinmux_tristate_disable(PINGRP_ATC);
+}
+
+/* this is a weak define that we are overriding */
+int board_mmc_init(bd_t *bd)
+{
+ debug(board_mmc_init called\n);
+
+ /* Enable muxes, etc. for SDMMC controllers */
+ pin_mux_mmc();
+
+ debug(board_mmc_init: init eMMC\n);
+ /* init dev 0, eMMC chip, with 4-bit bus */
+ /* The board has an 8-bit bus, but 8-bit doesn't work yet */
+ tegra_mmc_init(0, 4, -1, -1);
+
+ debug(board_mmc_init: init SD slot\n);
+ /* init dev 1, SD slot, with 4-bit bus */
+ tegra_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_TEGRA
+void pin_mux_usb(void)
+{
+ /* For USB's GPIO PD0. For now, since we have no pinmux in fdt */
+ pinmux_tristate_disable(PINGRP_SLXK);
+}
+#endif
diff --git a/board/nvidia/cardhu/pinmux-config-common.h
b/board/nvidia/cardhu/pinmux-config-common.h
new file mode 100644
index 000..20583c9
--- /dev/null
+++ b/board/nvidia/cardhu/pinmux-config-common.h
@@
[U-Boot] [PATCH 8/9] Tegra30: Add common pinmux config in board_early_init_f
Signed-off-by: Tom Warren twar...@nvidia.com
---
board/nvidia/common/board.c | 27 ++-
1 files changed, 26 insertions(+), 1 deletions(-)
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index afe832a..4a86c30 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010,2011
+ * (C) Copyright 2010-2012
* NVIDIA Corporation www.nvidia.com
*
* See file CREDITS for list of people who contributed to this
@@ -25,7 +25,11 @@
#include ns16550.h
#include linux/compiler.h
#include asm/io.h
+#if defined(CONFIG_TEGRA20)
#include asm/arch/tegra20.h
+#else /* Tegra30 */
+#include asm/arch/tegra30.h
+#endif
#include asm/arch/sys_proto.h
#include asm/arch/board.h
@@ -87,6 +91,25 @@ static void power_det_init(void)
#endif
}
+#ifdef CONFIG_TEGRA30
+#include ../cardhu/pinmux-config-common.h
+#endif
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+static void pinmux_init(void)
+{
+#if defined(CONFIG_TEGRA30)
+ pinmux_config_table(tegra3_pinmux_common,
+ ARRAY_SIZE(tegra3_pinmux_common));
+
+ pinmux_config_table(unused_pins_lowpower,
+ ARRAY_SIZE(unused_pins_lowpower));
+#endif
+}
+
/*
* Routine: board_init
* Description: Early hardware init.
@@ -152,6 +175,8 @@ void gpio_early_init(void) __attribute__((weak,
alias(__gpio_early_init)));
int board_early_init_f(void)
{
+ pinmux_init();
+
board_init_uart_f();
/* Initialize periph GPIOs */
--
1.7.0.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 9/9] Tegra30: Enable Cardhu build (SPL)
This builds boots to the command prompt on a Cardhu (T30) board.
This is a barebones binary - no I2C, USB, MMC, SPI, etc.
Drivers for those peripherals to follow.
Signed-off-by: Tom Warren twar...@nvidia.com
---
Makefile| 23 +++
arch/arm/cpu/armv7/Makefile |2 +-
arch/arm/cpu/armv7/start.S |4 ++--
boards.cfg |1 +
drivers/gpio/tegra_gpio.c |4
include/serial.h|3 ++-
spl/Makefile|3 +++
7 files changed, 36 insertions(+), 4 deletions(-)
diff --git a/Makefile b/Makefile
index d6d8ab2..13f4850 100644
--- a/Makefile
+++ b/Makefile
@@ -322,6 +322,9 @@ endif
ifeq ($(SOC),tegra20)
LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
endif
+ifeq ($(SOC),tegra30)
+LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
+endif
LIBS := $(addprefix $(obj),$(sort $(LIBS-y)))
.PHONY : $(LIBS)
@@ -389,6 +392,13 @@ else
ALL-y += $(obj)u-boot-nodtb-tegra.bin
endif
endif
+ifeq ($(SOC),tegra30)
+ifeq ($(CONFIG_OF_SEPARATE),y)
+ALL-y += $(obj)u-boot-dtb-tegra.bin
+else
+ALL-y += $(obj)u-boot-nodtb-tegra.bin
+endif
+endif
all: $(ALL-y) $(SUBDIR_EXAMPLES)
@@ -497,6 +507,19 @@ $(obj)u-boot-nodtb-tegra.bin:
$(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
rm $(obj)spl/u-boot-spl-pad.bin
endif
endif
+ifeq ($(SOC),tegra30)
+ifeq ($(CONFIG_OF_SEPARATE),y)
+$(obj)u-boot-dtb-tegra.bin:$(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(obj)u-boot.dtb
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O
binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
+ cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin
$(obj)u-boot.dtb $@
+ rm $(obj)spl/u-boot-spl-pad.bin
+else
+$(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O
binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
+ cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $@
+ rm $(obj)spl/u-boot-spl-pad.bin
+endif
+endif
ifeq ($(CONFIG_SANDBOX),y)
GEN_UBOOT = \
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 4fdbee4..6389d52 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,7 @@ COBJS += cache_v7.o
COBJS += cpu.o
COBJS += syslib.o
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
+ifneq
($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20)$(CONFIG_TEGRA30),)
SOBJS += lowlevel_init.o
endif
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 32658eb..b2bac3e 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -280,14 +280,14 @@ jump_2_ram:
/*
* Move vector table
*/
-#if !defined(CONFIG_TEGRA20)
+#if !defined(CONFIG_TEGRA)
#if !(defined(CONFIG_OMAP44XX) defined(CONFIG_SPL_BUILD))
/* Set vector address in CP15 VBAR register */
ldr r0, =_start
add r0, r0, r9
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
#endif
-#endif /* !Tegra20 */
+#endif /* !Tegra20 or 30 */
ldr r0, _board_init_r_ofs
adr r1, _start
diff --git a/boards.cfg b/boards.cfg
index 613d6b2..8da07ea 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -271,6 +271,7 @@ harmony arm armv7:arm720t
harmony nvidia
seaboard arm armv7:arm720t seaboard
nvidia tegra20
ventana arm armv7:arm720t ventana
nvidia tegra20
whistler arm armv7:arm720t whistler
nvidia tegra20
+cardhu arm armv7:arm720t cardhu
nvidia tegra30
u8500_href arm armv7 u8500
st-ericssonu8500
snowball arm armv7 snowball
st-ericssonu8500
actux1_4_16 arm ixp actux1 -
- actux1:FLASH2X2
diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c
index 747f4cf..6f6dceb 100644
--- a/drivers/gpio/tegra_gpio.c
+++ b/drivers/gpio/tegra_gpio.c
@@ -30,7 +30,11 @@
#include common.h
#include asm/io.h
#include asm/bitops.h
+#if defined(CONFIG_TEGRA20)
#include asm/arch/tegra20.h
+#else /* Tegra30 */
+#include asm/arch/tegra30.h
+#endif
#include asm/gpio.h
enum {
diff --git a/include/serial.h b/include/serial.h
index cbdf8a9..acb13de 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -31,7 +31,8 @@ extern struct serial_device *default_serial_console(void);
defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
- defined(CONFIG_TEGRA20)
[U-Boot] [PATCH 7/9] Tegra30: Add config files (common and Cardhu)
Signed-off-by: Tom Warren twar...@nvidia.com --- include/configs/cardhu.h | 52 +++ include/configs/tegra30-common.h | 188 ++ 2 files changed, 240 insertions(+), 0 deletions(-) create mode 100644 include/configs/cardhu.h create mode 100644 include/configs/tegra30-common.h diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h new file mode 100644 index 000..bfadbff --- /dev/null +++ b/include/configs/cardhu.h @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation www.nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include asm/sizes.h + +#include tegra30-common.h + +/* Enable fdt support for Cardhu. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra30-cardhu +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* High-level configuration options */ +#define V_PROMPT Tegra30 (Cardhu) # +#define CONFIG_TEGRA_BOARD_STRING NVIDIA Cardhu + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1NV_PA_APB_UARTA_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_CARDHU + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ENV_IS_NOWHERE + +#include tegra-common-post.h + +#endif /* __CONFIG_H */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h new file mode 100644 index 000..b23823d --- /dev/null +++ b/include/configs/tegra30-common.h @@ -0,0 +1,188 @@ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation www.nvidia.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __TEGRA30_COMMON_H +#define __TEGRA30_COMMON_H +#include asm/sizes.h + +/* + * QUOTE(m) will evaluate to a string version of the value of the macro m + * passed in. The extra level of indirection here is to first evaluate the + * macro m before applying the quoting operator. + */ +#define QUOTE_(m) #m +#define QUOTE(m)QUOTE_(m) + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */ +#define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */ +#define CONFIG_TEGRA /* which is a Tegra generic machine */ +#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ + +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#include asm/arch/tegra30.h /* get chip and board defs */ + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_OF_LIBFDT /* enable passing of devicetree */ + +/* Environment */ +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_SIZE0x2000 /* Total Size Environment */ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (4 20) /* 4MB */ + +/* + * PllX Configuration + */ +#define CONFIG_SYS_CPU_OSC_FREQUENCY 100 /* Set CPU clock to 1GHz */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 21600 /* 216MHz (pllp_out0) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE(-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console
Re: [U-Boot] using initrd with U-boot on the imx28evk
Dear Bill, Has anyone used U-boot on the imx28evk with initrd to setup a small rootfs in RAM? I need the ability to do have a small temp rootfs to assist in mounting a full rootfs from a USB for field upgrade purposes. Yes, it's a linux thingie though. What's the problem? What version of uboot do you use? Thanks, Bill Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Kernel boot halts with Verifying Checksum ... Bad Data CRC
Dear Ellis Andrew, Hi, I'm not sure if this is specifically related to u boot. I have compiled a linux kernel, which if I run on a system with flash memory with 256k sector size there are no problems, however if I rebuild for a system using flash with 64k sector size the boot process halts with the following errors Booting image at 0006 ... ## Copy image from flash 0006 to ram 0020 ... Image Name: Image Type: ARM Linux Kernel Image (uncompressed) Data Size:1759300 Bytes = 1.7 MB Load Address: 8000 Entry Point: 8000 Verifying Checksum ... Bad Data CRC The script I'm using to make my kernel image is: SRC=$2/arch/arm/boot/uImage if [ -f $SRC ]; then printf Kernel source in: %s\n $SRC else printf Error: No kernel source in : %s\n $SRC exit 0 fi mkimage -T kernel -C none -a 0x8000 -e 0x8000 -d $SRC scp_uimage The above script is called with: echo Destination: scp_zimagecreate_flash_image kernel linux-2.6.24/ I'd say it's a programming error (you're writing your flash incorrectly or your uboot is configured for 256kb flash)? This is not autodetected. Also not, make uImage in the kernel tree should do the job. What do I need to do differently with mkimage so that u boot is happy with the CRC? Andrew Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Cache alignment warnings on Tegra (ARM)
Dear Stephen Warren, On 09/12/2012 10:19 AM, Tom Warren wrote: Folks, Stephen Warren has posted an internal bug regarding the cache alignment 'warnings' seen on Tegra20 boards when accessing MMC. Here's the gist: Executing mmc dev 0 still yields cache warnings: Tegra20 (Harmony) # mmc dev 0 ERROR: v7_dcache_inval_range- stop address is not aligned- 0x3fb69908 mmc0 is current device ... There have been patches in the past (IIRC) that have tried to ensure all callers (FS, MMC driver, USB driver, etc.) force their buffers to the appropriate alignment, but I don't know that we can ever correct every instance, now or in the future. Can we start a discussion about what we can do about this warning? Adding an appropriate #ifdef (CONFIG_SYS_NO_CACHE_ALIGNMENT_WARNINGS, etc.) where Stephen put his #if 0's would be one approach, or changing the printf() to a debug(), perhaps. As far as I can tell, these alignment 'errors' don't seem to produce bad data in the transfer. I don't think simply turning off the warning is the correct approach; I believe they represent real problems that can in fact cause data corruption. I don't believe we have any choice other than to fully solve the root-cause. Try CONFIG_MMC_BOUNCE_BUFFER or what it was called ... see inclued/configs/m28evk.h , I use it there. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V5 1/2] ext4fs ls load support
On Mon, Aug 13, 2012 at 01:28:19PM -0500, Rob Herring wrote: On 08/13/2012 06:52 AM, Wolfgang Denk wrote: Dear Rob Herring, In message 50244d5a.3080...@gmail.com you wrote: I reported already that the prior version that ext4 has issues with sub-directories. I don't think that has been addressed in V5. Some directories show up fine and some don't. So it's kind of random whether u-boot can read a /boot directory. This was after full ubuntu installs. I'd guess a simple test with a couple of files and directories will not show the problem. We really need a test case here. In my (certainly not very extensive) tests I didn't see such a problem. Can you please describe what failed for you? I do an ubuntu install to a single ext4 fs and then ext2ls gives this: [snip] The problem is in the directories with sizes of 0. It does seem to be directories with higher blkno's. Perhaps the lack of support for hash table directory entries is a problem. Just guessing here as I don't know much about ext4 structure. I haven't been able to produce a simple example just creating a bunch of files and directories, so only the disk after an ubuntu install has the problem. I took an Ubuntu install I had (for x86) that was on a USB drive, had been pretty extensively used, and was is ext4. I couldn't find any size 0 directories. Are you able to reproduce this problem on other hardware? Is the image in question NOT remountable as ext3 (extents is set, generated) ? My biggest concern is breakage among ext2/3 filesystems. Thanks! -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V5 1/2] ext4fs ls load support
On 09/12/2012 05:49 PM, Tom Rini wrote: On Mon, Aug 13, 2012 at 01:28:19PM -0500, Rob Herring wrote: On 08/13/2012 06:52 AM, Wolfgang Denk wrote: Dear Rob Herring, In message 50244d5a.3080...@gmail.com you wrote: I reported already that the prior version that ext4 has issues with sub-directories. I don't think that has been addressed in V5. Some directories show up fine and some don't. So it's kind of random whether u-boot can read a /boot directory. This was after full ubuntu installs. I'd guess a simple test with a couple of files and directories will not show the problem. We really need a test case here. In my (certainly not very extensive) tests I didn't see such a problem. Can you please describe what failed for you? I do an ubuntu install to a single ext4 fs and then ext2ls gives this: [snip] The problem is in the directories with sizes of 0. It does seem to be directories with higher blkno's. Perhaps the lack of support for hash table directory entries is a problem. Just guessing here as I don't know much about ext4 structure. I haven't been able to produce a simple example just creating a bunch of files and directories, so only the disk after an ubuntu install has the problem. I took an Ubuntu install I had (for x86) that was on a USB drive, had been pretty extensively used, and was is ext4. I couldn't find any size 0 directories. Are you able to reproduce this problem on other hardware? Is the image in question NOT remountable as ext3 (extents is set, generated) ? My biggest concern is breakage among ext2/3 filesystems. Thanks! What size partition? It is also fine for me with a small 1.2GB partition. I only see the problem with larger partitions (most of a 250GB drive). I was under the impression that ext4 is not mountable as ext3. Rob ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Cache alignment warnings on Tegra (ARM)
On 09/12/2012 04:38 PM, Marek Vasut wrote: Dear Stephen Warren, On 09/12/2012 10:19 AM, Tom Warren wrote: Folks, Stephen Warren has posted an internal bug regarding the cache alignment 'warnings' seen on Tegra20 boards when accessing MMC. Here's the gist: Executing mmc dev 0 still yields cache warnings: Tegra20 (Harmony) # mmc dev 0 ERROR: v7_dcache_inval_range- stop address is not aligned- 0x3fb69908 mmc0 is current device ... There have been patches in the past (IIRC) that have tried to ensure all callers (FS, MMC driver, USB driver, etc.) force their buffers to the appropriate alignment, but I don't know that we can ever correct every instance, now or in the future. Can we start a discussion about what we can do about this warning? Adding an appropriate #ifdef (CONFIG_SYS_NO_CACHE_ALIGNMENT_WARNINGS, etc.) where Stephen put his #if 0's would be one approach, or changing the printf() to a debug(), perhaps. As far as I can tell, these alignment 'errors' don't seem to produce bad data in the transfer. I don't think simply turning off the warning is the correct approach; I believe they represent real problems that can in fact cause data corruption. I don't believe we have any choice other than to fully solve the root-cause. Try CONFIG_MMC_BOUNCE_BUFFER or what it was called ... see inclued/configs/m28evk.h , I use it there. That didn't seem to change anything. I just re-tested and it looks like there's one single instance of this cache warning now when running mmc dev 0; there used to be hundreds of them when loading files from eMMC. Perhaps it depends on some runtime allocation or something though, and I'm just getting lucky and seeing fewer of them. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
