[U-Boot] U-boot: Erase/read/write issue with S25fl256S flash device
Hi,
I am working on qspi flash device S25FL256S at u-boot level. I am trying to
make use of the existing spi_flash.c framework available at u-boot for
erasing/reading/writing
into the flash device.
There are several issues(mentioned below), which I faced while using
S25FL256s flash device
with my dra7xx board which has a qspi controller to which the above
mentioned flash device is attached.
1. Erase (spi_flash_cmd_erase)
Issuing a command something like this..
sf erase 0x0 0x5
- erases only first 0x2 bytes of flash device, anything above that
is not erase. I need to
issue separate commands after 0x2 for every 0x1 bytes.
Am i missing anything here?
2. read
sf read 8100 0 0x1
Read is not happening properly. The last few byte along the 4k boundary
always shows zero.
Above 4k bytes, read is not happening.
For ex:
DRA752 EVM # md 81000f00
81000f00:
81000f10:
81000f20:
81000f30:
81000f40:
81000f50:
81000f60:
81000f70:
81000f80:
81000f90:
81000fa0:
81000fb0:
81000fc0:
81000fd0:
81000fe0:
81000ff0: 00ff
In this dump, if you see 81000ff0 the last column shows 00 which is
not expected. and it happens along every 4k bytes.
So, to get rid of the above issue, I switched to page read with the
below patch[1],
which is giving me the correct result.
[1]:
@@ -147,17 +153,40 @@ int spi_flash_read_common(struct spi_flash *flash,
const u8 *cmd,
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- u8 cmd[5];
+ unsigned long page_addr, byte_addr, page_size;
+ size_t chunk_len, actual;
+ int ret = 0;
+ u8 cmd[4];
/* Handle memory-mapped SPI */
if (flash-memory_map)
memcpy(data, flash-memory_map + offset, len);
+ page_size = flash-page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ cmd[0] = CMD_READ_ARRAY_SLOW;
+ for (actual = 0; actual len; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size - byte_addr);
+
+ cmd[1] = page_addr 8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
data + actual, chunk_len);
+ if (ret 0) {
+ debug(SF: read failed);
+ break;
+ }
- cmd[0] = CMD_READ_ARRAY_FAST;
- spi_flash_addr(offset, cmd);
- cmd[4] = 0x00;
+ byte_addr += chunk_len;
+ if (byte_addr == page_size) {
+ page_addr++;
+ byte_addr = 0;
+ }
+ }
- return spi_flash_read_common(flash, cmd, sizeof(cmd), data, len);
+ return ret;
}
Any idea about this?
3. write (spi_flash_cmd_write_multi)
write not happening properly.
observations: only able to write single page, anything after a page is
not getting
written.
Workaround:
I did a write disable latch at the end of every write cycle(page
program) and enable it
again for the next loop. With this, I see I get rid of the above issue.
@@ -117,6 +117,12 @@ int spi_flash_cmd_write_multi(struct spi_flash
*flash, u32 offset,
if (ret)
break;
+ ret = spi_flash_cmd_write_disable(flash);
+ if (ret 0) {
+ printf(SF: disabling write failed\n);
+ break;
+ }
+
Have anyone seen the above mentioned issues regarding read/write/erase?
OR is there any
configurations that I might be missing ?
___
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[U-Boot] [PATCH v6 0/5] Add gdsys ControlCenter Digital board
From: Dirk Eibach dirk.eib...@gdsys.cc Changes in v6: - Add CONFIG_PCI_INDIRECT_BRIDGE to controlcenterd.h - Add MAINTAINERS entry - drop mpc85xx: Add CONFIG_RELEASE_CORE0_ONLY and use mp_holdoff instead - rename CONFIG_ATMEL_TWI_TPM to CONFIG_TPM_ATMEL_TWI - rename drivers/tpm/atmel_twi_tpm.c to drivers/tpm/tpm_atmel_twi.c - replace DEBUG_ATMEL_TWI_TPM, simply use DEBUG - sort drivers/tpm/Makefile - timeout on waiting for TPM reply Changes in v5: - avoid probing dp501 i2c bridge addresses - fix i2c_probe Changes in v4: - consider CONFIG_CMD_BOOTM for all architectures Changes in v3: - fix email addresses Changes in v2: - configuration for SPI builds was missing - replace some numeric constants with named constants - style fixes (as shown by checkpatch.pl) in common/cmd_tpm.c and lib/tpm.c - whitespace fixes Dirk Eibach (3): Add Atmel I2C tpm Build arch/$ARCH/lib/bootm.o depending on CONFIG_CMD_BOOTM mpc85xx: Add gdsys ControlCenter Digital board Reinhard Pfau (2): tpm: add AUTH1 cmds for LoadKey2 and GetPubKey i2c: fsl_i2c: i2c_read(): dont try to write address w/ alen=0 .checkpatch.conf |4 +- MAINTAINERS |3 +- README| 17 + arch/arm/lib/Makefile |2 +- arch/avr32/lib/Makefile |2 +- arch/m68k/lib/Makefile|2 +- arch/microblaze/lib/Makefile |2 +- arch/mips/lib/Makefile|4 +- arch/nds32/lib/Makefile |3 +- arch/nios2/lib/Makefile |2 +- arch/openrisc/lib/Makefile|2 +- arch/powerpc/lib/Makefile |2 +- arch/sh/lib/Makefile |2 +- arch/sparc/lib/Makefile |3 +- arch/x86/lib/Makefile |2 +- board/gdsys/common/Makefile |1 + board/gdsys/common/dp501.c| 107 +++ board/gdsys/common/dp501.h| 30 + board/gdsys/p1022/Makefile| 37 + board/gdsys/p1022/controlcenterd-id.c | 1205 + board/gdsys/p1022/controlcenterd-id.h | 29 + board/gdsys/p1022/controlcenterd.c| 447 board/gdsys/p1022/ddr.c | 71 ++ board/gdsys/p1022/diu.c | 87 +++ board/gdsys/p1022/law.c | 20 + board/gdsys/p1022/sdhc_boot.c | 63 ++ board/gdsys/p1022/tlb.c | 77 +++ boards.cfg|7 + common/cmd_tpm.c | 100 +++ drivers/i2c/fsl_i2c.c |9 +- drivers/tpm/Makefile |1 + drivers/tpm/tpm_atmel_twi.c | 121 include/configs/controlcenterd.h | 528 +++ include/tpm.h | 174 + lib/tpm.c | 351 +- 35 files changed, 3497 insertions(+), 20 deletions(-) create mode 100644 board/gdsys/common/dp501.c create mode 100644 board/gdsys/common/dp501.h create mode 100644 board/gdsys/p1022/Makefile create mode 100644 board/gdsys/p1022/controlcenterd-id.c create mode 100644 board/gdsys/p1022/controlcenterd-id.h create mode 100644 board/gdsys/p1022/controlcenterd.c create mode 100644 board/gdsys/p1022/ddr.c create mode 100644 board/gdsys/p1022/diu.c create mode 100644 board/gdsys/p1022/law.c create mode 100644 board/gdsys/p1022/sdhc_boot.c create mode 100644 board/gdsys/p1022/tlb.c create mode 100644 drivers/tpm/tpm_atmel_twi.c create mode 100644 include/configs/controlcenterd.h -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 3/5] Add Atmel I2C tpm
From: Dirk Eibach eib...@gdsys.de
Add support for Atmel TPM devices with two wire interface.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
Signed-off-by: Reinhard Pfau reinhard.p...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v6:
- rename CONFIG_ATMEL_TWI_TPM to CONFIG_TPM_ATMEL_TWI
- rename drivers/tpm/atmel_twi_tpm.c to drivers/tpm/tpm_atmel_twi.c
- replace DEBUG_ATMEL_TWI_TPM, simply use DEBUG
- sort drivers/tpm/Makefile
- timeout on waiting for TPM reply
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
README | 3 ++
drivers/tpm/Makefile| 1 +
drivers/tpm/tpm_atmel_twi.c | 121
3 files changed, 125 insertions(+)
create mode 100644 drivers/tpm/tpm_atmel_twi.c
diff --git a/README b/README
index 3d1fa08..44dd4b6 100644
--- a/README
+++ b/README
@@ -1225,6 +1225,9 @@ The following options need to be configured:
CONFIG_TPM_TIS_I2C_BURST_LIMITATION
Define the burst count bytes upper limit
+ CONFIG_TPM_ATMEL_TWI
+ Support for Atmel TWI TPM device. Requires I2C support.
+
CONFIG_TPM_TIS_LPC
Support for generic parallel port TPM devices. Only one device
per system is supported at this time.
diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile
index 913dd9c..c3010ba 100644
--- a/drivers/tpm/Makefile
+++ b/drivers/tpm/Makefile
@@ -26,6 +26,7 @@ LIB := $(obj)libtpm.o
$(shell mkdir -p $(obj)slb9635_i2c)
# TODO: Merge tpm_tis_lpc.c with tpm.c
+COBJS-$(CONFIG_TPM_ATMEL_TWI) += tpm_atmel_twi.o
COBJS-$(CONFIG_TPM_TIS_I2C) += tpm.o
COBJS-$(CONFIG_TPM_TIS_I2C) += tpm_tis_i2c.o
COBJS-$(CONFIG_TPM_TIS_LPC) += tpm_tis_lpc.o
diff --git a/drivers/tpm/tpm_atmel_twi.c b/drivers/tpm/tpm_atmel_twi.c
new file mode 100644
index 000..361a772
--- /dev/null
+++ b/drivers/tpm/tpm_atmel_twi.c
@@ -0,0 +1,121 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include tpm.h
+#include i2c.h
+#include asm/unaligned.h
+
+#define ATMEL_TPM_TIMEOUT_MS 5000 /* sufficient for anything but
+generating/exporting keys */
+
+/*
+ * tis_init()
+ *
+ * Initialize the TPM device. Returns 0 on success or -1 on
+ * failure (in case device probing did not succeed).
+ */
+int tis_init(void)
+{
+ return 0;
+}
+
+/*
+ * tis_open()
+ *
+ * Requests access to locality 0 for the caller. After all commands have been
+ * completed the caller is supposed to call tis_close().
+ *
+ * Returns 0 on success, -1 on failure.
+ */
+int tis_open(void)
+{
+ return 0;
+}
+
+/*
+ * tis_close()
+ *
+ * terminate the currect session with the TPM by releasing the locked
+ * locality. Returns 0 on success of -1 on failure (in case lock
+ * removal did not succeed).
+ */
+int tis_close(void)
+{
+ return 0;
+}
+
+/*
+ * tis_sendrecv()
+ *
+ * Send the requested data to the TPM and then try to get its response
+ *
+ * @sendbuf - buffer of the data to send
+ * @send_size size of the data to send
+ * @recvbuf - memory to save the response to
+ * @recv_len - pointer to the size of the response buffer
+ *
+ * Returns 0 on success (and places the number of response bytes at recv_len)
+ * or -1 on failure.
+ */
+int tis_sendrecv(const uint8_t *sendbuf, size_t send_size, uint8_t *recvbuf,
+ size_t *recv_len)
+{
+ int res;
+ unsigned long start;
+
+#ifdef DEBUG
+ memset(recvbuf, 0xcc, *recv_len);
+ printf(send to TPM (%d bytes, recv_len=%d):\n, send_size, *recv_len);
+ print_buffer(0, (void *)sendbuf, 1, send_size, 0);
+#endif
+
+ res = i2c_write(0x29, 0, 0, (uchar *)sendbuf, send_size);
+ if (res) {
+ printf(i2c_write returned %d\n, res);
+ return -1;
+ }
+
+ start = get_timer(0);
+ while ((res = i2c_read(0x29, 0, 0, recvbuf, 10))) {
+ if (get_timer(start) ATMEL_TPM_TIMEOUT_MS) {
+ puts(tpm timed out\n);
+ return -1;
+ }
+ udelay(100);
+ }
+ if (!res) {
+ *recv_len = get_unaligned_be32(recvbuf + 2);
+ if (*recv_len 10)
+
[U-Boot] [PATCH v6 1/5] tpm: add AUTH1 cmds for LoadKey2 and GetPubKey
From: Reinhard Pfau p...@gdsys.de
Extend the tpm library with support for single authorized (AUTH1) commands
as specified in the TCG Main Specification 1.2. (The internally used helper
functions are implemented in a way that they could also be used for double
authorized commands if someone needs it.)
Provide enums with the return codes from the TCG Main specification.
For now only a single OIAP session is supported.
OIAP authorized version of the commands TPM_LoadKey2 and TPM_GetPubKey are
provided. Both features are available using the 'tpm' command, too.
Authorized commands are enabled with CONFIG_TPM_AUTH_SESSIONS. (Note that
this also requires CONFIG_SHA1 to be enabled.)
Signed-off-by: Reinhard Pfau reinhard.p...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- fix email addresses
Changes in v2:
- replace some numeric constants with named constants
- style fixes (as shown by checkpatch.pl) in common/cmd_tpm.c and lib/tpm.c
README | 14 +++
common/cmd_tpm.c | 100
include/tpm.h| 174 +++
lib/tpm.c| 351 ++-
4 files changed, 638 insertions(+), 1 deletion(-)
diff --git a/README b/README
index 33bda8c..3d1fa08 100644
--- a/README
+++ b/README
@@ -1234,6 +1234,20 @@ The following options need to be configured:
to. Contemporary x86 systems usually map it at
0xfed4.
+ CONFIG_CMD_TPM
+ Add tpm monitor functions.
+ Requires CONFIG_TPM. If CONFIG_TPM_AUTH_SESSIONS is set, also
+ provides monitor access to authorized functions.
+
+ CONFIG_TPM
+ Define this to enable the TPM support library which provides
+ functional interfaces to some TPM commands.
+ Requires support for a TPM device.
+
+ CONFIG_TPM_AUTH_SESSIONS
+ Define this to enable authorized functions in the TPM library.
+ Requires CONFIG_TPM and CONFIG_SHA1.
+
- USB Support:
At the moment only the UHCI host controller is
supported (PIP405, MIP405, MPC5200); define
diff --git a/common/cmd_tpm.c b/common/cmd_tpm.c
index 46fae18..c34000a 100644
--- a/common/cmd_tpm.c
+++ b/common/cmd_tpm.c
@@ -27,6 +27,13 @@
#include asm/unaligned.h
#include linux/string.h
+/* Useful constants */
+enum {
+ DIGEST_LENGTH = 20,
+ /* max lengths, valid for RSA keys = 2048 bits */
+ TPM_PUBKEY_MAX_LENGTH = 288,
+};
+
/**
* Print a byte string in hexdecimal format, 16-bytes per line.
*
@@ -546,6 +553,72 @@ static int do_tpm_nv_write(cmd_tbl_t *cmdtp, int flag,
return convert_return_code(err);
}
+#ifdef CONFIG_TPM_AUTH_SESSIONS
+
+static int do_tpm_oiap(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ uint32_t auth_handle, err;
+
+ err = tpm_oiap(auth_handle);
+
+ return convert_return_code(err);
+}
+
+static int do_tpm_load_key2_oiap(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ uint32_t parent_handle, key_len, key_handle, err;
+ uint8_t usage_auth[DIGEST_LENGTH];
+ void *key;
+
+ if (argc 5)
+ return CMD_RET_USAGE;
+
+ parent_handle = simple_strtoul(argv[1], NULL, 0);
+ key = (void *)simple_strtoul(argv[2], NULL, 0);
+ key_len = simple_strtoul(argv[3], NULL, 0);
+ if (strlen(argv[4]) != 2 * DIGEST_LENGTH)
+ return CMD_RET_FAILURE;
+ parse_byte_string(argv[4], usage_auth, NULL);
+
+ err = tpm_load_key2_oiap(parent_handle, key, key_len, usage_auth,
+ key_handle);
+ if (!err)
+ printf(Key handle is 0x%x\n, key_handle);
+
+ return convert_return_code(err);
+}
+
+static int do_tpm_get_pub_key_oiap(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ uint32_t key_handle, err;
+ uint8_t usage_auth[DIGEST_LENGTH];
+ uint8_t pub_key_buffer[TPM_PUBKEY_MAX_LENGTH];
+ size_t pub_key_len = sizeof(pub_key_buffer);
+
+ if (argc 3)
+ return CMD_RET_USAGE;
+
+ key_handle = simple_strtoul(argv[1], NULL, 0);
+ if (strlen(argv[2]) != 2 * DIGEST_LENGTH)
+ return CMD_RET_FAILURE;
+ parse_byte_string(argv[2], usage_auth, NULL);
+
+ err = tpm_get_pub_key_oiap(key_handle, usage_auth,
+ pub_key_buffer, pub_key_len);
+ if (!err) {
+ printf(dump of received pub key structure:\n);
+ print_byte_string(pub_key_buffer, pub_key_len);
+ }
+ return convert_return_code(err);
+}
+
+TPM_COMMAND_NO_ARG(tpm_end_oiap)
+
+#endif /* CONFIG_TPM_AUTH_SESSIONS */
+
#define MAKE_TPM_CMD_ENTRY(cmd) \
U_BOOT_CMD_MKENT(cmd, 0, 1,
[U-Boot] [PATCH v6 4/5] Build arch/$ARCH/lib/bootm.o depending on CONFIG_CMD_BOOTM
From: Dirk Eibach eib...@gdsys.de MAKEALL is fine for ppc4xx and mpc85xx. Run checks were done on our controlcenterd hardware. Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc --- Changes in v6: None Changes in v5: None Changes in v4: - consider CONFIG_CMD_BOOTM for all architectures Changes in v3: None Changes in v2: None arch/arm/lib/Makefile| 2 +- arch/avr32/lib/Makefile | 2 +- arch/m68k/lib/Makefile | 2 +- arch/microblaze/lib/Makefile | 2 +- arch/mips/lib/Makefile | 4 ++-- arch/nds32/lib/Makefile | 3 ++- arch/nios2/lib/Makefile | 2 +- arch/openrisc/lib/Makefile | 2 +- arch/powerpc/lib/Makefile| 2 +- arch/sh/lib/Makefile | 2 +- arch/sparc/lib/Makefile | 3 ++- arch/x86/lib/Makefile| 2 +- 12 files changed, 15 insertions(+), 13 deletions(-) diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 8ad9f66..6526fc8 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -45,8 +45,8 @@ COBJS-y += board.o endif COBJS-y += bss.o -COBJS-y+= bootm.o COBJS-$(CONFIG_OF_LIBFDT) += bootm-fdt.o +COBJS-$(CONFIG_CMD_BOOTM) += bootm.o COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o diff --git a/arch/avr32/lib/Makefile b/arch/avr32/lib/Makefile index ee6d067..fce8af3 100644 --- a/arch/avr32/lib/Makefile +++ b/arch/avr32/lib/Makefile @@ -30,7 +30,7 @@ LIB = $(obj)lib$(ARCH).o SOBJS-y+= memset.o COBJS-y+= board.o -COBJS-y+= bootm.o +COBJS-$(CONFIG_CMD_BOOTM) += bootm.o COBJS-y+= interrupts.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile index a8d6cd5..5722b67 100644 --- a/arch/m68k/lib/Makefile +++ b/arch/m68k/lib/Makefile @@ -28,7 +28,7 @@ LIB = $(obj)lib$(ARCH).o SOBJS-y+= COBJS-y+= board.o -COBJS-y+= bootm.o +COBJS-$(CONFIG_CMD_BOOTM) += bootm.o COBJS-y+= cache.o COBJS-y+= interrupts.o COBJS-y+= time.o diff --git a/arch/microblaze/lib/Makefile b/arch/microblaze/lib/Makefile index 8d7febd..a40e8d4 100644 --- a/arch/microblaze/lib/Makefile +++ b/arch/microblaze/lib/Makefile @@ -28,7 +28,7 @@ LIB = $(obj)lib$(ARCH).o SOBJS-y+= COBJS-y+= board.o -COBJS-y+= bootm.o +COBJS-$(CONFIG_CMD_BOOTM) += bootm.o COBJS-y+= muldi3.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 967e98a..b6ded54 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -36,9 +36,9 @@ SOBJS-y += COBJS-y+= board.o ifeq ($(CONFIG_QEMU_MIPS),y) -COBJS-y+= bootm_qemu_mips.o +COBJS-$(CONFIG_CMD_BOOTM) += bootm_qemu_mips.o else -COBJS-y+= bootm.o +COBJS-$(CONFIG_CMD_BOOTM) += bootm.o endif SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile index 581a2e7..705e1ff 100644 --- a/arch/nds32/lib/Makefile +++ b/arch/nds32/lib/Makefile @@ -29,7 +29,8 @@ include $(TOPDIR)/config.mk LIB= $(obj)lib$(ARCH).o -OBJS := board.o bootm.o cache.o interrupts.o +OBJS := board.o cache.o interrupts.o +COBJS-$(CONFIG_CMD_BOOTM) += bootm.o all: $(LIB) diff --git a/arch/nios2/lib/Makefile b/arch/nios2/lib/Makefile index 443f99e..f33f96a 100644 --- a/arch/nios2/lib/Makefile +++ b/arch/nios2/lib/Makefile @@ -28,7 +28,7 @@ LIB = $(obj)lib$(ARCH).o SOBJS-y+= cache.o COBJS-y+= board.o -COBJS-y+= bootm.o +COBJS-$(CONFIG_CMD_BOOTM) += bootm.o COBJS-y+= libgcc.o COBJS-y+= time.o diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile index db3c657..ab822f4 100644 --- a/arch/openrisc/lib/Makefile +++ b/arch/openrisc/lib/Makefile @@ -28,7 +28,7 @@ LIB = $(obj)lib$(ARCH).o SOBJS-y+= COBJS-y+= board.o -COBJS-y+= bootm.o +COBJS-$(CONFIG_CMD_BOOTM) += bootm.o COBJS-y+= timer.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 59c723b..8c4920b 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -63,7 +63,7 @@ ifndef CONFIG_SYS_GENERIC_BOARD COBJS-y+= board.o endif endif -COBJS-y+= bootm.o +COBJS-$(CONFIG_CMD_BOOTM) += bootm.o COBJS-y+= cache.o COBJS-y+= extable.o COBJS-y+= interrupts.o diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile index 256811a..3d4eb53 100644 --- a/arch/sh/lib/Makefile +++ b/arch/sh/lib/Makefile @@ -33,7 +33,7 @@ GLSOBJS += lshrdi3.o GLSOBJS+= movmem.o COBJS-y+= board.o -COBJS-y+= bootm.o +COBJS-$(CONFIG_CMD_BOOTM) += bootm.o ifeq ($(CONFIG_SH2),y) COBJS-y+= time_sh2.o else diff --git a/arch/sparc/lib/Makefile b/arch/sparc/lib/Makefile index 7133ef1..aec29b3
[U-Boot] [PATCH v6 2/5] i2c: fsl_i2c: i2c_read(): dont try to write address w/ alen=0
From: Reinhard Pfau p...@gdsys.de if alen is 0: no longer start a write cycle before reading data. Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc Signed-off-by: Reinhard Pfau reinhard.p...@gdsys.cc Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc --- Changes in v6: None Changes in v5: - fix i2c_probe Changes in v4: None Changes in v3: None Changes in v2: - whitespace fixes drivers/i2c/fsl_i2c.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 1c7265d..5d7e010 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -383,13 +383,16 @@ i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) int i = -1; /* signal error */ u8 *a = (u8*)addr; - if (i2c_wait4bus() = 0 + if (i2c_wait4bus() 0) + return -1; + + if ((!length || alen 0) i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 __i2c_write(a[4 - alen], alen) == alen) i = 0; /* No error so far */ - if (length -i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) + if (length + i2c_write_addr(dev, I2C_READ_BIT, alen ? 1 : 0) != 0) i = __i2c_read(data, length); writeb(I2C_CR_MEN, i2c_dev[i2c_bus_num]-cr); -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [u-boot V5] spi: arm-pl022: Add support for ARM PL022 spi controller
This patch adds the support for the ARM PL022 SPI controller for the standard
variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO.
Signed-off-by: Armando Visconti armando.visco...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Acked-by: Stefan Roese s...@denx.de
---
V4-V5:
Changed the commit message to a more standard format.
Armando
drivers/spi/Makefile| 1 +
drivers/spi/pl022_spi.c | 310
2 files changed, 311 insertions(+)
create mode 100644 drivers/spi/pl022_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d08609e..b6443b1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
new file mode 100644
index 000..8a8b9ab
--- /dev/null
+++ b/drivers/spi/pl022_spi.c
@@ -0,0 +1,310 @@
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visco...@st.com.
+ *
+ * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c
+ * by Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+/* SSP registers mapping */
+struct pl022 {
+ u32 ssp_cr0;/* 0x000 */
+ u32 ssp_cr1;/* 0x004 */
+ u32 ssp_dr; /* 0x008 */
+ u32 ssp_sr; /* 0x00c */
+ u32 ssp_cpsr; /* 0x010 */
+ u32 ssp_imsc; /* 0x014 */
+ u32 ssp_ris;/* 0x018 */
+ u32 ssp_mis;/* 0x01c */
+ u32 ssp_icr;/* 0x020 */
+ u32 ssp_dmacr; /* 0x024 */
+ u8 reserved_1[0x080 - 0x028];
+ u32 ssp_itcr; /* 0x080 */
+ u32 ssp_itip; /* 0x084 */
+ u32 ssp_itop; /* 0x088 */
+ u32 ssp_tdr;/* 0x08c */
+ u8 reserved_2[0xFE0 - 0x090];
+ u32 ssp_pid0; /* 0xfe0 */
+ u32 ssp_pid1; /* 0xfe4 */
+ u32 ssp_pid2; /* 0xfe8 */
+ u32 ssp_pid3; /* 0xfec */
+ u32 ssp_cid0; /* 0xff0 */
+ u32 ssp_cid1; /* 0xff4 */
+ u32 ssp_cid2; /* 0xff8 */
+ u32 ssp_cid3; /* 0xffc */
+};
+
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO(0x1 6)
+#define SSP_CR0_SPH(0x1 7)
+#define SSP_CR0_8BIT_MODE (0x07)
+#define SSP_SCR_MAX(0xFF)
+#define SSP_SCR_SHFT 8
+
+/* SSP Control Register 0 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 1)
+
+#define SSP_CPSR_MAX (0xFE)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE(0x1 0) /* Transmit FIFO empty */
+#define SSP_SR_MASK_TNF(0x1 1) /* Transmit FIFO not full */
+#define SSP_SR_MASK_RNE(0x1 2) /* Receive FIFO not empty */
+#define SSP_SR_MASK_RFF(0x1 3) /* Receive FIFO full */
+#define SSP_SR_MASK_BSY(0x1 4) /* Busy Flag */
+
+struct pl022_spi_slave {
+ struct spi_slave slave;
+ void *regs;
+ unsigned int freq;
+};
+
+static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct pl022_spi_slave, slave);
+}
+
+/*
+ * Following three functions should be provided by the
+ * board support package.
+ */
+int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void __weak spi_cs_activate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void __weak spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void spi_init(void)
+{
+ /* do nothing */
+}
+
+/*
+ * ARM PL022 exists in different 'flavors'.
+ * This drivers currently support the standard variant (0x00041022), that has a
+ * 16bit wide and 8 locations deep TX/RX FIFO.
+ */
+static int
Re: [U-Boot] dfu: make data buffer size configurable
Dear Tom Rini, On Mon, Jun 10, 2013 at 09:05:48AM +0200, Wolfgang Denk wrote: Dear Heiko Schocher, In message 51b555d7.5010...@denx.de you wrote: Ok, I can change this. Envvar name dfu_data_buf_size is ok? Such long names are a paint to type. As we can't buffer anything else but data, we should be able to omit this, i. e. what about dfu_bufsiz [bufsiz as used for example as BUFSIZ in C89 stdio.h] Works for me. WFM, but I need to read the discussion around here. I just stopped playing dead beetle. Actually, I'm trying to find out why such a variable is needed at all. Can the buffer not be allocated dynamically (and thus dependant only on malloc area size)? Please ignore this if it's been answered in one of the emails I didn't read yet. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] spi: armada100_spi: Remove unnecessary NULL test for dout and din
Dear Simon Glass, On Tue, Jun 11, 2013 at 6:57 AM, Axel Lin axel@ingics.com wrote: Signed-off-by: Axel Lin axel@ingics.com Reviewed-by: Simon Glass s...@chromium.org Reviewed-by: Marek Vasut ma...@denx.de Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] dfu: make data buffer size configurable
Hello Marek, Am 12.06.2013 10:36, schrieb Marek Vasut: Dear Tom Rini, On Mon, Jun 10, 2013 at 09:05:48AM +0200, Wolfgang Denk wrote: Dear Heiko Schocher, In message 51b555d7.5010...@denx.de you wrote: Ok, I can change this. Envvar name dfu_data_buf_size is ok? Such long names are a paint to type. As we can't buffer anything else but data, we should be able to omit this, i. e. what about dfu_bufsiz [bufsiz as used for example as BUFSIZ in C89 stdio.h] Works for me. WFM, but I need to read the discussion around here. I just stopped playing dead beetle. Actually, I'm trying to find out why such a variable is needed at all. Can the buffer not be allocated dynamically (and thus dependant only on malloc area size)? Please ignore this if it's been answered in one of the emails I didn't read yet. posted a v2 for this here: http://patchwork.ozlabs.org/patch/250665/ which allocates the buffer in the malloc area, dependend on the environemnt variable dfu_bufsiz. A reason why we should have at last a config option see here: http://lists.denx.de/pipermail/u-boot/2013-June/155924.html bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] arm, arm335x: save_omap_boot_params question
Hello tom, your commit 4596dcc1d4ea5763e0f92cf5becd9fc7d4c6e674 Author: Tom Rini tr...@ti.com Date: Fri May 31 12:31:59 2013 -0400 am33xx/omap: Move save_omap_boot_params to omap-common/boot-common.c introduced, that all am335x based boards must call save_omap_boot_params() from the board specific s_init function. I just stumbled over it, as I updated to current head and my upcoming am335x based siemens boards didn't boot anymore ... should we think about to move this s_init() to a common place, and extract board specific things? Maybe arch/arm/cpu/armv7/omap-common/boot-common.c is a place for it? bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [u-boot V5] spi: arm-pl022: Add support for ARM PL022 spi controller
Hi,
Your patch looks good to me, but the same time
I have sent some comments on v4 patch
http://patchwork.ozlabs.org/patch/249603/
I think you might respond to above thread before sending v5, may be
your missing my
earlier comments?
fyi: One one more thing the patch subject prefix should be PATCH like
--subject-prefix=PATCH v5
Please respond to above thread for sending next level patch.
--
Thanks,
Jagan.
On Wed, Jun 12, 2013 at 1:38 PM, Armando Visconti
armando.visco...@st.com wrote:
This patch adds the support for the ARM PL022 SPI controller for the standard
variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO.
Signed-off-by: Armando Visconti armando.visco...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Acked-by: Stefan Roese s...@denx.de
---
V4-V5:
Changed the commit message to a more standard format.
Armando
drivers/spi/Makefile| 1 +
drivers/spi/pl022_spi.c | 310
2 files changed, 311 insertions(+)
create mode 100644 drivers/spi/pl022_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d08609e..b6443b1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
new file mode 100644
index 000..8a8b9ab
--- /dev/null
+++ b/drivers/spi/pl022_spi.c
@@ -0,0 +1,310 @@
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visco...@st.com.
+ *
+ * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c
+ * by Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+/* SSP registers mapping */
+struct pl022 {
+ u32 ssp_cr0;/* 0x000 */
+ u32 ssp_cr1;/* 0x004 */
+ u32 ssp_dr; /* 0x008 */
+ u32 ssp_sr; /* 0x00c */
+ u32 ssp_cpsr; /* 0x010 */
+ u32 ssp_imsc; /* 0x014 */
+ u32 ssp_ris;/* 0x018 */
+ u32 ssp_mis;/* 0x01c */
+ u32 ssp_icr;/* 0x020 */
+ u32 ssp_dmacr; /* 0x024 */
+ u8 reserved_1[0x080 - 0x028];
+ u32 ssp_itcr; /* 0x080 */
+ u32 ssp_itip; /* 0x084 */
+ u32 ssp_itop; /* 0x088 */
+ u32 ssp_tdr;/* 0x08c */
+ u8 reserved_2[0xFE0 - 0x090];
+ u32 ssp_pid0; /* 0xfe0 */
+ u32 ssp_pid1; /* 0xfe4 */
+ u32 ssp_pid2; /* 0xfe8 */
+ u32 ssp_pid3; /* 0xfec */
+ u32 ssp_cid0; /* 0xff0 */
+ u32 ssp_cid1; /* 0xff4 */
+ u32 ssp_cid2; /* 0xff8 */
+ u32 ssp_cid3; /* 0xffc */
+};
+
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO(0x1 6)
+#define SSP_CR0_SPH(0x1 7)
+#define SSP_CR0_8BIT_MODE (0x07)
+#define SSP_SCR_MAX(0xFF)
+#define SSP_SCR_SHFT 8
+
+/* SSP Control Register 0 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 1)
+
+#define SSP_CPSR_MAX (0xFE)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE(0x1 0) /* Transmit FIFO empty */
+#define SSP_SR_MASK_TNF(0x1 1) /* Transmit FIFO not full
*/
+#define SSP_SR_MASK_RNE(0x1 2) /* Receive FIFO not empty
*/
+#define SSP_SR_MASK_RFF(0x1 3) /* Receive FIFO full */
+#define SSP_SR_MASK_BSY(0x1 4) /* Busy Flag */
+
+struct pl022_spi_slave {
+ struct spi_slave slave;
+ void *regs;
+ unsigned int freq;
+};
+
+static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct pl022_spi_slave, slave);
+}
[U-Boot] [PATCH v4] sf: Add bank addr code in CONFIG_SPI_FLASH_BAR
Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the
size for existing boards which has 16Mbytes SPI flashes.
It's upto user which has provision to use the bank addr code for
flashes which has 16Mbytes.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v4:
- init bank_curr to 0 for 16Mbytes if CONFIG_SPI_FLASH_BAR defined
Changes for v4:
- none
Changes for v4:
- none
README | 5
drivers/mtd/spi/spi_flash.c | 45 +++-
drivers/mtd/spi/spi_flash_internal.h | 14 ++-
include/spi_flash.h | 3 ++-
4 files changed, 44 insertions(+), 23 deletions(-)
diff --git a/README b/README
index 3d81092..a2b956e 100644
--- a/README
+++ b/README
@@ -2489,6 +2489,11 @@ CBFS (Coreboot Filesystem) support
Define this option to include a destructive SPI flash
test ('sf test').
+ CONFIG_SPI_FLASH_BARBan/Extended Addr Reg
+
+ Define this option to use the Bank addr/Extended addr
+ support on SPI flashes which has size 16Mbytes.
+
- SystemACE Support:
CONFIG_SYSTEMACE
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 40c0389..2307f2b 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -74,7 +74,7 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32
offset,
unsigned long page_addr, byte_addr, page_size;
size_t chunk_len, actual;
int ret;
- u8 cmd[4], bank_sel;
+ u8 cmd[4];
page_size = flash-page_size;
@@ -86,6 +86,9 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32
offset,
cmd[0] = CMD_PAGE_PROGRAM;
for (actual = 0; actual len; actual += chunk_len) {
+#ifdef CONFIG_SPI_FLASH_BAR
+ u8 bank_sel;
+
bank_sel = offset / SPI_FLASH_16MB_BOUN;
ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
@@ -93,7 +96,7 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32
offset,
debug(SF: fail to set bank%d\n, bank_sel);
return ret;
}
-
+#endif
page_addr = offset / page_size;
byte_addr = offset % page_size;
chunk_len = min(len - actual, page_size - byte_addr);
@@ -162,6 +165,7 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32
offset,
cmd[4] = 0x00;
while (len) {
+#ifdef CONFIG_SPI_FLASH_BAR
bank_sel = offset / SPI_FLASH_16MB_BOUN;
ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
@@ -169,7 +173,7 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32
offset,
debug(SF: fail to set bank%d\n, bank_sel);
return ret;
}
-
+#endif
remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset);
if (len remain_len)
read_len = len;
@@ -240,7 +244,7 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32
offset, size_t len)
{
u32 erase_size;
int ret;
- u8 cmd[4], bank_sel;
+ u8 cmd[4];
erase_size = flash-sector_size;
if (offset % erase_size || len % erase_size) {
@@ -260,6 +264,9 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32
offset, size_t len)
cmd[0] = CMD_ERASE_64K;
while (len) {
+#ifdef CONFIG_SPI_FLASH_BAR
+ u8 bank_sel;
+
bank_sel = offset / SPI_FLASH_16MB_BOUN;
ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
@@ -267,7 +274,7 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32
offset, size_t len)
debug(SF: fail to set bank%d\n, bank_sel);
return ret;
}
-
+#endif
spi_flash_addr(offset, cmd);
debug(SF: erase %2x %2x %2x %2x (%x)\n, cmd[0], cmd[1],
@@ -321,6 +328,7 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8
sr)
return 0;
}
+#ifdef CONFIG_SPI_FLASH_BAR
int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
{
u8 cmd, idcode0;
@@ -379,6 +387,7 @@ int spi_flash_cmd_bankaddr_read(struct spi_flash *flash,
void *data)
return spi_flash_read_common(flash, cmd, 1, data, 1);
}
+#endif
#ifdef CONFIG_OF_CONTROL
int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
@@ -481,7 +490,6 @@ struct spi_flash *spi_flash_probe(unsigned int bus,
unsigned int cs,
struct spi_flash *flash = NULL;
int ret, i, shift;
u8 idcode[IDCODE_LEN], *idp;
- u8 curr_bank = 0;
spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
if (!spi) {
@@ -525,9 +533,24 @@ struct spi_flash *spi_flash_probe(unsigned int bus,
unsigned int cs,
goto
Re: [U-Boot] [u-boot V5] spi: arm-pl022: Add support for ARM PL022 spi controller
On 06/12/2013 10:56 AM, Jagan Teki wrote: Hi, Your patch looks good to me, but the same time I have sent some comments on v4 patch http://patchwork.ozlabs.org/patch/249603/ I think you might respond to above thread before sending v5, may be your missing my earlier comments? Yes, I missed them. Sorry... I'm doing too many things at the same time... :( I will analyse them right now. fyi: One one more thing the patch subject prefix should be PATCH like --subject-prefix=PATCH v5 ok, I will. Next will be v6 at thi point.. Please respond to above thread for sending next level patch. sure Arm ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] spi: armada100_spi: Remove unnecessary NULL test for dout and din
- Marek Vasut ma...@denx.de wrote: Dear Simon Glass, On Tue, Jun 11, 2013 at 6:57 AM, Axel Lin axel@ingics.com wrote: Signed-off-by: Axel Lin axel@ingics.com Reviewed-by: Simon Glass s...@chromium.org Reviewed-by: Marek Vasut ma...@denx.de Acked-by: Ajay Bhargav ajay.bhar...@einfochips.com Regards, Ajay Bhargav - Notice: This message has been scanned by Trend Micro Mail Security scanner and is believed to be clean - ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [u-boot V5] spi: arm-pl022: Add support for ARM PL022 spi controller
On Wed, Jun 12, 2013 at 3:56 PM, Armando Visconti armando.visco...@st.com wrote: On 06/12/2013 10:56 AM, Jagan Teki wrote: Hi, Your patch looks good to me, but the same time I have sent some comments on v4 patch http://patchwork.ozlabs.org/patch/249603/ I think you might respond to above thread before sending v5, may be your missing my earlier comments? Yes, I missed them. Sorry... I'm doing too many things at the same time... :( I will analyse them right now. fyi: One one more thing the patch subject prefix should be PATCH like --subject-prefix=PATCH v5 ok, I will. Next will be v6 at thi point.. Please respond to above thread for sending next level patch. no issues, thanks. Also please use the commit header as spi: pl022_spi: -- Thanks, Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [u-boot V4] spi/arm-pl022: Add support for ARM PL022 spi controller
On 06/10/2013 06:01 PM, Jagan Teki wrote:
Hi,
Please use the commit header as below: just to sync with remaining
drivers in tree.
spi: arm-pl022: Add support for ARM PL022 spi controller
OK,
I already did it for v5.
I'll keep it for v6 as well...
On Fri, Jun 7, 2013 at 1:14 PM, Armando Visconti
armando.visco...@st.com wrote:
This patch adds the support for the ARM PL022 SPI controller for the standard
variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO.
Signed-off-by: Armando Visconti armando.visco...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Acked-by: Stefan Roese s...@denx.de
---
v3-v4
Just removed all warnings when running checkpatch.
Didn't find Jagan's feedback... So, pls, let me know if we
need to change anything else...
Armando
drivers/spi/Makefile| 1 +
drivers/spi/pl022_spi.c | 310
2 files changed, 311 insertions(+)
create mode 100644 drivers/spi/pl022_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d08609e..b6443b1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
new file mode 100644
index 000..8a8b9ab
--- /dev/null
+++ b/drivers/spi/pl022_spi.c
@@ -0,0 +1,310 @@
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visco...@st.com.
+ *
+ * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c
+ * by Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+/* SSP registers mapping */
+struct pl022 {
+ u32 ssp_cr0;/* 0x000 */
+ u32 ssp_cr1;/* 0x004 */
+ u32 ssp_dr; /* 0x008 */
+ u32 ssp_sr; /* 0x00c */
+ u32 ssp_cpsr; /* 0x010 */
+ u32 ssp_imsc; /* 0x014 */
+ u32 ssp_ris;/* 0x018 */
+ u32 ssp_mis;/* 0x01c */
+ u32 ssp_icr;/* 0x020 */
+ u32 ssp_dmacr; /* 0x024 */
+ u8 reserved_1[0x080 - 0x028];
+ u32 ssp_itcr; /* 0x080 */
+ u32 ssp_itip; /* 0x084 */
+ u32 ssp_itop; /* 0x088 */
+ u32 ssp_tdr;/* 0x08c */
+ u8 reserved_2[0xFE0 - 0x090];
+ u32 ssp_pid0; /* 0xfe0 */
+ u32 ssp_pid1; /* 0xfe4 */
+ u32 ssp_pid2; /* 0xfe8 */
+ u32 ssp_pid3; /* 0xfec */
+ u32 ssp_cid0; /* 0xff0 */
+ u32 ssp_cid1; /* 0xff4 */
+ u32 ssp_cid2; /* 0xff8 */
+ u32 ssp_cid3; /* 0xffc */
+};
+
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO(0x1 6)
+#define SSP_CR0_SPH(0x1 7)
+#define SSP_CR0_8BIT_MODE (0x07)
+#define SSP_SCR_MAX(0xFF)
+#define SSP_SCR_SHFT 8
+
+/* SSP Control Register 0 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 1)
+
+#define SSP_CPSR_MAX (0xFE)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE(0x1 0) /* Transmit FIFO empty */
+#define SSP_SR_MASK_TNF(0x1 1) /* Transmit FIFO not full */
+#define SSP_SR_MASK_RNE(0x1 2) /* Receive FIFO not empty */
+#define SSP_SR_MASK_RFF(0x1 3) /* Receive FIFO full */
+#define SSP_SR_MASK_BSY(0x1 4) /* Busy Flag */
+
+struct pl022_spi_slave {
+ struct spi_slave slave;
+ void *regs;
+ unsigned int freq;
+};
+
+static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct pl022_spi_slave, slave);
+}
+
-- TAG+
+/*
+ * Following three functions should be provided by the
+ * board support package.
+ */
+int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+
Re: [U-Boot] [u-boot V4] spi/arm-pl022: Add support for ARM PL022 spi controller
On Wed, Jun 12, 2013 at 4:40 PM, Armando Visconti
armando.visco...@st.com wrote:
On 06/10/2013 06:01 PM, Jagan Teki wrote:
Hi,
Please use the commit header as below: just to sync with remaining
drivers in tree.
spi: arm-pl022: Add support for ARM PL022 spi controller
OK,
I already did it for v5.
I'll keep it for v6 as well...
On Fri, Jun 7, 2013 at 1:14 PM, Armando Visconti
armando.visco...@st.com wrote:
This patch adds the support for the ARM PL022 SPI controller for the
standard
variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX
FIFO.
Signed-off-by: Armando Visconti armando.visco...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Acked-by: Stefan Roese s...@denx.de
---
v3-v4
Just removed all warnings when running checkpatch.
Didn't find Jagan's feedback... So, pls, let me know if we
need to change anything else...
Armando
drivers/spi/Makefile| 1 +
drivers/spi/pl022_spi.c | 310
2 files changed, 311 insertions(+)
create mode 100644 drivers/spi/pl022_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d08609e..b6443b1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
new file mode 100644
index 000..8a8b9ab
--- /dev/null
+++ b/drivers/spi/pl022_spi.c
@@ -0,0 +1,310 @@
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visco...@st.com.
+ *
+ * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c
+ * by Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+/* SSP registers mapping */
+struct pl022 {
+ u32 ssp_cr0;/* 0x000 */
+ u32 ssp_cr1;/* 0x004 */
+ u32 ssp_dr; /* 0x008 */
+ u32 ssp_sr; /* 0x00c */
+ u32 ssp_cpsr; /* 0x010 */
+ u32 ssp_imsc; /* 0x014 */
+ u32 ssp_ris;/* 0x018 */
+ u32 ssp_mis;/* 0x01c */
+ u32 ssp_icr;/* 0x020 */
+ u32 ssp_dmacr; /* 0x024 */
+ u8 reserved_1[0x080 - 0x028];
+ u32 ssp_itcr; /* 0x080 */
+ u32 ssp_itip; /* 0x084 */
+ u32 ssp_itop; /* 0x088 */
+ u32 ssp_tdr;/* 0x08c */
+ u8 reserved_2[0xFE0 - 0x090];
+ u32 ssp_pid0; /* 0xfe0 */
+ u32 ssp_pid1; /* 0xfe4 */
+ u32 ssp_pid2; /* 0xfe8 */
+ u32 ssp_pid3; /* 0xfec */
+ u32 ssp_cid0; /* 0xff0 */
+ u32 ssp_cid1; /* 0xff4 */
+ u32 ssp_cid2; /* 0xff8 */
+ u32 ssp_cid3; /* 0xffc */
+};
+
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO(0x1 6)
+#define SSP_CR0_SPH(0x1 7)
+#define SSP_CR0_8BIT_MODE (0x07)
+#define SSP_SCR_MAX(0xFF)
+#define SSP_SCR_SHFT 8
+
+/* SSP Control Register 0 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 1)
+
+#define SSP_CPSR_MAX (0xFE)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE(0x1 0) /* Transmit FIFO empty
*/
+#define SSP_SR_MASK_TNF(0x1 1) /* Transmit FIFO not
full */
+#define SSP_SR_MASK_RNE(0x1 2) /* Receive FIFO not
empty */
+#define SSP_SR_MASK_RFF(0x1 3) /* Receive FIFO full
*/
+#define SSP_SR_MASK_BSY(0x1 4) /* Busy Flag */
+
+struct pl022_spi_slave {
+ struct spi_slave slave;
+ void *regs;
+ unsigned int freq;
+};
+
+static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave
*slave)
+{
+ return container_of(slave,
Re: [U-Boot] [u-boot V4] spi/arm-pl022: Add support for ARM PL022 spi controller
Hello Jagan,
+
+/*
+ * ARM PL022 exists in different 'flavors'.
+ * This drivers currently support the standard variant (0x00041022),
that has a
+ * 16bit wide and 8 locations deep TX/RX FIFO.
+ */
+static int pl022_is_supported(struct pl022_spi_slave *ps)
+{
+ struct pl022 *pl022 = (struct pl022 *)ps-regs;
+
+ /* PL022 version is 0x00041022 */
+ if ((readl(pl022-ssp_pid0) == 0x22)
+ (readl(pl022-ssp_pid1) == 0x10)
+ ((readl(pl022-ssp_pid2) 0xf) == 0x04)
+ (readl(pl022-ssp_pid3) == 0x00))
Tab space is required, for this if statement i guess, please check.
If I do then checkpatch reports a warning, saying that I need to keep
all lines of a 'if' statement aligned properly...
So, I guess that this way is more proper.
Agree, but it should be easy to interpret where should the if block
end and where should the code block starts.
I always use tab space like
+static int pl022_is_supported(struct pl022_spi_slave *ps)
+{
+ struct pl022 *pl022 = (struct pl022 *)ps-regs;
+
+ /* PL022 version is 0x00041022 */
+ if ((readl(pl022-ssp_pid0) == 0x22)
+ (readl(pl022-ssp_pid1) == 0x10)
+ ((readl(pl022-ssp_pid2) 0xf) == 0x04)
+ (readl(pl022-ssp_pid3) == 0x00))
+ return 1;
+
+ return 0;
+}
If you see return 1 is code block, so prior to this if ends.
OK, I'll do it in this way even if it may generate warnings.
Give me few mins and I'll send a v6 patch!
Thx,
Arm
--
-- Every step appears to be the unavoidable consequence of the
-- preceding one. (A. Einstein)
--
Armando Visconti Mobile: (+39) 346 8879146
Senior SW EngineerFax:(+39) 02 93519290
CPG Work: (+39) 02 93519683
Computer System Division e-mail: armando.visco...@st.com
ST Microelectronics TINA: 051 4683
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Re: [U-Boot] arm, arm335x: save_omap_boot_params question
On Wed, Jun 12, 2013 at 10:56:01AM +0200, Heiko Schocher wrote: Hello tom, your commit 4596dcc1d4ea5763e0f92cf5becd9fc7d4c6e674 Author: Tom Rini tr...@ti.com Date: Fri May 31 12:31:59 2013 -0400 am33xx/omap: Move save_omap_boot_params to omap-common/boot-common.c introduced, that all am335x based boards must call save_omap_boot_params() from the board specific s_init function. I just stumbled over it, as I updated to current head and my upcoming am335x based siemens boards didn't boot anymore ... should we think about to move this s_init() to a common place, and extract board specific things? Maybe arch/arm/cpu/armv7/omap-common/boot-common.c is a place for it? I think the first non-am335x_evm board pulled the code we need in board/ a bit too far in the board-specific direction. Whacking the WDT (which could be done differently I imagine based on your other patches), calling save_omap_boot_params and UART stuff is common. Figuring out which DDR and how is not. I think we can learn from omap-common/hwinit-common.c::s_init but need to have our own in arch/arm/cpu/armv7/am33xx/board.c and declared __weak or wrapped with CONFIG_AM33XX since TI814x (and TI816x) are different. Or maybe some more thinking share still. Do you have time for this? Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [u-boot V4] spi/arm-pl022: Add support for ARM PL022 spi controller
On Wed, Jun 12, 2013 at 5:48 PM, Armando Visconti
armando.visco...@st.com wrote:
Hello Jagan,
+
+/*
+ * ARM PL022 exists in different 'flavors'.
+ * This drivers currently support the standard variant (0x00041022),
that has a
+ * 16bit wide and 8 locations deep TX/RX FIFO.
+ */
+static int pl022_is_supported(struct pl022_spi_slave *ps)
+{
+ struct pl022 *pl022 = (struct pl022 *)ps-regs;
+
+ /* PL022 version is 0x00041022 */
+ if ((readl(pl022-ssp_pid0) == 0x22)
+ (readl(pl022-ssp_pid1) == 0x10)
+ ((readl(pl022-ssp_pid2) 0xf) == 0x04)
+ (readl(pl022-ssp_pid3) == 0x00))
Tab space is required, for this if statement i guess, please check.
If I do then checkpatch reports a warning, saying that I need to keep
all lines of a 'if' statement aligned properly...
So, I guess that this way is more proper.
Agree, but it should be easy to interpret where should the if block
end and where should the code block starts.
I always use tab space like
+static int pl022_is_supported(struct pl022_spi_slave *ps)
+{
+ struct pl022 *pl022 = (struct pl022 *)ps-regs;
+
+ /* PL022 version is 0x00041022 */
+ if ((readl(pl022-ssp_pid0) == 0x22)
+ (readl(pl022-ssp_pid1) == 0x10)
+ ((readl(pl022-ssp_pid2) 0xf) == 0x04)
+ (readl(pl022-ssp_pid3) == 0x00))
+ return 1;
+
+ return 0;
+}
If you see return 1 is code block, so prior to this if ends.
OK, I'll do it in this way even if it may generate warnings.
Give me few mins and I'll send a v6 patch!
Thx,
Arm
--
-- Every step appears to be the unavoidable consequence of the
-- preceding one. (A. Einstein)
--
Armando Visconti Mobile: (+39) 346 8879146
Senior SW EngineerFax:(+39) 02 93519290
CPG Work: (+39) 02 93519683
Computer System Division e-mail: armando.visco...@st.com
ST Microelectronics TINA: 051 4683
Please use the commit header as spi: pl022_spi:
as you haven't use the same on v5 i guess, please check.
--
Thanks,
Jagan.
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Re: [U-Boot] arm, arm335x: save_omap_boot_params question
Hello Tom, Am 12.06.2013 14:28, schrieb Tom Rini: On Wed, Jun 12, 2013 at 10:56:01AM +0200, Heiko Schocher wrote: Hello tom, your commit 4596dcc1d4ea5763e0f92cf5becd9fc7d4c6e674 Author: Tom Rini tr...@ti.com Date: Fri May 31 12:31:59 2013 -0400 am33xx/omap: Move save_omap_boot_params to omap-common/boot-common.c introduced, that all am335x based boards must call save_omap_boot_params() from the board specific s_init function. I just stumbled over it, as I updated to current head and my upcoming am335x based siemens boards didn't boot anymore ... should we think about to move this s_init() to a common place, and extract board specific things? Maybe arch/arm/cpu/armv7/omap-common/boot-common.c is a place for it? I think the first non-am335x_evm board pulled the code we need in board/ a bit too far in the board-specific direction. Whacking the WDT (which could be done differently I imagine based on your other patches), calling save_omap_boot_params and UART stuff is common. Figuring out which DDR and how is not. I think we can learn from omap-common/hwinit-common.c::s_init but need to have our own in arch/arm/cpu/armv7/am33xx/board.c and declared __weak or wrapped with CONFIG_AM33XX since TI814x (and TI816x) are different. Or maybe some more thinking share still. Do you have time for this? Thanks! I try to find some ;-) Maybe something like this: add in arch/arm/cpu/armv7/am33xx/board.c a weak s_init(), which all am35xx boards use, and call in this s_init() a s_init_board() which all am335x boards must have defined? bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [u-boot V4] spi/arm-pl022: Add support for ARM PL022 spi controller
Please use the commit header as spi: pl022_spi: as you haven't use the same on v5 i guess, please check. OK, Jagan, I'll do it! Armando ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5] arm: dra7xx: Update the EXTRA_ENV_SETTINGS
On Tue, Jun 11, 2013 at 11:22:30AM -0500, Dan Murphy wrote: Update the EXTRA_ENV_SETTING for the dra7xx. The console needs to be set to ttyO0 and the findfdt needs to be updated to load the dra7xx-evm.dtb file. Signed-off-by: Dan Murphy dmur...@ti.com Reviewed-by: Tom Rini tr...@ti.com -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller
This patch adds the support for the ARM PL022 SPI controller for the standard
variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO.
Signed-off-by: Armando Visconti armando.visco...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Acked-by: Stefan Roese s...@denx.de
---
v5-v6
1. Make use of spi_alloc_slave() macro.
2. Changed the identation on 'if statement' as requested
by Jagan.
drivers/spi/Makefile| 1 +
drivers/spi/pl022_spi.c | 308
2 files changed, 309 insertions(+)
create mode 100644 drivers/spi/pl022_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d08609e..b6443b1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
new file mode 100644
index 000..5b47413
--- /dev/null
+++ b/drivers/spi/pl022_spi.c
@@ -0,0 +1,308 @@
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visco...@st.com.
+ *
+ * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c
+ * by Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+/* SSP registers mapping */
+struct pl022 {
+ u32 ssp_cr0;/* 0x000 */
+ u32 ssp_cr1;/* 0x004 */
+ u32 ssp_dr; /* 0x008 */
+ u32 ssp_sr; /* 0x00c */
+ u32 ssp_cpsr; /* 0x010 */
+ u32 ssp_imsc; /* 0x014 */
+ u32 ssp_ris;/* 0x018 */
+ u32 ssp_mis;/* 0x01c */
+ u32 ssp_icr;/* 0x020 */
+ u32 ssp_dmacr; /* 0x024 */
+ u8 reserved_1[0x080 - 0x028];
+ u32 ssp_itcr; /* 0x080 */
+ u32 ssp_itip; /* 0x084 */
+ u32 ssp_itop; /* 0x088 */
+ u32 ssp_tdr;/* 0x08c */
+ u8 reserved_2[0xFE0 - 0x090];
+ u32 ssp_pid0; /* 0xfe0 */
+ u32 ssp_pid1; /* 0xfe4 */
+ u32 ssp_pid2; /* 0xfe8 */
+ u32 ssp_pid3; /* 0xfec */
+ u32 ssp_cid0; /* 0xff0 */
+ u32 ssp_cid1; /* 0xff4 */
+ u32 ssp_cid2; /* 0xff8 */
+ u32 ssp_cid3; /* 0xffc */
+};
+
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO(0x1 6)
+#define SSP_CR0_SPH(0x1 7)
+#define SSP_CR0_8BIT_MODE (0x07)
+#define SSP_SCR_MAX(0xFF)
+#define SSP_SCR_SHFT 8
+
+/* SSP Control Register 0 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 1)
+
+#define SSP_CPSR_MAX (0xFE)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE(0x1 0) /* Transmit FIFO empty */
+#define SSP_SR_MASK_TNF(0x1 1) /* Transmit FIFO not full */
+#define SSP_SR_MASK_RNE(0x1 2) /* Receive FIFO not empty */
+#define SSP_SR_MASK_RFF(0x1 3) /* Receive FIFO full */
+#define SSP_SR_MASK_BSY(0x1 4) /* Busy Flag */
+
+struct pl022_spi_slave {
+ struct spi_slave slave;
+ void *regs;
+ unsigned int freq;
+};
+
+static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct pl022_spi_slave, slave);
+}
+
+/*
+ * Following three functions should be provided by the
+ * board support package.
+ */
+int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void __weak spi_cs_activate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void __weak spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* do nothing */
+}
+
+void spi_init(void)
+{
+ /* do nothing */
+}
+
+/*
+ * ARM PL022 exists in different 'flavors'.
+ * This drivers currently support the standard variant (0x00041022), that has a
+ * 16bit wide and 8
Re: [U-Boot] arm, arm335x: save_omap_boot_params question
On Wed, Jun 12, 2013 at 02:39:13PM +0200, Heiko Schocher wrote: Hello Tom, Am 12.06.2013 14:28, schrieb Tom Rini: On Wed, Jun 12, 2013 at 10:56:01AM +0200, Heiko Schocher wrote: Hello tom, your commit 4596dcc1d4ea5763e0f92cf5becd9fc7d4c6e674 Author: Tom Rini tr...@ti.com Date: Fri May 31 12:31:59 2013 -0400 am33xx/omap: Move save_omap_boot_params to omap-common/boot-common.c introduced, that all am335x based boards must call save_omap_boot_params() from the board specific s_init function. I just stumbled over it, as I updated to current head and my upcoming am335x based siemens boards didn't boot anymore ... should we think about to move this s_init() to a common place, and extract board specific things? Maybe arch/arm/cpu/armv7/omap-common/boot-common.c is a place for it? I think the first non-am335x_evm board pulled the code we need in board/ a bit too far in the board-specific direction. Whacking the WDT (which could be done differently I imagine based on your other patches), calling save_omap_boot_params and UART stuff is common. Figuring out which DDR and how is not. I think we can learn from omap-common/hwinit-common.c::s_init but need to have our own in arch/arm/cpu/armv7/am33xx/board.c and declared __weak or wrapped with CONFIG_AM33XX since TI814x (and TI816x) are different. Or maybe some more thinking share still. Do you have time for this? Thanks! I try to find some ;-) Maybe something like this: add in arch/arm/cpu/armv7/am33xx/board.c a weak s_init(), which all am35xx boards use, and call in this s_init() a s_init_board() which all am335x boards must have defined? s/s_init_board/sdram_init/ and yes. If we whack the UART stuff out into uart_enable (ala ti814x) and add a board_enable_early_pinmux (for the muxes needed, and put this right after save_omap_...) we might not need to make s_init __weak. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] fix displaying IRQ stack info
On Mon, 27 May 2013 14:29:20 +0900, Masahiro Yamada yamad...@jp.panasonic.com wrote: These series of patches fix the location of displaying IRQ stack infomation. Because ARM architecture supports generic_board, I separated my commit into 2 patches. The first one fix arch/arm/lib/board.c The second one fix common/board_f.c and common/board_r.c Masahiro Yamada (2): arm: fix displaying IRQ stack info common: arm: fix displaying IRQ stack info arch/arm/lib/board.c | 10 ++ common/board_f.c |4 common/board_r.c | 10 ++ 3 files changed, 16 insertions(+), 8 deletions(-) After discussing with Masahiro and Wolfgang, this patch will not be applied, as currently no board defines CONFIG_USE_IRQ any more. What becomes of code which depends on CONFIG_USE_IRQ will be sorted out through discussing an RFC on interrupt handling in U-boot which I will post within a couple of days. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller
Thanks for v6 sent.
Have you tested this?
on which board, include/configs/*.h file?
--
Thanks,
Jagan.
On Wed, Jun 12, 2013 at 6:17 PM, Armando Visconti
armando.visco...@st.com wrote:
This patch adds the support for the ARM PL022 SPI controller for the standard
variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO.
Signed-off-by: Armando Visconti armando.visco...@st.com
Signed-off-by: Vipin Kumar vipin.ku...@st.com
Acked-by: Stefan Roese s...@denx.de
---
v5-v6
1. Make use of spi_alloc_slave() macro.
2. Changed the identation on 'if statement' as requested
by Jagan.
drivers/spi/Makefile| 1 +
drivers/spi/pl022_spi.c | 308
2 files changed, 309 insertions(+)
create mode 100644 drivers/spi/pl022_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d08609e..b6443b1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
new file mode 100644
index 000..5b47413
--- /dev/null
+++ b/drivers/spi/pl022_spi.c
@@ -0,0 +1,308 @@
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visco...@st.com.
+ *
+ * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c
+ * by Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+/* SSP registers mapping */
+struct pl022 {
+ u32 ssp_cr0;/* 0x000 */
+ u32 ssp_cr1;/* 0x004 */
+ u32 ssp_dr; /* 0x008 */
+ u32 ssp_sr; /* 0x00c */
+ u32 ssp_cpsr; /* 0x010 */
+ u32 ssp_imsc; /* 0x014 */
+ u32 ssp_ris;/* 0x018 */
+ u32 ssp_mis;/* 0x01c */
+ u32 ssp_icr;/* 0x020 */
+ u32 ssp_dmacr; /* 0x024 */
+ u8 reserved_1[0x080 - 0x028];
+ u32 ssp_itcr; /* 0x080 */
+ u32 ssp_itip; /* 0x084 */
+ u32 ssp_itop; /* 0x088 */
+ u32 ssp_tdr;/* 0x08c */
+ u8 reserved_2[0xFE0 - 0x090];
+ u32 ssp_pid0; /* 0xfe0 */
+ u32 ssp_pid1; /* 0xfe4 */
+ u32 ssp_pid2; /* 0xfe8 */
+ u32 ssp_pid3; /* 0xfec */
+ u32 ssp_cid0; /* 0xff0 */
+ u32 ssp_cid1; /* 0xff4 */
+ u32 ssp_cid2; /* 0xff8 */
+ u32 ssp_cid3; /* 0xffc */
+};
+
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO(0x1 6)
+#define SSP_CR0_SPH(0x1 7)
+#define SSP_CR0_8BIT_MODE (0x07)
+#define SSP_SCR_MAX(0xFF)
+#define SSP_SCR_SHFT 8
+
+/* SSP Control Register 0 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 1)
+
+#define SSP_CPSR_MAX (0xFE)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE(0x1 0) /* Transmit FIFO empty */
+#define SSP_SR_MASK_TNF(0x1 1) /* Transmit FIFO not full
*/
+#define SSP_SR_MASK_RNE(0x1 2) /* Receive FIFO not empty
*/
+#define SSP_SR_MASK_RFF(0x1 3) /* Receive FIFO full */
+#define SSP_SR_MASK_BSY(0x1 4) /* Busy Flag */
+
+struct pl022_spi_slave {
+ struct spi_slave slave;
+ void *regs;
+ unsigned int freq;
+};
+
+static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct pl022_spi_slave, slave);
+}
+
+/*
+ * Following three functions should be provided by the
+ * board support package.
+ */
+int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void __weak spi_cs_activate(struct spi_slave *slave)
+{
+
[U-Boot] DHCP Gateway
Is there a reason why the gateway address (NetOurGatewayIP) doesn't get set from the BOOTP header (bp_giaddr) as a default before processing the DHCP options? Sure would help me. Thanks, Dean ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] U-boot for 64bit ARMv8
Is anyone considering porting/supporting uboot for ARMv8. Our initial investigation of boot loader support for ARMv8 indicates that the only boot loader currently being targeted is UEFI. The decisions we need to make are: - Do we move to UEFI on ARM? - Can we leverage someone else's enablement of ARMv8? - Do we provide our own enablement of ARMv8? Any opinions? Rich___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller
On 06/12/2013 04:25 PM, Jagan Teki wrote: Thanks for v6 sent. Have you tested this? on which board, include/configs/*.h file? No Jagan. I have not tested v6, as I currently don't have a spare board. Nevertheless, Vipin tested it up to v3. And he tested it on spear1340 evaluation board. After v3, no big changes have been performed. Just style changes and make use of spi_alloc_slave()... But if you prefer to be on safer side I think we need to re-do some checks on a spare 1340 board... Pls let me know, Arm -- -- Every step appears to be the unavoidable consequence of the -- preceding one. (A. Einstein) -- Armando Visconti Mobile: (+39) 346 8879146 Senior SW EngineerFax:(+39) 02 93519290 CPG Work: (+39) 02 93519683 Computer System Division e-mail: armando.visco...@st.com ST Microelectronics TINA: 051 4683 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller
But if you prefer to be on safer side I think we need to re-do some checks on a spare 1340 board... OK, maybe it is better to re-check again. I need to find some time and a spare board... I'll let you know, Arm ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller
On Wed, Jun 12, 2013 at 8:49 PM, Armando Visconti armando.visco...@st.com wrote: But if you prefer to be on safer side I think we need to re-do some checks on a spare 1340 board... OK, maybe it is better to re-check again. I need to find some time and a spare board... I'll let you know, Arm Do we have an config file available in master, i need to build at-least. -- Thanks, Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] spi: mxc_spi: Update pre and post divider algorithm
Hi Dirk,
On 12/06/2013 07:28, Dirk Behme wrote:
On 11.05.2013 07:25, Dirk Behme wrote:
The spi clock divisor is of the form x * (2**y), or x y, where x is
1 to 16, and y is 0 to 15. Note the similarity with floating point
numbers.
Convert the desired divisor to the smallest number which is = desired
divisor,
and can be represented in this form. The previous algorithm chose a
divisor
which could be almost twice as large as needed.
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
Signed-off-by: Dirk Behme dirk.be...@gmail.com
While we are talking about a first -rc now, could we get these two patches
http://patchwork.ozlabs.org/patch/242709/
http://patchwork.ozlabs.org/patch/243113/
Sorry to come late with these two patches - after a first glance when
you post then, I put the patches at the bottom of my queue and I never
checked again.
I will work them before end of the week.
Best regards,
Stefano Babic
applied?
Thanks
Dirk
---
Notes:
- Changes in v2: Make the alogrithm simpler by removing the -1 as
proposed
by Troy. Make the pre_div and post_div u32.
- This replaces v1 of this patch and depends on the previous sent patch
http://patchwork.ozlabs.org/patch/242709/
drivers/spi/mxc_spi.c | 30 --
1 file changed, 12 insertions(+), 18 deletions(-)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 3e903b3..e87b899 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -128,8 +128,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs,
unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
-s32 pre_div = 1, post_div = 0, i, reg_ctrl, reg_config;
-u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
+s32 reg_ctrl, reg_config;
+u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, pre_div = 0, post_div = 0;
struct cspi_regs *regs = (struct cspi_regs *)mxcs-base;
if (max_hz == 0) {
@@ -147,26 +147,20 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave
*mxcs, unsigned int cs,
reg_ctrl |= MXC_CSPICTRL_EN;
reg_write(regs-ctrl, reg_ctrl);
-/*
- * The following computation is taken directly from Freescale's
code.
- */
if (clk_src max_hz) {
-pre_div = DIV_ROUND_UP(clk_src, max_hz);
-if (pre_div 16) {
-post_div = pre_div / 16;
-pre_div = 16;
-}
-if (post_div != 0) {
-for (i = 0; i 16; i++) {
-if ((1 i) = post_div)
-break;
-}
-if (i == 16) {
+pre_div = (clk_src - 1) / max_hz;
+/* fls(1) = 1, fls(0x8000) = 32, fls(16) = 5 */
+post_div = fls(pre_div);
+if (post_div 4) {
+post_div -= 4;
+if (post_div = 16) {
printf(Error: no divider for the freq: %d\n,
max_hz);
return -1;
}
-post_div = i;
+pre_div = post_div;
+} else {
+post_div = 0;
}
}
@@ -174,7 +168,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs,
unsigned int cs,
reg_ctrl = (reg_ctrl ~MXC_CSPICTRL_SELCHAN(3)) |
MXC_CSPICTRL_SELCHAN(cs);
reg_ctrl = (reg_ctrl ~MXC_CSPICTRL_PREDIV(0x0F)) |
-MXC_CSPICTRL_PREDIV(pre_div - 1);
+MXC_CSPICTRL_PREDIV(pre_div);
reg_ctrl = (reg_ctrl ~MXC_CSPICTRL_POSTDIV(0x0F)) |
MXC_CSPICTRL_POSTDIV(post_div);
--
=
DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
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Re: [U-Boot] [PATCH v2] spi: mxc_spi: Update pre and post divider algorithm
On Wed, Jun 12, 2013 at 9:12 PM, Stefano Babic sba...@denx.de wrote:
Hi Dirk,
On 12/06/2013 07:28, Dirk Behme wrote:
On 11.05.2013 07:25, Dirk Behme wrote:
The spi clock divisor is of the form x * (2**y), or x y, where x is
1 to 16, and y is 0 to 15. Note the similarity with floating point
numbers.
Convert the desired divisor to the smallest number which is = desired
divisor,
and can be represented in this form. The previous algorithm chose a
divisor
which could be almost twice as large as needed.
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
Signed-off-by: Dirk Behme dirk.be...@gmail.com
While we are talking about a first -rc now, could we get these two patches
http://patchwork.ozlabs.org/patch/242709/
http://patchwork.ozlabs.org/patch/243113/
Sorry to come late with these two patches - after a first glance when
you post then, I put the patches at the bottom of my queue and I never
checked again.
I will work them before end of the week.
Best regards,
Stefano Babic
applied?
Thanks
Dirk
---
Notes:
- Changes in v2: Make the alogrithm simpler by removing the -1 as
proposed
by Troy. Make the pre_div and post_div u32.
- This replaces v1 of this patch and depends on the previous sent patch
http://patchwork.ozlabs.org/patch/242709/
drivers/spi/mxc_spi.c | 30 --
1 file changed, 12 insertions(+), 18 deletions(-)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 3e903b3..e87b899 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -128,8 +128,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs,
unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
-s32 pre_div = 1, post_div = 0, i, reg_ctrl, reg_config;
-u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
+s32 reg_ctrl, reg_config;
+u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, pre_div = 0, post_div = 0;
struct cspi_regs *regs = (struct cspi_regs *)mxcs-base;
if (max_hz == 0) {
@@ -147,26 +147,20 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave
*mxcs, unsigned int cs,
reg_ctrl |= MXC_CSPICTRL_EN;
reg_write(regs-ctrl, reg_ctrl);
-/*
- * The following computation is taken directly from Freescale's
code.
- */
if (clk_src max_hz) {
-pre_div = DIV_ROUND_UP(clk_src, max_hz);
-if (pre_div 16) {
-post_div = pre_div / 16;
-pre_div = 16;
-}
-if (post_div != 0) {
-for (i = 0; i 16; i++) {
-if ((1 i) = post_div)
-break;
-}
-if (i == 16) {
+pre_div = (clk_src - 1) / max_hz;
+/* fls(1) = 1, fls(0x8000) = 32, fls(16) = 5 */
+post_div = fls(pre_div);
+if (post_div 4) {
+post_div -= 4;
+if (post_div = 16) {
printf(Error: no divider for the freq: %d\n,
max_hz);
return -1;
}
-post_div = i;
+pre_div = post_div;
+} else {
+post_div = 0;
}
}
@@ -174,7 +168,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs,
unsigned int cs,
reg_ctrl = (reg_ctrl ~MXC_CSPICTRL_SELCHAN(3)) |
MXC_CSPICTRL_SELCHAN(cs);
reg_ctrl = (reg_ctrl ~MXC_CSPICTRL_PREDIV(0x0F)) |
-MXC_CSPICTRL_PREDIV(pre_div - 1);
+MXC_CSPICTRL_PREDIV(pre_div);
reg_ctrl = (reg_ctrl ~MXC_CSPICTRL_POSTDIV(0x0F)) |
MXC_CSPICTRL_POSTDIV(post_div);
--
=
DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
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Sorry, i didn't understand the conversation here, was this fix applied?
Could you please explain.
--
Thanks,
Jagan.
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Re: [U-Boot] [PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller
On 06/12/2013 05:29 PM, Jagan Teki wrote: On Wed, Jun 12, 2013 at 8:49 PM, Armando Visconti armando.visco...@st.com wrote: But if you prefer to be on safer side I think we need to re-do some checks on a spare 1340 board... OK, maybe it is better to re-check again. I need to find some time and a spare board... I'll let you know, Arm Do we have an config file available in master, i need to build at-least. Mmmh... currently in mainline there is only spear3xx config file, but there is no PL022 support there. In fact, to compile locally here I had to change it in this way, even if they cannot be used for testing (only compiling): diff --git a/include/configs/spear3xx_evb.h b/include/configs/spear3xx_evb.h index 3cd56dc..03a046e 100644 --- a/include/configs/spear3xx_evb.h +++ b/include/configs/spear3xx_evb.h @@ -54,6 +54,11 @@ /* Ethernet driver configuration */ #define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_PL022_SPI1 +#define CONFIG_SYS_SPI_BASE 0xE010 +#define CONFIG_SYS_SPI_CLK 8300 +#define CONFIG_CMD_SPI 1 + #if defined(CONFIG_SPEAR310) #define CONFIG_MACB #define CONFIG_MACB0_PHY 0x01 I know that Vipin was going to add support of spear1340 in mainline. His patches are currently already submitted and partially acked but I'm not sure what is the status now... Vipin, can you update us? Rgds, Arm ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] spi: mxc_spi: Update pre and post divider algorithm
Hi, On 12/06/2013 17:47, Jagan Teki wrote: Sorry, i didn't understand the conversation here, was this fix applied? Could you please explain. Patches are not applied and are currently assigned to me. As they concerned the SPI subsystem (really, it is the SPI driver for iMX), they could be applied by you as SPI custodian or by me as IMX custodian. Should I assign them to you ? Regards, Stefano -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/4] MIPS: mips64/interrupt.c: remove superfluous include
Nothing is used from asm/mipsregs.h.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
---
arch/mips/cpu/mips64/interrupts.c |1 -
1 file changed, 1 deletion(-)
diff --git a/arch/mips/cpu/mips64/interrupts.c
b/arch/mips/cpu/mips64/interrupts.c
index e4e9aae..87f7a9f 100644
--- a/arch/mips/cpu/mips64/interrupts.c
+++ b/arch/mips/cpu/mips64/interrupts.c
@@ -22,7 +22,6 @@
*/
#include common.h
-#include asm/mipsregs.h
void enable_interrupts(void)
{
--
1.7.10
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[U-Boot] [PATCH 0/4] MIPS: minor cleanups
Gabor Juhos (4): MIPS: mips32/time.c: fix checkpatch errors/warnings MIPS: mips64/interrupt.c: remove superfluous include MIPS: remove obsolete TODO items MIPS: mips32/cache.S: remove superfluous register assignment arch/mips/cpu/mips32/cache.S |3 +-- arch/mips/cpu/mips32/time.c |5 +++-- arch/mips/cpu/mips64/interrupts.c |1 - doc/README.mips |4 4 files changed, 4 insertions(+), 9 deletions(-) -- 1.7.10 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/4] MIPS: mips32/cache.S: remove superfluous register assignment
The t4 register already holds the cache line size, and the value of the register is not changed in mips_init_icache. Get the cache line size value from t4 for mips_init_dcache as well and remove the superfluous assignment of t5 register. Signed-off-by: Gabor Juhos juh...@openwrt.org --- arch/mips/cpu/mips32/cache.S |3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 64dfad0..8158ea8 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -145,7 +145,6 @@ NESTED(mips_cache_reset, 0, ra) li t2, CONFIG_SYS_ICACHE_SIZE li t3, CONFIG_SYS_DCACHE_SIZE li t4, CONFIG_SYS_CACHELINE_SIZE - movet5, t4 li v0, MIPS_MAX_CACHE_SIZE @@ -180,7 +179,7 @@ NESTED(mips_cache_reset, 0, ra) * then initialize D-cache. */ movea1, t3 - movea2, t5 + movea2, t4 PTR_LA t7, mips_init_dcache jalrt7 -- 1.7.10 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/4] MIPS: mips32/time.c: fix checkpatch errors/warnings
Checking mips32/time.c with checkpatch.pl shows this: arch/mips/cpu/mips32/time.c:30: WARNING: line over 80 characters arch/mips/cpu/mips32/time.c:57: ERROR: return is not a function, parentheses are not required total: 1 errors, 1 warnings, 0 checks, 85 lines checked Fix the code to make checkpatch.pl happy. Signed-off-by: Gabor Juhos juh...@openwrt.org Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com --- arch/mips/cpu/mips32/time.c |5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/mips/cpu/mips32/time.c b/arch/mips/cpu/mips32/time.c index 09fc842..e9ed7fc 100644 --- a/arch/mips/cpu/mips32/time.c +++ b/arch/mips/cpu/mips32/time.c @@ -27,7 +27,8 @@ static unsigned long timestamp; /* how many counter cycles in a jiffy */ -#define CYCLES_PER_JIFFY (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ +#define CYCLES_PER_JIFFY \ + (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ /* * timer without interrupts @@ -54,7 +55,7 @@ ulong get_timer(ulong base) } write_c0_compare(expirelo); - return (timestamp - base); + return timestamp - base; } void __udelay(unsigned long usec) -- 1.7.10 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4] MIPS: remove obsolete TODO items
The MIPS code uses centralized u-boot.lds script already, and dynamic relocation is supported as well. Signed-off-by: Gabor Juhos juh...@openwrt.org Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com --- doc/README.mips |4 1 file changed, 4 deletions(-) diff --git a/doc/README.mips b/doc/README.mips index f4f770b..b28f628 100644 --- a/doc/README.mips +++ b/doc/README.mips @@ -39,8 +39,6 @@ TODOs * Secondary cache support missing - * Centralize the link directive files - * Initialize TLB entries redardless of their use * R2000/R3000 class parts are not supported @@ -51,8 +49,6 @@ TODOs initialized in board specific assembler language before the cache init code is run -- that is, initialize the DRAM in lowlevel_init(). - * get rid of CONFIG_MANUAL_RELOC - * centralize/share more CPU code of MIPS32, MIPS64 and XBurst * support Qemu Malta -- 1.7.10 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] spi: mxc_spi: Update pre and post divider algorithm
On Wed, Jun 12, 2013 at 9:30 PM, Stefano Babic sba...@denx.de wrote: Hi, On 12/06/2013 17:47, Jagan Teki wrote: Sorry, i didn't understand the conversation here, was this fix applied? Could you please explain. Patches are not applied and are currently assigned to me. As they concerned the SPI subsystem (really, it is the SPI driver for iMX), they could be applied by you as SPI custodian or by me as IMX custodian. Should I assign them to you ? np, thanks for your information. if your are in middle of this conversation/review please go ahead, but please let me know once the review has done so-that i will apply this on my custodian tree. Is it ok for you? -- Thanks, Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] dfu: make data buffer size configurable
On Wed, Jun 12, 2013 at 06:05:51AM +0200, Heiko Schocher wrote: Dfu transfer uses a buffer before writing data to the raw storage device. Make the size (in bytes) of this buffer configurable through environment variable dfu_bufsiz. Defaut value is configurable through CONFIG_SYS_DFU_DATA_BUF_SIZE Signed-off-by: Heiko Schocher h...@denx.de Cc: Pantelis Antoniou pa...@antoniou-consulting.com Cc: Tom Rini tr...@ti.com Cc: Lukasz Majewski l.majew...@samsung.com Cc: Kyungmin Park kyungmin.p...@samsung.com Cc: Marek Vasut ma...@denx.de Cc: Wolfgang Denk w...@denx.de Acked-by: Tom Rini tr...@ti.com -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [STATUS] ARM - pending PRs or patches for -rc1
Hello, (cc:ing all ARM related repo custodians for PRs) I have cleaned up my todo list for 2013.07 and am now preparing for -rc1. ARM related repo custodians who have PRs still pending to be sent to me, please do now. Any patches that their submitter feels should be in some ARM repo by now but are not yet, please yell at the corresponding custodian, myself included. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-boot for 64bit ARMv8
On Wed, Jun 12, 2013 at 06:10:06AM -0700, Richard Schmitt wrote: Is anyone considering porting/supporting uboot for ARMv8. ?Our initial investigation of boot loader support for ARMv8 indicates that the only boot loader currently being targeted is UEFI. ? The decisions we need to make are: - Do we move to UEFI on ARM? - Can we leverage someone else's enablement of ARMv8? - Do we provide our own enablement of ARMv8? Any opinions? The general push from ARM Ltd is to use UEFI. I would strongly suspect that there are U-Boot forks that companies that have announced they are doing ARMv8 chips have something as a stop-gap until they have the functionality they want in uEFI. I am quite open to ARMv8 support being added to U-Boot and addressing the concerns companies may have. Sometimes it seems like GPLv2+ makes people think Project will be moving to GPLv3, RUN AWAY! when all it really means is Project is GPLv2+, will evaluate the appropriateness of later versions. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 00/17] sf: Update sf framework to support all sizes of flashes
Hi Simon, On Wed, Jun 12, 2013 at 3:59 AM, Simon Glass s...@chromium.org wrote: Hi Jagan, On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com wrote: This series is v3 for the patch series sent few weeks back with a head sf: Update sf framework to support all sizes of flashes All patch are looks same for v2 and v3 but placed the bank addr code on CONFIG_SPI_FLASH_BAR to reduce the sizes. The current implementation in sf supports 3-byte address mode due to this up to 16MB amount of flash is able to access for those flashes which has an actual size of 16MB. This series of patches is more detailed/meatured changes w.r.t the current sf framework in addition to changes related to support all sizes using bank/exnt register addr accessing support. With these new updates on sf framework, the flashes which has 16MB are not effected as per as performance is concern and but the u-boot.bin size incrased ~600 bytes. sf update(for first 16MBytes), Changes before: U-Boot sf update 0x100 0x0 0x100 - N25Q256 16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s - W25Q128BV 16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s - S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s sf update(for first 16MBytes), Changes after: U-Boot sf update 0x100 0x0 0x100 - N25Q256 16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s - W25Q128BV 16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s - S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s The main aim of these changes is to not effect the current framework and at the same time to support the 16Mbyte flashes, becuase of this I involved few flash vendor people in CC [thought that they may/mayn't be a mailing list members] to know their views. REQUEST FOR ALL SPI CODE CONTRIBUTORS/USERS, PLEASE TEST THESE CHANGES W.R.T YOUR HW IF POSSIBLE. Well the code size looks good - lots of changes within the series: Same as v2 with two additional patches for CONFIG_SPI_FLASH_BAR and removed one read common usage patch. ./tools/buildman/buildman -b try-spi2 smdk5250 -Ss Summary of 18 commits for 2 boards (2 threads, 16 jobs per thread) 01: cmd_sf: Add print mesgs on sf read/write commands 02: sf: Add bank address register writing support arm: (for 2/2 boards) all +202.0 bss -4.0 rodata +38.0 text +168.0 03: sf: Add bank address register reading support arm: (for 2/2 boards) all +133.0 bss +16.0 rodata +37.0 text +80.0 04: sf: Add extended addr write support for winbond|stmicro arm: (for 2/2 boards) bss -8.0 text +8.0 05: sf: Add extended addr read support for winbond|stmicro arm: (for 2/2 boards) bss -24.0 text +24.0 06: sf: read flash bank addr register at probe time arm: (for 2/2 boards) all +128.0 bss +48.0 text +80.0 07: sf: Update sf to support all sizes of flashes arm: (for 2/2 boards) bss -32.0 text +32.0 08: sf: Update sf read to support all sizes of flashes arm: (for 2/2 boards) all +128.0 bss +32.0 text +96.0 09: sf: Add bank addr code in CONFIG_SPI_FLASH_BAR arm: + snow smdk5250 arm: (for 2/2 boards) all -527.0 bss -28.0 rodata -75.0 text -424.0 10: sf: Initialize bank_sel to zero for read ops arm:snow smdk5250 arm: (for 2/2 boards) bss +8.0 text -8.0 11: sf: Use spi_flash_addr() in write call arm: (for 2/2 boards) bss +24.0 text -24.0 12: sf: stmicro: Add support for N25Q512 13: sf: stmicro: Add support for N25Q512A 14: sf: stmicro: Add support for N25Q1024 15: sf: stmicro: Add support for N25Q1024A 16: sf: spansion: Add support for S25FL512S_64K 17: sf: Remove spi_flash_cmd_poll_bit() arm: (for 2/2 boards) all -64.0 bss -48.0 text -16.0 18: sf: Add Flag status register polling support but no change overall: ./tools/buildman/buildman -b try-spi2 smdk5250 -Ss --step 0 Summary of 2 commits for 2 boards (2 threads, 16 jobs per thread) 01: cmd_sf: Add print mesgs on sf read/write commands 18: sf: Add Flag status register polling support arm: (for 2/2 boards) bss -16.0 text +16.0 Please let know for any issues. -- Thanks, Jagan. Please let me know for any issues/concerns/questions. Jagannadha Sutradharudu Teki (17): sf: Add bank address register writing support sf: Add bank address register reading support sf: Add extended addr write support for winbond|stmicro sf: Add extended addr read support for winbond|stmicro sf: read flash bank addr register at probe time sf: Update sf to support all sizes of flashes sf: Update sf read to support all sizes of flashes sf: Add bank addr code in CONFIG_SPI_FLASH_BAR sf: Initialize bank_sel to zero for read ops sf: Use spi_flash_addr() in write call sf: stmicro: Add support
Re: [U-Boot] U-boot for 64bit ARMv8
Hi Tom, On Wed, 12 Jun 2013 12:33:39 -0400, Tom Rini tr...@ti.com wrote: On Wed, Jun 12, 2013 at 06:10:06AM -0700, Richard Schmitt wrote: Is anyone considering porting/supporting uboot for ARMv8. ?Our initial investigation of boot loader support for ARMv8 indicates that the only boot loader currently being targeted is UEFI. ? The decisions we need to make are: - Do we move to UEFI on ARM? - Can we leverage someone else's enablement of ARMv8? - Do we provide our own enablement of ARMv8? Any opinions? The general push from ARM Ltd is to use UEFI. I would strongly suspect that there are U-Boot forks that companies that have announced they are doing ARMv8 chips have something as a stop-gap until they have the functionality they want in uEFI. I am quite open to ARMv8 support being added to U-Boot and addressing the concerns companies may have. Sometimes it seems like GPLv2+ makes people think Project will be moving to GPLv3, RUN AWAY! when all it really means is Project is GPLv2+, will evaluate the appropriateness of later versions. This is not specific to 64-Bit ARM support, though. GPLv2+ has been there for very long. Aren't companies educated by now? (I am quite open to helping spread education, anyway) Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-boot for 64bit ARMv8
On Wed, Jun 12, 2013 at 06:54:54PM +0200, Albert ARIBAUD wrote: Hi Tom, On Wed, 12 Jun 2013 12:33:39 -0400, Tom Rini tr...@ti.com wrote: On Wed, Jun 12, 2013 at 06:10:06AM -0700, Richard Schmitt wrote: Is anyone considering porting/supporting uboot for ARMv8. ?Our initial investigation of boot loader support for ARMv8 indicates that the only boot loader currently being targeted is UEFI. ? The decisions we need to make are: - Do we move to UEFI on ARM? - Can we leverage someone else's enablement of ARMv8? - Do we provide our own enablement of ARMv8? Any opinions? The general push from ARM Ltd is to use UEFI. I would strongly suspect that there are U-Boot forks that companies that have announced they are doing ARMv8 chips have something as a stop-gap until they have the functionality they want in uEFI. I am quite open to ARMv8 support being added to U-Boot and addressing the concerns companies may have. Sometimes it seems like GPLv2+ makes people think Project will be moving to GPLv3, RUN AWAY! when all it really means is Project is GPLv2+, will evaluate the appropriateness of later versions. This is not specific to 64-Bit ARM support, though. GPLv2+ has been there for very long. Aren't companies educated by now? (I am quite open to helping spread education, anyway) Indeed, it applies to the project as a whole. I have however, gotten some private feedback that to me says that there are companies out there afraid that because we retain our + we're going to switch to GPLv3 any minute, rather than keeping our options open, should some future GPL provide a compromise both developers, companies and regular consumers can live with. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arm: omap4: panda: Add reading of the board revision
Detect if we are running on a panda revision A1-A6,
or an ES panda board. This can be done by reading
the level of GPIOs and checking the processor revisions.
This should result in:
Panda 4430:
GPIO171, GPIO101, GPIO182: 0 1 1 = A1-A5
GPIO171, GPIO101, GPIO182: 1 0 1 = A6
Panda ES:
GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 = B1/B2
GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 = B3
Set the board name appropriately for the board revision that
is detected.
Update the findfdt macro to load the a4 device tree binary.
Signed-off-by: Dan Murphy dmur...@ti.com
---
board/ti/panda/panda.c | 71 +---
include/configs/omap4_common.h |2 +
2 files changed, 68 insertions(+), 5 deletions(-)
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 2bbe392..65a6e14 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -37,6 +37,11 @@
#endif
#define PANDA_ULPI_PHY_TYPE_GPIO 182
+#define PANDA_BOARD_ID_1_GPIO 101
+#define PANDA_ES_BOARD_ID_1_GPIO48
+#define PANDA_BOARD_ID_2_GPIO 171
+#define PANDA_ES_BOARD_ID_3_GPIO 3
+#define PANDA_ES_BOARD_ID_4_GPIO 2
DECLARE_GLOBAL_DATA_PTR;
@@ -66,6 +71,66 @@ int board_eth_init(bd_t *bis)
return 0;
}
+/*
+* Routine: get_board_revision
+* Description: Detect if we are running on a panda revision A1-A6,
+* or an ES panda board. This can be done by reading
+* the level of GPIOs and checking the processor revisions.
+* This should result in:
+* Panda 4430:
+* GPIO171, GPIO101, GPIO182: 0 1 1 = A1-A5
+* GPIO171, GPIO101, GPIO182: 1 0 1 = A6
+* Panda ES:
+* GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 = B1/B2
+* GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 = B3
+*/
+int get_board_revision(void)
+{
+ int board_id0, board_id1, board_id2;
+ int board_id3, board_id4;
+ int board_id;
+
+ int processor_rev = omap_revision();
+
+ /* Setup the mux for the common board ID pins */
+ writew((IEN | M3), CONTROL_PADCONF_CORE + UNIPRO_TX0); /* gpio 171 */
+ writew((IEN | M3), CONTROL_PADCONF_CORE + FREF_CLK2_OUT); /* gpio 182 */
+
+ board_id0 = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
+ board_id2 = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
+
+ if (processor_rev = OMAP4460_ES1_0
+ processor_rev = OMAP4460_ES1_1) {
+ /* Setup the mux for the ES specific board ID pins */
+ writew((IEN | M3), CONTROL_PADCONF_CORE + GPMC_A24); /* gpio
101 */
+ writew((IEN | M3), CONTROL_PADCONF_CORE + UNIPRO_RY0); /* gpio
2 */
+ writew((IEN | M3), CONTROL_PADCONF_CORE + UNIPRO_RX1); /* gpio
3 */
+
+ board_id1 = gpio_get_value(PANDA_ES_BOARD_ID_1_GPIO);
+ board_id3 = gpio_get_value(PANDA_ES_BOARD_ID_3_GPIO);
+ board_id4 = gpio_get_value(PANDA_ES_BOARD_ID_4_GPIO);
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ setenv(board_name, strcat(CONFIG_SYS_BOARD, -es));
+#endif
+ board_id = ((board_id4 4) | (board_id3 3) | (board_id2
2) |
+ (board_id1 1) | (board_id0));
+ } else {
+ /* Setup the mux for the Ax specific board ID pins */
+ writew((IEN | M3), CONTROL_PADCONF_CORE + FREF_CLK2_OUT); /*
gpio 101 */
+
+ board_id1 = gpio_get_value(PANDA_BOARD_ID_1_GPIO);
+ board_id = ((board_id2 2) | (board_id1 1) | (board_id0));
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ if ((board_id = 0x3) (processor_rev ==
OMAP4430_ES2_3))
+ setenv(board_name, strcat(CONFIG_SYS_BOARD,
-a4));
+#endif
+ }
+
+ return board_id;
+}
+
/**
* @brief misc_init_r - Configure Panda board specific configurations
* such as power configurations, ethernet initialization as phase2 of
@@ -82,11 +147,7 @@ int misc_init_r(void)
if (omap_revision() == OMAP4430_ES1_0)
return 0;
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- if (omap_revision() = OMAP4460_ES1_0 ||
- omap_revision() = OMAP4460_ES1_1)
- setenv(board_name, strcat(CONFIG_SYS_BOARD, -es));
-#endif
+ get_board_revision();
gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index d6448b0..cf41d9c 100644
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -181,6 +181,8 @@
setenv fdtfile omap4-sdp.dtb; fi; \
if test $board_name = panda; then \
setenv fdtfile omap4-panda.dtb; fi; \
+ if test $board_name = panda-a4; then \
+
Re: [U-Boot] [PATCH v6 5/5] mpc85xx: Add gdsys ControlCenter Digital board
Dear dirk.eib...@gdsys.cc,
In message 1371024486-15629-6-git-send-email-dirk.eib...@gdsys.cc you wrote:
The gdsys ControlCenter Digital board is based on a Freescale P1022 QorIQ SOC.
It boots from SPI-Flash but can be configured to boot from SD-card for
factory programming and testing.
On board peripherals include:
diff --git a/.checkpatch.conf b/.checkpatch.conf
index d88af57..ef9b595 100644
--- a/.checkpatch.conf
+++ b/.checkpatch.conf
@@ -2,10 +2,10 @@
--no-tree
# Temporary for false positive in checkpatch
---ignore COMPLEX_MACRO
+#--ignore COMPLEX_MACRO
# For CONFIG_SYS_I2C_NOPROBES
---ignore MULTISTATEMENT_MACRO_USE_DO_WHILE
+#--ignore MULTISTATEMENT_MACRO_USE_DO_WHILE
NAK. Please do not mess with public settings.
+static void *compute_and(void *_dst, const void *_src, size_t n)
+{
+ uint8_t *dst = _dst;
+ const uint8_t *src = _src;
+ size_t i;
+ for (i = n; i-- 0; )
+ *dst++ = *src++;
+ return _dst;
+}
Here and everywhere else: please separate declarations and code by
inserting a blank line.
+ for (i = 0; i 20; ++i)
+ if (src_reg-digest[i])
+ return NULL;
This muti-line statement requires braces.
+enum {
+ REG_REFLECTION_LOW = 0x,
+ REG_VERSIONS = 0x0004,
+ REG_FPGA_VERSION = 0x0008,
+ REG_FEATURES = 0x000C,
+ REG_TOP_INTERRUPT = 0x0010,
+ REG_TOP_INTERRUPT_SET = 0x0014,
+ REG_TOP_INTERRUPT_CLEAR = 0x0018,
+ REG_STATUS = 0x001C,
+ REG_CONTROL = 0x0020,
+ REG_TESTMEM1 = 0x100,
+ REG_DMA_WRITE_CONTROL = 0x0200,
+ REG_DMA_WRITE_BASE_ADDRESS_LOW = 0x0204,
+ REG_DMA_WRITE_BASE_ADDRESS_HIGH = 0x0208,
+ REG_DMA_WRITE_LENGTH = 0x020C,
+ REG_DMA_WRITE_HEAD = 0x0210,
+ REG_DMA_WRITE_TAIL = 0x0214,
+ REG_DMA_WRITE_MIN_INT_INTERVAL = 0x0218,
+ REG_DMA_WRITE_MAX_PACKETS_INT_INTERVAL = 0x021C,
+ REG_DMA_READ_CONTROL = 0x0300,
+ REG_DMA_READ_BASE_ADDRESS_LOW = 0x0304,
+ REG_DMA_READ_BASE_ADDRESS_HIGH = 0x0308,
+ REG_DMA_READ_LENGTH = 0x030C,
+ REG_DMA_READ_HEAD = 0x0310,
+ REG_DMA_READ_TAIL = 0x0314,
+ REG_DMA_READ_MIN_INT_INTERVAL = 0x0318,
+ REG_DMA_READ_MAX_PACKETS_INT_INTERVAL = 0x031C,
+};
This looks very much like register offsets to me, that should rather
be represented by a C struct ?
--- a/boards.cfg
+++ b/boards.cfg
@@ -904,6 +904,13 @@ BSC9132QDS_SDCARD_DDRCLK100 powerpc mpc85xx
bsc9132qds freesca
BSC9132QDS_SDCARD_DDRCLK133 powerpc mpc85xx bsc9132qds
freescale - BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133
BSC9132QDS_SPIFLASH_DDRCLK100 powerpcmpc85xx bsc9132qds
freescale - BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100
BSC9132QDS_SPIFLASH_DDRCLK133 powerpcmpc85xx bsc9132qds
freescale - BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133
+controlcenterd_36BIT_SDCARD powerpc mpc85xx p1022
gdsys - controlcenterd:36BIT,SDCARD
+controlcenterd_36BIT_SDCARD_DEVELOP powerpc mpc85xx p1022
gdsys - controlcenterd:36BIT,SDCARD,DEVELOP
+controlcenterd_36BIT_SPIFLASH powerpc mpc85xx p1022
gdsys - controlcenterd:36BIT,SPIFLASH
+controlcenterd_SDCARD powerpc mpc85xx p1022
gdsys - controlcenterd:SDCARD
+controlcenterd_SPIFLASH powerpc mpc85xx p1022
gdsys - controlcenterd:SPIFLASH
+controlcenterd_TRAILBLAZER powerpc mpc85xx p1022
gdsys - controlcenterd:TRAILBLAZER,SPIFLASH
+controlcenterd_TRAILBLAZER_DEVELOP powerpc mpc85xx p1022
gdsys - controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP
stxgp3 powerpc mpc85xx stxgp3 stx
stxssa powerpc mpc85xx stxssa stx
- stxssa
stxssa_4Mpowerpc mpc85xx stxssa stx
- stxssa:STXSSA_4M
Is it really, _really_ necessary to add 7 entries just for a single
board? Please decide which configurations you really need, and omit
the rest.
...
+#define CONFIG_HDBOOT\
+ setenv bootargs root=/dev/$bdev rw\
+ console=$consoledev,$baudrate $othbootargs $videobootargs;\
+ tftp $loadaddr $bootfile; \
+ tftp $fdtaddr $fdtfile; \
+ bootm $loadaddr - $fdtaddr
Should this definition (and the follwing ones) not rather be NUL
terminated?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel
HRB 165235 Munich, Office:
Re: [U-Boot] U-boot for 64bit ARMv8
Hi Tom, On Wed, 12 Jun 2013 13:47:18 -0400, Tom Rini tr...@ti.com wrote: On Wed, Jun 12, 2013 at 06:54:54PM +0200, Albert ARIBAUD wrote: Hi Tom, On Wed, 12 Jun 2013 12:33:39 -0400, Tom Rini tr...@ti.com wrote: On Wed, Jun 12, 2013 at 06:10:06AM -0700, Richard Schmitt wrote: Is anyone considering porting/supporting uboot for ARMv8. ?Our initial investigation of boot loader support for ARMv8 indicates that the only boot loader currently being targeted is UEFI. ? The decisions we need to make are: - Do we move to UEFI on ARM? - Can we leverage someone else's enablement of ARMv8? - Do we provide our own enablement of ARMv8? Any opinions? The general push from ARM Ltd is to use UEFI. I would strongly suspect that there are U-Boot forks that companies that have announced they are doing ARMv8 chips have something as a stop-gap until they have the functionality they want in uEFI. I am quite open to ARMv8 support being added to U-Boot and addressing the concerns companies may have. Sometimes it seems like GPLv2+ makes people think Project will be moving to GPLv3, RUN AWAY! when all it really means is Project is GPLv2+, will evaluate the appropriateness of later versions. This is not specific to 64-Bit ARM support, though. GPLv2+ has been there for very long. Aren't companies educated by now? (I am quite open to helping spread education, anyway) Indeed, it applies to the project as a whole. I have however, gotten some private feedback that to me says that there are companies out there afraid that because we retain our + we're going to switch to GPLv3 any minute, rather than keeping our options open, should some future GPL provide a compromise both developers, companies and regular consumers can live with. Maybe some FAQ entry about the licence [version] on the Denx project might make things easier. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v4] spi: add Faraday FTSPI010 SPI controller support
Hi,
Few comments, please get back your inputs.
Use commit header as spi: ftssp010_spi:
On 07-05-2013 12:04, Kuo-Jung Su wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FTSSP010 is a multi-function controller
which supports I2S/SPI/SSP/AC97/SPDIF. However This
patch implements only the SPI mode.
NOTE:
The DMA and CS/Clock control logic has been altered
since hardware revision 1.19.0. So this patch
would first detects the revision id of the underlying
chip, and then switch to the corresponding software
control routines.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Tom Rini tr...@ti.com
---
Changes for v4:
- Coding Style cleanup.
- Make it a separate patch, rather then a part of
Faraday A36x patch series
- Use macro constants for timeout control
Changes for v3:
- Coding Style cleanup.
- Drop macros for wirtel()/readl(), call them directly.
- Always insert a blank line between declarations and code.
- Replace all the infinite wait loop with a timeout.
- Add '__iomem' to all the declaration of HW register pointers.
Changes for v2:
- Coding Style cleanup.
- Use readl(), writel(), clrsetbits_le32() to replace REG() macros.
- Use structure based hardware registers to replace the macro constants.
- Replace BIT() with BIT_MASK().
drivers/spi/Makefile|1 +
drivers/spi/ftssp010_spi.c | 385 +++
drivers/spi/ftssp010_spi.h | 86 ++
include/faraday/ftgpio010.h | 25 +++
4 files changed, 497 insertions(+)
create mode 100644 drivers/spi/ftssp010_spi.c
create mode 100644 drivers/spi/ftssp010_spi.h
create mode 100644 include/faraday/ftgpio010.h
--
1.7.9.5
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d08609e..947d60e 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
COBJS-$(CONFIG_CF_SPI) += cf_spi.o
COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+COBJS-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
Place into in alphabetic order, to make sure some kind of coding style.
COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
COBJS-$(CONFIG_ICH_SPI) += ich.o
COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
diff --git a/drivers/spi/ftssp010_spi.c b/drivers/spi/ftssp010_spi.c
new file mode 100644
index 000..d401ecc
--- /dev/null
+++ b/drivers/spi/ftssp010_spi.c
@@ -0,0 +1,385 @@
+/*
+ * Faraday Multi-function Controller - SPI Mode
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su dant...@faraday-tech.com
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
Little bit uneasy with the above license note, any reason for this GPL
w.r.t your company style. refer license note on drivers/spi/exynos_spi.c
+
+#include common.h
+#include asm/io.h
+#include spi.h
+#include malloc.h
+#include faraday/ftgpio010.h
Does this include file is an arch' specific, means struct ftgpio010_regs
is used by some other drivers on ur board?
+#include ftssp010_spi.h
Please don't use extra include file, use the same structure's in driver
it self, IMHO.
+
+#define CFG_PIO_TIMEOUT (CONFIG_SYS_HZ 3) /* 125 ms */
+#define CFG_CS_TIMEOUT (CONFIG_SYS_HZ 2) /* 250 ms */
+
- TAG+
+struct ftssp010_chip {
+ void __iomem *regs;
+ uint32_t fifo;
+ uint32_t rev;
+ uint32_t div;
+ uint32_t mode;
+
+ struct {
+ void __iomem *regs;
+ uint32_t pin;
+ } gpio;
+};
+
+static struct ftssp010_chip chip_list[] = {
+#ifdef CONFIG_FTSSP010_BASE
+ {
+ .regs = (void __iomem *)CONFIG_FTSSP010_BASE,
+# ifdef CONFIG_FTSSP010_GPIO_BASE
+ .gpio = {
+ (void __iomem *)CONFIG_FTSSP010_GPIO_BASE,
+ CONFIG_FTSSP010_GPIO_PIN
+ },
+# endif
+ },
+#endif /* #ifdef CONFIG_FTSSP010_BASE */
+#ifdef CONFIG_FTSSP010_BASE1
+ { .regs = (void __iomem *)CONFIG_FTSSP010_BASE1, },
+# ifdef CONFIG_FTSSP010_GPIO_BASE1
+ .gpio = {
+ (void __iomem *)CONFIG_FTSSP010_GPIO_BASE1,
+ CONFIG_FTSSP010_GPIO_PIN1
+ },
+# endif
+#endif
+#ifdef CONFIG_FTSSP010_BASE2
+ { .regs = (void __iomem *)CONFIG_FTSSP010_BASE2, },
+# ifdef CONFIG_FTSSP010_GPIO_BASE2
+ .gpio = {
+ (void __iomem *)CONFIG_FTSSP010_GPIO_BASE2,
+ CONFIG_FTSSP010_GPIO_PIN2
+ },
+# endif
+#endif
+#ifdef CONFIG_FTSSP010_BASE3
+ { .regs = (void __iomem *)CONFIG_FTSSP010_BASE3, },
+# ifdef CONFIG_FTSSP010_GPIO_BASE3
+ .gpio = {
+ (void __iomem *)CONFIG_FTSSP010_GPIO_BASE3,
+ CONFIG_FTSSP010_GPIO_PIN3
+ },
+# endif
+#endif
+};
Re: [U-Boot] [PATCH v4 05/10] SPI: Add Dove SPI driver
Hi,
On 03-06-2013 23:50, Jagan Teki wrote:
Hi,
Looks ok to me as per coding style after a quick look.
On Mon, May 27, 2013 at 12:06 AM, Sascha Silbe t-ub...@infra-silbe.de wrote:
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
This adds an SPI driver for Marvell Dove SoCs. This driver is taken
from kirkwood_spi but removes mpp configuration as dove has dedicated
spi pins.
As a future clean-up step, the code for orion5x, kirkwood and dove
could be merged, with MPP configuration being be handled as part of
cpu/board-specific setup.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de
---
v3-v4: renamed to dove, adjusted description, removed unused
variable, made checkpatch clean
drivers/spi/Makefile | 1 +
drivers/spi/dove_spi.c | 212 +
2 files changed, 213 insertions(+)
create mode 100644 drivers/spi/dove_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d08609e..62ad970 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
COBJS-$(CONFIG_CF_SPI) += cf_spi.o
COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+COBJS-$(CONFIG_DOVE_SPI) += dove_spi.o
COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
COBJS-$(CONFIG_ICH_SPI) += ich.o
COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
diff --git a/drivers/spi/dove_spi.c b/drivers/spi/dove_spi.c
new file mode 100644
index 000..c61ba89
--- /dev/null
+++ b/drivers/spi/dove_spi.c
@@ -0,0 +1,212 @@
+/*
+ * Marvell Dove SoCs common spi driver
+ *
+ * Sebastian Hesselbarth sebastian.hesselba...@gmail.com
+ * based on kirkwood_spi.c written by
+ * Prafulla Wadaskar prafu...@marvell.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/arch/config.h
+
+/* SPI Registers on dove SOC */
+struct dovespi_registers {
+ u32 ctrl; /* 0x00 */
+ u32 cfg;/* 0x04 */
+ u32 dout; /* 0x08 */
+ u32 din;/* 0x0c */
+ u32 irq_cause; /* 0x10 */
+ u32 irq_mask; /* 0x14 */
+};
+
+#define DOVESPI_CLKPRESCL_MASK 0x1f
+#define DOVESPI_CLKPRESCL_MIN 0x12
+#define DOVESPI_CSN_ACT1 /* Activates serial memory interface */
+#define DOVESPI_SMEMRDY(1 1) /* SerMem Data xfer ready */
+#define DOVESPI_IRQUNMASK 1 /* unmask SPI interrupt */
+#define DOVESPI_IRQMASK0 /* mask SPI interrupt */
+#define DOVESPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */
+#define DOVESPI_XFERLEN_1BYTE 0
+#define DOVESPI_XFERLEN_2BYTE (1 5)
+#define DOVESPI_XFERLEN_MASK (1 5)
+#define DOVESPI_ADRLEN_1BYTE 0
+#define DOVESPI_ADRLEN_2BYTE (1 8)
+#define DOVESPI_ADRLEN_3BYTE (2 8)
+#define DOVESPI_ADRLEN_4BYTE (3 8)
+#define DOVESPI_ADRLEN_MASK(3 8)
+#define DOVESPI_TIMEOUT1
+
+static struct dovespi_registers *spireg =
+ (struct dovespi_registers *)DOVE_SPI_BASE;
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct spi_slave *slave;
+ u32 data;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
Done use the below tag code instead go for spi_alloc_slave()
see the sample code on drivers/spi/exynos_spi.c
--- TAG+
+ slave = malloc(sizeof(struct spi_slave));
+ if (!slave)
+ return NULL;
+
+ slave-bus = bus;
+ slave-cs = cs;
+
- TAG-
+ writel(~DOVESPI_CSN_ACT | DOVESPI_SMEMRDY, spireg-ctrl);
+
+ /* calculate spi clock prescaller using max_hz */
+ data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
+ data = data DOVESPI_CLKPRESCL_MIN ? DOVESPI_CLKPRESCL_MIN : data;
+ data = data DOVESPI_CLKPRESCL_MASK ? DOVESPI_CLKPRESCL_MASK : data;
+
+ /* program spi clock prescaller using max_hz */
+ writel(DOVESPI_ADRLEN_3BYTE | data, spireg-cfg);
+ debug(data = 0x%08x\n, data);
+
+ writel(DOVESPI_SMEMRDIRQ,
Re: [U-Boot] FSL SPI read fix.
Hi,
Can you please update the commit header and logic of the code
w.r.t current master tree.
also please use proper commit body.
--
Thanks,
Jagan.
On 27-09-2012 02:37, Dale Smith wrote:
The fsl spi engine is non functional when reading from a device. This
patch fixes it.
Note that none of the other spi interfaces parse through the
datastream looking for 0x0b bytes.
-Dale
}
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index a1ebd33..737719b 100644
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -291,17 +291,10 @@ int spi_xfer(struct spi_slave *slave, unsigned
int bitlen, const void *data_out,
debug(***spi_xfer:...%08x readed\n, tmpdin);
}
}
- if (data_in) {
- memcpy(data_in, buffer + 2 * cmd_len, tran_len);
- if (*buffer == 0x0b) {
- data_in += tran_len;
- data_len -= tran_len;
- *(int *)buffer += tran_len;
- }
- }
spi_cs_deactivate(slave);
}
-
+ if (data_in)
+ memcpy(data_in, buffer + rx_offset, len);
free(buffer);
return 0;
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] spi: armada100_spi: Remove unnecessary NULL test for dout and din
On 12-06-2013 15:49, Ajay Bhargav wrote: - Marek Vasut ma...@denx.de wrote: Dear Simon Glass, On Tue, Jun 11, 2013 at 6:57 AM, Axel Lin axel@ingics.com wrote: Signed-off-by: Axel Lin axel@ingics.com Reviewed-by: Simon Glass s...@chromium.org Reviewed-by: Marek Vasut ma...@denx.de Acked-by: Ajay Bhargav ajay.bhar...@einfochips.com Regards, Ajay Bhargav - Notice: This message has been scanned by Trend Micro Mail Security scanner and is believed to be clean - Reviewed-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com -- Thanks, Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 05/10] SPI: Add Dove SPI driver
On 06/12/2013 08:58 PM, Jagan Teki wrote: On 03-06-2013 23:50, Jagan Teki wrote: Looks ok to me as per coding style after a quick look. On Mon, May 27, 2013 at 12:06 AM, Sascha Silbe t-ub...@infra-silbe.de wrote: From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com This adds an SPI driver for Marvell Dove SoCs. This driver is taken from kirkwood_spi but removes mpp configuration as dove has dedicated spi pins. As a future clean-up step, the code for orion5x, kirkwood and dove could be merged, with MPP configuration being be handled as part of cpu/board-specific setup. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de --- v3-v4: renamed to dove, adjusted description, removed unused variable, made checkpatch clean [...] Any update on this. Is any of you even listening? Please do _not_ name it after Dove! It is compatible with _at least_ Kirkwood, Orion5x and MV78x00. Now is the chance to have a common name or you will end up with either non-sense naming or four copies of that very driver. Originally, it was named after the Linux group of SoCs compatible with Dove (orion-spi), IIRC Prafulla suggested mv-spi. Sebastian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 05/10] SPI: Add Dove SPI driver
On Thu, Jun 13, 2013 at 12:56 AM, Sebastian Hesselbarth sebastian.hesselba...@gmail.com wrote: On 06/12/2013 08:58 PM, Jagan Teki wrote: On 03-06-2013 23:50, Jagan Teki wrote: Looks ok to me as per coding style after a quick look. On Mon, May 27, 2013 at 12:06 AM, Sascha Silbe t-ub...@infra-silbe.de wrote: From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com This adds an SPI driver for Marvell Dove SoCs. This driver is taken from kirkwood_spi but removes mpp configuration as dove has dedicated spi pins. As a future clean-up step, the code for orion5x, kirkwood and dove could be merged, with MPP configuration being be handled as part of cpu/board-specific setup. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de --- v3-v4: renamed to dove, adjusted description, removed unused variable, made checkpatch clean [...] Any update on this. Is any of you even listening? Please do _not_ name it after Dove! It is compatible with _at least_ Kirkwood, Orion5x and MV78x00. Now is the chance to have a common name or you will end up with either non-sense naming or four copies of that very driver. Originally, it was named after the Linux group of SoCs compatible with Dove (orion-spi), IIRC Prafulla suggested mv-spi. Sebastian Common to use means orion_spi instead of Dove? -- Thanks, Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 05/10] SPI: Add Dove SPI driver
On 06/12/2013 09:30 PM, Jagan Teki wrote: On Thu, Jun 13, 2013 at 12:56 AM, Sebastian Hesselbarth sebastian.hesselba...@gmail.com wrote: Is any of you even listening? Please do _not_ name it after Dove! It is compatible with _at least_ Kirkwood, Orion5x and MV78x00. Now is the chance to have a common name or you will end up with either non-sense naming or four copies of that very driver. Originally, it was named after the Linux group of SoCs compatible with Dove (orion-spi), IIRC Prafulla suggested mv-spi. Common to use means orion_spi instead of Dove? Either orion_spi as it was named originally, or mv_spi as Prafulla suggested. Then move mpp (pinctrl) from kirkwood_spi to corresponding boards, switch to orion_/mv_spi, and remove kirkwood_spi. I suggest orion_spi, but Prafulla had his word so it should be mv_spi I guess. Sebastian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] exynos5250: remove redundant SPI and PMIC related configs
Hi, Can you separate the PMIC and SPI changes into two different patches. Also may i know why you remove the SPI from configs, does it defined some where or you don't want SPI at all.? -- Thanks, Jagan. On 07-06-2013 17:25, Inderpal Singh wrote: They have been defined once already. Hence remove the redundant definitions. Signed-off-by: Inderpal Singh inderpal.si...@linaro.org --- v1 was posted as the first patch of [1] Changes in v2: - split from the patchset at [1] - removed redundant configs for PMIC - rebased to latest u-boot-samsung master branch [1] http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/157101 include/configs/exynos5250-dt.h | 26 -- 1 file changed, 26 deletions(-) diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 62b83d4..03b07b2 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -246,11 +246,6 @@ #define CONFIG_SYS_I2C_SLAVE0x0 #define CONFIG_I2C_EDID -/* PMIC */ -#define CONFIG_PMIC -#define CONFIG_PMIC_I2C -#define CONFIG_PMIC_MAX77686 - /* SPI */ #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_SPI_FLASH @@ -278,27 +273,6 @@ #define CONFIG_POWER_I2C #define CONFIG_POWER_MAX77686 -/* SPI */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SPI_FLASH - -#ifdef CONFIG_SPI_FLASH -#define CONFIG_EXYNOS_SPI -#define CONFIG_CMD_SF -#define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_SF_DEFAULT_SPEED5000 -#define EXYNOS5_SPI_NUM_CONTROLLERS5 -#endif - -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_MODESPI_MODE_0 -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -#define CONFIG_ENV_SPI_BUS 1 -#define CONFIG_ENV_SPI_MAX_HZ 5000 -#endif - /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET #define CONFIG_SMC911X ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2 V3] spi: exynos: Support a delay after deactivate
Hi,
On 30-05-2013 10:49, Rajeshwari Shinde wrote:
For devices that need some time to react after a spi transaction
finishes, add the ability to set a delay.
Implement this as a delay on the first/next transaction to avoid
any delay in the fairly common case where a SPI transaction is
followed by other processing.
Based on:
[U-Boot] [PATCH 0/2 V5] spi: Enable SPI_PREAMBLE Mode
Please use the below format for referring previous commits
ex:
PREVIOUS_COMMIT_HEAD
(sha1: PREVIOUS_COMMIT_ID)
in this case
spi: exynos: Support SPI_PREAMBLE mode
(sha1: e4eaef8910df805d511b1cb9b2caafa7d2827fdc)
Signed-off-by: Simon Glass s...@chromium.org
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Changes in V2:
- None.
Changes in V3:
- Rebased on [PATCH 0/2 V5] spi: Enable SPI_PREAMBLE Mode
drivers/spi/exynos_spi.c | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
index 01378d0..03cf503 100644
--- a/drivers/spi/exynos_spi.c
+++ b/drivers/spi/exynos_spi.c
@@ -38,6 +38,7 @@ struct spi_bus {
struct exynos_spi *regs;
int inited; /* 1 if this bus is ready for use */
int node;
+ uint deactivate_delay_us; /* Delay to wait after deactivate */
};
/* A list of spi buses that we know about */
@@ -52,6 +53,8 @@ struct exynos_spi_slave {
enum periph_id periph_id; /* Peripheral ID for this device */
unsigned int fifo_size;
int skip_preamble;
+ struct spi_bus *bus;/* Pointer to our SPI bus info */
+ ulong last_transaction_us; /* Time of last transaction end */
};
static struct spi_bus *spi_get_bus(unsigned dev_index)
@@ -97,6 +100,7 @@ struct spi_slave *spi_setup_slave(unsigned int busnum,
unsigned int cs,
}
bus = spi_bus[busnum];
+ spi_slave-bus = bus;
spi_slave-regs = bus-regs;
spi_slave-mode = mode;
spi_slave-periph_id = bus-periph_id;
@@ -107,6 +111,7 @@ struct spi_slave *spi_setup_slave(unsigned int busnum,
unsigned int cs,
spi_slave-fifo_size = 256;
spi_slave-skip_preamble = 0;
+ spi_slave-last_transaction_us = timer_get_us();
spi_slave-freq = bus-frequency;
if (max_hz)
@@ -371,9 +376,21 @@ void spi_cs_activate(struct spi_slave *slave)
{
struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
+ /* If it's too soon to do another transaction, wait */
+ if (spi_slave-bus-deactivate_delay_us
+ spi_slave-last_transaction_us) {
+ ulong delay_us; /* The delay completed so far */
+ delay_us = timer_get_us() - spi_slave-last_transaction_us;
+ if (delay_us spi_slave-bus-deactivate_delay_us)
+ udelay(spi_slave-bus-deactivate_delay_us - delay_us);
+ }
Add one space
clrbits_le32(spi_slave-regs-cs_reg, SPI_SLAVE_SIG_INACT);
debug(Activate CS, bus %d\n, spi_slave-slave.bus);
spi_slave-skip_preamble = spi_slave-mode SPI_PREAMBLE;
+
+ /* Remember time of this transaction so we can honour the bus delay */
+ if (spi_slave-bus-deactivate_delay_us)
+ spi_slave-last_transaction_us = timer_get_us();
}
/**
@@ -423,6 +440,8 @@ static int spi_get_config(const void *blob, int node,
struct spi_bus *bus)
/* Use 500KHz as a suitable default */
bus-frequency = fdtdec_get_int(blob, node, spi-max-frequency,
50);
+ bus-deactivate_delay_us = fdtdec_get_int(blob, node,
+ spi-deactivate-delay, 0);
return 0;
}
Was this tested, usually what is the max deactivate delay?
In this case your are passing through dts is it?
Thanks,
Jagan.
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Re: [U-Boot] [PATCH V2] spi: exynos: Minimise access to SPI FIFO level
On 30-05-2013 10:57, Rajeshwari Shinde wrote:
Accessing SPI registers is slow, but access to the FIFO level register
in particular seems to be extraordinarily expensive (I measure up to
600ns). Perhaps it is required to synchronise with the SPI byte output
logic which might run at 1/8th of the 40MHz SPI speed (just a guess).
Reduce access to this register by filling up and emptying FIFOs
more completely, rather than just one word each time around the inner
loop.
Since the rxfifo value will now likely be much greater that what we read
before we fill the txfifo, we only fill the txfifo halfway. This is
because if the txfifo is empty, but the rxfifo has data in it, then writing
too much data to the txfifo may overflow the rxfifo as data arrives.
This speeds up SPI flash reading from about 1MB/s to about 2MB/s on snow.
Based on [PATCH 0/2 V3] exynos: Support a delay after deactivate for SPI
Please use the format i suggested on earlier patch
http://patchwork.ozlabs.org/patch/247451/
Thanks,
Jagan.
Signed-off-by: Simon Glass s...@chromium.org
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Changes in V2:
- Rebased on [PATCH 0/2 V5] spi: Enable SPI_PREAMBLE Mode
drivers/spi/exynos_spi.c | 27 +++
1 files changed, 15 insertions(+), 12 deletions(-)
diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
index deb32bd..bcca3d6 100644
--- a/drivers/spi/exynos_spi.c
+++ b/drivers/spi/exynos_spi.c
@@ -259,24 +259,27 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave,
int todo,
/* Keep the fifos full/empty. */
spi_get_fifo_levels(regs, rx_lvl, tx_lvl);
- if (tx_lvl spi_slave-fifo_size out_bytes) {
+ while (tx_lvl spi_slave-fifo_size/2 out_bytes) {
temp = txp ? *txp++ : 0xff;
writel(temp, regs-tx_data);
out_bytes--;
+ tx_lvl++;
}
if (rx_lvl 0) {
- temp = readl(regs-rx_data);
- if (spi_slave-skip_preamble) {
- if (temp == SPI_PREAMBLE_END_BYTE) {
- spi_slave-skip_preamble = 0;
- stopping = 0;
+ while (rx_lvl 0) {
+ temp = readl(regs-rx_data);
+ if (spi_slave-skip_preamble) {
+ if (temp == SPI_PREAMBLE_END_BYTE) {
+ spi_slave-skip_preamble = 0;
+ stopping = 0;
+ }
+ } else {
+ if (rxp || stopping)
+ *rxp++ = temp;
+ in_bytes--;
}
- } else {
- if (rxp || stopping)
- *rxp++ = temp;
- in_bytes--;
- }
- toread--;
+ toread--;
+ rx_lvl--;
} else if (!toread) {
/*
* We have run out of input data, but haven't read
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Re: [U-Boot] [STATUS] ARM - pending PRs or patches for -rc1
The following changes since commit 58bb8f5f6138fa56875574a709f5af98c600c2a9: cosmetic: arm: fix comments in arch/arm/lib/crt0.S (2013-06-10 21:24:22 +0200) are available in the git repository at: git://git.denx.de/u-boot-pxa.git master for you to fetch changes up to 847e6693ccb529bf8346db62876f38f0c4e04ade: arm: pxa: config option for PXA270 turbo mode (2013-06-12 22:24:12 +0200) Sergey Yanovich (2): arm: pxa: Add support for ICP DAS LP-8x4x arm: pxa: config option for PXA270 turbo mode MAINTAINERS |4 +++ arch/arm/cpu/pxa/pxa2xx.c|2 +- board/icpdas/lp8x4x/Makefile | 41 +++ board/icpdas/lp8x4x/lp8x4x.c | 147 boards.cfg |1 + include/configs/lp8x4x.h | 262 ++ 6 files changed, 456 insertions(+), 1 deletion(-) create mode 100644 board/icpdas/lp8x4x/Makefile create mode 100644 board/icpdas/lp8x4x/lp8x4x.c create mode 100644 include/configs/lp8x4x.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PULL] u-boot-usb/master
The following changes since commit e1208c2fe5e07f9a248cfbf9bbb212aa34ad2806: MIPS: asm/errno.h: switch to asm-generic/errno.h (2013-06-08 23:10:10 +0200) are available in the git repository at: git://git.denx.de/u-boot-usb.git master for you to fetch changes up to c67b0e42a59c7ef15495bfde006398abaf2f562f: usb, composite: after unregister gadget driver set composite to NULL (2013-06-12 22:22:52 +0200) Heiko Schocher (1): usb, composite: after unregister gadget driver set composite to NULL Julius Werner (1): usb: asix: Move software resets to basic_init Kuo-Jung Su (5): usb: ehci: prevent bad PORTSC register access usb: ehci: add weak-aliased function for PORTSC usb: hub: make minimum power-on delay configurable usb: ehci: add Faraday USB 2.0 EHCI support usb: gadget: add Faraday FOTG210 USB gadget support Simon Glass (1): usb: Correct CLEAR_FEATURE code in ehci-hcd Stephen Warren (1): usb: ehci: add missing cache managment Vincent Palatin (2): usb: properly re-initialize the USB keyboard. usb: workaround non-working keyboards. Vivek Gautam (2): usb: Use get_unaligned() in usb_endpoint_maxp() for wMaxPacketSize usb: gadget: Use unaligned access for wMaxPacketSize README |3 + common/usb_hub.c| 15 ++- common/usb_kbd.c| 10 +- drivers/usb/eth/asix.c | 40 +++--- drivers/usb/gadget/Makefile |1 + drivers/usb/gadget/composite.c |1 + drivers/usb/gadget/f_mass_storage.c |3 +- drivers/usb/gadget/fotg210.c| 948 +++ drivers/usb/gadget/gadget_chips.h |8 ++ drivers/usb/gadget/pxa25x_udc.c | 13 +- drivers/usb/host/Makefile |1 + drivers/usb/host/ehci-faraday.c | 148 + drivers/usb/host/ehci-hcd.c | 74 +-- include/linux/usb/ch9.h |3 +- include/usb/fotg210.h | 364 include/usb/fusbh200.h | 61 + 16 files changed, 1648 insertions(+), 45 deletions(-) create mode 100644 drivers/usb/gadget/fotg210.c create mode 100644 drivers/usb/host/ehci-faraday.c create mode 100644 include/usb/fotg210.h create mode 100644 include/usb/fusbh200.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] PPC: 74xx/7xx: Pull request
On Tue, Jun 11, 2013 at 11:25:58PM +0200, Wolfgang Denk wrote: Dear Tom, The following changes since commit e1208c2fe5e07f9a248cfbf9bbb212aa34ad2806: MIPS: asm/errno.h: switch to asm-generic/errno.h (2013-06-08 23:10:10 +0200) are available in the git repository at: git://git.denx.de/u-boot-74xx-7xx master for you to fetch changes up to 8cf695537f55f6574d2a85ae4ddc5b9c9f0d26b3: ppc: ppmc7xx: Fix possible out-of-bound access (2013-06-11 22:11:38 +0200) Marek Vasut (1): ppc: ppmc7xx: Fix possible out-of-bound access include/configs/ppmc7xx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] PPC: MPC8xx / MPC82xx: Pull request
On Tue, Jun 11, 2013 at 11:25:57PM +0200, Wolfgang Denk wrote: Dear Tom, The following changes since commit e1208c2fe5e07f9a248cfbf9bbb212aa34ad2806: MIPS: asm/errno.h: switch to asm-generic/errno.h (2013-06-08 23:10:10 +0200) are available in the git repository at: git://git.denx.de/u-boot-mpc82xx master for you to fetch changes up to a166fbca20e40937bf37cc18c389f68e995c1821: powerpc: fix 8xx and 82xx type-punning warnings with GCC 4.7 (2013-06-11 22:01:45 +0200) Scott Wood (1): powerpc: fix 8xx and 82xx type-punning warnings with GCC 4.7 arch/powerpc/cpu/mpc8260/commproc.c| 2 +- arch/powerpc/cpu/mpc8260/cpu.c | 2 +- arch/powerpc/cpu/mpc8260/i2c.c | 8 arch/powerpc/cpu/mpc8260/serial_smc.c | 4 ++-- arch/powerpc/cpu/mpc8260/spi.c | 2 +- arch/powerpc/cpu/mpc8xx/cpu.c | 12 arch/powerpc/include/asm/8xx_immap.h | 7 ++- arch/powerpc/include/asm/immap_8260.h | 19 --- common/cmd_immap.c | 2 +- examples/standalone/mem_to_mem_idma2intr.c | 3 ++- include/commproc.h | 1 + 11 files changed, 39 insertions(+), 23 deletions(-) Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PULL] u-boot-pxa/master
The following changes since commit 58bb8f5f6138fa56875574a709f5af98c600c2a9: cosmetic: arm: fix comments in arch/arm/lib/crt0.S (2013-06-10 21:24:22 +0200) are available in the git repository at: git://git.denx.de/u-boot-pxa.git master for you to fetch changes up to 847e6693ccb529bf8346db62876f38f0c4e04ade: arm: pxa: config option for PXA270 turbo mode (2013-06-12 22:24:12 +0200) Sergey Yanovich (2): arm: pxa: Add support for ICP DAS LP-8x4x arm: pxa: config option for PXA270 turbo mode MAINTAINERS |4 +++ arch/arm/cpu/pxa/pxa2xx.c|2 +- board/icpdas/lp8x4x/Makefile | 41 +++ board/icpdas/lp8x4x/lp8x4x.c | 147 boards.cfg |1 + include/configs/lp8x4x.h | 262 ++ 6 files changed, 456 insertions(+), 1 deletion(-) create mode 100644 board/icpdas/lp8x4x/Makefile create mode 100644 board/icpdas/lp8x4x/lp8x4x.c create mode 100644 include/configs/lp8x4x.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 1/5] tpm: add AUTH1 cmds for LoadKey2 and GetPubKey
Acked-by: Che-Liang Chiou clch...@chromium.org
On Wed, Jun 12, 2013 at 1:08 AM, dirk.eib...@gdsys.cc wrote:
From: Reinhard Pfau p...@gdsys.de
Extend the tpm library with support for single authorized (AUTH1) commands
as specified in the TCG Main Specification 1.2. (The internally used helper
functions are implemented in a way that they could also be used for double
authorized commands if someone needs it.)
Provide enums with the return codes from the TCG Main specification.
For now only a single OIAP session is supported.
OIAP authorized version of the commands TPM_LoadKey2 and TPM_GetPubKey are
provided. Both features are available using the 'tpm' command, too.
Authorized commands are enabled with CONFIG_TPM_AUTH_SESSIONS. (Note that
this also requires CONFIG_SHA1 to be enabled.)
Signed-off-by: Reinhard Pfau reinhard.p...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- fix email addresses
Changes in v2:
- replace some numeric constants with named constants
- style fixes (as shown by checkpatch.pl) in common/cmd_tpm.c and lib/tpm.c
README | 14 +++
common/cmd_tpm.c | 100
include/tpm.h| 174 +++
lib/tpm.c| 351
++-
4 files changed, 638 insertions(+), 1 deletion(-)
diff --git a/README b/README
index 33bda8c..3d1fa08 100644
--- a/README
+++ b/README
@@ -1234,6 +1234,20 @@ The following options need to be configured:
to. Contemporary x86 systems usually map it at
0xfed4.
+ CONFIG_CMD_TPM
+ Add tpm monitor functions.
+ Requires CONFIG_TPM. If CONFIG_TPM_AUTH_SESSIONS is set, also
+ provides monitor access to authorized functions.
+
+ CONFIG_TPM
+ Define this to enable the TPM support library which provides
+ functional interfaces to some TPM commands.
+ Requires support for a TPM device.
+
+ CONFIG_TPM_AUTH_SESSIONS
+ Define this to enable authorized functions in the TPM library.
+ Requires CONFIG_TPM and CONFIG_SHA1.
+
- USB Support:
At the moment only the UHCI host controller is
supported (PIP405, MIP405, MPC5200); define
diff --git a/common/cmd_tpm.c b/common/cmd_tpm.c
index 46fae18..c34000a 100644
--- a/common/cmd_tpm.c
+++ b/common/cmd_tpm.c
@@ -27,6 +27,13 @@
#include asm/unaligned.h
#include linux/string.h
+/* Useful constants */
+enum {
+ DIGEST_LENGTH = 20,
+ /* max lengths, valid for RSA keys = 2048 bits */
+ TPM_PUBKEY_MAX_LENGTH = 288,
+};
+
/**
* Print a byte string in hexdecimal format, 16-bytes per line.
*
@@ -546,6 +553,72 @@ static int do_tpm_nv_write(cmd_tbl_t *cmdtp, int flag,
return convert_return_code(err);
}
+#ifdef CONFIG_TPM_AUTH_SESSIONS
+
+static int do_tpm_oiap(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ uint32_t auth_handle, err;
+
+ err = tpm_oiap(auth_handle);
+
+ return convert_return_code(err);
+}
+
+static int do_tpm_load_key2_oiap(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ uint32_t parent_handle, key_len, key_handle, err;
+ uint8_t usage_auth[DIGEST_LENGTH];
+ void *key;
+
+ if (argc 5)
+ return CMD_RET_USAGE;
+
+ parent_handle = simple_strtoul(argv[1], NULL, 0);
+ key = (void *)simple_strtoul(argv[2], NULL, 0);
+ key_len = simple_strtoul(argv[3], NULL, 0);
+ if (strlen(argv[4]) != 2 * DIGEST_LENGTH)
+ return CMD_RET_FAILURE;
+ parse_byte_string(argv[4], usage_auth, NULL);
+
+ err = tpm_load_key2_oiap(parent_handle, key, key_len, usage_auth,
+ key_handle);
+ if (!err)
+ printf(Key handle is 0x%x\n, key_handle);
+
+ return convert_return_code(err);
+}
+
+static int do_tpm_get_pub_key_oiap(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ uint32_t key_handle, err;
+ uint8_t usage_auth[DIGEST_LENGTH];
+ uint8_t pub_key_buffer[TPM_PUBKEY_MAX_LENGTH];
+ size_t pub_key_len = sizeof(pub_key_buffer);
+
+ if (argc 3)
+ return CMD_RET_USAGE;
+
+ key_handle = simple_strtoul(argv[1], NULL, 0);
+ if (strlen(argv[2]) != 2 * DIGEST_LENGTH)
+ return CMD_RET_FAILURE;
+ parse_byte_string(argv[2], usage_auth, NULL);
+
+ err = tpm_get_pub_key_oiap(key_handle, usage_auth,
+ pub_key_buffer, pub_key_len);
+ if (!err) {
+ printf(dump of received pub key structure:\n);
+
Re: [U-Boot] [PATCH 0/4] MIPS: minor cleanups
2013/6/12 Gabor Juhos juh...@openwrt.org: Gabor Juhos (4): MIPS: mips32/time.c: fix checkpatch errors/warnings MIPS: mips64/interrupt.c: remove superfluous include MIPS: remove obsolete TODO items MIPS: mips32/cache.S: remove superfluous register assignment arch/mips/cpu/mips32/cache.S |3 +-- arch/mips/cpu/mips32/time.c |5 +++-- arch/mips/cpu/mips64/interrupts.c |1 - doc/README.mips |4 4 files changed, 4 insertions(+), 9 deletions(-) all four patches applied to u-boot-mips/next, thanks -- Best regards, Daniel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2 V3] spi: exynos: Support a delay after deactivate
Hi Jagan,
On Wed, Jun 12, 2013 at 12:51 PM, Jagan Teki jagannadh.t...@gmail.comwrote:
Hi,
On 30-05-2013 10:49, Rajeshwari Shinde wrote:
For devices that need some time to react after a spi transaction
finishes, add the ability to set a delay.
Implement this as a delay on the first/next transaction to avoid
any delay in the fairly common case where a SPI transaction is
followed by other processing.
Based on:
[U-Boot] [PATCH 0/2 V5] spi: Enable SPI_PREAMBLE Mode
Please use the below format for referring previous commits
ex:
PREVIOUS_COMMIT_HEAD
(sha1: PREVIOUS_COMMIT_ID)
in this case
spi: exynos: Support SPI_PREAMBLE mode
(sha1: e4eaef8910df805d511b1cb9b2caaf**a7d2827fdc)
I hope you don't mind me answering part of this...
Signed-off-by: Simon Glass s...@chromium.org
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Changes in V2:
- None.
Changes in V3:
- Rebased on [PATCH 0/2 V5] spi: Enable SPI_PREAMBLE Mode
drivers/spi/exynos_spi.c | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
index 01378d0..03cf503 100644
--- a/drivers/spi/exynos_spi.c
+++ b/drivers/spi/exynos_spi.c
@@ -38,6 +38,7 @@ struct spi_bus {
struct exynos_spi *regs;
int inited; /* 1 if this bus is ready for use */
int node;
+ uint deactivate_delay_us; /* Delay to wait after deactivate
*/
};
/* A list of spi buses that we know about */
@@ -52,6 +53,8 @@ struct exynos_spi_slave {
enum periph_id periph_id; /* Peripheral ID for this device
*/
unsigned int fifo_size;
int skip_preamble;
+ struct spi_bus *bus;/* Pointer to our SPI bus info */
+ ulong last_transaction_us; /* Time of last transaction end */
};
static struct spi_bus *spi_get_bus(unsigned dev_index)
@@ -97,6 +100,7 @@ struct spi_slave *spi_setup_slave(unsigned int busnum,
unsigned int cs,
}
bus = spi_bus[busnum];
+ spi_slave-bus = bus;
spi_slave-regs = bus-regs;
spi_slave-mode = mode;
spi_slave-periph_id = bus-periph_id;
@@ -107,6 +111,7 @@ struct spi_slave *spi_setup_slave(unsigned int
busnum, unsigned int cs,
spi_slave-fifo_size = 256;
spi_slave-skip_preamble = 0;
+ spi_slave-last_transaction_us = timer_get_us();
spi_slave-freq = bus-frequency;
if (max_hz)
@@ -371,9 +376,21 @@ void spi_cs_activate(struct spi_slave *slave)
{
struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
+ /* If it's too soon to do another transaction, wait */
+ if (spi_slave-bus-deactivate_**delay_us
+ spi_slave-last_transaction_**us) {
+ ulong delay_us; /* The delay completed so far */
+ delay_us = timer_get_us() - spi_slave-last_transaction_*
*us;
+ if (delay_us spi_slave-bus-deactivate_**delay_us)
+ udelay(spi_slave-bus-**deactivate_delay_us -
delay_us);
+ }
Add one space
clrbits_le32(spi_slave-regs-**cs_reg, SPI_SLAVE_SIG_INACT);
debug(Activate CS, bus %d\n, spi_slave-slave.bus);
spi_slave-skip_preamble = spi_slave-mode SPI_PREAMBLE;
+
+ /* Remember time of this transaction so we can honour the bus
delay */
+ if (spi_slave-bus-deactivate_**delay_us)
+ spi_slave-last_transaction_us = timer_get_us();
}
/**
@@ -423,6 +440,8 @@ static int spi_get_config(const void *blob, int node,
struct spi_bus *bus)
/* Use 500KHz as a suitable default */
bus-frequency = fdtdec_get_int(blob, node, spi-max-frequency,
50);
+ bus-deactivate_delay_us = fdtdec_get_int(blob, node,
+ spi-deactivate-delay, 0);
return 0;
}
Was this tested, usually what is the max deactivate delay?
This was tested with 50us.
In this case your are passing through dts is it?
Yes that's right.
Regards,
Simon
Thanks,
Jagan.
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Re: [U-Boot] [PATCH v3 01/17] sf: Add bank address register writing support
Hi Jagan,
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
This patch provides support to program a flash bank address
register.
extended/bank address register contains an information to access
the 4th byte addressing in 3-byte address mode.
Currently added an bank address register writing support for
spansion flashes.
reff' the spec for more details about bank addr register
in Page-63, Table 8.16
http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Reviewed-by: Simon Glass s...@chromium.org
See comment below, perhaps a follow-on patch so you can get this in first?
---
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 37
drivers/mtd/spi/spi_flash_internal.h | 6 ++
include/spi_flash.h | 2 ++
3 files changed, 45 insertions(+)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 0e38f59..7aba520 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -278,6 +278,40 @@ int spi_flash_cmd_write_status(struct spi_flash
*flash, u8 sr)
return 0;
}
+int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
+{
+ u8 cmd, idcode0;
+ int ret;
+
+ idcode0 = flash-idcode0;
+ if (idcode0 == 0x01) {
I wonder why you need this to be hard-coded here? As a follow-on patch, I
suggest you have something in the probe function which decides which bank
addressing algorithm to use (e.g. winbond, ST, none). and then this code
can be:
switch (flash-bank_addr_algo) {
case SF_ALGO_WINBOND:
...
case SF_ALGO_ST:
...
}
+ cmd = CMD_BANKADDR_BRWR;
+ } else {
+ printf(SF: Unsupported bank addr write %02x\n, idcode0);
+ return -1;
+ }
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret 0) {
+ debug(SF: enabling write failed\n);
+ return ret;
+ }
+
+ ret = spi_flash_cmd_write(flash-spi, cmd, 1, bank_sel, 1);
+ if (ret) {
+ debug(SF: fail to write bank addr register\n);
+ return ret;
+ }
+
+ ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ if (ret 0) {
+ debug(SF: write bank addr register timed out\n);
+ return ret;
+ }
+
+ return 0;
+}
+
#ifdef CONFIG_OF_CONTROL
int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
{
@@ -422,6 +456,9 @@ struct spi_flash *spi_flash_probe(unsigned int bus,
unsigned int cs,
goto err_manufacturer_probe;
}
+ /* store the manuf id, for performing specific flash ops */
+ flash-idcode0 = *idp;
+
#ifdef CONFIG_OF_CONTROL
if (spi_flash_decode_fdt(gd-fdt_blob, flash)) {
debug(SF: FDT decode error\n);
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index 141cfa8..6e38494 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -28,6 +28,9 @@
#define CMD_ERASE_64K 0xd8
#define CMD_ERASE_CHIP 0xc7
+/* Bank addr acess commands */
+#define CMD_BANKADDR_BRWR 0x17
+
/* Common status */
#define STATUS_WIP 0x01
@@ -77,6 +80,9 @@ static inline int spi_flash_cmd_write_disable(struct
spi_flash *flash)
/* Program the status register. */
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
+/* Program the bank address register */
+int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel);
+
/*
* Same as spi_flash_cmd_read() except it also claims/releases the SPI
* bus. Used as common part of the -read() operation.
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 3b6a44e..5ea42e1 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -38,6 +38,8 @@ struct spi_flash {
u32 page_size;
/* Erase (sector) size */
u32 sector_size;
+ /* ID code0 */
+ u8 idcode0;
void *memory_map; /* Address of read-only SPI flash access */
int (*read)(struct spi_flash *flash, u32 offset,
--
1.8.3
Regards,
Simon
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Re: [U-Boot] [PATCH v3 02/17] sf: Add bank address register reading support
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
This patch provides support to read a flash bank address register.
reading extended/bank address register will give whether the flash
is operated on extended/bank addressing or normal addressing in
3-byte address mode.
Currently added an extended/bank address register reading support
for spansion flashes.
reff' the spec for more details about bank addr register
in Page-63, Table 8.16
http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Reviewed-by: Simon Glass s...@chromium.org
(same comment as previous patch)
---
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 15 +++
drivers/mtd/spi/spi_flash_internal.h | 4
2 files changed, 19 insertions(+)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 7aba520..193de42 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -312,6 +312,21 @@ int spi_flash_cmd_bankaddr_write(struct spi_flash
*flash, u8 bank_sel)
return 0;
}
+int spi_flash_cmd_bankaddr_read(struct spi_flash *flash, void *data)
+{
+ u8 cmd;
+ u8 idcode0 = flash-idcode0;
+
+ if (idcode0 == 0x01) {
+ cmd = CMD_BANKADDR_BRRD;
+ } else {
+ printf(SF: Unsupported bank addr read %02x\n, idcode0);
+ return -1;
+ }
+
+ return spi_flash_read_common(flash, cmd, 1, data, 1);
+}
+
#ifdef CONFIG_OF_CONTROL
int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
{
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index 6e38494..2567bbc 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -30,6 +30,7 @@
/* Bank addr acess commands */
#define CMD_BANKADDR_BRWR 0x17
+#define CMD_BANKADDR_BRRD 0x16
/* Common status */
#define STATUS_WIP 0x01
@@ -83,6 +84,9 @@ int spi_flash_cmd_write_status(struct spi_flash *flash,
u8 sr);
/* Program the bank address register */
int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel);
+/* Read the bank address register */
+int spi_flash_cmd_bankaddr_read(struct spi_flash *flash, void *data);
+
/*
* Same as spi_flash_cmd_read() except it also claims/releases the SPI
* bus. Used as common part of the -read() operation.
--
1.8.3
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Re: [U-Boot] [PATCH v3 04/17] sf: Add extended addr read support for winbond|stmicro
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
This patch provides support to read a flash extended address
register for winbond and stmicro SPI flashes.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Reviewed-by: Simon Glass s...@chromium.org
Same comment as previous patch.
---
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 2 ++
drivers/mtd/spi/spi_flash_internal.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 05d1792..66b6b14 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -321,6 +321,8 @@ int spi_flash_cmd_bankaddr_read(struct spi_flash
*flash, void *data)
if (idcode0 == 0x01) {
cmd = CMD_BANKADDR_BRRD;
+ } else if ((idcode0 == 0xef) || (idcode0 == 0x20)) {
+ cmd = CMD_EXTNADDR_RDEAR;
} else {
printf(SF: Unsupported bank addr read %02x\n, idcode0);
return -1;
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index de1a0df..1b29e2d 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -32,6 +32,7 @@
#define CMD_BANKADDR_BRWR 0x17
#define CMD_BANKADDR_BRRD 0x16
#define CMD_EXTNADDR_WREAR 0xC5
+#define CMD_EXTNADDR_RDEAR 0xC8
/* Common status */
#define STATUS_WIP 0x01
--
1.8.3
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Re: [U-Boot] [PATCH v3 03/17] sf: Add extended addr write support for winbond|stmicro
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
This patch provides support to program a flash extended address
register for winbond and stmicro SPI flashes.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Reviewed-by: Simon Glass s...@chromium.org
Looks good, same comment as previous patch.
---
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 2 ++
drivers/mtd/spi/spi_flash_internal.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 193de42..05d1792 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -286,6 +286,8 @@ int spi_flash_cmd_bankaddr_write(struct spi_flash
*flash, u8 bank_sel)
idcode0 = flash-idcode0;
if (idcode0 == 0x01) {
cmd = CMD_BANKADDR_BRWR;
+ } else if ((idcode0 == 0xef) || (idcode0 == 0x20)) {
+ cmd = CMD_EXTNADDR_WREAR;
} else {
printf(SF: Unsupported bank addr write %02x\n, idcode0);
return -1;
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index 2567bbc..de1a0df 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -31,6 +31,7 @@
/* Bank addr acess commands */
#define CMD_BANKADDR_BRWR 0x17
#define CMD_BANKADDR_BRRD 0x16
+#define CMD_EXTNADDR_WREAR 0xC5
/* Common status */
#define STATUS_WIP 0x01
--
1.8.3
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Re: [U-Boot] [PATCH v3 05/17] sf: read flash bank addr register at probe time
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
Read the flash bank addr register to get the state of bank in
a perticular flash. and also bank write happens only when there is
a change in bank selection from user.
bank read only valid for flashes which has 16Mbytes those are
opearted in 3-byte addr mode, each bank occupies 16Mytes.
Suppose if the flash has 64Mbytes size consists of 4 banks like
bank0, bank1, bank2 and bank3.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Reviewed-by: Simon Glass s...@chromium.org
---
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 17 +
drivers/mtd/spi/spi_flash_internal.h | 2 ++
include/spi_flash.h | 2 ++
3 files changed, 21 insertions(+)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 66b6b14..4576a16 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -283,6 +283,11 @@ int spi_flash_cmd_bankaddr_write(struct spi_flash
*flash, u8 bank_sel)
u8 cmd, idcode0;
int ret;
+ if (flash-bank_curr == bank_sel) {
+ debug(SF: not require to enable bank%d\n, bank_sel);
+ return 0;
+ }
+
idcode0 = flash-idcode0;
if (idcode0 == 0x01) {
cmd = CMD_BANKADDR_BRWR;
@@ -304,6 +309,7 @@ int spi_flash_cmd_bankaddr_write(struct spi_flash
*flash, u8 bank_sel)
debug(SF: fail to write bank addr register\n);
return ret;
}
+ flash-bank_curr = bank_sel;
ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
if (ret 0) {
@@ -432,6 +438,7 @@ struct spi_flash *spi_flash_probe(unsigned int bus,
unsigned int cs,
struct spi_flash *flash = NULL;
int ret, i, shift;
u8 idcode[IDCODE_LEN], *idp;
+ u8 curr_bank = 0;
spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
if (!spi) {
@@ -491,6 +498,16 @@ struct spi_flash *spi_flash_probe(unsigned int bus,
unsigned int cs,
printf(, mapped at %p, flash-memory_map);
puts(\n);
+ if (flash-size SPI_FLASH_16MB_BOUN) {
+ if (spi_flash_cmd_bankaddr_read(flash, curr_bank)) {
+ debug(SF: fail to read bank addr register\n);
+ goto err_manufacturer_probe;
+ }
+ flash-bank_curr = curr_bank;
+ } else {
+ flash-bank_curr = curr_bank;
+ }
+
spi_release_bus(spi);
return flash;
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index 1b29e2d..455dc02 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -12,6 +12,8 @@
#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
+#define SPI_FLASH_16MB_BOUN0x100
+
/* Common commands */
#define CMD_READ_ID0x9f
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 5ea42e1..acac17a 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -40,6 +40,8 @@ struct spi_flash {
u32 sector_size;
/* ID code0 */
u8 idcode0;
+ /* Current flash bank */
+ u8 bank_curr;
void *memory_map; /* Address of read-only SPI flash access */
int (*read)(struct spi_flash *flash, u32 offset,
--
1.8.3
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[U-Boot] [PATCH] FSL espi: Return all data read from device unmodified.
Signed-off-by: Dale P. Smith dsm...@vtiinstruments.com
---
drivers/spi/fsl_espi.c | 10 ++
1 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index 28609ee..bd9dc64 100644
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -287,17 +287,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int
bitlen, const void *data_out,
debug(***spi_xfer:...%08x readed\n, tmpdin);
}
}
- if (data_in) {
- memcpy(data_in, buffer + 2 * cmd_len, tran_len);
- if (*buffer == 0x0b) {
- data_in += tran_len;
- data_len -= tran_len;
- *(int *)buffer += tran_len;
- }
- }
spi_cs_deactivate(slave);
}
+ if (data_in)
+ memcpy(data_in, buffer + rx_offset, len);
free(buffer);
return 0;
}
--
1.7.2.5
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Re: [U-Boot] [PATCH] powerpc/p1022ds: nand: introduce the TPL based on the SPL
On 06/09/2013 12:54:43 AM, ying.zh...@freescale.com wrote:
From: Ying Zhang b40...@freescale.com
Due to the nand SPL on the board P1022DS has a size limit, it can not
be
more than 4K. So, the SPL cannot initialize the DDR with the SPD code.
This patch introduces TPL to enable a loader stub that runs in the L2
SRAM,
after being loaded by the code from the SPL. It initializes the DDR
with
the SPD.
The TPL's size is sizeable, the maximum size must not exceed the size
of L2
SRAM. It initializes the DDR through SPD code, and copys final uboot
image
to DDR. So there are three stage uboot images:
* spl_boot, 4KB size, pad to 128K byte.
* tpl_boot, 88K size, pad to 128K size. The env variables are
copied to L2 SRAM, so that ddr SPD code can get the interleaving
mode setting in env. It loads final uboot image from offset
256KB.
* final uboot image, size is variable depends on the functions
enabled.
This patch is on top of the patch:
powerpc/p1022ds: boot from SD Card with SPL
Signed-off-by: Ying Zhang b40...@freescale.com
---
Makefile | 25 +++-
README | 55 ++-
arch/powerpc/config.mk |2 +
arch/powerpc/cpu/mpc85xx/spl_minimal.c | 16 ++
arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds| 80 +
.../cpu/mpc8xxx/ddr/lc_common_dimm_params.c|4 +-
arch/powerpc/lib/Makefile |2 +
board/freescale/p1022ds/Makefile |3 +
board/freescale/p1022ds/spl_minimal.c | 56 +--
board/freescale/p1022ds/tlb.c |4 +-
board/freescale/p1022ds/tpl.c | 101
common/Makefile|9 +
common/cmd_nvedit.c|8 +-
config.mk | 32
doc/README.TPL | 93 +++
drivers/mtd/nand/Makefile |8 +
drivers/mtd/nand/fsl_elbc_tpl.c| 168
drivers/serial/serial.c|2 +-
include/bootstage.h|3 +-
include/configs/P1022DS.h | 75 +++--
tpl/Makefile | 161
+++
21 files changed, 824 insertions(+), 83 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
create mode 100644 board/freescale/p1022ds/tpl.c
create mode 100644 doc/README.TPL
create mode 100644 drivers/mtd/nand/fsl_elbc_tpl.c
create mode 100644 tpl/Makefile
diff --git a/Makefile b/Makefile
index ef154aa..65849d1 100644
--- a/Makefile
+++ b/Makefile
@@ -118,10 +118,11 @@ endif # ifneq ($(BUILD_DIR),)
OBJTREE:= $(if $(BUILD_DIR),$(BUILD_DIR),$(CURDIR))
SPLTREE:= $(OBJTREE)/spl
+TPLTREE:= $(OBJTREE)/tpl
SRCTREE:= $(CURDIR)
TOPDIR := $(SRCTREE)
LNDIR := $(OBJTREE)
-export TOPDIR SRCTREE OBJTREE SPLTREE
+export TOPDIR SRCTREE OBJTREE SPLTREE TPLTREE
MKCONFIG := $(SRCTREE)/mkconfig
export MKCONFIG
@@ -412,9 +413,14 @@ ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin
$(obj)System.map
ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
+ALL-$(CONFIG_TPL) += $(obj)tpl/u-boot-tpl.bin
ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
ifneq ($(CONFIG_SPL_TARGET),)
ALL-$(CONFIG_SPL) += $(obj)$(subst ,,$(CONFIG_SPL_TARGET))
+else
+ifneq ($(CONFIG_TPL_TARGET),)
+ALL-$(CONFIG_TPL) += $(obj)$(subst ,,$(CONFIG_TPL_TARGET))
+endif
endif
# enable combined SPL/u-boot/dtb rules for tegra
@@ -498,6 +504,18 @@ $(obj)u-boot-with-spl.bin:
$(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $@
rm $(obj)spl/u-boot-spl-pad.bin
+$(obj)u-boot-with-tpl.bin: $(obj)spl/u-boot-spl.bin
$(obj)tpl/u-boot-tpl.bin \
+ $(obj)u-boot.bin
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
+ -I binary -O binary \
+ $(obj)spl/u-boot-spl.bin
$(obj)spl/u-boot-spl-pad.bin
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_TPL_PAD_TO) \
+ -I binary -O binary \
+ $(obj)tpl/u-boot-tpl.bin
$(obj)tpl/u-boot-tpl-pad.bin
+ cat $(obj)spl/u-boot-spl-pad.bin
$(obj)tpl/u-boot-tpl-pad.bin \
+ $(obj)u-boot.bin $@
+ rm $(obj)spl/u-boot-spl-pad.bin
$(obj)tpl/u-boot-tpl-pad.bin
+
$(obj)u-boot-with-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(MAKE) -C $(SRCTREE)/arch/arm/imx-common \
$(OBJTREE)/u-boot-with-spl.imx
@@ -622,6 +640,9 @@
Re: [U-Boot] [PATCH v3 06/17] sf: Update sf to support all sizes of flashes
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com wrote: Updated the spi_flash framework to handle all sizes of flashes using bank/extd addr reg facility The current implementation in spi_flash supports 3-byte address mode due to this up to 16Mbytes amount of flash is able to access for those flashes which has an actual size of 16MB. As most of the flashes introduces a bank/extd address registers for accessing the flashes in 16Mbytes of banks if the flash size is 16Mbytes, this new scheme will add the bank selection feature for performing write/erase operations on all flashes. Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com Reviewed-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 07/17] sf: Update sf read to support all sizes of flashes
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com wrote: This patch updated the spi_flash read func to support all sizes of flashes using bank reg addr facility. The same support has been added in below patch for erase/write spi_flash functions: sf: Support all sizes of flashes using bank addr reg facility (sha1: c956f600cbb0943d0afe1004cdb503f4fcd8f415) With these new updates on sf framework, the flashes which has 16MB are not effected as per as performance is concern and but the u-boot.bin size incrased ~600 bytes. sf update(for first 16MBytes), Changes before: U-Boot sf update 0x100 0x0 0x100 - N25Q256 16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s - W25Q128BV 16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s - S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s sf update(for first 16MBytes), Changes before: U-Boot sf update 0x100 0x0 0x100 - N25Q256 16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s - W25Q128BV 16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s - S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com Reviewed-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 08/17] sf: Add bank addr code in CONFIG_SPI_FLASH_BAR
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com wrote: Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the size for existing boards which has 16Mbytes SPI flashes. It's upto user which has provision to use the bank addr code for flashes which has 16Mbytes. Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com Reviewed-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 09/17] sf: Initialize bank_sel to zero for read ops
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com wrote: Initialized bank_sel variable to 0 to support the updated read ops for flashes which has 16Mbytes. Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com Reviewed-by: Simon Glass s...@chromium.org (This seems like it could be merged with an early patch?) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 10/17] sf: Use spi_flash_addr() in write call
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com wrote: Use the existing spi_flash_addr() for 3-byte addressing cmd filling in write call. Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com Reviewed-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 16/17] sf: Remove spi_flash_cmd_poll_bit()
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com wrote: There is no other call other than spi_flash_cmd_wait_ready(), hence removed spi_flash_cmd_poll_bit and use the poll status code spi_flash_cmd_wait_ready() itself. Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com Reviewed-by: Simon Glass s...@chromium.org --- Changes for v3: - none Really? It seems different. Changes for v2: - none drivers/mtd/spi/spi_flash.c | 11 +++ drivers/mtd/spi/spi_flash_internal.h | 4 2 files changed, 3 insertions(+), 12 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 17/17] sf: Add Flag status register polling support
Hi Jagan,
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
Flag status register polling is required for micron 512Mb flash
devices onwards, for performing erase/program operations.
Like polling for WIP(Write-In-Progress) bit in read status register,
spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control)
bit in flag status register.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v3:
- define the flag status code on CONFIG_SPI_FLASH_STMICRO
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 16 +---
drivers/mtd/spi/spi_flash_internal.h | 2 ++
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index bb37f54..4f97fab0 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -200,12 +200,22 @@ int spi_flash_cmd_wait_ready(struct spi_flash
*flash, unsigned long timeout)
unsigned long timebase;
int ret;
u8 status;
+ u8 check_status = 0x0;
u8 poll_bit = STATUS_WIP;
u8 cmd = CMD_READ_STATUS;
+#ifdef CONFIG_SPI_FLASH_STMICRO
+ if (flash-size = 0x400) {
+ poll_bit = STATUS_PEC;
+ check_status = poll_bit;
+ cmd = CMD_FLAG_STATUS;
+ }
+#endif
+
Similarly to the bank addressing I think this might be better done as a
'poll method' rather than a hack for a particular flash type.
Also I worry that in a system with more than one type of flash, this code
will fire for all flash types.
Regards,
Simon
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Re: [U-Boot] [PATCH v3 0/6] Optimize ARM relocation
Hi Albert, On Tuesday, June 11, 2013 2:17:29 PM, Albert ARIBAUD wrote: This series optimizes relocation by ensuring ARM binaries only use one type of relocation record, R_ARM_RELATIVE., then optimizing relocation code accordingly. 1. A Makefile rule is added that checks that no other relocation record types are generated except R_ARM_RELATIVE; build fails if this is the case. 2. All references to dymsym are removed, as this table is not used for R_ARM_RELATIVE relocations. 3. arch/arm/lib/bss.c is replaced by a more generic arch/arm/lib/sections.c where all section symbols will be defined. 4. __image_copy_start and __image_copy_end symbols are moved from linker scripts to arch/arm/lib/sections.c 5. __rel_dyn_start and __rel_dyn_end are moved from linker scripts into arch/arm/lib/sections.c 6. relocate_code is optimized based on the fact that symbol references are now always valid even before relcation, and that only R_ARM_RELATIVE relocations will be met. Changes in v3: - fix commit message typo (of - if) - fix commit message typo (breaks - break) For this v3 series: Reviewed-by: Benoît Thébaudeau benoit.thebaud...@advansee.com Best regards, Benoît ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 17/17] sf: Add Flag status register polling support
On Wed, Jun 12, 2013 at 3:42 PM, Simon Glass s...@chromium.org wrote:
Hi Jagan,
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
Flag status register polling is required for micron 512Mb flash
devices onwards, for performing erase/program operations.
Like polling for WIP(Write-In-Progress) bit in read status register,
spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control)
bit in flag status register.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v3:
- define the flag status code on CONFIG_SPI_FLASH_STMICRO
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 16 +---
drivers/mtd/spi/spi_flash_internal.h | 2 ++
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index bb37f54..4f97fab0 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -200,12 +200,22 @@ int spi_flash_cmd_wait_ready(struct spi_flash
*flash, unsigned long timeout)
unsigned long timebase;
int ret;
u8 status;
+ u8 check_status = 0x0;
u8 poll_bit = STATUS_WIP;
u8 cmd = CMD_READ_STATUS;
+#ifdef CONFIG_SPI_FLASH_STMICRO
+ if (flash-size = 0x400) {
+ poll_bit = STATUS_PEC;
+ check_status = poll_bit;
+ cmd = CMD_FLAG_STATUS;
+ }
+#endif
+
Similarly to the bank addressing I think this might be better done as a
'poll method' rather than a hack for a particular flash type.
Also I worry that in a system with more than one type of flash, this code
will fire for all flash types.
Also just a note that I tested this series on snow and it seems to have no
ill effects.
The series:
Tested-by: Simon Glass s...@chromium.org
Regards,
Simon
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[U-Boot] crash in usb_stor_get_info using pre-relocation address for ss-transport
Hi, I've just found a crash in usb_stor_get_info (actually usb_inquiry which gets auto-inlined). The cause seems to be that ss-transport is set to the pre-relocation address of usb_stor_BBB_transport. Yet ss-transport_reset is set to the correct relocated address of. The difference between the two is that usb_stor_BBB_reset is declared static and usb_stor_BBB_transport is not. Changing usb_stor_BBB_transport to a static makes things work but I notice that none of the other transport functions are static either so I'm thinking I haven't actually fixed the problem rather just masked it. I did some poking with a lauterbach and from the disassembly it looks like there is a translation table being used when the function pointers are setup by usb_storage_probe and when declared normally usb_stor_BBB_transport ends up at the end. Everything else has the correct relocated address so I wonder if there is an off-by-one error in whatever creates that table. Does this sound familiar to anyone. Thanks, Chris Extra debug info: Board: Custom design based on P2041RDB u-boot version: based on U-Boot 2012.10 = usb start (Re)start USB... USB: Register 10011 NbrPorts 1 USB EHCI 1.00 scanning bus for devices... 2 USB Device(s) found scanning bus for storage devices... i=0 i=1 USB Mass Storage device detected Transport: Bulk/Bulk/Bulk Endpoints In 1 Out 2 Int 0 Get Max LUN - len = 1, result = 0 dev_desc 7ffbbe4c usb_ccb 7ffbc0c0 pccb 7ffbc0c0 address 2 srb 7ffbc0c0 ss 7ffbbd48 ss-transport fffa98f4 ss-transport_reset 7ff586e8 Bad trap at PC: fffa98f4, SR: 29200, vector=e00 NIP: FFFA98F4 XER: LR: 7FF59F24 REGS: 7fd2daa0 TRAP: 0e00 DAR: MSR: 00029200 EE: 1 PR: 0 FP: 0 ME: 1 IR/DR: 00 GPR00: FFFA98F4 7FD2DB90 7FD2DF30 7FFBC0C0 7FFBBD48 7FFBC0C8 0010 GPR08: FFFE 0020 0020 7FD2DB90 42022044 21A40D64 7FD2E238 GPR16: 7FD2EA28 7FF94E29 0012 0024 GPR24: 0024 000C 7FF94D18 7FD2DBC0 7FFBBD48 7FFBC0C0 7FF9BE78 7FFBBE4C Call backtrace: 7FF59EDC 7FF5A35C 7FF4BBD0 7FF4CA48 7FF51E24 7FF5247C 7FF52600 7FF56178 7FF38C4C 7FF31650 Exception in kernel pc fffa98f4 signal 0 usb_inquiry usb_storage.c:922 usb_stor_scan usb_storage.c:280 do_usb cmd_usb.c:388 cmd_process command.c:544 run_pipe_real hush.c:1668 run_list hush.c:2021 parse_file_outer hush.c:3273 main_loop main.c:431 board_init_r board.c:1089 trap_init start.S:1824 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] crash in usb_stor_get_info using pre-relocation address for ss-transport
On Thu, Jun 13, 2013 at 12:02 PM, Chris Packham judge.pack...@gmail.com wrote: Hi, I've just found a crash in usb_stor_get_info (actually usb_inquiry which gets auto-inlined). The cause seems to be that ss-transport is set to the pre-relocation address of usb_stor_BBB_transport. Yet ss-transport_reset is set to the correct relocated address of. The difference between the two is that usb_stor_BBB_reset is declared static and usb_stor_BBB_transport is not. Changing usb_stor_BBB_transport to a static makes things work but I notice that none of the other transport functions are static either so I'm thinking I haven't actually fixed the problem rather just masked it. Actually I see commit 199adb60 (common/misc: sparse fixes) does change the transport functions to static. Which is the change I was looking at. I still don't know if it is fixing a problem or masking a different one but this is probably why no-one else is complaining that their usb mass storage devices are causing crashes. I'll cherry-pick this to fix my problem. I did some poking with a lauterbach and from the disassembly it looks like there is a translation table being used when the function pointers are setup by usb_storage_probe and when declared normally usb_stor_BBB_transport ends up at the end. Everything else has the correct relocated address so I wonder if there is an off-by-one error in whatever creates that table. Does this sound familiar to anyone. Thanks, Chris ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] FSL espi: Return all data read from device unmodified.
Hi,
Thanks for sending this.
Few comments.
1. Please use subject prefix with version number this case it should
be PATH v3
2. Commit header should be stand' one as all follows.
spi: fsl_espi:
On Thu, Jun 13, 2013 at 3:24 AM, Dale P. Smith
dsm...@vtiinstruments.com wrote:
Signed-off-by: Dale P. Smith dsm...@vtiinstruments.com
---
drivers/spi/fsl_espi.c | 10 ++
1 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index 28609ee..bd9dc64 100644
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -287,17 +287,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int
bitlen, const void *data_out,
debug(***spi_xfer:...%08x readed\n, tmpdin);
}
}
- if (data_in) {
- memcpy(data_in, buffer + 2 * cmd_len, tran_len);
- if (*buffer == 0x0b) {
- data_in += tran_len;
- data_len -= tran_len;
- *(int *)buffer += tran_len;
- }
- }
spi_cs_deactivate(slave);
}
+ if (data_in)
+ memcpy(data_in, buffer + rx_offset, len);
free(buffer);
return 0;
Have tested this recently?
Thanks,
Jagan.
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Re: [U-Boot] [PATCH v3 16/17] sf: Remove spi_flash_cmd_poll_bit()
Hi Simon, On Thu, Jun 13, 2013 at 4:09 AM, Simon Glass s...@chromium.org wrote: On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com wrote: There is no other call other than spi_flash_cmd_wait_ready(), hence removed spi_flash_cmd_poll_bit and use the poll status code spi_flash_cmd_wait_ready() itself. Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com Reviewed-by: Simon Glass s...@chromium.org --- Changes for v3: - none Really? It seems different. Can you please tell me what is the difference. As there is no changes in v2 to v3 i have written none was there any wrong with code style or something? Thanks, Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 01/17] sf: Add bank address register writing support
Hi Simon,
On Thu, Jun 13, 2013 at 3:48 AM, Simon Glass s...@chromium.org wrote:
Hi Jagan,
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
This patch provides support to program a flash bank address
register.
extended/bank address register contains an information to access
the 4th byte addressing in 3-byte address mode.
Currently added an bank address register writing support for
spansion flashes.
reff' the spec for more details about bank addr register
in Page-63, Table 8.16
http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Reviewed-by: Simon Glass s...@chromium.org
See comment below, perhaps a follow-on patch so you can get this in first?
---
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 37
drivers/mtd/spi/spi_flash_internal.h | 6 ++
include/spi_flash.h | 2 ++
3 files changed, 45 insertions(+)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 0e38f59..7aba520 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -278,6 +278,40 @@ int spi_flash_cmd_write_status(struct spi_flash
*flash, u8 sr)
return 0;
}
+int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
+{
+ u8 cmd, idcode0;
+ int ret;
+
+ idcode0 = flash-idcode0;
+ if (idcode0 == 0x01) {
I wonder why you need this to be hard-coded here? As a follow-on patch, I
suggest you have something in the probe function which decides which bank
addressing algorithm to use (e.g. winbond, ST, none). and then this code can
be:
switch (flash-bank_addr_algo) {
case SF_ALGO_WINBOND:
...
case SF_ALGO_ST:
...
}
Means in probe time we can assign particular bank commands something like
switch (*idp) {
case SF_WINBOND_IDCODE0:
flash-bank_wr_cmd = ;
flash-bank_rd_cmd = ;
case SF_SPAN_IDCODE0:
flash-bank_wr_cmd = ;
flash-bank_rd_cmd = ;
}
Please let me know your comments.
--
Thanks,
Jagan.
+ cmd = CMD_BANKADDR_BRWR;
+ } else {
+ printf(SF: Unsupported bank addr write %02x\n, idcode0);
+ return -1;
+ }
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret 0) {
+ debug(SF: enabling write failed\n);
+ return ret;
+ }
+
+ ret = spi_flash_cmd_write(flash-spi, cmd, 1, bank_sel, 1);
+ if (ret) {
+ debug(SF: fail to write bank addr register\n);
+ return ret;
+ }
+
+ ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ if (ret 0) {
+ debug(SF: write bank addr register timed out\n);
+ return ret;
+ }
+
+ return 0;
+}
+
#ifdef CONFIG_OF_CONTROL
int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
{
@@ -422,6 +456,9 @@ struct spi_flash *spi_flash_probe(unsigned int bus,
unsigned int cs,
goto err_manufacturer_probe;
}
+ /* store the manuf id, for performing specific flash ops */
+ flash-idcode0 = *idp;
+
#ifdef CONFIG_OF_CONTROL
if (spi_flash_decode_fdt(gd-fdt_blob, flash)) {
debug(SF: FDT decode error\n);
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index 141cfa8..6e38494 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -28,6 +28,9 @@
#define CMD_ERASE_64K 0xd8
#define CMD_ERASE_CHIP 0xc7
+/* Bank addr acess commands */
+#define CMD_BANKADDR_BRWR 0x17
+
/* Common status */
#define STATUS_WIP 0x01
@@ -77,6 +80,9 @@ static inline int spi_flash_cmd_write_disable(struct
spi_flash *flash)
/* Program the status register. */
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
+/* Program the bank address register */
+int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel);
+
/*
* Same as spi_flash_cmd_read() except it also claims/releases the SPI
* bus. Used as common part of the -read() operation.
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 3b6a44e..5ea42e1 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -38,6 +38,8 @@ struct spi_flash {
u32 page_size;
/* Erase (sector) size */
u32 sector_size;
+ /* ID code0 */
+ u8 idcode0;
void *memory_map; /* Address of read-only SPI flash access
*/
int (*read)(struct spi_flash *flash, u32 offset,
--
1.8.3
Regards,
Simon
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Re: [U-Boot] [PATCH 2/2 V3] spi: exynos: Support a delay after deactivate
On Thu, Jun 13, 2013 at 3:36 AM, Simon Glass s...@chromium.org wrote:
Hi Jagan,
On Wed, Jun 12, 2013 at 12:51 PM, Jagan Teki jagannadh.t...@gmail.com
wrote:
Hi,
On 30-05-2013 10:49, Rajeshwari Shinde wrote:
For devices that need some time to react after a spi transaction
finishes, add the ability to set a delay.
Implement this as a delay on the first/next transaction to avoid
any delay in the fairly common case where a SPI transaction is
followed by other processing.
Based on:
[U-Boot] [PATCH 0/2 V5] spi: Enable SPI_PREAMBLE Mode
Please use the below format for referring previous commits
ex:
PREVIOUS_COMMIT_HEAD
(sha1: PREVIOUS_COMMIT_ID)
in this case
spi: exynos: Support SPI_PREAMBLE mode
(sha1: e4eaef8910df805d511b1cb9b2caafa7d2827fdc)
I hope you don't mind me answering part of this...
Signed-off-by: Simon Glass s...@chromium.org
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Changes in V2:
- None.
Changes in V3:
- Rebased on [PATCH 0/2 V5] spi: Enable SPI_PREAMBLE Mode
drivers/spi/exynos_spi.c | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
index 01378d0..03cf503 100644
--- a/drivers/spi/exynos_spi.c
+++ b/drivers/spi/exynos_spi.c
@@ -38,6 +38,7 @@ struct spi_bus {
struct exynos_spi *regs;
int inited; /* 1 if this bus is ready for use */
int node;
+ uint deactivate_delay_us; /* Delay to wait after deactivate
*/
};
/* A list of spi buses that we know about */
@@ -52,6 +53,8 @@ struct exynos_spi_slave {
enum periph_id periph_id; /* Peripheral ID for this device
*/
unsigned int fifo_size;
int skip_preamble;
+ struct spi_bus *bus;/* Pointer to our SPI bus info */
+ ulong last_transaction_us; /* Time of last transaction end
*/
};
static struct spi_bus *spi_get_bus(unsigned dev_index)
@@ -97,6 +100,7 @@ struct spi_slave *spi_setup_slave(unsigned int busnum,
unsigned int cs,
}
bus = spi_bus[busnum];
+ spi_slave-bus = bus;
spi_slave-regs = bus-regs;
spi_slave-mode = mode;
spi_slave-periph_id = bus-periph_id;
@@ -107,6 +111,7 @@ struct spi_slave *spi_setup_slave(unsigned int
busnum, unsigned int cs,
spi_slave-fifo_size = 256;
spi_slave-skip_preamble = 0;
+ spi_slave-last_transaction_us = timer_get_us();
spi_slave-freq = bus-frequency;
if (max_hz)
@@ -371,9 +376,21 @@ void spi_cs_activate(struct spi_slave *slave)
{
struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
+ /* If it's too soon to do another transaction, wait */
+ if (spi_slave-bus-deactivate_delay_us
+ spi_slave-last_transaction_us) {
+ ulong delay_us; /* The delay completed so far */
+ delay_us = timer_get_us() -
spi_slave-last_transaction_us;
+ if (delay_us spi_slave-bus-deactivate_delay_us)
+ udelay(spi_slave-bus-deactivate_delay_us -
delay_us);
+ }
Add one space
clrbits_le32(spi_slave-regs-cs_reg, SPI_SLAVE_SIG_INACT);
debug(Activate CS, bus %d\n, spi_slave-slave.bus);
spi_slave-skip_preamble = spi_slave-mode SPI_PREAMBLE;
+
+ /* Remember time of this transaction so we can honour the bus
delay */
+ if (spi_slave-bus-deactivate_delay_us)
+ spi_slave-last_transaction_us = timer_get_us();
}
/**
@@ -423,6 +440,8 @@ static int spi_get_config(const void *blob, int node,
struct spi_bus *bus)
/* Use 500KHz as a suitable default */
bus-frequency = fdtdec_get_int(blob, node, spi-max-frequency,
50);
+ bus-deactivate_delay_us = fdtdec_get_int(blob, node,
+ spi-deactivate-delay, 0);
return 0;
}
Was this tested, usually what is the max deactivate delay?
This was tested with 50us.
In this case your are passing through dts is it?
Yes that's right.
Regards,
Simon
Thanks,
Jagan.
Can you please send the next version patches.
--
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[U-Boot] [PATCH v2 01/10] ARM: move interrupt_init to before relocation
From: Rob Herring rob.herr...@calxeda.com interrupt_init also sets up the abort stack, but is not setup before relocation. So any aborts during relocation will hang and not print out any useful information. Fix this by moving the interrupt_init to after the stack setup in board_init_f. Signed-off-by: Rob Herring rob.herr...@calxeda.com --- v2: - Remove interrupt_init from board_init_r arch/arm/lib/board.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 09ab4ad..c90843e 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -447,6 +447,7 @@ void board_init_f(ulong bootflag) addr_sp += 128; /* leave 32 words for abort-stack */ gd-irq_sp = addr_sp; #endif + interrupt_init(); debug(New Stack Pointer is: %08lx\n, addr_sp); @@ -648,8 +649,6 @@ void board_init_r(gd_t *id, ulong dest_addr) misc_init_r(); #endif -/* set up exceptions */ - interrupt_init(); /* enable exceptions */ enable_interrupts(); -- 1.8.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 04/10] ARM: highbank: fix get_tbclk value to timer rate
From: Rob Herring rob.herr...@calxeda.com
get_tbclk should return the timer's frequency, not CONFIG_SYS_HZ.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
---
v2: no change, resend
arch/arm/cpu/armv7/highbank/timer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/highbank/timer.c
b/arch/arm/cpu/armv7/highbank/timer.c
index 0f985e2..da33d3c 100644
--- a/arch/arm/cpu/armv7/highbank/timer.c
+++ b/arch/arm/cpu/armv7/highbank/timer.c
@@ -124,5 +124,5 @@ ulong get_timer_masked(void)
ulong get_tbclk(void)
{
- return CONFIG_SYS_HZ;
+ return SYSTIMER_RATE;
}
--
1.8.1.2
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[U-Boot] [PATCH v2 05/10] ARM: highbank: set timer prescaler to 256
From: Rob Herring rob.herr...@calxeda.com
The 150MHz clock rate gives u-boot time functions problems and there's no
benefit to a fast clock, so lower the rate.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
---
v2: no change, resend
arch/arm/cpu/armv7/highbank/timer.c| 6 --
arch/arm/include/asm/arch-armv7/systimer.h | 2 ++
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/highbank/timer.c
b/arch/arm/cpu/armv7/highbank/timer.c
index da33d3c..d93de1e 100644
--- a/arch/arm/cpu/armv7/highbank/timer.c
+++ b/arch/arm/cpu/armv7/highbank/timer.c
@@ -26,7 +26,7 @@
#undef SYSTIMER_BASE
#define SYSTIMER_BASE 0xFFF34000 /* Timer 0 and 1 base */
-#define SYSTIMER_RATE 15000
+#define SYSTIMER_RATE (15000 / 256)
static ulong timestamp;
static ulong lastinc;
@@ -40,9 +40,11 @@ int timer_init(void)
/*
* Setup timer0
*/
+ writel(0, systimer_base-timer0control);
writel(SYSTIMER_RELOAD, systimer_base-timer0load);
writel(SYSTIMER_RELOAD, systimer_base-timer0value);
- writel(SYSTIMER_EN | SYSTIMER_32BIT, systimer_base-timer0control);
+ writel(SYSTIMER_EN | SYSTIMER_32BIT | SYSTIMER_PRESC_256,
+ systimer_base-timer0control);
reset_timer_masked();
diff --git a/arch/arm/include/asm/arch-armv7/systimer.h
b/arch/arm/include/asm/arch-armv7/systimer.h
index e745e37..08125f7 100644
--- a/arch/arm/include/asm/arch-armv7/systimer.h
+++ b/arch/arm/include/asm/arch-armv7/systimer.h
@@ -30,6 +30,8 @@
#define SYSTIMER_RELOAD0x
#define SYSTIMER_EN(1 7)
#define SYSTIMER_32BIT (1 1)
+#define SYSTIMER_PRESC_16 (1 2)
+#define SYSTIMER_PRESC_256 (1 3)
struct systimer {
u32 timer0load; /* 0x00 */
--
1.8.1.2
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[U-Boot] [PATCH v2 02/10] net: calxedaxgmac: enable rx cut-thru
From: Rob Herring rob.herr...@calxeda.com There is no reason to wait for the entire frame to start DMA on receive, so enable rx cut-thru for better performance. Signed-off-by: Rob Herring rob.herr...@calxeda.com --- v2: no change, resend drivers/net/calxedaxgmac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c index e3553d6..803687a 100644 --- a/drivers/net/calxedaxgmac.c +++ b/drivers/net/calxedaxgmac.c @@ -400,7 +400,7 @@ static int xgmac_init(struct eth_device *dev, bd_t * bis) /* set flow control parameters and store and forward mode */ value = (FIFO_MINUS_12K XGMAC_CORE_OMR_RFD_SHIFT) | (FIFO_MINUS_4K XGMAC_CORE_OMR_RFA_SHIFT) | - XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF | XGMAC_CORE_OMR_RSF; + XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF; writel(value, regs-core_opmode); /* enable pause frames */ -- 1.8.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 06/10] ARM: highbank: avoid bss write in timer_init
From: Rob Herring rob.herr...@calxeda.com The timer_init function is called before relocation and writes to bss data were corrupting relocation data. Fix this by removing the call to reset_timer_masked. The initial timer count should be 0 or near 0 anyway, so initializing the variables are not needed. Signed-off-by: Rob Herring rob.herr...@calxeda.com --- v2: no change, resend arch/arm/cpu/armv7/highbank/timer.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/cpu/armv7/highbank/timer.c index d93de1e..832c012 100644 --- a/arch/arm/cpu/armv7/highbank/timer.c +++ b/arch/arm/cpu/armv7/highbank/timer.c @@ -46,8 +46,6 @@ int timer_init(void) writel(SYSTIMER_EN | SYSTIMER_32BIT | SYSTIMER_PRESC_256, systimer_base-timer0control); - reset_timer_masked(); - return 0; } -- 1.8.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 03/10] ARM: highbank: update config options
From: Rob Herring rob.herr...@calxeda.com
Various changes to highbank config:
Enable EFI partitions
Enable ext4 and FAT filesystems
Enable bootz command and raw initrd
Increase cmd and print buffer size to 1K
Change serial baudrate to 115200
Enable hush shell
Signed-off-by: Rob Herring rob.herr...@calxeda.com
---
v2:
- Drop CONFIG_SYS_PROMPT_HUSH_PS2
include/configs/highbank.h | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/include/configs/highbank.h b/include/configs/highbank.h
index 62cc08c..5e5d8e6 100644
--- a/include/configs/highbank.h
+++ b/include/configs/highbank.h
@@ -18,7 +18,9 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_L2_OFF
+#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_NO_FLASH
#define CFG_HZ 1000
@@ -26,6 +28,7 @@
#define CONFIG_OF_LIBFDT
#define CONFIG_FIT
+#define CONFIG_SUPPORT_RAW_INITRD
#define CONFIG_SYS_BOOTMAPSZ (16 20)
/*
@@ -38,7 +41,7 @@
#define CONFIG_PL01x_PORTS { (void *)(0xFFF36000) }
#define CONFIG_CONS_INDEX 0
-#define CONFIG_BAUDRATE38400
+#define CONFIG_BAUDRATE115200
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_SYS_BOOTCOUNT_SINGLEWORD
@@ -54,6 +57,7 @@
CONFIG_SYS_SCSI_MAX_LUN)
#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
#define CONFIG_CALXEDA_XGMAC
@@ -68,12 +72,15 @@
#include config_cmd_default.h
#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
#define CONFIG_CMD_PXE
#define CONFIG_MENU
@@ -84,15 +91,18 @@
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_LONGHELP/* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE
#define CONFIG_SYS_PROMPT Highbank #
+#define CONFIG_SYS_HUSH_PARSER
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_LOAD_ADDR 0x80
+#define CONFIG_SYS_64BIT_LBA
+
/*---
* Physical Memory Map
--
1.8.1.2
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[U-Boot] [PATCH v2 07/10] ARM: highbank: enable reset on command timeout
From: Rob Herring rob.herr...@calxeda.com Enable resetting on command timeout. The timeout is set with environment setting bootretry. Signed-off-by: Rob Herring rob.herr...@calxeda.com --- v2: no change, resend include/configs/highbank.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 5e5d8e6..9bf56c7 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -85,6 +85,9 @@ #define CONFIG_MENU #define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_RESET_TO_RETRY + /* * Miscellaneous configurable options */ -- 1.8.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 09/10] ARM: highbank: compile misc_init_r only if CONFIG_MISC_INIT_R
From: Rob Herring rob.herr...@calxeda.com
Compile misc_init_r only if CONFIG_MISC_INIT_R is enabled.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
---
v2:
- Reword commit message
board/highbank/highbank.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index b224aae..b0c20fe 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -62,6 +62,7 @@ int board_eth_init(bd_t *bis)
return rc;
}
+#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
char envbuffer[16];
@@ -83,6 +84,7 @@ int misc_init_r(void)
return 0;
}
+#endif
int dram_init(void)
{
--
1.8.1.2
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