[U-Boot] [PATCH V2 04/19] imx-common: timer: add i.MX6SLL support

2016-12-11 Thread Peng Fan 
Add i.MX6 SLL GPT timer support.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/imx-common/timer.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index 1f7c671..ee6eff2 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -45,7 +45,7 @@ static inline int gpt_has_clk_source_osc(void)
 #if defined(CONFIG_MX6)
if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
-   is_mx6ull())
+   is_mx6ull() || is_mx6sll())
return 1;
 
return 0;
@@ -84,8 +84,12 @@ int timer_init(void)
if (gpt_has_clk_source_osc()) {
i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
 
-   /* For DL/S, SX, UL, ULL set 24Mhz OSC Enable bit and prescaler 
*/
-   if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull()) {
+   /*
+* For DL/S, SX, UL, ULL, SLL set 24Mhz OSC
+* Enable bit and prescaler
+*/
+   if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
+   is_mx6sll()) {
i |= GPTCR_24MEN;
 
/* Produce 3Mhz clock */
-- 
2.6.2

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[U-Boot] [PATCH V2 02/19] imx: mx6sll: add pinmux header files

2016-12-11 Thread Peng Fan 
Add i.MX6SLL pinmux header files

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/include/asm/arch-mx6/mx6-pins.h|2 +
 arch/arm/include/asm/arch-mx6/mx6sll_pins.h | 1019 +++
 2 files changed, 1021 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mx6/mx6sll_pins.h

diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h 
b/arch/arm/include/asm/arch-mx6/mx6-pins.h
index b9cd670..2934b12 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h
@@ -33,6 +33,8 @@ enum {
MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
 #include "mx6dl_pins.h"
 };
+#elif defined(CONFIG_MX6SLL)
+#include "mx6sll_pins.h"
 #elif defined(CONFIG_MX6SL)
 #include "mx6sl_pins.h"
 #elif defined(CONFIG_MX6SX)
diff --git a/arch/arm/include/asm/arch-mx6/mx6sll_pins.h 
b/arch/arm/include/asm/arch-mx6/mx6sll_pins.h
new file mode 100644
index 000..1ecb7ce
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6sll_pins.h
@@ -0,0 +1,1019 @@
+/*
+ * Copyright (C) 2014 - 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_IMX6SLL_PINS_H__
+#define __ASM_ARCH_IMX6SLL_PINS_H__
+
+#include 
+
+enum {
+   MX6_PAD_WDOG_B__WDOG1_B   = 
IOMUX_PAD(0x02DC, 0x0014, 0, 0x, 0, 0),
+   MX6_PAD_WDOG_B__WDOG1_RESET_B_DEB = 
IOMUX_PAD(0x02DC, 0x0014, 1, 0x, 0, 0),
+   MX6_PAD_WDOG_B__UART5_RI_B= 
IOMUX_PAD(0x02DC, 0x0014, 2, 0x, 0, 0),
+   MX6_PAD_WDOG_B__GPIO3_IO18= 
IOMUX_PAD(0x02DC, 0x0014, 5, 0x, 0, 0),
+
+   MX6_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M  = 
IOMUX_PAD(0x02E0, 0x0018, 0, 0x, 0, 0),
+   MX6_PAD_REF_CLK_24M__I2C3_SCL = 
IOMUX_PAD(0x02E0, 0x0018, IOMUX_CONFIG_SION | 1, 0x068C, 0, 0),
+   MX6_PAD_REF_CLK_24M__PWM3_OUT = 
IOMUX_PAD(0x02E0, 0x0018, 2, 0x, 0, 0),
+   MX6_PAD_REF_CLK_24M__USB_OTG2_ID  = 
IOMUX_PAD(0x02E0, 0x0018, 3, 0x0560, 0, 0),
+   MX6_PAD_REF_CLK_24M__CCM_PMIC_READY   = 
IOMUX_PAD(0x02E0, 0x0018, 4, 0x05AC, 0, 0),
+   MX6_PAD_REF_CLK_24M__GPIO3_IO21   = 
IOMUX_PAD(0x02E0, 0x0018, 5, 0x, 0, 0),
+   MX6_PAD_REF_CLK_24M__SD3_WP   = 
IOMUX_PAD(0x02E0, 0x0018, 6, 0x0794, 0, 0),
+
+   MX6_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K  = 
IOMUX_PAD(0x02E4, 0x001C, 0, 0x, 0, 0),
+   MX6_PAD_REF_CLK_32K__I2C3_SDA = 
IOMUX_PAD(0x02E4, 0x001C, IOMUX_CONFIG_SION | 1, 0x0690, 0, 0),
+   MX6_PAD_REF_CLK_32K__PWM4_OUT = 
IOMUX_PAD(0x02E4, 0x001C, 2, 0x, 0, 0),
+   MX6_PAD_REF_CLK_32K__USB_OTG1_ID  = 
IOMUX_PAD(0x02E4, 0x001C, 3, 0x055C, 0, 0),
+   MX6_PAD_REF_CLK_32K__SD1_LCTL = 
IOMUX_PAD(0x02E4, 0x001C, 4, 0x, 0, 0),
+   MX6_PAD_REF_CLK_32K__GPIO3_IO22   = 
IOMUX_PAD(0x02E4, 0x001C, 5, 0x, 0, 0),
+   MX6_PAD_REF_CLK_32K__SD3_CD_B = 
IOMUX_PAD(0x02E4, 0x001C, 6, 0x0780, 0, 0),
+
+   MX6_PAD_PWM1__PWM1_OUT= 
IOMUX_PAD(0x02E8, 0x0020, 0, 0x, 0, 0),
+   MX6_PAD_PWM1__CCM_CLKO= 
IOMUX_PAD(0x02E8, 0x0020, 1, 0x, 0, 0),
+   MX6_PAD_PWM1__AUDIO_CLK_OUT   = 
IOMUX_PAD(0x02E8, 0x0020, 2, 0x, 0, 0),
+   MX6_PAD_PWM1__CSI_MCLK= 
IOMUX_PAD(0x02E8, 0x0020, 4, 0x, 0, 0),
+   MX6_PAD_PWM1__GPIO3_IO23  = 
IOMUX_PAD(0x02E8, 0x0020, 5, 0x, 0, 0),
+   MX6_PAD_PWM1__EPIT1_OUT   = 
IOMUX_PAD(0x02E8, 0x0020, 6, 0x, 0, 0),
+
+   MX6_PAD_KEY_COL0__KEY_COL0= 
IOMUX_PAD(0x02EC, 0x0024, 0, 0x06A0, 0, 0),
+   MX6_PAD_KEY_COL0__I2C2_SCL= 
IOMUX_PAD(0x02EC, 0x0024, IOMUX_CONFIG_SION | 1, 0x0684, 0, 0),
+   MX6_PAD_KEY_COL0__LCD_DATA00  = 
IOMUX_PAD(0x02EC, 0x0024, 2, 0x06D8, 0, 0),
+   MX6_PAD_KEY_COL0__SD1_CD_B= 
IOMUX_PAD(0x02EC, 0x0024, 4, 0x0770, 1, 0),
+   MX6_PAD_KEY_COL0__GPIO3_IO24  = 
IOMUX_PAD(0x02EC, 0x0024, 5, 0x, 0, 0),
+
+   MX6_PAD_KEY_ROW0__KEY_ROW0= 
IOMUX_PAD(0x02F0, 0x0028, 0, 0x06C0, 0, 0),
+   MX6_PAD_KEY_ROW0__I2C2_SDA= 
IOMUX_PAD(0x02F0, 0x0028, IOMUX_CONFIG_SION | 1, 0x0688, 0, 0),
+   MX6_PAD_KEY_ROW0__LCD_DATA01  = 
IOMUX_PAD(0x02F0, 0x0028, 2, 0x06DC, 0, 0),
+   MX6_PAD_KEY_ROW0__SD1_WP  = 
IOMUX_PAD(0x02F0, 0x0028, 4, 0x0774, 1, 0),
+

[U-Boot] [PATCH V2 07/19] imx: mx6: lcdif: gate clock before changing mux

2016-12-11 Thread Peng Fan 
The mux for the lcd clock is not glitchless,
so need to first gate the clock before changing the mux.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/cpu/armv7/mx6/clock.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 88f68f1..2092260 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -771,6 +771,16 @@ int enable_lcdif_clock(u32 base_addr)
return 0;
}
 
+   /* Gate LCDIF clock first */
+   reg = readl(_ccm->CCGR3);
+   reg &= ~lcdif_ccgr3_mask;
+   writel(reg, _ccm->CCGR3);
+
+   reg = readl(_ccm->CCGR2);
+   reg &= ~MXC_CCM_CCGR2_LCD_MASK;
+   writel(reg, _ccm->CCGR2);
+
+   /* Select pre-mux */
reg = readl(_ccm->cscdr2);
reg &= ~lcdif_clk_sel_mask;
writel(reg, _ccm->cscdr2);
-- 
2.6.2

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[U-Boot] [PATCH V2 03/19] imx: mx6sll: update register address

2016-12-11 Thread Peng Fan 
Update register address for i.MX6 SLL

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/include/asm/arch-mx6/imx-regs.h | 77 +---
 1 file changed, 50 insertions(+), 27 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 8bb36eb..6727c56 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -26,7 +26,7 @@
 #define APBH_DMA_ARB_END_ADDR   0x0180BFFF
 #define M4_BOOTROM_BASE_ADDR   0x007F8000
 
-#else
+#elif !defined(CONFIG_MX6SLL)
 #define CAAM_ARB_BASE_ADDR  0x0010
 #define CAAM_ARB_END_ADDR   0x00103FFF
 #define APBH_DMA_ARB_BASE_ADDR  0x0011
@@ -46,13 +46,9 @@
 #define MXS_BCH_BASE   (APBH_DMA_ARB_BASE_ADDR + 0x04000)
 
 /* GPV - PL301 configuration ports */
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+   defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL))
 #define GPV2_BASE_ADDR  0x00D0
-#else
-#define GPV2_BASE_ADDR 0x0020
-#endif
-
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 #define GPV3_BASE_ADDR 0x00E0
 #define GPV4_BASE_ADDR 0x00F0
 #define GPV5_BASE_ADDR 0x0100
@@ -61,6 +57,7 @@
 #define PCIE_ARB_END_ADDR   0x08FF
 
 #else
+#define GPV2_BASE_ADDR 0x0020
 #define GPV3_BASE_ADDR 0x0030
 #define GPV4_BASE_ADDR 0x0080
 #define PCIE_ARB_BASE_ADDR  0x0100
@@ -96,7 +93,7 @@
 #define WEIM_ARB_END_ADDR   0x57FF
 #define QSPI0_AMBA_BASE 0x6000
 #define QSPI0_AMBA_END  0x6FFF
-#else
+#elif !defined(CONFIG_MX6SLL)
 #define SATA_ARB_BASE_ADDR  0x0220
 #define SATA_ARB_END_ADDR   0x02203FFF
 #define OPENVG_ARB_BASE_ADDR0x02204000
@@ -111,7 +108,8 @@
 #define WEIM_ARB_END_ADDR   0x0FFF
 #endif
 
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+#if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
+   defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 #define MMDC0_ARB_BASE_ADDR 0x8000
 #define MMDC0_ARB_END_ADDR  0x
 #define MMDC1_ARB_BASE_ADDR 0xC000
@@ -141,19 +139,21 @@
 #define ECSPI2_BASE_ADDR(ATZ1_BASE_ADDR + 0x0C000)
 #define ECSPI3_BASE_ADDR(ATZ1_BASE_ADDR + 0x1)
 #define ECSPI4_BASE_ADDR(ATZ1_BASE_ADDR + 0x14000)
-#ifdef CONFIG_MX6SL
-#define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
-#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2)
-#define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
-#define SSI1_IPS_BASE_ADDR  (ATZ1_BASE_ADDR + 0x28000)
-#define SSI2_IPS_BASE_ADDR  (ATZ1_BASE_ADDR + 0x2C000)
-#define SSI3_IPS_BASE_ADDR  (ATZ1_BASE_ADDR + 0x3)
-#define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
-#define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
-#else
+
+#define MX6SL_UART5_BASE_ADDR   (ATZ1_BASE_ADDR + 0x18000)
+#define MX6SLL_UART4_BASE_ADDR  (ATZ1_BASE_ADDR + 0x18000)
+#define MX6UL_UART7_BASE_ADDR   (ATZ1_BASE_ADDR + 0x18000)
+#define MX6SL_UART2_BASE_ADDR   (ATZ1_BASE_ADDR + 0x24000)
+#define MX6SLL_UART2_BASE_ADDR  (ATZ1_BASE_ADDR + 0x24000)
+#define MX6UL_UART8_BASE_ADDR   (ATZ1_BASE_ADDR + 0x24000)
+#define MX6SL_UART3_BASE_ADDR   (ATZ1_BASE_ADDR + 0x34000)
+#define MX6SLL_UART3_BASE_ADDR  (ATZ1_BASE_ADDR + 0x34000)
+#define MX6SL_UART4_BASE_ADDR   (ATZ1_BASE_ADDR + 0x38000)
+
 #ifndef CONFIG_MX6SX
 #define ECSPI5_BASE_ADDR(ATZ1_BASE_ADDR + 0x18000)
 #endif
+#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2)
 #define UART1_BASE  (ATZ1_BASE_ADDR + 0x2)
 #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
 #define UART8_BASE  (ATZ1_BASE_ADDR + 0x24000)
@@ -161,7 +161,6 @@
 #define SSI2_BASE_ADDR  (ATZ1_BASE_ADDR + 0x2C000)
 #define SSI3_BASE_ADDR  (ATZ1_BASE_ADDR + 0x3)
 #define ASRC_BASE_ADDR  (ATZ1_BASE_ADDR + 0x34000)
-#endif
 
 #ifndef CONFIG_MX6SX
 #define SPBA_BASE_ADDR  (ATZ1_BASE_ADDR + 0x3C000)
@@ -176,6 +175,8 @@
 #define PWM4_BASE_ADDR  (AIPS1_OFF_BASE_ADDR + 0xC000)
 #define CAN1_BASE_ADDR  (AIPS1_OFF_BASE_ADDR + 0x1)
 #define CAN2_BASE_ADDR  (AIPS1_OFF_BASE_ADDR + 0x14000)
+/* QOSC on i.MX6SLL */
+#define QOSC_BASE_ADDR  (AIPS1_OFF_BASE_ADDR + 0x14000)
 #define GPT1_BASE_ADDR  (AIPS1_OFF_BASE_ADDR + 0x18000)
 #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
 #define

[U-Boot] [PATCH V2 09/19] imx: clock: gate clk before changing pix clk mux

2016-12-11 Thread Peng Fan 
The LCDIF Pixel clock mux is not glitchless, so need
to gate before changing mux.

Also change enable_lcdif_clock prototype with a new input
parameter to indicate disable or enable.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/cpu/armv7/mx6/clock.c| 50 ++-
 arch/arm/include/asm/arch-mx6/clock.h |  2 +-
 board/freescale/mx6sxsabresd/mx6sxsabresd.c   |  2 +-
 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c |  2 +-
 4 files changed, 33 insertions(+), 23 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 007c135..de3665f 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -707,6 +707,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
return;
 
+   enable_lcdif_clock(base_addr, 0);
if (!is_mx6sl()) {
/* Select pre-lcd clock to PLL5 and set pre divider */
clrsetbits_le32(_ccm->cscdr2,
@@ -736,11 +737,14 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
(((postd - 1)^0x6) <<
 MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET));
}
+
+   enable_lcdif_clock(base_addr, 1);
} else if (is_mx6sx()) {
/* Setting LCDIF2 for i.MX6SX */
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
return;
 
+   enable_lcdif_clock(base_addr, 0);
/* Select pre-lcd clock to PLL5 and set pre divider */
clrsetbits_le32(_ccm->cscdr2,
MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
@@ -754,10 +758,12 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
((postd - 1) <<
 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
+
+   enable_lcdif_clock(base_addr, 1);
}
 }
 
-int enable_lcdif_clock(u32 base_addr)
+int enable_lcdif_clock(u32 base_addr, bool enable)
 {
u32 reg = 0;
u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
@@ -796,15 +802,17 @@ int enable_lcdif_clock(u32 base_addr)
 MXC_CCM_CCGR3_LCDIF_PIX_MASK);
writel(reg, _ccm->CCGR3);
 
-   reg = readl(_ccm->cscdr3);
-   reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK;
-   reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET;
-   writel(reg, _ccm->cscdr3);
+   if (enable) {
+   reg = readl(_ccm->cscdr3);
+   reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK;
+   reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET;
+   writel(reg, _ccm->cscdr3);
 
-   reg = readl(_ccm->CCGR3);
-   reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK |
-   MXC_CCM_CCGR3_LCDIF_PIX_MASK;
-   writel(reg, _ccm->CCGR3);
+   reg = readl(_ccm->CCGR3);
+   reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK |
+   MXC_CCM_CCGR3_LCDIF_PIX_MASK;
+   writel(reg, _ccm->CCGR3);
+   }
 
return 0;
} else {
@@ -820,19 +828,21 @@ int enable_lcdif_clock(u32 base_addr)
reg &= ~MXC_CCM_CCGR2_LCD_MASK;
writel(reg, _ccm->CCGR2);
 
-   /* Select pre-mux */
-   reg = readl(_ccm->cscdr2);
-   reg &= ~lcdif_clk_sel_mask;
-   writel(reg, _ccm->cscdr2);
+   if (enable) {
+   /* Select pre-mux */
+   reg = readl(_ccm->cscdr2);
+   reg &= ~lcdif_clk_sel_mask;
+   writel(reg, _ccm->cscdr2);
 
-   /* Enable the LCDIF pix clock */
-   reg = readl(_ccm->CCGR3);
-   reg |= lcdif_ccgr3_mask;
-   writel(reg, _ccm->CCGR3);
+   /* Enable the LCDIF pix clock */
+   reg = readl(_ccm->CCGR3);
+   reg |= lcdif_ccgr3_mask;
+   writel(reg, _ccm->CCGR3);
 
-   reg = readl(_ccm->CCGR2);
-   reg |= MXC_CCM_CCGR2_LCD_MASK;
-   writel(reg, _ccm->CCGR2);
+   reg = readl(_ccm->CCGR2);
+   reg |= MXC_CCM_CCGR2_LCD_MASK;
+   writel(reg, _ccm->CCGR2);
+   }
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-mx6/clock.h 
b/arch/arm/include/asm/arch-mx6/clock.h
index ed1433e..2d9c45e 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -74,7 +74,7 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num);
 void enable_ipu_clock(void);
 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
 void enable_enet_clk(unsigned char enable);
-int enable_lcdif_clock(u32 base_addr);

[U-Boot] [PATCH V2 00/19] imx: add i.MX6SLL support

2016-12-11 Thread Peng Fan 
This patch set is to add i.MX6SLL support.
1. There are also a few patches to fix bugs in this patchset.
2. Default add device tree support.
3. Add two defconfigs, one for DCD, the other for plugin.

V2 changes:
 Patch 16/19: Add Simon's review tag
 Patch 18/19: Change PHYS_SDRAM_SIZE to imx_ddr_size()

Peng Fan (19):
  imx: add i.MX 6SLL CPU type
  imx: mx6sll: add pinmux header files
  imx: mx6sll: update register address
  imx-common: timer: add i.MX6SLL support
  imx: mx6sll: add iomux settings
  imx: mx6: fix mmdc ch0 clk for 6SL
  imx: mx6: lcdif: gate clock before changing mux
  imx: mx6sl: add lcdif clock support
  imx: clock: gate clk before changing pix clk mux
  imx: mx6sll: add clock support
  imx-common: cache: configure L2 Cache for i.MX6SLL
  imx: mx6sll: add Kconfig entry for i.MX6SLL
  mx6_common: correct loadaddr and text base for i.MX6SLL
  OCOTP: Update OCOTP driver to support i.MX6SLL
  imx-common: lcdif: update lcdif regs for i.MX6SL/SLL
  pinctrl: imx6: support i.MX6SLL
  arm: dts: add i.MX6SLL device tree
  arm: imx: add i.MX6SLL EVK board support
  imx: mx6sllevk: add plugin support

 arch/arm/cpu/armv7/mx6/Kconfig|   11 +
 arch/arm/cpu/armv7/mx6/clock.c|  143 ++-
 arch/arm/dts/Makefile |1 +
 arch/arm/dts/imx6sll-evk.dts  |  801 
 arch/arm/dts/imx6sll-pinfunc.h|  882 ++
 arch/arm/dts/imx6sll.dtsi |  859 +
 arch/arm/imx-common/cache.c   |   17 +-
 arch/arm/imx-common/cpu.c |2 +
 arch/arm/imx-common/iomux-v3.c|   10 +-
 arch/arm/imx-common/timer.c   |   10 +-
 arch/arm/include/asm/arch-imx/cpu.h   |3 +-
 arch/arm/include/asm/arch-mx6/clock.h |2 +-
 arch/arm/include/asm/arch-mx6/crm_regs.h  |   21 +
 arch/arm/include/asm/arch-mx6/imx-regs.h  |   77 +-
 arch/arm/include/asm/arch-mx6/mx6-pins.h  |2 +
 arch/arm/include/asm/arch-mx6/mx6sll_pins.h   | 1019 +
 arch/arm/include/asm/imx-common/iomux-v3.h|6 +-
 arch/arm/include/asm/imx-common/regs-lcdif.h  |7 +-
 arch/arm/include/asm/imx-common/sys_proto.h   |1 +
 board/freescale/mx6sllevk/Kconfig |   12 +
 board/freescale/mx6sllevk/Makefile|6 +
 board/freescale/mx6sllevk/imximage.cfg|  127 +++
 board/freescale/mx6sllevk/mx6sllevk.c |  131 +++
 board/freescale/mx6sllevk/plugin.S|  155 
 board/freescale/mx6sxsabresd/mx6sxsabresd.c   |2 +-
 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c |2 +-
 configs/mx6sllevk_defconfig   |   36 +
 configs/mx6sllevk_plugin_defconfig|   37 +
 drivers/misc/mxc_ocotp.c  |   16 +-
 drivers/pinctrl/nxp/pinctrl-imx6.c|2 +
 include/configs/mx6_common.h  |3 +-
 include/configs/mx6sllevk.h   |  152 +++
 include/dt-bindings/clock/imx6sll-clock.h |  204 +
 33 files changed, 4668 insertions(+), 91 deletions(-)
 create mode 100644 arch/arm/dts/imx6sll-evk.dts
 create mode 100644 arch/arm/dts/imx6sll-pinfunc.h
 create mode 100644 arch/arm/dts/imx6sll.dtsi
 create mode 100644 arch/arm/include/asm/arch-mx6/mx6sll_pins.h
 create mode 100644 board/freescale/mx6sllevk/Kconfig
 create mode 100644 board/freescale/mx6sllevk/Makefile
 create mode 100644 board/freescale/mx6sllevk/imximage.cfg
 create mode 100644 board/freescale/mx6sllevk/mx6sllevk.c
 create mode 100644 board/freescale/mx6sllevk/plugin.S
 create mode 100644 configs/mx6sllevk_defconfig
 create mode 100644 configs/mx6sllevk_plugin_defconfig
 create mode 100644 include/configs/mx6sllevk.h
 create mode 100644 include/dt-bindings/clock/imx6sll-clock.h

-- 
2.6.2

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[U-Boot] [PATCH V2 01/19] imx: add i.MX 6SLL CPU type

2016-12-11 Thread Peng Fan 
Add i.MX6SLL cpu type.
MXC_CPU_MX6D is not a real value in chip, so change it to 0x6A.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/imx-common/cpu.c   | 2 ++
 arch/arm/include/asm/arch-imx/cpu.h | 3 ++-
 arch/arm/include/asm/imx-common/sys_proto.h | 1 +
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 632faca..40fe813 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -155,6 +155,8 @@ const char *get_imx_type(u32 imxtype)
return "6SOLO"; /* Solo version of the mx6 */
case MXC_CPU_MX6SL:
return "6SL";   /* Solo-Lite version of the mx6 */
+   case MXC_CPU_MX6SLL:
+   return "6SLL";  /* SLL version of the mx6 */
case MXC_CPU_MX6SX:
return "6SX";   /* SoloX version of the mx6 */
case MXC_CPU_MX6UL:
diff --git a/arch/arm/include/asm/arch-imx/cpu.h 
b/arch/arm/include/asm/arch-imx/cpu.h
index 667115b0..8bd1421 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -19,7 +19,8 @@
 #define MXC_CPU_MX6UL  0x64
 #define MXC_CPU_MX6ULL 0x65
 #define MXC_CPU_MX6SOLO0x66 /* dummy */
-#define MXC_CPU_MX6D   0x67
+#define MXC_CPU_MX6SLL 0x67
+#define MXC_CPU_MX6D   0x6A
 #define MXC_CPU_MX6DP  0x68
 #define MXC_CPU_MX6QP  0x69
 #define MXC_CPU_MX7S   0x71 /* dummy ID */
diff --git a/arch/arm/include/asm/imx-common/sys_proto.h 
b/arch/arm/include/asm/imx-common/sys_proto.h
index 005435a..539d34b 100644
--- a/arch/arm/include/asm/imx-common/sys_proto.h
+++ b/arch/arm/include/asm/imx-common/sys_proto.h
@@ -36,6 +36,7 @@
 #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
 #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
 #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
+#define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
 
 u32 get_nr_cpus(void);
 u32 get_cpu_rev(void);
-- 
2.6.2

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[U-Boot] [PATCH V2 08/19] imx: mx6sl: add lcdif clock support

2016-12-11 Thread Peng Fan 
Add lcdif clock support for i.MX6SL.

Signed-off-by: Peng Fan 
---
 arch/arm/cpu/armv7/mx6/clock.c   | 78 
 arch/arm/include/asm/arch-mx6/crm_regs.h | 21 +
 2 files changed, 80 insertions(+), 19 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 2092260..007c135 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -625,16 +625,18 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 
debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
 
-   if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull()) {
+   if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) {
debug("This chip not support lcd!\n");
return;
}
 
-   if (base_addr == LCDIF1_BASE_ADDR) {
-   reg = readl(_ccm->cscdr2);
-   /* Can't change clocks when clock not from pre-mux */
-   if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
-   return;
+   if (!is_mx6sl()) {
+   if (base_addr == LCDIF1_BASE_ADDR) {
+   reg = readl(_ccm->cscdr2);
+   /* Can't change clocks when clock not from pre-mux */
+   if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
+   return;
+   }
}
 
if (is_mx6sx()) {
@@ -705,19 +707,35 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
return;
 
-   /* Select pre-lcd clock to PLL5 and set pre divider */
-   clrsetbits_le32(_ccm->cscdr2,
-   MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
-   MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
-   (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
-   ((pred - 1) <<
-MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
-
-   /* Set the post divider */
-   clrsetbits_le32(_ccm->cbcmr,
-   MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
-   ((postd - 1) <<
-MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
+   if (!is_mx6sl()) {
+   /* Select pre-lcd clock to PLL5 and set pre divider */
+   clrsetbits_le32(_ccm->cscdr2,
+   MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
+   MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
+   (0x2 << 
MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
+   ((pred - 1) <<
+MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
+
+   /* Set the post divider */
+   clrsetbits_le32(_ccm->cbcmr,
+   MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
+   ((postd - 1) <<
+   MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
+   } else {
+   /* Select pre-lcd clock to PLL5 and set pre divider */
+   clrsetbits_le32(_ccm->cscdr2,
+   MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK |
+   MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK,
+   (0x2 << 
MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET) |
+   ((pred - 1) <<
+
MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET));
+
+   /* Set the post divider */
+   clrsetbits_le32(_ccm->cscmr1,
+   MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK,
+   (((postd - 1)^0x6) <<
+MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET));
+   }
} else if (is_mx6sx()) {
/* Setting LCDIF2 for i.MX6SX */
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
@@ -767,6 +785,28 @@ int enable_lcdif_clock(u32 base_addr)
/* Set to pre-mux clock at default */
lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
lcdif_ccgr3_mask =  MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
+   } else if (is_mx6sl()) {
+   if (base_addr != LCDIF1_BASE_ADDR) {
+   puts("Wrong LCD interface!\n");
+   return -EINVAL;
+   }
+
+   reg = readl(_ccm->CCGR3);
+   reg &= ~(MXC_CCM_CCGR3_LCDIF_AXI_MASK |
+MXC_CCM_CCGR3_LCDIF_PIX_MASK);
+   writel(reg, _ccm->CCGR3);
+
+   reg = readl(_ccm->cscdr3);
+   reg &=

[U-Boot] [PATCH V2 11/19] imx-common: cache: configure L2 Cache for i.MX6SLL

2016-12-11 Thread Peng Fan 
If L2 cache configured as OCRAM, reset it.
Switch to use runtime check.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/imx-common/cache.c | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c
index b775488..1c4a9a2 100644
--- a/arch/arm/imx-common/cache.c
+++ b/arch/arm/imx-common/cache.c
@@ -8,6 +8,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
@@ -39,6 +40,7 @@ void enable_caches(void)
 void v7_outer_cache_enable(void)
 {
struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+   struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
unsigned int val;
 
 
@@ -55,15 +57,14 @@ void v7_outer_cache_enable(void)
 */
setbits_le32(>pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
 
-#if defined CONFIG_MX6SL
-   struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-   val = readl(>gpr[11]);
-   if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
-   /* L2 cache configured as OCRAM, reset it */
-   val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
-   writel(val, >gpr[11]);
+   if (is_mx6sl() || is_mx6sll()) {
+   val = readl(>gpr[11]);
+   if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
+   /* L2 cache configured as OCRAM, reset it */
+   val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
+   writel(val, >gpr[11]);
+   }
}
-#endif
 
writel(0x132, >pl310_tag_latency_ctrl);
writel(0x132, >pl310_data_latency_ctrl);
-- 
2.6.2

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[U-Boot] [PATCH V2 06/19] imx: mx6: fix mmdc ch0 clk for 6SL

2016-12-11 Thread Peng Fan 
>From RM, per_periph2_clk_sel option3 is:
"derive clock from 198MHz clock (divided 392MHz PLL2 PFD)."

So fix it.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/cpu/armv7/mx6/clock.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 2995628..88f68f1 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -514,6 +514,11 @@ static u32 get_mmdc_ch0_clk(void)
freq = mxc_get_pll_pfd(PLL_BUS, 0);
break;
case 3:
+   if (is_mx6sl()) {
+   freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1;
+   break;
+   }
+
pmu_misc2_audio_div = 
PMU_MISC2_AUDIO_DIV(__raw_readl(_ccm->pmu_misc2));
switch (pmu_misc2_audio_div) {
case 0:
-- 
2.6.2

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[U-Boot] pull request: u-boot-uniphier/master

2016-12-11 Thread Masahiro Yamada 
Hi Tom,

Please pull some updates for v2017.01-rc2, thanks!
  - DT sync with Linux
  - Disable CONFIG_ARCH_FIXUP_FDT_MEMORY
  - Minor fixes

The following changes since commit 361a879902a3cbdb692149a1ac580e3199e771ba:

  Revert "Merge branch 'master' of
git://www.denx.de/git/u-boot-microblaze" (2016-12-09 07:56:54 -0500)

are available in the git repository at:

  git://git.denx.de/u-boot-uniphier.git master

for you to fetch changes up to 6c498835af560ad850de4dad4ff8c60d26ef2898:

  ARM: uniphier: remove BLK select (2016-12-11 17:55:13 +0900)


Masahiro Yamada (5):
  ARM: uniphier: remove unneeded initializer
  ARM: uniphier: remove unneeded parentheses
  ARM: uniphier: disable CONFIG_ARCH_FIXUP_FDT_MEMORY
  ARM: dts: uniphier: sync Device Tree with Linux
  ARM: uniphier: remove BLK select

 arch/arm/Kconfig |   1 -
 arch/arm/dts/uniphier-common32.dtsi  | 177 --
 arch/arm/dts/uniphier-ld11.dtsi  | 111 +++-
 arch/arm/dts/uniphier-ld20.dtsi  | 188 +--
 arch/arm/dts/uniphier-ld4.dtsi   | 651 +-
 arch/arm/dts/uniphier-pro4-ref.dts   |  10 +-
 arch/arm/dts/uniphier-pro4.dtsi  | 903 +-
 arch/arm/dts/uniphier-pro5.dtsi  | 925 +++
 arch/arm/dts/uniphier-pxs2-gentil.dts|   2 +-
 arch/arm/dts/uniphier-pxs2-vodka.dts |   2 +-
 arch/arm/dts/uniphier-pxs2.dtsi  | 878 +
 arch/arm/dts/uniphier-sld3.dtsi  |  37 +-
 arch/arm/dts/uniphier-sld8.dtsi  | 651 +-
 arch/arm/mach-uniphier/dram/umc-ld20.c   |   6 +-
 arch/arm/mach-uniphier/memconf/memconf.c |   6 +-
 configs/uniphier_ld11_defconfig  |   1 +
 configs/uniphier_ld20_defconfig  |   1 +
 configs/uniphier_ld4_sld8_defconfig  |   1 +
 configs/uniphier_pro4_defconfig  |   1 +
 configs/uniphier_pxs2_ld6b_defconfig |   1 +
 configs/uniphier_sld3_defconfig  |   1 +
 21 files changed, 2697 insertions(+), 1857 deletions(-)
 delete mode 100644 arch/arm/dts/uniphier-common32.dtsi


-- 
Best Regards
Masahiro Yamada
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[U-Boot] [PATCH 1/3] fdt: add memory bank decoding functions for board setup

2016-12-11 Thread Nathan Rossi 
Add two functions for use by board implementations to decode the memory
banks of the /memory node so as to populate the global data with
ram_size and board info for memory banks.

The fdtdec_setup_memory_size() function decodes the first memory bank
and sets up the gd->ram_size with the size of the memory bank. This
function should be called from the boards dram_init().

The fdtdec_setup_memory_banksize() function decode the memory banks
(up to the CONFIG_NR_DRAM_BANKS) and populates the base address and size
into the gd->bd->bi_dram array of banks. This function should be called
from the boards dram_init_banksize().

Signed-off-by: Nathan Rossi 
Cc: Simon Glass 
Cc: Michal Simek 
---
This implementation of decoding has been tested on zynq and zynqmp
boards with address/size cells of (1, 1), (1, 2), (2, 1), (2, 2) and
up to 2 memory banks.
---
 include/fdtdec.h | 25 +
 lib/fdtdec.c | 54 ++
 2 files changed, 79 insertions(+)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 27887c8c21..59a204b571 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -976,6 +976,31 @@ struct display_timing {
  */
 int fdtdec_decode_display_timing(const void *blob, int node, int index,
 struct display_timing *config);
+
+/**
+ * fdtdec_setup_memory_size() - decode and setup gd->ram_size
+ *
+ * Decode the /memory 'reg' property to determine the size of the first memory
+ * bank, populate the global data with the size of the first bank of memory.
+ * This function should be called from the boards dram_init().
+ *
+ * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or
+ * invalid
+ */
+int fdtdec_setup_memory_size(void);
+
+/**
+ * fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram
+ *
+ * Decode the /memory 'reg' property to determine the address and size of the
+ * memory banks. Use this data to populate the global data board info with the
+ * phys address and size of memory banks. This function should be called from
+ * the boards dram_init_banksize().
+ *
+ * @return 0 if OK, negative on error
+ */
+int fdtdec_setup_memory_banksize(void);
+
 /**
  * Set up the device tree ready for use
  */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 4e619c49a2..bc3be017b6 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1174,6 +1174,60 @@ int fdtdec_decode_display_timing(const void *blob, int 
parent, int index,
return ret;
 }
 
+int fdtdec_setup_memory_size(void)
+{
+   int ret, mem;
+   struct fdt_resource res;
+
+   mem = fdt_path_offset(gd->fdt_blob, "/memory");
+   if (mem < 0) {
+   debug("%s: Missing /memory node\n", __func__);
+   return -EINVAL;
+   }
+
+   ret = fdt_get_resource(gd->fdt_blob, mem, "reg", 0, );
+   if (ret != 0) {
+   debug("%s: Unable to decode first memory bank\n", __func__);
+   return -EINVAL;
+   }
+
+   gd->ram_size = (phys_size_t)(res.end - res.start + 1);
+   debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
+
+   return 0;
+}
+
+int fdtdec_setup_memory_banksize(void)
+{
+   int bank, ret, mem;
+   struct fdt_resource res;
+
+   mem = fdt_path_offset(gd->fdt_blob, "/memory");
+   if (mem < 0) {
+   debug("%s: Missing /memory node\n", __func__);
+   return -EINVAL;
+   }
+
+   for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+   ret = fdt_get_resource(gd->fdt_blob, mem, "reg", bank, );
+   if (ret == -FDT_ERR_NOTFOUND)
+   break;
+   if (ret != 0)
+   return ret;
+
+   gd->bd->bi_dram[bank].start = (phys_addr_t)res.start;
+   gd->bd->bi_dram[bank].size =
+   (phys_size_t)(res.end - res.start + 1);
+
+   debug("%s: DRAM Bank #%d: start = 0x%llx, size = 0x%llx\n",
+ __func__, bank,
+ (unsigned long long)gd->bd->bi_dram[bank].start,
+ (unsigned long long)gd->bd->bi_dram[bank].size);
+   }
+
+   return 0;
+}
+
 int fdtdec_setup(void)
 {
 #if CONFIG_IS_ENABLED(OF_CONTROL)
-- 
2.10.2

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[U-Boot] [PATCH 2/3] ARM: zynq: Replace board specific with generic memory bank decoding

2016-12-11 Thread Nathan Rossi 
The dram_init and dram_init_banksize functions were using a board
specific implementation for decoding the memory banks from the fdt. This
board specific implementation uses a static variable 'tmp' which makes
these functions unsafe for execution from within the board_init_f
context.

This unsafe use of a static variable was causing a specific bug when
using the zynq_zybo configuration, U-Boot would generate the following
error during image load. This was caused due to dram_init overwriting
the relocations for the 'image' variable within the do_bootm function.
Out of coincidence the un-initialized memory has a compression type
which is the same as the value for the relocation type R_ARM_RELATIVE.

   Uncompressing Invalid Image ... Unimplemented compression type 23

It should be noted that this is just one way the issue could surface,
other cases my not be observed in normal boot flow. Depending on the
size of various sections, and location of relocations within __rel_dyn
and the compiler/linker the outcome of this bug can differ greatly.

This change makes the dram_init* functions use a generic implementation
of decoding and populating memory bank and size data.

Signed-off-by: Nathan Rossi 
Fixes: 758f29d0f8 ("ARM: zynq: Support systems with more memory banks")
Cc: Michal Simek 
---
 board/xilinx/zynq/board.c | 112 ++
 1 file changed, 3 insertions(+), 109 deletions(-)

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 2c86940957..5cd9bbf711 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -124,121 +124,15 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 }
 
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
-/*
- * fdt_get_reg - Fill buffer by information from DT
- */
-static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
-  const u32 *cell, int n)
-{
-   int i = 0, b, banks;
-   int parent_offset = fdt_parent_offset(fdt, nodeoffset);
-   int address_cells = fdt_address_cells(fdt, parent_offset);
-   int size_cells = fdt_size_cells(fdt, parent_offset);
-   char *p = buf;
-   u64 val;
-   u64 vals;
-
-   debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
- __func__, address_cells, size_cells, buf, cell);
-
-   /* Check memory bank setup */
-   banks = n % (address_cells + size_cells);
-   if (banks)
-   panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
- n, address_cells, size_cells);
-
-   banks = n / (address_cells + size_cells);
-
-   for (b = 0; b < banks; b++) {
-   debug("%s: Bank #%d:\n", __func__, b);
-   if (address_cells == 2) {
-   val = cell[i + 1];
-   val <<= 32;
-   val |= cell[i];
-   val = fdt64_to_cpu(val);
-   debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
- __func__, val, p, [i]);
-   *(phys_addr_t *)p = val;
-   } else {
-   debug("%s: addr32=%x, ptr=%p\n",
- __func__, fdt32_to_cpu(cell[i]), p);
-   *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
-   }
-   p += sizeof(phys_addr_t);
-   i += address_cells;
-
-   debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
- sizeof(phys_addr_t));
-
-   if (size_cells == 2) {
-   vals = cell[i + 1];
-   vals <<= 32;
-   vals |= cell[i];
-   vals = fdt64_to_cpu(vals);
-
-   debug("%s: size64=%llx, ptr=%p, cell=%p\n",
- __func__, vals, p, [i]);
-   *(phys_size_t *)p = vals;
-   } else {
-   debug("%s: size32=%x, ptr=%p\n",
- __func__, fdt32_to_cpu(cell[i]), p);
-   *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
-   }
-   p += sizeof(phys_size_t);
-   i += size_cells;
-
-   debug("%s: ps=%p, i=%x, size=%zu\n",
- __func__, p, i, sizeof(phys_size_t));
-   }
-
-   /* Return the first address size */
-   return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
-}
-
-#define FDT_REG_SIZE  sizeof(u32)
-/* Temp location for sharing data for storing */
-/* Up to 64-bit address + 64-bit size */
-static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
-
 void dram_init_banksize(void)
 {
-   int bank;
-
-   memcpy(>bd->bi_dram[0], , sizeof(tmp));
-
-   for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-   debug("Bank #%d: start %llx\n", bank,
- (unsigned long

[U-Boot] [PATCH 0/3] Add generic FDT memory bank decoding and gd initialization

2016-12-11 Thread Nathan Rossi 
This series adds two functions for handling the memory bank decoding and
initialization of global data for use by boards in their dram_init and
dram_init_banksize functions.

The series also changes the zynq and zynqmp board implementations to use
these functions to resolve a issue with static variable use.

Nathan Rossi (3):
  fdt: add memory bank decoding functions for board setup
  ARM: zynq: Replace board specific with generic memory bank decoding
  ARM64: zynqmp: Replace board specific with generic memory bank
decoding

 board/xilinx/zynq/board.c| 112 ++-
 board/xilinx/zynqmp/zynqmp.c | 112 ++-
 include/fdtdec.h |  25 ++
 lib/fdtdec.c |  54 +
 4 files changed, 85 insertions(+), 218 deletions(-)

-- 
2.10.2
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[U-Boot] [PATCH 3/3] ARM64: zynqmp: Replace board specific with generic memory bank decoding

2016-12-11 Thread Nathan Rossi 
The dram_init and dram_init_banksize functions were using a board
specific implementation for decoding the memory banks from the fdt. This
board specific implementation uses a static variable 'tmp' which makes
these functions unsafe for execution from within the board_init_f
context.

This change makes the dram_init* functions use a generic implementation
of decoding and populating memory bank and size data.

Signed-off-by: Nathan Rossi 
Fixes: 8d59d7f63b ("ARM64: zynqmp: Read RAM information from DT")
Cc: Michal Simek 
---
 board/xilinx/zynqmp/zynqmp.c | 112 ++-
 1 file changed, 3 insertions(+), 109 deletions(-)

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index cef1f6a13a..8a3d0043b9 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -180,121 +180,15 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 }
 
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
-/*
- * fdt_get_reg - Fill buffer by information from DT
- */
-static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
-  const u32 *cell, int n)
-{
-   int i = 0, b, banks;
-   int parent_offset = fdt_parent_offset(fdt, nodeoffset);
-   int address_cells = fdt_address_cells(fdt, parent_offset);
-   int size_cells = fdt_size_cells(fdt, parent_offset);
-   char *p = buf;
-   u64 val;
-   u64 vals;
-
-   debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
- __func__, address_cells, size_cells, buf, cell);
-
-   /* Check memory bank setup */
-   banks = n % (address_cells + size_cells);
-   if (banks)
-   panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
- n, address_cells, size_cells);
-
-   banks = n / (address_cells + size_cells);
-
-   for (b = 0; b < banks; b++) {
-   debug("%s: Bank #%d:\n", __func__, b);
-   if (address_cells == 2) {
-   val = cell[i + 1];
-   val <<= 32;
-   val |= cell[i];
-   val = fdt64_to_cpu(val);
-   debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
- __func__, val, p, [i]);
-   *(phys_addr_t *)p = val;
-   } else {
-   debug("%s: addr32=%x, ptr=%p\n",
- __func__, fdt32_to_cpu(cell[i]), p);
-   *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
-   }
-   p += sizeof(phys_addr_t);
-   i += address_cells;
-
-   debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
- sizeof(phys_addr_t));
-
-   if (size_cells == 2) {
-   vals = cell[i + 1];
-   vals <<= 32;
-   vals |= cell[i];
-   vals = fdt64_to_cpu(vals);
-
-   debug("%s: size64=%llx, ptr=%p, cell=%p\n",
- __func__, vals, p, [i]);
-   *(phys_size_t *)p = vals;
-   } else {
-   debug("%s: size32=%x, ptr=%p\n",
- __func__, fdt32_to_cpu(cell[i]), p);
-   *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
-   }
-   p += sizeof(phys_size_t);
-   i += size_cells;
-
-   debug("%s: ps=%p, i=%x, size=%zu\n",
- __func__, p, i, sizeof(phys_size_t));
-   }
-
-   /* Return the first address size */
-   return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
-}
-
-#define FDT_REG_SIZE  sizeof(u32)
-/* Temp location for sharing data for storing */
-/* Up to 64-bit address + 64-bit size */
-static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
-
 void dram_init_banksize(void)
 {
-   int bank;
-
-   memcpy(>bd->bi_dram[0], , sizeof(tmp));
-
-   for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-   debug("Bank #%d: start %llx\n", bank,
- (unsigned long long)gd->bd->bi_dram[bank].start);
-   debug("Bank #%d: size %llx\n", bank,
- (unsigned long long)gd->bd->bi_dram[bank].size);
-   }
+   fdtdec_setup_memory_banksize();
 }
 
 int dram_init(void)
 {
-   int node, len;
-   const void *blob = gd->fdt_blob;
-   const u32 *cell;
-
-   memset(, 0, sizeof(tmp));
-
-   /* find or create "/memory" node. */
-   node = fdt_subnode_offset(blob, 0, "memory");
-   if (node < 0) {
-   printf("%s: Can't get memory node\n", __func__);
-   return node;
-   }
-
-   /* Get pointer to cells and lenght of it */
-   cell = fdt_getprop(blob, node, "reg", );
-   if (!cell) {
-   printf("%s: Can't get reg property\n", __func__);
-

[U-Boot] [PATCH V2 18/19] arm: imx: add i.MX6SLL EVK board support

2016-12-11 Thread Peng Fan 
Add i.MX6SLL EVK board support.
1. Add imx6sll-evk device tree.
2. Enable SDHC/I2C/UART.
3. Enable REGULATOR/PMIC/I2C/GPIO/SDHC/PINCTRL driver.

Boot Log:
U-Boot 2016.11-00127-gc635871-dirty (Nov 24 2016 - 13:28:19 +0800)

CPU:   Freescale i.MX6SLL rev1.0 at 792MHz
CPU:   Commercial temperature grade (0C to 95C)Reset cause: POR
Model: Freescale i.MX6SLL EVK Board
Board: MX6SLL EVK
DRAM:  2 GiB
i2c bus 0 at 35258368, no gpio pinctrl state.
PMIC: PFUZE100! DEV_ID=0x10 REV_ID=0x21
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
In:serial
Out:   serial
Err:   serial
Net:   CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/cpu/armv7/mx6/Kconfig |   7 +
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/imx6sll-evk.dts   | 801 +
 board/freescale/mx6sllevk/Kconfig  |  12 +
 board/freescale/mx6sllevk/Makefile |   6 +
 board/freescale/mx6sllevk/imximage.cfg | 121 +
 board/freescale/mx6sllevk/mx6sllevk.c  | 131 ++
 configs/mx6sllevk_defconfig|  36 ++
 include/configs/mx6sllevk.h| 152 +++
 9 files changed, 1267 insertions(+)
 create mode 100644 arch/arm/dts/imx6sll-evk.dts
 create mode 100644 board/freescale/mx6sllevk/Kconfig
 create mode 100644 board/freescale/mx6sllevk/Makefile
 create mode 100644 board/freescale/mx6sllevk/imximage.cfg
 create mode 100644 board/freescale/mx6sllevk/mx6sllevk.c
 create mode 100644 configs/mx6sllevk_defconfig
 create mode 100644 include/configs/mx6sllevk.h

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 6b6476d..10d598e 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -132,6 +132,12 @@ config TARGET_MX6SLEVK
bool "mx6slevk"
select SUPPORT_SPL
 
+config TARGET_MX6SLLEVK
+bool "mx6sll evk"
+select MX6SLL
+select DM
+select DM_THERMAL
+
 config TARGET_MX6SXSABRESD
bool "mx6sxsabresd"
select MX6SX
@@ -262,6 +268,7 @@ source "board/freescale/mx6qarm2/Kconfig"
 source "board/freescale/mx6qsabreauto/Kconfig"
 source "board/freescale/mx6sabresd/Kconfig"
 source "board/freescale/mx6slevk/Kconfig"
+source "board/freescale/mx6sllevk/Kconfig"
 source "board/freescale/mx6sxsabresd/Kconfig"
 source "board/freescale/mx6sxsabreauto/Kconfig"
 source "board/freescale/mx6ul_14x14_evk/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f437469..fde1232 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -294,6 +294,7 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
bk4r1.dtb
 
 dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
+   imx6sll-evk.dtb \
imx6dl-icore.dtb \
imx6q-icore.dtb
 
diff --git a/arch/arm/dts/imx6sll-evk.dts b/arch/arm/dts/imx6sll-evk.dts
new file mode 100644
index 000..b4af007
--- /dev/null
+++ b/arch/arm/dts/imx6sll-evk.dts
@@ -0,0 +1,801 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include 
+#include 
+#include "imx6sll.dtsi"
+
+/ {
+   model = "Freescale i.MX6SLL EVK Board";
+   compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
+
+   memory {
+   reg = <0x8000 0x8000>;
+   };
+
+   backlight {
+   compatible = "pwm-backlight";
+   pwms = < 0 500>;
+   brightness-levels = <0 4 8 16 32 64 128 255>;
+   default-brightness-level = <6>;
+   status = "okay";
+   };
+
+   battery: max8903@0 {
+   compatible = "fsl,max8903-charger";
+   pinctrl-names = "default";
+   dok_input = < 13 1>;
+   uok_input = < 13 1>;
+   chg_input = < 15 1>;
+   flt_input = < 14 1>;
+   fsl,dcm_always_high;
+   fsl,dc_valid;
+   fsl,adc_disable;
+   status = "okay";
+   };
+
+   pxp_v4l2_out {
+   compatible = "fsl,imx6sl-pxp-v4l2";
+   status = "okay";
+   };
+
+   regulators {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   reg_usb_otg1_vbus: regulator@0 {
+   compatible = "regulator-fixed";
+   reg = <0>;
+   regulator-name = "usb_otg1_vbus";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   gpio = < 0 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+
+   reg_usb_otg2_vbus: regulator@1 {
+

[U-Boot] [PATCH V2 15/19] imx-common: lcdif: update lcdif regs for i.MX6SL/SLL

2016-12-11 Thread Peng Fan 
Update lcdif regs for i.MX6SL/SLL

Signed-off-by: Ye.Li 
Signed-off-by: Peng Fan 
---
 arch/arm/include/asm/imx-common/regs-lcdif.h | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/imx-common/regs-lcdif.h 
b/arch/arm/include/asm/imx-common/regs-lcdif.h
index 5a4f61f..ab147b5 100644
--- a/arch/arm/include/asm/imx-common/regs-lcdif.h
+++ b/arch/arm/include/asm/imx-common/regs-lcdif.h
@@ -20,7 +20,7 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_ctrl)   /* 0x00 */
mxs_reg_32(hw_lcdif_ctrl1)  /* 0x10 */
 #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
-   defined(CONFIG_MX7)
+   defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
mxs_reg_32(hw_lcdif_ctrl2)  /* 0x20 */
 #endif
mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
@@ -56,7 +56,7 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_data)   /* 0x1b0/0x180 */
mxs_reg_32(hw_lcdif_bm_error_stat)  /* 0x1c0/0x190 */
 #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
-   defined(CONFIG_MX7)
+   defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
mxs_reg_32(hw_lcdif_crc_stat)   /* 0x1a0 */
 #endif
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
@@ -64,7 +64,8 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */
mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */
mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */
-#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7)
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7) || \
+   defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
mxs_reg_32(hw_lcdif_thres)
mxs_reg_32(hw_lcdif_as_ctrl)
mxs_reg_32(hw_lcdif_as_buf)
-- 
2.6.2

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[U-Boot] [PATCH V2 19/19] imx: mx6sllevk: add plugin support

2016-12-11 Thread Peng Fan 
Add plugin support for mx6sllevk board.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 board/freescale/mx6sllevk/imximage.cfg |   6 ++
 board/freescale/mx6sllevk/plugin.S | 155 +
 configs/mx6sllevk_plugin_defconfig |  37 
 3 files changed, 198 insertions(+)
 create mode 100644 board/freescale/mx6sllevk/plugin.S
 create mode 100644 configs/mx6sllevk_plugin_defconfig

diff --git a/board/freescale/mx6sllevk/imximage.cfg 
b/board/freescale/mx6sllevk/imximage.cfg
index 53fb74f..7d8b323 100644
--- a/board/freescale/mx6sllevk/imximage.cfg
+++ b/board/freescale/mx6sllevk/imximage.cfg
@@ -23,6 +23,11 @@ IMAGE_VERSION 2
 
 BOOT_FROM  sd
 
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGINplugin-binary-fileIRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6sllevk/plugin.bin 0x00907000
+#else
+
 #ifdef CONFIG_SECURE_BOOT
 CSF CONFIG_CSF_SIZE
 #endif
@@ -119,3 +124,4 @@ DATA 4 0x021B0800 0xA1390003
 DATA 4 0x021B0004 0x00020052
 DATA 4 0x021B0404 0x00011006
 DATA 4 0x021B001C 0x
+#endif
diff --git a/board/freescale/mx6sllevk/plugin.S 
b/board/freescale/mx6sllevk/plugin.S
new file mode 100644
index 000..f9ef35a
--- /dev/null
+++ b/board/freescale/mx6sllevk/plugin.S
@@ -0,0 +1,155 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+
+/* DDR script */
+.macro imx6sll_evk_ddr_setting
+   ldr r0, =IOMUXC_BASE_ADDR
+   ldr r1, =0x0008
+   str r1, [r0, #0x550]
+   ldr r1, =0x
+   str r1, [r0, #0x534]
+   ldr r1, =0x0030
+   str r1, [r0, #0x2AC]
+   str r1, [r0, #0x548]
+   str r1, [r0, #0x52C]
+   ldr r1, =0x0002
+   str r1, [r0, #0x530]
+   ldr r1, =0x3030
+   str r1, [r0, #0x2B0]
+   str r1, [r0, #0x2B4]
+   str r1, [r0, #0x2B8]
+   str r1, [r0, #0x2BC]
+
+   ldr r1, =0x0002
+   str r1, [r0, #0x540]
+   ldr r1, =0x0030
+   str r1, [r0, #0x544]
+   str r1, [r0, #0x54C]
+   str r1, [r0, #0x554]
+   str r1, [r0, #0x558]
+   str r1, [r0, #0x294]
+   str r1, [r0, #0x298]
+   str r1, [r0, #0x29C]
+   str r1, [r0, #0x2A0]
+
+   ldr r1, =0x00082030
+   str r1, [r0, #0x2C0]
+
+   ldr r0, =MMDC_P0_BASE_ADDR
+   ldr r1, =0x8000
+   str r1, [r0, #0x1C]
+   ldr r1, =0xA1390003
+   str r1, [r0, #0x800]
+   ldr r1, =0x084700C7
+   str r1, [r0, #0x85C]
+   ldr r1, =0x0040
+   str r1, [r0, #0x890]
+
+   ldr r1, =0x3F393B3C
+   str r1, [r0, #0x848]
+   ldr r1, =0x262C3826
+   str r1, [r0, #0x850]
+
+   ldr r1, =0x
+   str r1, [r0, #0x81C]
+   str r1, [r0, #0x820]
+   str r1, [r0, #0x824]
+   str r1, [r0, #0x828]
+
+   ldr r1, =0xf333
+   str r1, [r0, #0x82C]
+   str r1, [r0, #0x830]
+   str r1, [r0, #0x834]
+   str r1, [r0, #0x838]
+
+   ldr r1, =0x24922492
+   str r1, [r0, #0x8C0]
+   ldr r1, =0x0800
+   str r1, [r0, #0x8B8]
+
+   ldr r1, =0x00020052
+   str r1, [r0, #0x004]
+   ldr r1, =0x53574333
+   str r1, [r0, #0x00C]
+   ldr r1, =0x00100B22
+   str r1, [r0, #0x010]
+   ldr r1, =0x00170778
+   str r1, [r0, #0x038]
+   ldr r1, =0x00C700DB
+   str r1, [r0, #0x014]
+   ldr r1, =0x00201718
+   str r1, [r0, #0x018]
+   ldr r1, =0x0F9F26D2
+   str r1, [r0, #0x02C]
+   ldr r1, =0x009F0E10
+   str r1, [r0, #0x030]
+   ldr r1, =0x005F
+   str r1, [r0, #0x040]
+   ldr r1, =0xC419
+   str r1, [r0, #0x000]
+   ldr r1, =0x2000
+   str r1, [r0, #0x83C]
+
+   ldr r1, =0x8050
+   str r1, [r0, #0x01C]
+   ldr r1, =0x8058
+   str r1, [r0, #0x01C]
+   ldr r1, =0x003F8030
+   str r1, [r0, #0x01C]
+   ldr r1, =0x003F8038
+   str r1, [r0, #0x01C]
+   ldr r1, =0xFF0A8030
+   str r1, [r0, #0x01C]
+   ldr r1, =0xFF0A8038
+   str r1, [r0, #0x01C]
+   ldr r1, =0x04028030
+   str r1, [r0, #0x01C]
+   ldr r1, =0x04028038
+   str r1, [r0, #0x01C]
+   ldr r1, =0x83018030
+   str r1, [r0, #0x01C]
+   ldr r1, =0x83018038
+   str r1, [r0, #0x01C]
+   ldr r1, =0x01038030
+   str r1, [r0, #0x01C]
+   ldr r1, =0x01038038
+   str r1, [r0, #0x01C]
+
+   ldr r1, =0x1800
+   str r1, [r0, #0x020]
+   ldr r1, =0xA1390003
+   str r1, [r0, #0x800]
+   ldr r1, =0x00020052
+   str r1, [r0, #0x004]
+   ldr r1, =0x00011006
+   str r1, [r0, #0x404]
+   ldr r1, =0x
+   str r1, [r0, #0x01C]
+.endm
+
+.macro imx6_clock_gating
+   ldr r0, =CCM_BASE_ADDR
+   ldr r1, =0x
+   str r1, [r0, #0x068]
+   str r1, [r0, #0x06c]
+   str r1, [r0, #0x070]
+   str r1, [r0, #0x074]
+   str r1, [r0, #0x078]
+   str r1, [r0, #0x07c]
+   str r1, [r0, #0x080]
+.endm
+

[U-Boot] [PATCH V2 12/19] imx: mx6sll: add Kconfig entry for i.MX6SLL

2016-12-11 Thread Peng Fan 
add Kconfig entry for i.MX6SLL

Signed-off-by: Peng Fan 
---
 arch/arm/cpu/armv7/mx6/Kconfig | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 8c96ba3..6b6476d 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -26,6 +26,10 @@ config MX6SX
select ROM_UNIFIED_SECTIONS
bool
 
+config MX6SLL
+   select ROM_UNIFIED_SECTIONS
+   bool
+
 config MX6UL
select SYS_L2CACHE_OFF
select ROM_UNIFIED_SECTIONS
-- 
2.6.2

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[U-Boot] [PATCH V2 10/19] imx: mx6sll: add clock support

2016-12-11 Thread Peng Fan 
Add clock support for i.MX6SLL.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/cpu/armv7/mx6/clock.c | 28 +---
 1 file changed, 21 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index de3665f..fa54c95 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -171,6 +171,8 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
reg &= ~mask;
__raw_writel(reg, _ccm->CCGR2);
} else {
+   if (is_mx6sll())
+   return -EINVAL;
if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
mask = MXC_CCM_CCGR6_I2C4_MASK;
addr = _ccm->CCGR6;
@@ -382,7 +384,7 @@ static u32 get_ipg_per_clk(void)
u32 reg, perclk_podf;
 
reg = __raw_readl(_ccm->cscmr1);
-   if (is_mx6sl() || is_mx6sx() ||
+   if (is_mx6sll() || is_mx6sl() || is_mx6sx() ||
is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
return MXC_HCLK; /* OSC 24Mhz */
@@ -400,7 +402,7 @@ static u32 get_uart_clk(void)
reg = __raw_readl(_ccm->cscdr1);
 
if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
-   is_mx6ull()) {
+   is_mx6sll() || is_mx6ull()) {
if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
freq = MXC_HCLK;
}
@@ -420,7 +422,7 @@ static u32 get_cspi_clk(void)
 MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 
if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
-   is_mx6ull()) {
+   is_mx6sll() || is_mx6ull()) {
if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
return MXC_HCLK / (cspi_podf + 1);
}
@@ -482,7 +484,8 @@ static u32 get_mmdc_ch0_clk(void)
 
u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
 
-   if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) {
+   if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() ||
+   is_mx6sll()) {
podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
@@ -625,7 +628,8 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 
debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
 
-   if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) {
+   if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
+   !is_mx6sll()) {
debug("This chip not support lcd!\n");
return;
}
@@ -783,7 +787,7 @@ int enable_lcdif_clock(u32 base_addr, bool enable)
 MXC_CCM_CCGR3_DISP_AXI_MASK) :
(MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
 MXC_CCM_CCGR3_DISP_AXI_MASK);
-   } else if (is_mx6ul() || is_mx6ull()) {
+   } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
if (base_addr != LCDIF1_BASE_ADDR) {
puts("Wrong LCD interface!\n");
return -EINVAL;
@@ -981,6 +985,16 @@ static u32 get_usdhc_clk(u32 port)
u32 cscmr1 = __raw_readl(_ccm->cscmr1);
u32 cscdr1 = __raw_readl(_ccm->cscdr1);
 
+   if (is_mx6ul() || is_mx6ull()) {
+   if (port > 1)
+   return 0;
+   }
+
+   if (is_mx6sll()) {
+   if (port > 2)
+   return 0;
+   }
+
switch (port) {
case 0:
usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
@@ -1144,7 +1158,7 @@ void hab_caam_clock_enable(unsigned char enable)
 {
u32 reg;
 
-   if (is_mx6ull()) {
+   if (is_mx6ull() || is_mx6sll()) {
/* CG5, DCP clock */
reg = __raw_readl(_ccm->CCGR0);
if (enable)
-- 
2.6.2

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[U-Boot] [PATCH V2 13/19] mx6_common: correct loadaddr and text base for i.MX6SLL

2016-12-11 Thread Peng Fan 
Correct loadaddr and text base for i.MX6SLL

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 include/configs/mx6_common.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index d28654b..e79ec21 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -44,7 +44,8 @@
 #define CONFIG_REVISION_TAG
 
 /* Boot options */
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6UL))
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \
+   defined(CONFIG_MX6UL) || defined(CONFIG_MX6SLL))
 #define CONFIG_LOADADDR0x8200
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE   0x8780
-- 
2.6.2

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Re: [U-Boot] [PATCH] ARM: uniphier: remove BLK select

2016-12-11 Thread Masahiro Yamada 
2016-12-10 10:52 GMT+09:00 Masahiro Yamada :
> This is a user configurable option, but "select BLK" forces users to
> enable it.
>
> Even with this commit, BLK is still enabled by "default y if DM_MMC"
> for UniPhier SoCs; the difference is users can disable it if they
> do not need it.
>
> Signed-off-by: Masahiro Yamada 

Applied to u-boot-uniphier/master.



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Re: [U-Boot] [PATCH 0/4] ARM: uniphier: UniPhier updates for v2016.11-rc1

2016-12-11 Thread Masahiro Yamada 
2016-12-05 18:31 GMT+09:00 Masahiro Yamada :
>
>
>
> Masahiro Yamada (4):
>   ARM: uniphier: remove unneeded initializer
>   ARM: uniphier: remove unneeded parentheses
>   ARM: uniphier: disable CONFIG_ARCH_FIXUP_FDT_MEMORY
>   ARM: dts: uniphier: sync Device Tree with Linux


Applied to u-boot-uniphier/master.


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Re: [U-Boot] [PATCH 1/5] pmic: pmic_mc34vr500: Add a driver for the mc34vr500 pmic

2016-12-11 Thread Z.Q. Hou 
Hi Simon,

Thanks a lot for your comments!

> -Original Message-
> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
> Sent: 2016年12月12日 4:28
> To: Z.Q. Hou 
> Cc: U-Boot Mailing List ; york sun
> ; Prabhakar Kushwaha ;
> Shengzhou Liu ; Priyanka Jain
> ; Mingkai Hu 
> Subject: Re: [PATCH 1/5] pmic: pmic_mc34vr500: Add a driver for the
> mc34vr500 pmic
> 
> Hi,
> 
> On 9 December 2016 at 03:08, Zhiqiang Hou  wrote:
> > From: Hou Zhiqiang 
> >
> > This patch adds a simple pmic driver for the mc34vr500 pmic which is
> > used in conjunction with the fsl T1 and LS1 series SoC.
> >
> > Signed-off-by: Hou Zhiqiang 
> > ---
> >  drivers/power/pmic/Kconfig  |   7 ++
> >  drivers/power/pmic/Makefile |   1 +
> >  drivers/power/pmic/pmic_mc34vr500.c |  32 +++
> >  include/power/mc34vr500_pmic.h  | 166
> 
> >  4 files changed, 206 insertions(+)
> >  create mode 100644 drivers/power/pmic/pmic_mc34vr500.c
> >  create mode 100644 include/power/mc34vr500_pmic.h
> >
> > diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
> > index ce204b3..73e1d53 100644
> > --- a/drivers/power/pmic/Kconfig
> > +++ b/drivers/power/pmic/Kconfig
> > @@ -157,3 +157,10 @@ config PMIC_LP873X
> > ---help---
> > The LP873X is a PMIC containing couple of LDOs and couple of
> SMPS.
> > This driver binds the pmic children.
> > +
> > +config POWER_MC34VR500
> > +   bool "Enable driver for Freescale MC34VR500 PMIC"
> > +   ---help---
> > +   The MC34VR500 is used in conjunction with the FSL T1 and LS1
> series
> > +   SoC. It provides 4 buck DC-DC convertors and 5 LDOs, and it is
> accessed
> > +   via an I2C interface.
> > diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
> > index cd1c694..58d0241 100644
> > --- a/drivers/power/pmic/Makefile
> > +++ b/drivers/power/pmic/Makefile
> > @@ -32,3 +32,4 @@ obj-$(CONFIG_POWER_TPS65218) += pmic_tps62362.o
> >  obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
> >  obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
> >  obj-$(CONFIG_POWER_HI6553) += pmic_hi6553.o
> > +obj-$(CONFIG_POWER_MC34VR500) += pmic_mc34vr500.o
> > diff --git a/drivers/power/pmic/pmic_mc34vr500.c
> > b/drivers/power/pmic/pmic_mc34vr500.c
> > new file mode 100644
> > index 000..db9e210
> > --- /dev/null
> > +++ b/drivers/power/pmic/pmic_mc34vr500.c
> > @@ -0,0 +1,32 @@
> > +/*
> > + * Copyright 2016 Freescale Semiconductor, Inc.
> > + * Hou Zhiqiang 
> > + *
> > + * SPDX-License-Identifier:GPL-2.0+
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +int power_mc34vr500_init(unsigned char bus) {
> > +   static const char name[] = "MC34VR500";
> > +   struct pmic *p = pmic_alloc();
> 
> We have a driver-model PMIC framework now so can you please convert this
> to use that? We should move towards removing the old framework.

Yes, I know. Actually, I have written the driver based on driver-model PMIC 
framework, but it depends on DM_I2C, while the DM_I2C isn't ready on Layerscape 
SoCs.
I will send the DM PMIC based MC34VR500 driver once the DM_I2C ready.

Thanks,
Zhiqiang
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Re: [U-Boot] [PATCH 1/3] fdt: add memory bank decoding functions for board setup

2016-12-11 Thread Nathan Rossi 
On 12 December 2016 at 06:27, Simon Glass  wrote:
> Hi Nathan,
>
> On 11 December 2016 at 08:58, Nathan Rossi  wrote:
>> Add two functions for use by board implementations to decode the memory
>> banks of the /memory node so as to populate the global data with
>> ram_size and board info for memory banks.
>>
>> The fdtdec_setup_memory_size() function decodes the first memory bank
>> and sets up the gd->ram_size with the size of the memory bank. This
>> function should be called from the boards dram_init().
>>
>> The fdtdec_setup_memory_banksize() function decode the memory banks
>> (up to the CONFIG_NR_DRAM_BANKS) and populates the base address and size
>> into the gd->bd->bi_dram array of banks. This function should be called
>> from the boards dram_init_banksize().
>>
>> Signed-off-by: Nathan Rossi 
>> Cc: Simon Glass 
>> Cc: Michal Simek 
>> ---
>> This implementation of decoding has been tested on zynq and zynqmp
>> boards with address/size cells of (1, 1), (1, 2), (2, 1), (2, 2) and
>> up to 2 memory banks.
>> ---
>>  include/fdtdec.h | 25 +
>>  lib/fdtdec.c | 54 ++
>>  2 files changed, 79 insertions(+)
>
> Reviewed-by: Simon Glass 
>
> Please see nit below.
>
>>
>> diff --git a/include/fdtdec.h b/include/fdtdec.h
>> index 27887c8c21..59a204b571 100644
>> --- a/include/fdtdec.h
>> +++ b/include/fdtdec.h
>> @@ -976,6 +976,31 @@ struct display_timing {
>>   */
>>  int fdtdec_decode_display_timing(const void *blob, int node, int index,
>>  struct display_timing *config);
>> +
>> +/**
>> + * fdtdec_setup_memory_size() - decode and setup gd->ram_size
>> + *
>> + * Decode the /memory 'reg' property to determine the size of the first 
>> memory
>> + * bank, populate the global data with the size of the first bank of memory.
>> + * This function should be called from the boards dram_init().
>> + *
>> + * @return 0 if OK, -EINVAL if the /memory node or reg property is missing 
>> or
>> + * invalid
>> + */
>> +int fdtdec_setup_memory_size(void);
>> +
>> +/**
>> + * fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram
>> + *
>> + * Decode the /memory 'reg' property to determine the address and size of 
>> the
>> + * memory banks. Use this data to populate the global data board info with 
>> the
>> + * phys address and size of memory banks. This function should be called 
>> from
>> + * the boards dram_init_banksize().
>> + *
>> + * @return 0 if OK, negative on error
>
> Good to be specific, if e.g. it can only return -EINVAL.

I will update this based on the change below.

>
>> + */
>> +int fdtdec_setup_memory_banksize(void);
>> +
>>  /**
>>   * Set up the device tree ready for use
>>   */
>> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
>> index 4e619c49a2..bc3be017b6 100644
>> --- a/lib/fdtdec.c
>> +++ b/lib/fdtdec.c
>> @@ -1174,6 +1174,60 @@ int fdtdec_decode_display_timing(const void *blob, 
>> int parent, int index,
>> return ret;
>>  }
>>
>> +int fdtdec_setup_memory_size(void)
>> +{
>> +   int ret, mem;
>> +   struct fdt_resource res;
>> +
>> +   mem = fdt_path_offset(gd->fdt_blob, "/memory");
>> +   if (mem < 0) {
>> +   debug("%s: Missing /memory node\n", __func__);
>> +   return -EINVAL;
>> +   }
>> +
>> +   ret = fdt_get_resource(gd->fdt_blob, mem, "reg", 0, );
>> +   if (ret != 0) {
>> +   debug("%s: Unable to decode first memory bank\n", __func__);
>> +   return -EINVAL;
>> +   }
>> +
>> +   gd->ram_size = (phys_size_t)(res.end - res.start + 1);
>> +   debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
>> +
>> +   return 0;
>> +}
>> +
>> +int fdtdec_setup_memory_banksize(void)
>> +{
>> +   int bank, ret, mem;
>> +   struct fdt_resource res;
>> +
>> +   mem = fdt_path_offset(gd->fdt_blob, "/memory");
>> +   if (mem < 0) {
>> +   debug("%s: Missing /memory node\n", __func__);
>> +   return -EINVAL;
>> +   }
>> +
>> +   for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
>> +   ret = fdt_get_resource(gd->fdt_blob, mem, "reg", bank, );
>> +   if (ret == -FDT_ERR_NOTFOUND)
>> +   break;
>> +   if (ret != 0)
>> +   return ret;
>
> The return above return -EINVAL, but this one returns a -FDT_ERR_...
> which is different. So my suggestion here would be to return -EINVAL
> here, unless you want to change the function to always return an FDT
> error (although fdtdec_decode_memory_region() returns an errno error
> so perhaps it is better to be consistent with that).

Agreed, returning only -EINVAL in both error conditions makes more
sense than returning an -FDT_ERR_* error. This also makes it
consistent with the function above this

Re: [U-Boot] [PATCH 0/3] Add generic FDT memory bank decoding and gd initialization

2016-12-11 Thread Nathan Rossi 
On 12 December 2016 at 03:08, Igor Grinberg  wrote:
> On 12/11/16 18:47, Nathan Rossi wrote:
>> On 12 December 2016 at 01:08, Igor Grinberg  wrote:
>>> Hi Nathan,
>>>
>>> On 12/11/16 15:58, Nathan Rossi wrote:
 This series adds two functions for handling the memory bank decoding and
 initialization of global data for use by boards in their dram_init and
 dram_init_banksize functions.
>>>
>>> I might have missed some discussions on this meter,
>>> can you please provide the use cases for this?
>>> IMO, the bootloader's job is to initialize the DRAM, detect its size, and 
>>> pass
>>> the detected DRAM configuration on to an OS.
>>
>> Hi Igor,
>>
>> I do not think there have been any discussions on this (at least none
>> that I am aware of).
>>
>> Some boards (like Zynq and ZynqMP ones) are using
>> CONFIG_SYS_SDRAM_SIZE to define the amount of memory that is available
>> (since detection is not possible). However with the introduction of
>> dtbs for some boards they are also capable of loading the size of
>> memory from the embedded/appended dtb (instead of hardcoded). This
>> allows for more of the board config to be loaded from the device tree
>> instead of from include/configs/*.h. This however is up to the
>> individual board to implement in its dram_init* functions.
>
> Thanks for the explanation!
> I assume that the key point is "detection is not possible" and therefore
> we must rely on a user or a production process to place (append) the correct 
> dtb.
> Makes sense to me now and looks like an improvement to the current situation.
>
>>
>> The first patch of the series is only adding some decoding helper
>> functions to make this generic between the Zynq and ZynqMP boards as
>> well as to allow for any other boards that may want to use the same
>> mechanism to get the memory size from the fdt. There is no requirement
>> for boards to use these functions.
>
> Can you please next time place a similar explanation in at least the cover
> letter. This way, the intent might be understood the first time ;-)

Sorry about that, I will make sure future series have more complete
descriptions in the cover letter. I have however updated the
description for this in the v2 for completeness.

> I would also like to see some parts of the above explanation in the functions
> documentation (e.g. this allows to improve the DRAM configuration mechanics
> on boards that cannot detect its DRAM size/config).

Will add in v2.

Regards,
Nathan

>
> Thanks!
>
>>
>> Regards,
>> Nathan
>>
>>>

 The series also changes the zynq and zynqmp board implementations to use
 these functions to resolve a issue with static variable use.

 Nathan Rossi (3):
   fdt: add memory bank decoding functions for board setup
   ARM: zynq: Replace board specific with generic memory bank decoding
   ARM64: zynqmp: Replace board specific with generic memory bank
 decoding

  board/xilinx/zynq/board.c| 112 
 ++-
  board/xilinx/zynqmp/zynqmp.c | 112 
 ++-
  include/fdtdec.h |  25 ++
  lib/fdtdec.c |  54 +
  4 files changed, 85 insertions(+), 218 deletions(-)

>>>
>>> --
>>> Regards,
>>> Igor.
>>
>
> --
> Regards,
> Igor.
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Re: [U-Boot] post_codes in u-boot?

2016-12-11 Thread Bin Meng 
Hi,

On Sat, Dec 10, 2016 at 7:50 AM, Haleigh Novak  wrote:
> Hello All,
>
>
> I am currently deciphering post_code ouput on a machine running Yocto with a 
> bios of coreboot with a payload of SeaBIOS and another (i think) u-boot, in 
> searching online for one of the post_code values I stumbled on a post 
> (http://lists.denx.de/pipermail/u-boot/2016-January/241577.html) noting that 
> u-boot has post codes of its own. I was wondering if there was a 
> consolidation of most (if not all) of the post_codes used, like there sort of 
> is in coreboot at /src/console/post_code.h; or if there is not would someone 
> mind giving me a direction on what function(s) u-boot uses to post the u-boot 
> post_codes; i.e. coreboot utilizes a function called post_code as well as asm 
> code and some of the binaries have their own post codes  - is there anything 
> like that in u-boot?

See arch/x86/include/asm/post.h. There is a function post_code() to do
post codes.

Regards,
Bin
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[U-Boot] [PATCH v2 1/3] fdt: add memory bank decoding functions for board setup

2016-12-11 Thread Nathan Rossi 
Add two functions for use by board implementations to decode the memory
banks of the /memory node so as to populate the global data with
ram_size and board info for memory banks.

The fdtdec_setup_memory_size() function decodes the first memory bank
and sets up the gd->ram_size with the size of the memory bank. This
function should be called from the boards dram_init().

The fdtdec_setup_memory_banksize() function decode the memory banks
(up to the CONFIG_NR_DRAM_BANKS) and populates the base address and size
into the gd->bd->bi_dram array of banks. This function should be called
from the boards dram_init_banksize().

Signed-off-by: Nathan Rossi 
Cc: Simon Glass 
Cc: Michal Simek 
Reviewed-by: Simon Glass 
---
v2:
 * Make fdtdec_setup_memory_banksize() return value consistent
 * Add more detail into the function documentation

This implementation of decoding has been tested on zynq and zynqmp
boards with address/size cells of (1, 1), (1, 2), (2, 1), (2, 2) and
up to 2 memory banks.
---
 include/fdtdec.h | 34 ++
 lib/fdtdec.c | 54 ++
 2 files changed, 88 insertions(+)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 27887c8c21..d074478f14 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -976,6 +976,40 @@ struct display_timing {
  */
 int fdtdec_decode_display_timing(const void *blob, int node, int index,
 struct display_timing *config);
+
+/**
+ * fdtdec_setup_memory_size() - decode and setup gd->ram_size
+ *
+ * Decode the /memory 'reg' property to determine the size of the first memory
+ * bank, populate the global data with the size of the first bank of memory.
+ *
+ * This function should be called from a boards dram_init(). This helper
+ * function allows for boards to query the device tree for DRAM size instead of
+ * hard coding the value in the case where the memory size cannot be detected
+ * automatically.
+ *
+ * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or
+ * invalid
+ */
+int fdtdec_setup_memory_size(void);
+
+/**
+ * fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram
+ *
+ * Decode the /memory 'reg' property to determine the address and size of the
+ * memory banks. Use this data to populate the global data board info with the
+ * phys address and size of memory banks.
+ *
+ * This function should be called from a boards dram_init_banksize(). This
+ * helper function allows for boards to query the device tree for memory bank
+ * information instead of hard coding the information in cases where it cannot
+ * be detected automatically.
+ *
+ * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or
+ * invalid
+ */
+int fdtdec_setup_memory_banksize(void);
+
 /**
  * Set up the device tree ready for use
  */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 4e619c49a2..3bf9ff84f4 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1174,6 +1174,60 @@ int fdtdec_decode_display_timing(const void *blob, int 
parent, int index,
return ret;
 }
 
+int fdtdec_setup_memory_size(void)
+{
+   int ret, mem;
+   struct fdt_resource res;
+
+   mem = fdt_path_offset(gd->fdt_blob, "/memory");
+   if (mem < 0) {
+   debug("%s: Missing /memory node\n", __func__);
+   return -EINVAL;
+   }
+
+   ret = fdt_get_resource(gd->fdt_blob, mem, "reg", 0, );
+   if (ret != 0) {
+   debug("%s: Unable to decode first memory bank\n", __func__);
+   return -EINVAL;
+   }
+
+   gd->ram_size = (phys_size_t)(res.end - res.start + 1);
+   debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
+
+   return 0;
+}
+
+int fdtdec_setup_memory_banksize(void)
+{
+   int bank, ret, mem;
+   struct fdt_resource res;
+
+   mem = fdt_path_offset(gd->fdt_blob, "/memory");
+   if (mem < 0) {
+   debug("%s: Missing /memory node\n", __func__);
+   return -EINVAL;
+   }
+
+   for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+   ret = fdt_get_resource(gd->fdt_blob, mem, "reg", bank, );
+   if (ret == -FDT_ERR_NOTFOUND)
+   break;
+   if (ret != 0)
+   return -EINVAL;
+
+   gd->bd->bi_dram[bank].start = (phys_addr_t)res.start;
+   gd->bd->bi_dram[bank].size =
+   (phys_size_t)(res.end - res.start + 1);
+
+   debug("%s: DRAM Bank #%d: start = 0x%llx, size = 0x%llx\n",
+ __func__, bank,
+ (unsigned long long)gd->bd->bi_dram[bank].start,
+ (unsigned long long)gd->bd->bi_dram[bank].size);
+   }
+
+   return 0;
+}
+
 int fdtdec_setup(void)
 {
 #if CONFIG_IS_ENABLED(OF_CONTROL)
-- 
2.10.2

[U-Boot] [PATCH v2 3/3] ARM64: zynqmp: Replace board specific with generic memory bank decoding

2016-12-11 Thread Nathan Rossi 
The dram_init and dram_init_banksize functions were using a board
specific implementation for decoding the memory banks from the fdt. This
board specific implementation uses a static variable 'tmp' which makes
these functions unsafe for execution from within the board_init_f
context.

This change makes the dram_init* functions use a generic implementation
of decoding and populating memory bank and size data.

Signed-off-by: Nathan Rossi 
Fixes: 8d59d7f63b ("ARM64: zynqmp: Read RAM information from DT")
Cc: Michal Simek 
---
 board/xilinx/zynqmp/zynqmp.c | 112 ++-
 1 file changed, 3 insertions(+), 109 deletions(-)

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index cef1f6a13a..8a3d0043b9 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -180,121 +180,15 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 }
 
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
-/*
- * fdt_get_reg - Fill buffer by information from DT
- */
-static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
-  const u32 *cell, int n)
-{
-   int i = 0, b, banks;
-   int parent_offset = fdt_parent_offset(fdt, nodeoffset);
-   int address_cells = fdt_address_cells(fdt, parent_offset);
-   int size_cells = fdt_size_cells(fdt, parent_offset);
-   char *p = buf;
-   u64 val;
-   u64 vals;
-
-   debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
- __func__, address_cells, size_cells, buf, cell);
-
-   /* Check memory bank setup */
-   banks = n % (address_cells + size_cells);
-   if (banks)
-   panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
- n, address_cells, size_cells);
-
-   banks = n / (address_cells + size_cells);
-
-   for (b = 0; b < banks; b++) {
-   debug("%s: Bank #%d:\n", __func__, b);
-   if (address_cells == 2) {
-   val = cell[i + 1];
-   val <<= 32;
-   val |= cell[i];
-   val = fdt64_to_cpu(val);
-   debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
- __func__, val, p, [i]);
-   *(phys_addr_t *)p = val;
-   } else {
-   debug("%s: addr32=%x, ptr=%p\n",
- __func__, fdt32_to_cpu(cell[i]), p);
-   *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
-   }
-   p += sizeof(phys_addr_t);
-   i += address_cells;
-
-   debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
- sizeof(phys_addr_t));
-
-   if (size_cells == 2) {
-   vals = cell[i + 1];
-   vals <<= 32;
-   vals |= cell[i];
-   vals = fdt64_to_cpu(vals);
-
-   debug("%s: size64=%llx, ptr=%p, cell=%p\n",
- __func__, vals, p, [i]);
-   *(phys_size_t *)p = vals;
-   } else {
-   debug("%s: size32=%x, ptr=%p\n",
- __func__, fdt32_to_cpu(cell[i]), p);
-   *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
-   }
-   p += sizeof(phys_size_t);
-   i += size_cells;
-
-   debug("%s: ps=%p, i=%x, size=%zu\n",
- __func__, p, i, sizeof(phys_size_t));
-   }
-
-   /* Return the first address size */
-   return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
-}
-
-#define FDT_REG_SIZE  sizeof(u32)
-/* Temp location for sharing data for storing */
-/* Up to 64-bit address + 64-bit size */
-static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
-
 void dram_init_banksize(void)
 {
-   int bank;
-
-   memcpy(>bd->bi_dram[0], , sizeof(tmp));
-
-   for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-   debug("Bank #%d: start %llx\n", bank,
- (unsigned long long)gd->bd->bi_dram[bank].start);
-   debug("Bank #%d: size %llx\n", bank,
- (unsigned long long)gd->bd->bi_dram[bank].size);
-   }
+   fdtdec_setup_memory_banksize();
 }
 
 int dram_init(void)
 {
-   int node, len;
-   const void *blob = gd->fdt_blob;
-   const u32 *cell;
-
-   memset(, 0, sizeof(tmp));
-
-   /* find or create "/memory" node. */
-   node = fdt_subnode_offset(blob, 0, "memory");
-   if (node < 0) {
-   printf("%s: Can't get memory node\n", __func__);
-   return node;
-   }
-
-   /* Get pointer to cells and lenght of it */
-   cell = fdt_getprop(blob, node, "reg", );
-   if (!cell) {
-   printf("%s: Can't get reg property\n", __func__);
-

[U-Boot] [PATCH v2 0/3] Add generic FDT memory bank decoding and gd initialization

2016-12-11 Thread Nathan Rossi 
Currently most boards that have static memory config (which cannot be
detected automatically) use CONFIG_SYS_SDRAM_SIZE to define the size of
memory which is hard coded into U-Boot. With the addition of device tree
support into U-Boot, boards that have device tree data can instead query
the memory bank information from the embedded or appended device tree.
This allows for more dynamic memory configuration and avoids the need to
hard code memory configuration into U-Boot.

The first patch of this series adds two helper functions for handling
the memory bank decoding and initialization of global data which can be
used by boards in their dram_init and dram_init_banksize functions. The
purpose of these helper functions is to provide generic functions that
handle the decoding and setup of memory and memory banks for boards that
intend to use this mechanism.

The series also changes the zynq and zynqmp board implementations to use
these functions to resolve a issue with static variable use.

Changes in v2:
 * Make fdtdec_setup_memory_banksize() return value consistent
 * Add more detail into the function documentation

Nathan Rossi (3):
  fdt: add memory bank decoding functions for board setup
  ARM: zynq: Replace board specific with generic memory bank decoding
  ARM64: zynqmp: Replace board specific with generic memory bank
decoding

 board/xilinx/zynq/board.c| 112 ++-
 board/xilinx/zynqmp/zynqmp.c | 112 ++-
 include/fdtdec.h |  34 +
 lib/fdtdec.c |  54 +
 4 files changed, 94 insertions(+), 218 deletions(-)

-- 
2.10.2
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[U-Boot] [PATCH v2 2/3] ARM: zynq: Replace board specific with generic memory bank decoding

2016-12-11 Thread Nathan Rossi 
The dram_init and dram_init_banksize functions were using a board
specific implementation for decoding the memory banks from the fdt. This
board specific implementation uses a static variable 'tmp' which makes
these functions unsafe for execution from within the board_init_f
context.

This unsafe use of a static variable was causing a specific bug when
using the zynq_zybo configuration, U-Boot would generate the following
error during image load. This was caused due to dram_init overwriting
the relocations for the 'image' variable within the do_bootm function.
Out of coincidence the un-initialized memory has a compression type
which is the same as the value for the relocation type R_ARM_RELATIVE.

   Uncompressing Invalid Image ... Unimplemented compression type 23

It should be noted that this is just one way the issue could surface,
other cases my not be observed in normal boot flow. Depending on the
size of various sections, and location of relocations within __rel_dyn
and the compiler/linker the outcome of this bug can differ greatly.

This change makes the dram_init* functions use a generic implementation
of decoding and populating memory bank and size data.

Signed-off-by: Nathan Rossi 
Fixes: 758f29d0f8 ("ARM: zynq: Support systems with more memory banks")
Cc: Michal Simek 
---
 board/xilinx/zynq/board.c | 112 ++
 1 file changed, 3 insertions(+), 109 deletions(-)

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 2c86940957..5cd9bbf711 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -124,121 +124,15 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 }
 
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
-/*
- * fdt_get_reg - Fill buffer by information from DT
- */
-static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
-  const u32 *cell, int n)
-{
-   int i = 0, b, banks;
-   int parent_offset = fdt_parent_offset(fdt, nodeoffset);
-   int address_cells = fdt_address_cells(fdt, parent_offset);
-   int size_cells = fdt_size_cells(fdt, parent_offset);
-   char *p = buf;
-   u64 val;
-   u64 vals;
-
-   debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
- __func__, address_cells, size_cells, buf, cell);
-
-   /* Check memory bank setup */
-   banks = n % (address_cells + size_cells);
-   if (banks)
-   panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
- n, address_cells, size_cells);
-
-   banks = n / (address_cells + size_cells);
-
-   for (b = 0; b < banks; b++) {
-   debug("%s: Bank #%d:\n", __func__, b);
-   if (address_cells == 2) {
-   val = cell[i + 1];
-   val <<= 32;
-   val |= cell[i];
-   val = fdt64_to_cpu(val);
-   debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
- __func__, val, p, [i]);
-   *(phys_addr_t *)p = val;
-   } else {
-   debug("%s: addr32=%x, ptr=%p\n",
- __func__, fdt32_to_cpu(cell[i]), p);
-   *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
-   }
-   p += sizeof(phys_addr_t);
-   i += address_cells;
-
-   debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
- sizeof(phys_addr_t));
-
-   if (size_cells == 2) {
-   vals = cell[i + 1];
-   vals <<= 32;
-   vals |= cell[i];
-   vals = fdt64_to_cpu(vals);
-
-   debug("%s: size64=%llx, ptr=%p, cell=%p\n",
- __func__, vals, p, [i]);
-   *(phys_size_t *)p = vals;
-   } else {
-   debug("%s: size32=%x, ptr=%p\n",
- __func__, fdt32_to_cpu(cell[i]), p);
-   *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
-   }
-   p += sizeof(phys_size_t);
-   i += size_cells;
-
-   debug("%s: ps=%p, i=%x, size=%zu\n",
- __func__, p, i, sizeof(phys_size_t));
-   }
-
-   /* Return the first address size */
-   return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
-}
-
-#define FDT_REG_SIZE  sizeof(u32)
-/* Temp location for sharing data for storing */
-/* Up to 64-bit address + 64-bit size */
-static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
-
 void dram_init_banksize(void)
 {
-   int bank;
-
-   memcpy(>bd->bi_dram[0], , sizeof(tmp));
-
-   for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-   debug("Bank #%d: start %llx\n", bank,
- (unsigned long

Re: [U-Boot] [PATCH] board: topic: Detect RAM size at boot

2016-12-11 Thread Michal Simek 
Hi Mike,

On 22.11.2016 12:00, Michal Simek wrote:
> On 21.11.2016 09:30, Mike Looijmans wrote:
>> Miami boards can have memory sizes of 256M, 512M or 1GB. To prevent requiring
>> separate bootloaders for each variant, just detect the RAM size at boot time
>> instead of relying on the devicetree information.
>>
>> Signed-off-by: Mike Looijmans 
>> ---
>>  board/topic/zynq/board.c  | 39 
>> +++
>>  configs/topic_miami_defconfig |  1 +
>>  configs/topic_miamiplus_defconfig |  1 +
>>  3 files changed, 41 insertions(+)
>>
>> diff --git a/board/topic/zynq/board.c b/board/topic/zynq/board.c
>> index a95c9d1..8a5765e 100644
>> --- a/board/topic/zynq/board.c
>> +++ b/board/topic/zynq/board.c
>> @@ -1 +1,40 @@
>> +/*
>> + * (C) Copyright 2016 Topic Embedded Products
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +/*
>> + * Miami boards can have memory sizes of 256M, 512M or 1GB. To prevent 
>> needing
>> + * separate bootloaders for each variant, just detect the RAM size at boot 
>> time
>> + * instead of relying on the devicetree information.
>> + */
>> +#define CONFIG_SYS_SDRAM_BASE   0
>> +#define CONFIG_SYS_SDRAM_SIZE   topic_get_sdram_size()
> 
> I am not happy with this but I see where you go.
> 
>> +#define CONFIG_SYS_SDRAM_SIZE_MAX 0x4000u
>> +
>> +static unsigned int topic_get_sdram_size(void);
>> +
>>  #include "../../xilinx/zynq/board.c"
>> +
>> +#include 
>> +
>> +int ft_board_setup(void *blob, bd_t *bd)
>> +{
>> +fdt_fixup_memory(blob, (u64)CONFIG_SYS_SDRAM_BASE, (u64)gd->ram_size);
>> +
>> +return 0;
>> +}
> 
> This action is taken at arch_fixup_fdt(). Can you please confirm that
> this is really needed? And it is not done there? That you don't
> duplicate stuff here.

Did you check this?

Thanks,
Michal




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Re: [U-Boot] [PATCH v1] fat: fatwrite: fix the command for FAT12

2016-12-11 Thread Benoît Thébaudeau 
Dear Stefan Brüns,

On Sun, Dec 11, 2016 at 12:29 AM, Stefan Bruens
 wrote:
> On Freitag, 9. Dezember 2016 13:55:37 CET Philipp Skadorov wrote:
>> The u-boot command fatwrite empties FAT clusters from the beginning
>> till the end of the file.
>> Specifically for FAT12 it fails to detect the end of the file and goes
>> beyond the file bounds thus corrupting the file system.
>>
>> The users normally workaround this by re-formatting the partition as
>> FAT16/FAT32, like here:
>> https://github.com/FEDEVEL/openrex-uboot-v2015.10/issues/1
>>
>> The patch is to check file bounds by already-existing macro that
>> accounts for FAT12.
>> The command then works correctly for all types of FAT.
>>
>> Signed-off-by: Philipp Skadorov 
>> Cc:Donggeun Kim 
>> ---
>>  fs/fat/fat_write.c | 5 +
>>  1 file changed, 1 insertion(+), 4 deletions(-)
>>
>> diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
>> index 40a3860..e4f600e 100644
>> --- a/fs/fat/fat_write.c
>> +++ b/fs/fat/fat_write.c
>> @@ -670,16 +670,13 @@ static int clear_fatent(fsdata *mydata, __u32 entry)
>>  {
>>   __u32 fat_val;
>>
>> - while (1) {
>> + while (!CHECK_CLUST(entry, mydata->fatsize)) {
>>   fat_val = get_fatent_value(mydata, entry);
>>   if (fat_val != 0)
>>   set_fatent_value(mydata, entry, 0);
>>   else
>>   break;
>>
>> - if (fat_val == 0xfff || fat_val == 0x)
>> - break;
>> -
>>   entry = fat_val;
>>   }
>
> NAK.
>
> This corrupts the file system, as set_fatent_value(...) has:
>
> switch (mydata->fatsize) {
> case 32:
> bufnum = entry / FAT32BUFSIZE;
> offset = entry - bufnum * FAT32BUFSIZE;
> break;
> case 16:
> bufnum = entry / FAT16BUFSIZE;
> offset = entry - bufnum * FAT16BUFSIZE;
> break;
> default:
> /* Unsupported FAT size */
> return -1;
> }

So this patch can be kept, but it needs to be combined with a new one
in a series to fully fix fatwrite for FAT12.

Best regards,
Benoît
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Re: [U-Boot] [PATCH 0/3] Add generic FDT memory bank decoding and gd initialization

2016-12-11 Thread Igor Grinberg 
Hi Nathan,

On 12/11/16 15:58, Nathan Rossi wrote:
> This series adds two functions for handling the memory bank decoding and
> initialization of global data for use by boards in their dram_init and
> dram_init_banksize functions.

I might have missed some discussions on this meter,
can you please provide the use cases for this?
IMO, the bootloader's job is to initialize the DRAM, detect its size, and pass
the detected DRAM configuration on to an OS.

> 
> The series also changes the zynq and zynqmp board implementations to use
> these functions to resolve a issue with static variable use.
> 
> Nathan Rossi (3):
>   fdt: add memory bank decoding functions for board setup
>   ARM: zynq: Replace board specific with generic memory bank decoding
>   ARM64: zynqmp: Replace board specific with generic memory bank
> decoding
> 
>  board/xilinx/zynq/board.c| 112 
> ++-
>  board/xilinx/zynqmp/zynqmp.c | 112 
> ++-
>  include/fdtdec.h |  25 ++
>  lib/fdtdec.c |  54 +
>  4 files changed, 85 insertions(+), 218 deletions(-)
> 

-- 
Regards,
Igor.
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Re: [U-Boot] [PATCH 1/2] fs/fat: Avoid corruption of sectors following the FAT

2016-12-11 Thread Benoît Thébaudeau 
Dear Stefan Brüns,

On Sun, Dec 11, 2016 at 3:32 AM, Stefan Brüns
 wrote:
> From: Stefan Brüns 
>
> The FAT is read/flushed in segments of 6 (FATBUFBLOCKS) disk sectors. The
> last segment may be less than 6 sectors, cap the length.
>
> Signed-off-by: Stefan Brüns 

[...]

There's a character encoding issue for the "ü" in your last name in
"From:". It is correct in your "Signed-off-by:". Apart from that:
Reviewed-by: Benoît Thébaudeau 

Best regards,
Benoît
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[U-Boot] [PATCH V2 14/19] OCOTP: Update OCOTP driver to support i.MX6SLL

2016-12-11 Thread Peng Fan 
Add the i.MX6SLL support to OCOTP driver.

The i.MX6SLL reuses the i.MX6ULL fuse, bank 7 and bank8 have 4 words
each, and there is a hole between bank 5 and bank 6.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
---
 drivers/misc/mxc_ocotp.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 8a100c1..0b1c050 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -62,7 +62,7 @@
 #define FUSE_BANK_SIZE 0x80
 #ifdef CONFIG_MX6SL
 #define FUSE_BANKS 8
-#elif defined(CONFIG_MX6ULL)
+#elif defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)
 #define FUSE_BANKS 9
 #else
 #define FUSE_BANKS 16
@@ -79,7 +79,7 @@
 /*
  * There is a hole in shadow registers address map of size 0x100
  * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX,
- * iMX6UL and i.MX6ULL.
+ * iMX6UL, i.MX6ULL and i.MX6SLL.
  * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
  * we should account for this hole in address space.
  *
@@ -100,8 +100,8 @@ u32 fuse_bank_physical(int index)
 
if (is_mx6sl()) {
phy_index = index;
-   } else if (is_mx6ul() || is_mx6ull()) {
-   if (is_mx6ull() && index == 8)
+   } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
+   if ((is_mx6ull() || is_mx6sll()) && index == 8)
index = 7;
 
if (index >= 6)
@@ -121,7 +121,7 @@ u32 fuse_bank_physical(int index)
 
 u32 fuse_word_physical(u32 bank, u32 word_index)
 {
-   if (is_mx6ull()) {
+   if (is_mx6ull() || is_mx6sll()) {
if (bank == 8)
word_index = word_index + 4;
}
@@ -164,10 +164,10 @@ static int prepare_access(struct ocotp_regs **regs, u32 
bank, u32 word,
return -EINVAL;
}
 
-   if (is_mx6ull()) {
+   if (is_mx6ull() || is_mx6sll()) {
if ((bank == 7 || bank == 8) &&
word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) {
-   printf("mxc_ocotp %s(): Invalid argument on 6ULL\n", 
caller);
+   printf("mxc_ocotp %s(): Invalid argument\n", caller);
return -EINVAL;
}
}
@@ -271,7 +271,7 @@ static void setup_direct_access(struct ocotp_regs *regs, 
u32 bank, u32 word,
 #else
u32 addr;
/* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
-   if ((is_mx6ull()) && (bank > 7)) {
+   if ((is_mx6ull() || is_mx6sll()) && (bank > 7)) {
bank = bank - 1;
word += 4;
}
-- 
2.6.2

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[U-Boot] [PATCH v3 1/2] test/py: Pass u_boot_log instead of console for run_and_log

2016-12-11 Thread Stefan Brüns 
From: Stefan Brüns 

The runner actually has no console dependency, only on the log provided
by the console.

Signed-off-by: Stefan Brüns 
---
Alternate approach to the previous patch, always pass the logfile, change
all callers accordingly.

 test/py/tests/test_dfu.py   |  2 +-
 test/py/tests/test_ums.py   | 10 +-
 test/py/tests/test_vboot.py | 18 +-
 test/py/u_boot_utils.py | 12 ++--
 4 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/test/py/tests/test_dfu.py b/test/py/tests/test_dfu.py
index 585e6b29d7..b4f9a32abc 100644
--- a/test/py/tests/test_dfu.py
+++ b/test/py/tests/test_dfu.py
@@ -206,7 +206,7 @@ def test_dfu(u_boot_console, env__usb_dev_port, 
env__dfu_config):
 cmd = ['dfu-util', '-a', alt_setting, up_dn_load_arg, fn]
 if 'host_usb_port_path' in env__usb_dev_port:
 cmd += ['-p', env__usb_dev_port['host_usb_port_path']]
-u_boot_utils.run_and_log(u_boot_console, cmd)
+u_boot_utils.run_and_log(u_boot_console.log, cmd)
 u_boot_console.wait_for('Ctrl+C to exit ...')
 
 def dfu_write(alt_setting, fn):
diff --git a/test/py/tests/test_ums.py b/test/py/tests/test_ums.py
index 8c3ee2b053..54c47b0aee 100644
--- a/test/py/tests/test_ums.py
+++ b/test/py/tests/test_ums.py
@@ -156,7 +156,7 @@ def test_ums(u_boot_console, env__usb_dev_port, 
env__block_devs):
 
 u_boot_console.log.action('Mounting exported UMS device')
 cmd = ('/bin/mount', host_ums_part_node)
-u_boot_utils.run_and_log(u_boot_console, cmd)
+u_boot_utils.run_and_log(u_boot_console.log, cmd)
 
 def umount(ignore_errors):
 """Unmount the block device that U-Boot exports.
@@ -173,7 +173,7 @@ def test_ums(u_boot_console, env__usb_dev_port, 
env__block_devs):
 
 u_boot_console.log.action('Unmounting UMS device')
 cmd = ('/bin/umount', host_ums_part_node)
-u_boot_utils.run_and_log(u_boot_console, cmd, ignore_errors)
+u_boot_utils.run_and_log(u_boot_console.log, cmd, ignore_errors)
 
 def stop_ums(ignore_errors):
 """Stop U-Boot's ums shell command from executing.
@@ -207,11 +207,11 @@ def test_ums(u_boot_console, env__usb_dev_port, 
env__block_devs):
 mount()
 u_boot_console.log.action('Writing test file via UMS')
 cmd = ('rm', '-f', mounted_test_fn)
-u_boot_utils.run_and_log(u_boot_console, cmd)
+u_boot_utils.run_and_log(u_boot_console.log, cmd)
 if os.path.exists(mounted_test_fn):
 raise Exception('Could not rm target UMS test file')
 cmd = ('cp', test_f.abs_fn, mounted_test_fn)
-u_boot_utils.run_and_log(u_boot_console, cmd)
+u_boot_utils.run_and_log(u_boot_console.log, cmd)
 ignore_cleanup_errors = False
 finally:
 umount(ignore_errors=ignore_cleanup_errors)
@@ -226,7 +226,7 @@ def test_ums(u_boot_console, env__usb_dev_port, 
env__block_devs):
 u_boot_console.log.action('Reading test file back via UMS')
 read_back_hash = u_boot_utils.md5sum_file(mounted_test_fn)
 cmd = ('rm', '-f', mounted_test_fn)
-u_boot_utils.run_and_log(u_boot_console, cmd)
+u_boot_utils.run_and_log(u_boot_console.log, cmd)
 ignore_cleanup_errors = False
 finally:
 umount(ignore_errors=ignore_cleanup_errors)
diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py
index 6e62820743..0f893f1e91 100644
--- a/test/py/tests/test_vboot.py
+++ b/test/py/tests/test_vboot.py
@@ -50,7 +50,7 @@ def test_vboot(u_boot_console):
 dts: Device tree file to compile.
 """
 dtb = dts.replace('.dts', '.dtb')
-util.run_and_log(cons, 'dtc %s %s%s -O dtb '
+util.run_and_log(cons.log, 'dtc %s %s%s -O dtb '
  '-o %s%s' % (dtc_args, datadir, dts, tmpdir, dtb))
 
 def run_bootm(sha_algo, test_type, expect_string, boots):
@@ -85,7 +85,7 @@ def test_vboot(u_boot_console):
 Args:
 its: Filename containing .its source.
 """
-util.run_and_log(cons, [mkimage, '-D', dtc_args, '-f',
+util.run_and_log(cons.log, [mkimage, '-D', dtc_args, '-f',
 '%s%s' % (datadir, its), fit])
 
 def sign_fit(sha_algo):
@@ -99,7 +99,7 @@ def test_vboot(u_boot_console):
 use.
 """
 cons.log.action('%s: Sign images' % sha_algo)
-util.run_and_log(cons, [mkimage, '-F', '-k', tmpdir, '-K', dtb,
+util.run_and_log(cons.log, [mkimage, '-F', '-k', tmpdir, '-K', dtb,
 '-r', fit])
 
 def test_with_algo(sha_algo):
@@ -140,23 +140,23 @@ def test_vboot(u_boot_console):
 
 cons.log.action('%s: Check signed config on the host' % sha_algo)
 
-util.run_and_log(cons, [fit_check_sign, '-f',

[U-Boot] [PATCH V2 16/19] pinctrl: imx6: support i.MX6SLL

2016-12-11 Thread Peng Fan 
There two iomuxc for i.MX6SLL. One is normal IOMUXC, the other
is for IOMUXC_SNVS.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Simon Glass 
Reviewed-by: Simon Glass 
---
 drivers/pinctrl/nxp/pinctrl-imx6.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c 
b/drivers/pinctrl/nxp/pinctrl-imx6.c
index 32b4754..4488b16 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx6.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx6.c
@@ -28,6 +28,8 @@ static const struct udevice_id imx6_pinctrl_match[] = {
{ .compatible = "fsl,imx6q-iomuxc", .data = 
(ulong)_pinctrl_soc_info },
{ .compatible = "fsl,imx6dl-iomuxc", .data = 
(ulong)_pinctrl_soc_info },
{ .compatible = "fsl,imx6sl-iomuxc", .data = 
(ulong)_pinctrl_soc_info },
+   { .compatible = "fsl,imx6sll-iomuxc-snvs", .data = 
(ulong)_snvs_pinctrl_soc_info },
+   { .compatible = "fsl,imx6sll-iomuxc", .data = 
(ulong)_pinctrl_soc_info },
{ .compatible = "fsl,imx6sx-iomuxc", .data = 
(ulong)_pinctrl_soc_info },
{ .compatible = "fsl,imx6ul-iomuxc", .data = 
(ulong)_pinctrl_soc_info },
{ .compatible = "fsl,imx6ull-iomuxc-snvs", .data = 
(ulong)_snvs_pinctrl_soc_info },
-- 
2.6.2

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Re: [U-Boot] ext4: crash when writing a file

2016-12-11 Thread Stefan Bruens 
On Dienstag, 29. November 2016 16:23:28 CET Sébastien Szymanski wrote:
> On 11/29/2016 03:38 PM, Brüns, Stefan wrote:
> > On Dienstag, 29. November 2016 14:10:54 CET Sébastien Szymanski wrote:
> >>> Btw, which u-boot version are you using?
> >> 
> >> I first noticed the issue on U-Boot 2016.05 so I rebase on master from
> >> http://git.denx.de/u-boot.git
> >> 
> >> Regards,
> > 
> > That still doesn't make clear on which version you see this issue.
> > 2016.05?
> > Master? Which date/tag/hash?
> > 
> > U-Boot 2016.11 has received a huge number of fixes, and current master has
> > some more.
> 
> Sorry for being unclear.
> 
> I was working with U-Boot 2016.05 (commit
> aeaec0e682f45b9e0c62c522fafea353931f73ed) when I saw this issue. Then, I
> rebased on current master (commit
> e94793c844a40606252f2e3f6428063e057b3fd2) and I still see this issue.
> 
> I hope it's clearer now.
> 
> Regards,
> 
> > Regards,
> > 
> > Stefan
> 
> Sébastien Szymanski

So to restate what you are doing:

1. You have a partitioned MMC, where the 2nd partition starts at block 
264192/0x40800
2. You load a 93958144 byte (~90 MB) file via TFTP to ${loadaddr}
3. You write this partition image to 0x40800 using "mmc write"
4. You load another 5345128 byte (5 MB) file via TFTP to $loadaddr
5. You try to write this file to the 2nd partition, which now is ext4 
formatted, and already contains a file of the same name, i.e. boot/opos6ul-
linux.bin


Actually, I can't reproduce the crash. Maybe you have corrupted part of the 
memory when loading the image, e.g. overwritten part of u-boot or its heap.

Things you can try:
a) reboot the system after loading/writing the partion image.
b) checking the fs contents after the reboot, e.g "ls mmc 0:2 /boot" 
c) overwriting opos6ul-linux.bin with just a single byte, e.g "ext4write mmc 
0:2 0x0 /boot/opos6ul-linux.bin 1"
d) transferring back the partition image to your host and running fschk on it

You may also able to reproduce this using the u-boot sandbox.

Kind regards,

Stefan



-- 
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home: +49 241 53809034 mobile: +49 151 50412019
work: +49 2405 49936-424
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Re: [U-Boot] [PATCH v4 2/2] splash: add support for loading splash from a FIT image

2016-12-11 Thread Igor Grinberg 
Hi Tomas, Simon,

Sorry, to break in that late...
I have a quick question below.

On 12/05/16 09:36, Tomas Melin wrote:
> Enable support for loading a splash image from within a FIT image.
> The image is assumed to be generated with mkimage -E flag to hold
> the data external to the FIT.
> 
> Signed-off-by: Tomas Melin 

[...]

> diff --git a/common/splash_source.c b/common/splash_source.c
> index 70d724f..94b46d3 100644
> --- a/common/splash_source.c
> +++ b/common/splash_source.c

[...]

> +#ifdef CONFIG_FIT
> +static int splash_load_fit(struct splash_location *location, u32 
> bmp_load_addr)
> +{
> + int res;
> + int node_offset;
> + int splash_offset;
> + int splash_size;
> + struct image_header *img_header;
> + const u32 *fit_header;
> + u32 fit_size;
> + const size_t header_size = sizeof(struct image_header);
> +
> + /* Read in image header */
> + res = splash_storage_read_raw(location, bmp_load_addr, header_size);
> + if (res < 0)
> + return res;
> +
> + img_header = (struct image_header *)bmp_load_addr;
> + fit_size = fdt_totalsize(img_header);
> +
> + /* Read in entire FIT */
> + fit_header = (const u32 *)(bmp_load_addr + header_size);
> + res = splash_storage_read_raw(location, (u32)fit_header, fit_size);
> + if (res < 0)
> + return res;
> +
> + res = fit_check_format(fit_header);
> + if (!res) {
> + debug("Could not find valid FIT image\n");
> + return -EINVAL;
> + }
> +
> + node_offset = fit_image_get_node(fit_header, location->name);
> + if (node_offset < 0) {
> + debug("Could not find splash image '%s' in FIT\n",
> +   location->name);
> + return -ENOENT;
> + }
> +

I think two above debug() are very legitimate - no need to shout if no FIT image
or no splash in it...

> + res = fit_image_get_data_offset(fit_header, node_offset,
> + _offset);
> + if (res < 0) {
> + debug("Could not find 'data-offset' property in FIT\n");
> + return res;
> + }
> +
> + res = fit_image_get_data_size(fit_header, node_offset, _size);
> + if (res < 0) {
> + debug("Could not find 'data-size' property in FIT\n");
> + return res;
> + }

Now regarding these two, I'm not sure.
Since we have found a valid FIT and also a node with a correct splash name,
probably the intent is that we show the splash, right?
But in the two above checks, we find inconsistencies that do not allow us to
show the splash - meaning the FIT is not actually good (am I right here?).
So may be we should report it to the 'user' and allow correcting the FIT?
Otherwise, it is impossible to debug the image w/o a debug version of U-Boot...
Do I make sense, or do I miss something?

> +
> + /* Align data offset to 4-byte boundrary */
> + fit_size = fdt_totalsize(fit_header);
> + fit_size = (fit_size + 3) & ~3;
> +
> + /* Read in the splash data */
> + location->offset = (location->offset + fit_size + splash_offset);
> + res = splash_storage_read_raw(location, bmp_load_addr , splash_size);
> + if (res < 0)
> + return res;
> +
> + return 0;
> +}
> +#endif /* CONFIG_FIT */
> +
>  /**
>   * splash_source_load - load splash image from a supported location.
>   *
> @@ -277,5 +344,9 @@ int splash_source_load(struct splash_location *locations, 
> uint size)
>   return splash_load_raw(splash_location, bmp_load_addr);
>   else if (splash_location->flags == SPLASH_STORAGE_FS)
>   return splash_load_fs(splash_location, bmp_load_addr);
> +#ifdef CONFIG_FIT
> + else if (splash_location->flags == SPLASH_STORAGE_FIT)
> + return splash_load_fit(splash_location, bmp_load_addr);
> +#endif
>   return -EINVAL;
>  }
> diff --git a/doc/README.splashprepare b/doc/README.splashprepare
> index 56c1bef..f1418de 100644
> --- a/doc/README.splashprepare
> +++ b/doc/README.splashprepare
> @@ -5,7 +5,7 @@ The splash_screen_prepare() function is a weak function 
> defined in
>  common/splash.c. It is called as part of the splash screen display
>  sequence. It gives the board an opportunity to prepare the splash
>  image data before it is processed and sent to the frame buffer by
> -U-Boot.  Define your own version to use this feature.
> +U-Boot. Define your own version to use this feature.
>  
>  CONFIG_SPLASH_SOURCE
>  
> @@ -20,7 +20,12 @@ splashsource works as follows:
>  - If splashsource is undefined, use the first splash location as default.
>  - If splashsource is set to an unsupported value, do not load a splash 
> screen.
>  
> -A splash source location can describe either storage with raw data, or 
> storage
> -formatted with a file system. In case of a filesystem, the splash screen 
> data is
> -loaded as a file. The name of the splash screen file can be controlled with 
> the
>

Re: [U-Boot] [PATCH 2/2] fs/fat: merge readwrite get_fatent_value() with readonly get_fatent()

2016-12-11 Thread Benoît Thébaudeau 
Dear Stefan Brüns,

On Sun, Dec 11, 2016 at 3:32 AM, Stefan Brüns
 wrote:
> get_fatent_value(...) flushes changed FAT entries to disk when fetching
> the next FAT blocks, in every other aspect it is identical to
> get_fatent(...).
>
> Provide a stub implementation for flush_dirty_fat_buffer if
> CONFIG_FAT_WRITE is not set. Calling flush_dirty_fat_buffer during read
> only operation is fine as it checks if any buffers needs flushing.
>
> Signed-off-by: Stefan Brüns 
> ---
>  fs/fat/fat.c   |  19 +
>  fs/fat/fat_write.c | 118 
> +++--
>  2 files changed, 24 insertions(+), 113 deletions(-)

[...]

> diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
> index 0be60ecd99..c05fc7f099 100644
> --- a/fs/fat/fat_write.c
> +++ b/fs/fat/fat_write.c
> @@ -143,114 +143,6 @@ static int flush_dirty_fat_buffer(fsdata *mydata)
>  }
>
>  /*
> - * Get the entry at index 'entry' in a FAT (12/16/32) table.
> - * On failure 0x00 is returned.
> - * When bufnum is changed, write back the previous fatbuf to the disk.
> - */
> -static __u32 get_fatent_value(fsdata *mydata, __u32 entry)
> -{

[...]

> -   debug("FAT%d: ret: %08x, entry: %08x, offset: %04x\n",
> -  mydata->fatsize, ret, entry, offset);

It might be worth adding this entry info to the same line in get_fatent().

> -
> -   return ret;
> -}

[...]

Apart from that:
Reviewed-by: Benoît Thébaudeau 

Best regards,
Benoît
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[U-Boot] [PATCH V2 05/19] imx: mx6sll: add iomux settings

2016-12-11 Thread Peng Fan 
Add iomux settings for i.MX6 SLL

Signed-off-by: Peng Fan 
Signed-off-by: Ye.Li 
Cc: Stefano Babic 
---
 arch/arm/imx-common/iomux-v3.c | 10 +++---
 arch/arm/include/asm/imx-common/iomux-v3.h |  6 --
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 392f4bc..c9a3bf2 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -31,7 +31,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
 
-#if defined CONFIG_MX6SL
+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
/* Check whether LVE bit needs to be set */
if (pad_ctrl & PAD_CTL_LVE) {
pad_ctrl &= ~PAD_CTL_LVE;
@@ -51,7 +51,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
}
 #else
-   if (is_mx6ull()) {
+   if (is_mx6ull() || is_mx6sll()) {
if (lpsr == IOMUX_CONFIG_LPSR) {
base = (void *)IOMUXC_SNVS_BASE_ADDR;
mux_mode &= ~IOMUX_CONFIG_LPSR;
@@ -60,7 +60,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
 #endif
 #endif
 
-   if (is_soc_type(MXC_SOC_MX7) || is_cpu_type(MXC_CPU_MX6ULL) || 
mux_ctrl_ofs)
+   if (is_mx7() || is_mx6ull() || is_mx6sll() || mux_ctrl_ofs)
__raw_writel(mux_mode, base + mux_ctrl_ofs);
 
if (sel_input_ofs)
@@ -73,6 +73,10 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
 #else
if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
+#if defined(CONFIG_MX6SLL)
+   else if ((pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
+   clrbits_le32(base + pad_ctrl_ofs, PAD_CTL_IPD_BIT);
+#endif
 #endif
 
 #ifdef CONFIG_IOMUX_LPSR
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h 
b/arch/arm/include/asm/imx-common/iomux-v3.h
index b3af696..7587cbb 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -144,10 +144,12 @@ typedef u64 iomux_v3_cfg_t;
 #define PAD_CTL_DSE_40ohm  (6 << 3)
 #define PAD_CTL_DSE_34ohm  (7 << 3)
 
-#if defined CONFIG_MX6SL
+/* i.MX6SL/SLL */
 #define PAD_CTL_LVE(1 << 1)
 #define PAD_CTL_LVE_BIT(1 << 22)
-#endif
+
+/* i.MX6SLL */
+#define PAD_CTL_IPD_BIT(1 << 27)
 
 #elif defined(CONFIG_VF610)
 
-- 
2.6.2

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Re: [U-Boot] [PATCH 0/3] Add generic FDT memory bank decoding and gd initialization

2016-12-11 Thread Nathan Rossi 
On 12 December 2016 at 01:08, Igor Grinberg  wrote:
> Hi Nathan,
>
> On 12/11/16 15:58, Nathan Rossi wrote:
>> This series adds two functions for handling the memory bank decoding and
>> initialization of global data for use by boards in their dram_init and
>> dram_init_banksize functions.
>
> I might have missed some discussions on this meter,
> can you please provide the use cases for this?
> IMO, the bootloader's job is to initialize the DRAM, detect its size, and pass
> the detected DRAM configuration on to an OS.

Hi Igor,

I do not think there have been any discussions on this (at least none
that I am aware of).

Some boards (like Zynq and ZynqMP ones) are using
CONFIG_SYS_SDRAM_SIZE to define the amount of memory that is available
(since detection is not possible). However with the introduction of
dtbs for some boards they are also capable of loading the size of
memory from the embedded/appended dtb (instead of hardcoded). This
allows for more of the board config to be loaded from the device tree
instead of from include/configs/*.h. This however is up to the
individual board to implement in its dram_init* functions.

The first patch of the series is only adding some decoding helper
functions to make this generic between the Zynq and ZynqMP boards as
well as to allow for any other boards that may want to use the same
mechanism to get the memory size from the fdt. There is no requirement
for boards to use these functions.

Regards,
Nathan

>
>>
>> The series also changes the zynq and zynqmp board implementations to use
>> these functions to resolve a issue with static variable use.
>>
>> Nathan Rossi (3):
>>   fdt: add memory bank decoding functions for board setup
>>   ARM: zynq: Replace board specific with generic memory bank decoding
>>   ARM64: zynqmp: Replace board specific with generic memory bank
>> decoding
>>
>>  board/xilinx/zynq/board.c| 112 
>> ++-
>>  board/xilinx/zynqmp/zynqmp.c | 112 
>> ++-
>>  include/fdtdec.h |  25 ++
>>  lib/fdtdec.c |  54 +
>>  4 files changed, 85 insertions(+), 218 deletions(-)
>>
>
> --
> Regards,
> Igor.
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Re: [U-Boot] [PATCH 0/3] Add generic FDT memory bank decoding and gd initialization

2016-12-11 Thread Igor Grinberg 
On 12/11/16 18:47, Nathan Rossi wrote:
> On 12 December 2016 at 01:08, Igor Grinberg  wrote:
>> Hi Nathan,
>>
>> On 12/11/16 15:58, Nathan Rossi wrote:
>>> This series adds two functions for handling the memory bank decoding and
>>> initialization of global data for use by boards in their dram_init and
>>> dram_init_banksize functions.
>>
>> I might have missed some discussions on this meter,
>> can you please provide the use cases for this?
>> IMO, the bootloader's job is to initialize the DRAM, detect its size, and 
>> pass
>> the detected DRAM configuration on to an OS.
> 
> Hi Igor,
> 
> I do not think there have been any discussions on this (at least none
> that I am aware of).
> 
> Some boards (like Zynq and ZynqMP ones) are using
> CONFIG_SYS_SDRAM_SIZE to define the amount of memory that is available
> (since detection is not possible). However with the introduction of
> dtbs for some boards they are also capable of loading the size of
> memory from the embedded/appended dtb (instead of hardcoded). This
> allows for more of the board config to be loaded from the device tree
> instead of from include/configs/*.h. This however is up to the
> individual board to implement in its dram_init* functions.

Thanks for the explanation!
I assume that the key point is "detection is not possible" and therefore
we must rely on a user or a production process to place (append) the correct 
dtb.
Makes sense to me now and looks like an improvement to the current situation.

> 
> The first patch of the series is only adding some decoding helper
> functions to make this generic between the Zynq and ZynqMP boards as
> well as to allow for any other boards that may want to use the same
> mechanism to get the memory size from the fdt. There is no requirement
> for boards to use these functions.

Can you please next time place a similar explanation in at least the cover
letter. This way, the intent might be understood the first time ;-)
I would also like to see some parts of the above explanation in the functions
documentation (e.g. this allows to improve the DRAM configuration mechanics
on boards that cannot detect its DRAM size/config).

Thanks!

> 
> Regards,
> Nathan
> 
>>
>>>
>>> The series also changes the zynq and zynqmp board implementations to use
>>> these functions to resolve a issue with static variable use.
>>>
>>> Nathan Rossi (3):
>>>   fdt: add memory bank decoding functions for board setup
>>>   ARM: zynq: Replace board specific with generic memory bank decoding
>>>   ARM64: zynqmp: Replace board specific with generic memory bank
>>> decoding
>>>
>>>  board/xilinx/zynq/board.c| 112 
>>> ++-
>>>  board/xilinx/zynqmp/zynqmp.c | 112 
>>> ++-
>>>  include/fdtdec.h |  25 ++
>>>  lib/fdtdec.c |  54 +
>>>  4 files changed, 85 insertions(+), 218 deletions(-)
>>>
>>
>> --
>> Regards,
>> Igor.
> 

-- 
Regards,
Igor.
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[U-Boot] build u-boot

2016-12-11 Thread Zuoping Han 
Hi, I want to build u-boot to boot from UART, but I have problem with it.Is 
there any special options I have to select to build it?My system is arm am3352.
Thanks, Zuoping Han
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[U-Boot] [PATCH V2 17/19] arm: dts: add i.MX6SLL device tree

2016-12-11 Thread Peng Fan 
Add i.MX6SLL device tree.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/dts/imx6sll-pinfunc.h| 882 ++
 arch/arm/dts/imx6sll.dtsi | 859 +
 include/dt-bindings/clock/imx6sll-clock.h | 204 +++
 3 files changed, 1945 insertions(+)
 create mode 100644 arch/arm/dts/imx6sll-pinfunc.h
 create mode 100644 arch/arm/dts/imx6sll.dtsi
 create mode 100644 include/dt-bindings/clock/imx6sll-clock.h

diff --git a/arch/arm/dts/imx6sll-pinfunc.h b/arch/arm/dts/imx6sll-pinfunc.h
new file mode 100644
index 000..5a3700b
--- /dev/null
+++ b/arch/arm/dts/imx6sll-pinfunc.h
@@ -0,0 +1,882 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6SLL_PINFUNC_H
+#define __DTS_IMX6SLL_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * 
+ */
+#define MX6SLL_PAD_WDOG_B__WDOG1_B0x0014 
0x02DC 0x 0x0 0x0
+#define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB  0x0014 
0x02DC 0x 0x1 0x0
+#define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 
0x02DC 0x 0x2 0x0
+#define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 
0x02DC 0x 0x5 0x0
+#define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M   0x0018 
0x02E0 0x 0x0 0x0
+#define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL  0x0018 
0x02E0 0x068C 0x1 0x0
+#define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT  0x0018 
0x02E0 0x 0x2 0x0
+#define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID   0x0018 
0x02E0 0x0560 0x3 0x0
+#define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY0x0018 
0x02E0 0x05AC 0x4 0x0
+#define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO210x0018 
0x02E0 0x 0x5 0x0
+#define MX6SLL_PAD_REF_CLK_24M__SD3_WP0x0018 
0x02E0 0x0794 0x6 0x0
+#define MX6SLL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K   0x001C 
0x02E4 0x 0x0 0x0
+#define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA  0x001C 
0x02E4 0x0690 0x1 0x0
+#define MX6SLL_PAD_REF_CLK_32K__PWM4_OUT  0x001C 
0x02E4 0x 0x2 0x0
+#define MX6SLL_PAD_REF_CLK_32K__USB_OTG1_ID   0x001C 
0x02E4 0x055C 0x3 0x0
+#define MX6SLL_PAD_REF_CLK_32K__SD1_LCTL  0x001C 
0x02E4 0x 0x4 0x0
+#define MX6SLL_PAD_REF_CLK_32K__GPIO3_IO220x001C 
0x02E4 0x 0x5 0x0
+#define MX6SLL_PAD_REF_CLK_32K__SD3_CD_B  0x001C 
0x02E4 0x0780 0x6 0x0
+#define MX6SLL_PAD_PWM1__PWM1_OUT 0x0020 
0x02E8 0x 0x0 0x0
+#define MX6SLL_PAD_PWM1__CCM_CLKO 0x0020 
0x02E8 0x 0x1 0x0
+#define MX6SLL_PAD_PWM1__AUDIO_CLK_OUT0x0020 
0x02E8 0x 0x2 0x0
+#define MX6SLL_PAD_PWM1__CSI_MCLK 0x0020 
0x02E8 0x 0x4 0x0
+#define MX6SLL_PAD_PWM1__GPIO3_IO23   0x0020 
0x02E8 0x 0x5 0x0
+#define MX6SLL_PAD_PWM1__EPIT1_OUT0x0020 
0x02E8 0x 0x6 0x0
+#define MX6SLL_PAD_KEY_COL0__KEY_COL0 0x0024 
0x02EC 0x06A0 0x0 0x0
+#define MX6SLL_PAD_KEY_COL0__I2C2_SCL 0x0024 
0x02EC 0x0684 0x1 0x0
+#define MX6SLL_PAD_KEY_COL0__LCD_DATA00   0x0024 
0x02EC 0x06D8 0x2 0x0
+#define MX6SLL_PAD_KEY_COL0__SD1_CD_B 0x0024 
0x02EC 0x0770 0x4 0x1
+#define MX6SLL_PAD_KEY_COL0__GPIO3_IO24   0x0024 
0x02EC 0x 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW0__KEY_ROW0 0x0028 
0x02F0 0x06C0 0x0 0x0
+#define MX6SLL_PAD_KEY_ROW0__I2C2_SDA 0x0028 
0x02F0 0x0688 0x1 0x0
+#define MX6SLL_PAD_KEY_ROW0__LCD_DATA01   0x0028 
0x02F0 0x06DC 0x2 0x0
+#define MX6SLL_PAD_KEY_ROW0__SD1_WP   0x0028 
0x02F0 0x0774 0x4 0x1
+#define MX6SLL_PAD_KEY_ROW0__GPIO3_IO25   0x0028 
0x02F0 0x 0x5 0x0
+#define MX6SLL_PAD_KEY_COL1__KEY_COL1 0x002C 
0x02F4 0x06A4 0x0 0x0
+#define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI  0x002C 
0x02F4 0x0658 0x1 0x1
+#define MX6SLL_PAD_KEY_COL1__LCD_DATA02   0x002C 
0x02F4 0x06E0 0x2 0x0
+#define MX6SLL_PAD_KEY_COL1__SD3_DATA40x002C 
0x02F4 0x0784 0x4 0x0
+#define MX6SLL_PAD_KEY_COL1__GPIO3_IO26   0x002C 
0x02F4 0x 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW1__KEY_ROW1 0x0030 
0x02F8 0x06C4 0x0 0x0
+#define

[U-Boot] genext2fs fix for supporting filesystems generated by genext2fs

2016-12-11 Thread FrostyBytes 
I found that the latest U-Boot cannot handle filesystems generated by 
genext2fs. Attempts to list such a filesystem results in divide by zero.

Using git bisect with a test script, I got:

f798b1dda1c5de818b806189e523d1b75db7e72d is the first bad commit

That commit changes to using fs->gdsize rather than a calculated descriptor 
size.

The problem is that ext4fs_mount does not set fs->gdsize when revision_level is 
zero.

The simplest fix seemed to be to plug in the old calculation into the case when 
revision_level is zero, which made the problem go away. I know next to nothing 
about the internals ext2/3/4, so this may not be the right thing to do. I'm 
attaching a patch anyways:

The patch is also available at the following URL if the mailer has mangled it: 
https://ptpb.pw/KcQI

diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index bfebe7e..fa83586 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -2334,6 +2334,7 @@ int ext4fs_mount(unsigned part_length)

if (le32_to_cpu(data->sblock.revision_level) == 0) {
fs->inodesz = 128;
+ fs->gdsize = EXT2_BLOCK_SIZE(data) / sizeof(struct ext2_block_group);
} else {
debug("EXT4 features COMPAT: %08x INCOMPAT: %08x RO_COMPAT: %08x\n",
__le32_to_cpu(data->sblock.feature_compatibility),


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Re: [U-Boot] [PATCH v1] fat: fatwrite: fix the command for FAT12

2016-12-11 Thread Philipp Skadorov 
Good morning,
I will update and test set_fatent_value as well and will send you patch v.2

Regards,
Philipp

> On Dec 11, 2016, at 10:05 AM, Benoît Thébaudeau 
>  wrote:
> 
> Dear Stefan Brüns,
> 
> On Sun, Dec 11, 2016 at 12:29 AM, Stefan Bruens
>  wrote:
>> On Freitag, 9. Dezember 2016 13:55:37 CET Philipp Skadorov wrote:
>>> The u-boot command fatwrite empties FAT clusters from the beginning
>>> till the end of the file.
>>> Specifically for FAT12 it fails to detect the end of the file and goes
>>> beyond the file bounds thus corrupting the file system.
>>> 
>>> The users normally workaround this by re-formatting the partition as
>>> FAT16/FAT32, like here:
>>> https://github.com/FEDEVEL/openrex-uboot-v2015.10/issues/1
>>> 
>>> The patch is to check file bounds by already-existing macro that
>>> accounts for FAT12.
>>> The command then works correctly for all types of FAT.
>>> 
>>> Signed-off-by: Philipp Skadorov 
>>> Cc:Donggeun Kim 
>>> ---
>>> fs/fat/fat_write.c | 5 +
>>> 1 file changed, 1 insertion(+), 4 deletions(-)
>>> 
>>> diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
>>> index 40a3860..e4f600e 100644
>>> --- a/fs/fat/fat_write.c
>>> +++ b/fs/fat/fat_write.c
>>> @@ -670,16 +670,13 @@ static int clear_fatent(fsdata *mydata, __u32 entry)
>>> {
>>>  __u32 fat_val;
>>> 
>>> - while (1) {
>>> + while (!CHECK_CLUST(entry, mydata->fatsize)) {
>>>  fat_val = get_fatent_value(mydata, entry);
>>>  if (fat_val != 0)
>>>  set_fatent_value(mydata, entry, 0);
>>>  else
>>>  break;
>>> 
>>> - if (fat_val == 0xfff || fat_val == 0x)
>>> - break;
>>> -
>>>  entry = fat_val;
>>>  }
>> 
>> NAK.
>> 
>> This corrupts the file system, as set_fatent_value(...) has:
>> 
>>switch (mydata->fatsize) {
>>case 32:
>>bufnum = entry / FAT32BUFSIZE;
>>offset = entry - bufnum * FAT32BUFSIZE;
>>break;
>>case 16:
>>bufnum = entry / FAT16BUFSIZE;
>>offset = entry - bufnum * FAT16BUFSIZE;
>>break;
>>default:
>>/* Unsupported FAT size */
>>return -1;
>>}
> 
> So this patch can be kept, but it needs to be combined with a new one
> in a series to fully fix fatwrite for FAT12.
> 
> Best regards,
> Benoît
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[U-Boot] [PATCH] ARM: dts: tegra: Sync paz00 with Linux 4.8

2016-12-11 Thread Misha Komarovskiy 
Sync with Linux 4.8 dts plus vdd_bl regulator
to fix backlight start, display timings and USB
controller aliases fix.

Signed-off-by: Misha Komarovskiy 
Cc: Albert Aribaud 
Cc: Simon Glass 
Cc: Tom Warren 
Cc: Stephen Warren 
Cc: Jaehoon Chung 
---
 arch/arm/dts/tegra20-paz00.dts | 597 +++--
 1 file changed, 568 insertions(+), 29 deletions(-)

diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts
index cf6bd70..ecf9fbd 100644
--- a/arch/arm/dts/tegra20-paz00.dts
+++ b/arch/arm/dts/tegra20-paz00.dts
@@ -1,5 +1,6 @@
 /dts-v1/;
 
+#include 
 #include "tegra20.dtsi"
 
 / {
@@ -11,7 +12,13 @@
};
 
aliases {
-   usb0 = "/usb@c5008000";
+   rtc0 = "/i2c@7000d000/tps6586x@34";
+   rtc1 = "/rtc@7000e000";
+   serial0 = 
+   serial1 = 
+   usb0 = "/usb@c500";
+   usb1 = "/usb@c5004000";
+   usb2 = "/usb@c5008000";
mmc0 = "/sdhci@c8000600";
mmc1 = "/sdhci@c800";
};
@@ -26,19 +33,475 @@
status = "okay";
rgb {
status = "okay";
-   nvidia,panel = <_panel>;
+
+   nvidia,panel = <>;
+
+   display-timings {
+   timing@0 {
+   /* PAZ00 has 1024x600 */
+   clock-frequency = <5403>;
+   hactive = <1024>;
+   vactive = <600>;
+   hback-porch = <160>;
+   hfront-porch = <24>;
+   hsync-len = <136>;
+   vback-porch = <3>;
+   vfront-porch = <61>;
+   vsync-len = <6>;
+   hsync-active = <1>;
+   };
+   };
+   };
+   };
+
+   hdmi@5428 {
+   status = "okay";
+
+   vdd-supply = <_vdd_reg>;
+   pll-supply = <_pll_reg>;
+
+   nvidia,ddc-i2c-bus = <_ddc>;
+   nvidia,hpd-gpio = < TEGRA_GPIO(N, 7)
+   GPIO_ACTIVE_HIGH>;
+   };
+   };
+
+   pinmux@7014 {
+   pinctrl-names = "default";
+   pinctrl-0 = <_default>;
+
+   state_default: pinmux {
+   ata {
+   nvidia,pins = "ata", "atc", "atd", "ate",
+   "dap2", "gmb", "gmc", "gmd", "spia",
+   "spib", "spic", "spid", "spie";
+   nvidia,function = "gmi";
+   };
+   atb {
+   nvidia,pins = "atb", "gma", "gme";
+   nvidia,function = "sdio4";
+   };
+   cdev1 {
+   nvidia,pins = "cdev1";
+   nvidia,function = "plla_out";
+   };
+   cdev2 {
+   nvidia,pins = "cdev2";
+   nvidia,function = "pllp_out4";
+   };
+   crtp {
+   nvidia,pins = "crtp";
+   nvidia,function = "crt";
+   };
+   csus {
+   nvidia,pins = "csus";
+   nvidia,function = "pllc_out1";
+   };
+   dap1 {
+   nvidia,pins = "dap1";
+   nvidia,function = "dap1";
+   };
+   dap3 {
+   nvidia,pins = "dap3";
+   nvidia,function = "dap3";
+   };
+   dap4 {
+   nvidia,pins = "dap4";
+   nvidia,function = "dap4";
+   };
+   ddc {
+   nvidia,pins = "ddc";
+   nvidia,function = "i2c2";
+   };
+   dta {
+   nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+

Re: [U-Boot] [PATCH 1/2] common: miiphyutil: Add helper function for mdio bus name

2016-12-11 Thread Simon Glass 
Hi Michal,

On 9 December 2016 at 01:39, Michal Simek  wrote:
> The most of ethernet drivers are using this mdio registration sequence.
> strcpy(priv->bus->name, "emac");
> mdio_register(priv->bus);
> Where driver can be used only with one MDIO bus because only unique
> name should be used.
>
> Other drivers are using unique device name for MDIO registration to
> support multiple instances.
> snprintf(priv->bus->name, sizeof(bus->name), "%s", name);
>
> With DM dev->seq is used more even in logs
> (like random MAC address generation:
> printf("\nWarning: %s (eth%d) using random MAC address - %pM\n",
>dev->name, dev->seq, pdata->enetaddr);
> )
> where eth%d prefix is used.
>
> Simplify driver code to register mdio device with dev->seq number
> to simplify mdio registration and reduce code duplication across
> all drivers. With DM_SEQ_ALIAS enabled dev->seq reflects alias setting.
>
> Signed-off-by: Michal Simek 
> ---
>
> For example:
>
> Board: Xilinx Zynq
> Net:   ZYNQ GEM: e000b000, phyaddr 7, interface rgmii-id
>
> Warning: ethernet@e000b000 (eth0) using random MAC address -
> 7a:fc:90:53:6a:41
> eth0: ethernet@e000b000ZYNQ GEM: e000c000, phyaddr , interface
> rgmii-id
>
> Warning: ethernet@e000c000 (eth3) using random MAC address -
> 1a:ff:d7:1a:a1:b2
> , eth3: ethernet@e000c000
> ** Bad device size - mmc 0 **
> Checking if uenvcmd is set ...
> Hit any key to stop autoboot:  0
> Zynq> mdio list
> eth0:
> 17 - Marvell 88ES <--> ethernet@e000b000
> eth3:
> 17 - Marvell 88ES <--> ethernet@e000c000
> Zynq>
>
> ---
>  common/miiphyutil.c | 12 
>  include/miiphy.h|  1 +
>  2 files changed, 13 insertions(+)

Reviewed-by: Simon Glass 

But please see below.

>
> diff --git a/common/miiphyutil.c b/common/miiphyutil.c
> index aca18db52a00..8eb0f761bb01 100644
> --- a/common/miiphyutil.c
> +++ b/common/miiphyutil.c
> @@ -107,6 +107,18 @@ int mdio_register(struct mii_dev *bus)
> return 0;
>  }
>
> +int mdio_register_seq(struct mii_dev *bus, int seq)
> +{
> +   int ret;
> +
> +   /* Setup a unique name for each mdio bus */
> +   ret = snprintf(bus->name, MDIO_NAME_LEN, "eth%d", seq);
> +   if (ret < 0)
> +   return ret;
> +
> +   return mdio_register(bus);
> +}
> +
>  int mdio_unregister(struct mii_dev *bus)
>  {
> if (!bus)
> diff --git a/include/miiphy.h b/include/miiphy.h
> index 83141b4a6ae1..df371425441d 100644
> --- a/include/miiphy.h
> +++ b/include/miiphy.h
> @@ -48,6 +48,7 @@ void miiphy_listdev(void);
>  struct mii_dev *mdio_alloc(void);
>  void mdio_free(struct mii_dev *bus);
>  int mdio_register(struct mii_dev *bus);
> +int mdio_register_seq(struct mii_dev *bus, int seq);

Please can you add a comment for this function?

>  int mdio_unregister(struct mii_dev *bus);
>  void mdio_list_devices(void);
>
> --
> 1.9.1
>

Regards,
Simon
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Re: [U-Boot] [PATCH 1/3] fdt: add memory bank decoding functions for board setup

2016-12-11 Thread Simon Glass 
Hi Nathan,

On 11 December 2016 at 08:58, Nathan Rossi  wrote:
> Add two functions for use by board implementations to decode the memory
> banks of the /memory node so as to populate the global data with
> ram_size and board info for memory banks.
>
> The fdtdec_setup_memory_size() function decodes the first memory bank
> and sets up the gd->ram_size with the size of the memory bank. This
> function should be called from the boards dram_init().
>
> The fdtdec_setup_memory_banksize() function decode the memory banks
> (up to the CONFIG_NR_DRAM_BANKS) and populates the base address and size
> into the gd->bd->bi_dram array of banks. This function should be called
> from the boards dram_init_banksize().
>
> Signed-off-by: Nathan Rossi 
> Cc: Simon Glass 
> Cc: Michal Simek 
> ---
> This implementation of decoding has been tested on zynq and zynqmp
> boards with address/size cells of (1, 1), (1, 2), (2, 1), (2, 2) and
> up to 2 memory banks.
> ---
>  include/fdtdec.h | 25 +
>  lib/fdtdec.c | 54 ++
>  2 files changed, 79 insertions(+)

Reviewed-by: Simon Glass 

Please see nit below.

>
> diff --git a/include/fdtdec.h b/include/fdtdec.h
> index 27887c8c21..59a204b571 100644
> --- a/include/fdtdec.h
> +++ b/include/fdtdec.h
> @@ -976,6 +976,31 @@ struct display_timing {
>   */
>  int fdtdec_decode_display_timing(const void *blob, int node, int index,
>  struct display_timing *config);
> +
> +/**
> + * fdtdec_setup_memory_size() - decode and setup gd->ram_size
> + *
> + * Decode the /memory 'reg' property to determine the size of the first 
> memory
> + * bank, populate the global data with the size of the first bank of memory.
> + * This function should be called from the boards dram_init().
> + *
> + * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or
> + * invalid
> + */
> +int fdtdec_setup_memory_size(void);
> +
> +/**
> + * fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram
> + *
> + * Decode the /memory 'reg' property to determine the address and size of the
> + * memory banks. Use this data to populate the global data board info with 
> the
> + * phys address and size of memory banks. This function should be called from
> + * the boards dram_init_banksize().
> + *
> + * @return 0 if OK, negative on error

Good to be specific, if e.g. it can only return -EINVAL.

> + */
> +int fdtdec_setup_memory_banksize(void);
> +
>  /**
>   * Set up the device tree ready for use
>   */
> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
> index 4e619c49a2..bc3be017b6 100644
> --- a/lib/fdtdec.c
> +++ b/lib/fdtdec.c
> @@ -1174,6 +1174,60 @@ int fdtdec_decode_display_timing(const void *blob, int 
> parent, int index,
> return ret;
>  }
>
> +int fdtdec_setup_memory_size(void)
> +{
> +   int ret, mem;
> +   struct fdt_resource res;
> +
> +   mem = fdt_path_offset(gd->fdt_blob, "/memory");
> +   if (mem < 0) {
> +   debug("%s: Missing /memory node\n", __func__);
> +   return -EINVAL;
> +   }
> +
> +   ret = fdt_get_resource(gd->fdt_blob, mem, "reg", 0, );
> +   if (ret != 0) {
> +   debug("%s: Unable to decode first memory bank\n", __func__);
> +   return -EINVAL;
> +   }
> +
> +   gd->ram_size = (phys_size_t)(res.end - res.start + 1);
> +   debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
> +
> +   return 0;
> +}
> +
> +int fdtdec_setup_memory_banksize(void)
> +{
> +   int bank, ret, mem;
> +   struct fdt_resource res;
> +
> +   mem = fdt_path_offset(gd->fdt_blob, "/memory");
> +   if (mem < 0) {
> +   debug("%s: Missing /memory node\n", __func__);
> +   return -EINVAL;
> +   }
> +
> +   for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
> +   ret = fdt_get_resource(gd->fdt_blob, mem, "reg", bank, );
> +   if (ret == -FDT_ERR_NOTFOUND)
> +   break;
> +   if (ret != 0)
> +   return ret;

The return above return -EINVAL, but this one returns a -FDT_ERR_...
which is different. So my suggestion here would be to return -EINVAL
here, unless you want to change the function to always return an FDT
error (although fdtdec_decode_memory_region() returns an errno error
so perhaps it is better to be consistent with that).

> +
> +   gd->bd->bi_dram[bank].start = (phys_addr_t)res.start;
> +   gd->bd->bi_dram[bank].size =
> +   (phys_size_t)(res.end - res.start + 1);
> +
> +   debug("%s: DRAM Bank #%d: start = 0x%llx, size = 0x%llx\n",
> + __func__, bank,
> + (unsigned long long)gd->bd->bi_dram[bank].start,
> + (unsigned long

Re: [U-Boot] [PATCH v4 2/2] splash: add support for loading splash from a FIT image

2016-12-11 Thread Simon Glass 
Hi Igor,

On 11 December 2016 at 10:37, Igor Grinberg  wrote:
> Hi Tomas, Simon,
>
> Sorry, to break in that late...
> I have a quick question below.
>
> On 12/05/16 09:36, Tomas Melin wrote:
>> Enable support for loading a splash image from within a FIT image.
>> The image is assumed to be generated with mkimage -E flag to hold
>> the data external to the FIT.
>>
>> Signed-off-by: Tomas Melin 
>
> [...]
>
>> diff --git a/common/splash_source.c b/common/splash_source.c
>> index 70d724f..94b46d3 100644
>> --- a/common/splash_source.c
>> +++ b/common/splash_source.c
>
> [...]
>
>> +#ifdef CONFIG_FIT
>> +static int splash_load_fit(struct splash_location *location, u32 
>> bmp_load_addr)
>> +{
>> + int res;
>> + int node_offset;
>> + int splash_offset;
>> + int splash_size;
>> + struct image_header *img_header;
>> + const u32 *fit_header;
>> + u32 fit_size;
>> + const size_t header_size = sizeof(struct image_header);
>> +
>> + /* Read in image header */
>> + res = splash_storage_read_raw(location, bmp_load_addr, header_size);
>> + if (res < 0)
>> + return res;
>> +
>> + img_header = (struct image_header *)bmp_load_addr;
>> + fit_size = fdt_totalsize(img_header);
>> +
>> + /* Read in entire FIT */
>> + fit_header = (const u32 *)(bmp_load_addr + header_size);
>> + res = splash_storage_read_raw(location, (u32)fit_header, fit_size);
>> + if (res < 0)
>> + return res;
>> +
>> + res = fit_check_format(fit_header);
>> + if (!res) {
>> + debug("Could not find valid FIT image\n");
>> + return -EINVAL;
>> + }
>> +
>> + node_offset = fit_image_get_node(fit_header, location->name);
>> + if (node_offset < 0) {
>> + debug("Could not find splash image '%s' in FIT\n",
>> +   location->name);
>> + return -ENOENT;
>> + }
>> +
>
> I think two above debug() are very legitimate - no need to shout if no FIT 
> image
> or no splash in it...
>
>> + res = fit_image_get_data_offset(fit_header, node_offset,
>> + _offset);
>> + if (res < 0) {
>> + debug("Could not find 'data-offset' property in FIT\n");
>> + return res;
>> + }
>> +
>> + res = fit_image_get_data_size(fit_header, node_offset, _size);
>> + if (res < 0) {
>> + debug("Could not find 'data-size' property in FIT\n");
>> + return res;
>> + }
>
> Now regarding these two, I'm not sure.
> Since we have found a valid FIT and also a node with a correct splash name,
> probably the intent is that we show the splash, right?
> But in the two above checks, we find inconsistencies that do not allow us to
> show the splash - meaning the FIT is not actually good (am I right here?).
> So may be we should report it to the 'user' and allow correcting the FIT?
> Otherwise, it is impossible to debug the image w/o a debug version of 
> U-Boot...
> Do I make sense, or do I miss something?

Yes that makes some sense, but the problem is that then you are
including error messages always which would never happen in a working
system (i.e. it just bloats the code).

So long as the error is reported (even if it is not a very specific
error), people can add DEBUG and track it down.

Regards,
Simon
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Re: [U-Boot] [RFC v2 1/3] drivers: dma: Add the ARM PL330 DMA driver

2016-12-11 Thread Simon Glass 
Hi Dinh,

On 9 December 2016 at 12:03, Dinh Nguyen  wrote:
> From: Dinh Nguyen 
>
> Adopted from the Linux kernel PL330 DMA driver.
>
> Signed-off-by: Dinh Nguyen 
> ---
> v2: Add Kconfig CONFIG_PL330_DMA entry
> ---
>  arch/arm/include/asm/pl330.h | 105 +
>  drivers/dma/Kconfig  |   4 +
>  drivers/dma/Makefile |   1 +
>  drivers/dma/pl330.c  | 942 
> +++
>  4 files changed, 1052 insertions(+)
>  create mode 100644 arch/arm/include/asm/pl330.h
>  create mode 100644 drivers/dma/pl330.c

Reviewed-by: Simon Glass 

nit below.

>
> diff --git a/arch/arm/include/asm/pl330.h b/arch/arm/include/asm/pl330.h
> new file mode 100644
> index 000..dd19b4c
> --- /dev/null
> +++ b/arch/arm/include/asm/pl330.h
> @@ -0,0 +1,105 @@
> +/*
> + * Copyright (C) 2010 Samsung Electronics Co. Ltd.
> + * Jaswinder Singh 
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + *
> + * adapted from linux kernel pl330.h
> + */
> +
> +#ifndef__PL330_H_
> +#define__PL330_H_
> +
> +#define PL330_STATE_STOPPED(1 << 0)
> +#define PL330_STATE_EXECUTING  (1 << 1)
> +#define PL330_STATE_WFE(1 << 2)
> +#define PL330_STATE_FAULTING   (1 << 3)
> +#define PL330_STATE_COMPLETING (1 << 4)
> +#define PL330_STATE_WFP(1 << 5)
> +#define PL330_STATE_KILLING(1 << 6)
> +#define PL330_STATE_FAULT_COMPLETING   (1 << 7)
> +#define PL330_STATE_CACHEMISS  (1 << 8)
> +#define PL330_STATE_UPDTPC (1 << 9)
> +#define PL330_STATE_ATBARRIER  (1 << 10)
> +#define PL330_STATE_QUEUEBUSY  (1 << 11)
> +#define PL330_STATE_INVALID(1 << 15)
> +
> +#define PL330_DMA_MAX_BURST_SIZE   3
> +
> +/* structure to be passed in for pl330_transfer_x */
> +struct pl330_transfer_struct {

Is this used anywhere? Is this describing hardware registers?

> +   void __iomem *reg_base;
> +   u32 channel_num;
> +   u32 src_addr;
> +   u32 dst_addr;
> +   u32 len;
> +   u32 brst_size;
> +   u32 single_brst_size;
> +   u32 brst_len;
> +   u32 peripheral_id;
> +   u32 transfer_type;
> +   u32 enable_cache1;
> +   u32 buf_size;
> +   u8 *buf;
> +};
> +
> +enum pl330_srccachectrl {
> +   SCCTRL0 = 0,/* Noncacheable and nonbufferable */
> +   SCCTRL1,/* Bufferable only */
> +   SCCTRL2,/* Cacheable, but do not allocate */
> +   SCCTRL3,/* Cacheable and bufferable, but do not allocate */
> +   SINVALID1,
> +   SINVALID2,
> +   SCCTRL6,/* Cacheable write-through, allocate on reads only */
> +   SCCTRL7,/* Cacheable write-back, allocate on reads only */

You might consider naming these with their meaning instead of the number/

> +};
> +
> +enum pl330_dstcachectrl {
> +   DCCTRL0 = 0,/* Noncacheable and nonbufferable */
> +   DCCTRL1,/* Bufferable only */
> +   DCCTRL2,/* Cacheable, but do not allocate */
> +   DCCTRL3,/* Cacheable and bufferable, but do not allocate */
> +   DINVALID1 = 8,
> +   DINVALID2,
> +   DCCTRL6,/* Cacheable write-through, allocate on writes only */
> +   DCCTRL7,/* Cacheable write-back, allocate on writes only */
> +};
> +
> +enum pl330_byteswap {
> +   SWAP_NO = 0,
> +   SWAP_2,
> +   SWAP_4,
> +   SWAP_8,
> +   SWAP_16,
> +};
> +
> +/*
> + * Request Configuration.
> + * The PL330 core does not modify this and uses the last
> + * working configuration if the request doesn't provide any.
> + *
> + * The Client may want to provide this info only for the
> + * first request and a request with new settings.
> + */
> +struct pl330_reqcfg {
> +   /* Address Incrementing */
> +   unsigned dst_inc:1;
> +   unsigned src_inc:1;

Is this mapping a hardware register? The use of bitfields worries me.
If it is not mapping hardware, can you please add struct member
comments?

> +
> +   /*
> +* For now, the SRC & DST protection levels
> +* and burst size/length are assumed same.
> +*/
> +   int nonsecure;
> +   int privileged;
> +   int insnaccess;
> +   unsigned brst_len:5;
> +   unsigned brst_size:3; /* in power of 2 */
> +
> +   enum pl330_dstcachectrl dcctl;
> +   enum pl330_srccachectrl scctl;
> +   enum pl330_byteswap swap;
> +};
> +
> +void arm_pl330_transfer(struct pl330_transfer_struct *pl330);
> +#endif /* __PL330_H_ */
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index 1b92c77..d95f959 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -19,4 +19,8 @@ config TI_EDMA3
>   This driver support data transfer between memory
>   regions.
>
> +config PL330_DMA
> +   bool "PL330 DMA driver"
> +

Re: [U-Boot] [PATCH 12/14] fdt: eth_fixup: Add hook for board to override MAC

2016-12-11 Thread Simon Glass 
Hi Oliver,

On 9 December 2016 at 02:25, Olliver Schinagl  wrote:
> Hey simon
>
> On December 8, 2016 11:21:32 PM CET, Simon Glass  wrote:
>>Hi Oliver,
>>
>>On 7 December 2016 at 02:26, Olliver Schinagl 
>>wrote:
>>>
>>>
>>> On December 7, 2016 4:47:23 AM CET, Simon Glass 
>>wrote:
Hi Oliver,

On 5 December 2016 at 03:28, Olliver Schinagl 
wrote:
> Hey Simon,
>
>
>
> On 05-12-16 07:24, Simon Glass wrote:
>>
>> Hi Oliver,
>>
>> On 2 December 2016 at 03:16, Olliver Schinagl 
wrote:
>>>
>>> Hey Joe,
>>>
>>>
>>>
>>> On 30-11-16 21:40, Joe Hershberger wrote:

 On Fri, Nov 25, 2016 at 9:30 AM, Olliver Schinagl

 wrote:
>
> This patch adds a method for the board to set the MAC address
>>if
the
> environment is not yet set. The environment based MAC addresses
are not
> touched, but if the fdt has an alias set, it is parsed and put
into the
> environment.
>
> E.g. The environment contains ethaddr and eth1addr, and the fdt
> contains
> an ethernet1 nothing happens. If the fdt contains ethernet2
however, it
> is parsed and inserted into the environment as eth2addr.
>
> Signed-off-by: Olliver Schinagl 
> ---
>common/fdt_support.c | 8 +++-
>1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/common/fdt_support.c b/common/fdt_support.c
> index c34a13c..f127392 100644
> --- a/common/fdt_support.c
> +++ b/common/fdt_support.c
> @@ -465,6 +465,11 @@ int fdt_fixup_memory(void *blob, u64
>>start,
u64
> size)
>   return fdt_fixup_memory_banks(blob, , ,
>>1);
>}
>
> +__weak int board_get_enetaddr(const int i, unsigned char
*mac_addr)

 Ugh. This collides with a function in board/v38b/ethaddr.c and
>>in
 board/intercontrol/digsy_mtc/digsy_mtc.c

 Also, it's so generic, and only gets called by the fdt fixup
stuff...
 This function should probably be named in such a way that its
 association with fdt is clear.
>>>
>>> I did not notice that, sorry! But naming suggestions are welcome
>>:)
>>>
>>> Right now, I use it in two unrelated spots however.
>>>
>>> from the fdt as seen above and in a subclass driver (which will
come up
>>> for
>>> review) as suggested by Simon.
>>>
>>> There I do:
>>>
>>> +static int sunxi_gmac_eth_read_rom_hwaddr(struct udevice *dev)
>>> +{
>>> +   struct eth_pdata *pdata = dev_get_platdata(dev);
>>> +
>>> +   return board_get_enetaddr(dev->seq, pdata->enetaddr);
>>> +}
>>> +
>>>   const struct eth_ops sunxi_gmac_eth_ops = {
>>>  .start  = designware_eth_start,
>>>  .send   = designware_eth_send,
>>> @@ -102,6 +110,7 @@ const struct eth_ops sunxi_gmac_eth_ops = {
>>>  .free_pkt   = designware_eth_free_pkt,
>>>  .stop   = designware_eth_stop,
>>>  .write_hwaddr   = designware_eth_write_hwaddr,
>>> +   .read_rom_hwaddr= sunxi_gmac_eth_read_rom_hwaddr,
>>>   };
>>>
>>> which is completly unrelated to the fdt.
>>>
>>> So naming suggestion or overal suggestion how to handle this nice
and
>>> generically?
>>>
>>> Based from the name however I would think that all
board_get_enetaddr's
>>> work
>>> the same however so should have been interchangeable? Or was that
silly
>>> thinking?
>>
>> Would it be possible to use a name without 'board' in it? I think
this
>> / hope is actually sunxi-specific code, not board-specific?
>
> You are actually correct, we take the serial number of the SoC
>>(sunxi
> specific) and generate a serial/MAC from it. So nothing to do with
the
> board. So I can just name it sunxi_gen_enetaddr(). Would that be
>>then
(much)
> better?
>
> The reason why I went to 'board' with my mind, is because a) the
original
> mac gen code and b) the location was in board/sunxi/board.c. I
>>think
it is
> thus also sensible to move it out of board/sunxi/board.c as indeed,
it has
> nothing to do with board(s).

That sounds good to me - and you should be able to call it directly
from the driver and avoid any weak functions, right?
>>> The subclass driver can, the fdt fixup however still needs a weak
>>fdt_get_enetaddr()? (Which in our case calls then sunxi_get_enetaddr()
>>i think.)
>>
>>OK - I feel that the fdt fixups need a bit of thought. At the moment

Re: [U-Boot] [PATCH v2] miniarm-rk3288: set isp/vop qos priority level

2016-12-11 Thread Simon Glass 
Hi Nickey,

On 8 December 2016 at 21:39, Nickey Yang  wrote:
> isp-camera image will be broken when enter dual screen display mode.
> We set isp qos high to solve this problem.
>
> Signed-off-by: Nickey Yang 
> ---
>  arch/arm/include/asm/arch-rockchip/qos_rk3288.h | 21 +
>  board/rockchip/miniarm_rk3288/miniarm-rk3288.c  | 21 +
>  2 files changed, 42 insertions(+)
>  create mode 100644 arch/arm/include/asm/arch-rockchip/qos_rk3288.h
>
> diff --git a/arch/arm/include/asm/arch-rockchip/qos_rk3288.h 
> b/arch/arm/include/asm/arch-rockchip/qos_rk3288.h
> new file mode 100644
> index 000..d3d6c3e
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/qos_rk3288.h
> @@ -0,0 +1,21 @@
> +/*
> + * Copyright 2016 Rockchip Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +#ifndef _ASM_ARCH_QOS_RK3288_H
> +#define _ASM_ARCH_QOS_RK3288_H
> +
> +/* cpu axi qos priority */
> +#define CPU_AXI_QOS_PRIORITY_LEVEL(h, l) \
> +   h) & 3) << 2) | ((l) & 3))

Can you instead define

XXX_SHIFT   2
XXX_MASK  (3 << XXX_SHIFT)

and then use these in the .c code?

> +
> +#define CPU_AXI_QOS_PRIORITY0x08
> +
> +#define VIO0_VOP_QOS0xffad0400
> +#define VIO1_VOP_QOS0xffad
> +#define VIO1_ISP_R_QOS  0xffad0900
> +#define VIO1_ISP_W0_QOS 0xffad0100
> +#define VIO1_ISP_W1_QOS 0xffad0180
> +
> +#endif
> diff --git a/board/rockchip/miniarm_rk3288/miniarm-rk3288.c 
> b/board/rockchip/miniarm_rk3288/miniarm-rk3288.c
> index 79541a3..ba0f3a3 100644
> --- a/board/rockchip/miniarm_rk3288/miniarm-rk3288.c
> +++ b/board/rockchip/miniarm_rk3288/miniarm-rk3288.c
> @@ -5,3 +5,24 @@
>   */
>
>  #include 
> +#include 
> +#include 
> +
> +int rk_board_late_init(void)
> +{
> +   /* set isp qos to higher priority */
> +   writel(CPU_AXI_QOS_PRIORITY_LEVEL(2, 2),
> +  VIO1_ISP_R_QOS + CPU_AXI_QOS_PRIORITY);
> +   writel(CPU_AXI_QOS_PRIORITY_LEVEL(2, 2),
> +  VIO1_ISP_W0_QOS + CPU_AXI_QOS_PRIORITY);
> +   writel(CPU_AXI_QOS_PRIORITY_LEVEL(2, 2),
> +  VIO1_ISP_W1_QOS + CPU_AXI_QOS_PRIORITY);
> +
> +   /* set vop qos to higher priority */
> +   writel(CPU_AXI_QOS_PRIORITY_LEVEL(2, 2),
> +  VIO0_VOP_QOS + CPU_AXI_QOS_PRIORITY);
> +   writel(CPU_AXI_QOS_PRIORITY_LEVEL(2, 2),
> +  VIO1_VOP_QOS + CPU_AXI_QOS_PRIORITY);

Can you add a register struct for this in arch/arm/include/asm/arch-rockchip/ ?

Also I think it would be best to put this code somewhere in
arch/arm/mach-rockchip and call it from your late init routine.

> +
> +   return 0;
> +}
> --
> 1.9.1
>
>

Regards,
Simon
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Re: [U-Boot] [PATCH] zynq: spi: Honour the activation / deactivation delay

2016-12-11 Thread Simon Glass 
On 8 December 2016 at 15:11, Moritz Fischer  wrote:
> This is not currently implemented. Add support for this so that the
> Chrome OS EC can be used reliably.
>
> Signed-off-by: Moritz Fischer 
> Cc: Jagan Teki 
> Cc: Simon Glass 
> Cc: u-boot@lists.denx.de
> ---
>  drivers/spi/zynq_spi.c | 24 
>  1 file changed, 24 insertions(+)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 1/5] pmic: pmic_mc34vr500: Add a driver for the mc34vr500 pmic

2016-12-11 Thread Simon Glass 
Hi,

On 9 December 2016 at 03:08, Zhiqiang Hou  wrote:
> From: Hou Zhiqiang 
>
> This patch adds a simple pmic driver for the mc34vr500 pmic which
> is used in conjunction with the fsl T1 and LS1 series SoC.
>
> Signed-off-by: Hou Zhiqiang 
> ---
>  drivers/power/pmic/Kconfig  |   7 ++
>  drivers/power/pmic/Makefile |   1 +
>  drivers/power/pmic/pmic_mc34vr500.c |  32 +++
>  include/power/mc34vr500_pmic.h  | 166 
> 
>  4 files changed, 206 insertions(+)
>  create mode 100644 drivers/power/pmic/pmic_mc34vr500.c
>  create mode 100644 include/power/mc34vr500_pmic.h
>
> diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
> index ce204b3..73e1d53 100644
> --- a/drivers/power/pmic/Kconfig
> +++ b/drivers/power/pmic/Kconfig
> @@ -157,3 +157,10 @@ config PMIC_LP873X
> ---help---
> The LP873X is a PMIC containing couple of LDOs and couple of SMPS.
> This driver binds the pmic children.
> +
> +config POWER_MC34VR500
> +   bool "Enable driver for Freescale MC34VR500 PMIC"
> +   ---help---
> +   The MC34VR500 is used in conjunction with the FSL T1 and LS1 series
> +   SoC. It provides 4 buck DC-DC convertors and 5 LDOs, and it is 
> accessed
> +   via an I2C interface.
> diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
> index cd1c694..58d0241 100644
> --- a/drivers/power/pmic/Makefile
> +++ b/drivers/power/pmic/Makefile
> @@ -32,3 +32,4 @@ obj-$(CONFIG_POWER_TPS65218) += pmic_tps62362.o
>  obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
>  obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
>  obj-$(CONFIG_POWER_HI6553) += pmic_hi6553.o
> +obj-$(CONFIG_POWER_MC34VR500) += pmic_mc34vr500.o
> diff --git a/drivers/power/pmic/pmic_mc34vr500.c 
> b/drivers/power/pmic/pmic_mc34vr500.c
> new file mode 100644
> index 000..db9e210
> --- /dev/null
> +++ b/drivers/power/pmic/pmic_mc34vr500.c
> @@ -0,0 +1,32 @@
> +/*
> + * Copyright 2016 Freescale Semiconductor, Inc.
> + * Hou Zhiqiang 
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +int power_mc34vr500_init(unsigned char bus)
> +{
> +   static const char name[] = "MC34VR500";
> +   struct pmic *p = pmic_alloc();

We have a driver-model PMIC framework now so can you please convert
this to use that? We should move towards removing the old framework.

Regards,
Simon
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Re: [U-Boot] [PATCH v2 1/2] test/py: Allow to pass u_boot_log instead of console for run_and_log

2016-12-11 Thread Simon Glass 
Hi Stefan,

On 10 December 2016 at 14:35, Stefan Bruens
 wrote:
> On Dienstag, 6. Dezember 2016 22:47:42 CET Simon Glass wrote:
>> Hi Stefan,
>>
>> On 4 December 2016 at 19:52, Stefan Brüns 
> wrote:
>> > The runner actually has no console dependency, only on the log provided
>> > by the console. Accept both u_boot_console or a multiplexed_log.
>>
>> In that case I wonder if it would be better to change it to a log, only?
>>
>> I will leave it for Stephen to comment on this.
>
> Only accepting a log would require to change all callers, but that's a trivial
> task. If that's the preferred solution, I will prepare a patch.

I haven't looked in detail but I don't see a problem with changing the callers.

Regards,
Simon
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Re: [U-Boot] Rockchip RK3288 regulator device table problem

2016-12-11 Thread Simon Glass 
Hi Rick,

On 9 December 2016 at 18:12, Rick Bronson  wrote:
> Hi All,
>
>   How do I enable a particular regulator upon boot?  I have two
> identically set LDO entries:
>
> vccio_en: LDO_REG1 {
> regulator-always-on;
> regulator-boot-on;
> regulator-min-microvolt = <330>;
> regulator-max-microvolt = <330>;
> regulator-name = "vccio_en";
> regulator-state-mem {
> regulator-on-in-suspend;
> regulator-suspend-microvolt = 
> <330>;
> };
> };
>
> vcc33_mic: LDO_REG2 {
> regulator-always-on;
> regulator-boot-on;
> regulator-min-microvolt = <330>;
> regulator-max-microvolt = <330>;
> regulator-name = "vcc33_mic";
> regulator-state-mem {
> regulator-on-in-suspend;
> regulator-suspend-microvolt = 
> <330>;
> };
> };
>
>   Yet one is enabled, the other disabled, any idea why?:
>
> => regulator status
> Name EnableduV mA Mode
> ...
> vccio_en enabled   330  - -
> vcc33_micdisabled  330  - -
>
>   And oddly, the uV values actually don't come from the DT but from
> the rk808_ldo table in drivers/power/regulator/rk808.c

Do you think this is happening by PMIC settings (in the device) rather
than through U-Boot?

>
>   Any ideas?
>
> Thanks for any help.
>

There is a function called regulators_enable_boot_on() which enables
all boot-on regulators that have a fixed voltage, but I don't think
that is called with rockchip.

Now that I look at it, I cannot see why I put the voltage values in
the driver. They should come form DT.

>   Rick
>
>
>

Regards,
Simon
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Re: [U-Boot] [PATCH] ARM: dts: tegra: Sync paz00 with Linux 4.8

2016-12-11 Thread Simon Glass 
On 11 December 2016 at 14:28, Misha Komarovskiy  wrote:
> Sync with Linux 4.8 dts plus vdd_bl regulator
> to fix backlight start, display timings and USB
> controller aliases fix.
>
> Signed-off-by: Misha Komarovskiy 
> Cc: Albert Aribaud 
> Cc: Simon Glass 
> Cc: Tom Warren 
> Cc: Stephen Warren 
> Cc: Jaehoon Chung 
> ---
>  arch/arm/dts/tegra20-paz00.dts | 597 
> +++--
>  1 file changed, 568 insertions(+), 29 deletions(-)

Reviewed-by: Simon Glass 
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