[PATCH v2 0/8] rockchip: Add PCIe host support
This series support PCIe host controller support on rockchip rk3399 platform. It is based on previous version[1] changes. Works well on rk3399 boards like rock960, nanopc-t4 and roc-kr3399-pc-mezzanine board as Gen1 configurable host with M.2 SSD. Changes for v2: - handle USB, GMAC clocks - collect kever r-o-b tag - simplify rd and wr conf API [1] http://patchwork.ozlabs.org/project/uboot/cover/20200425110354.12381-1-ja...@amarulasolutions.com/ Any inputs? Jagan. Jagan Teki (8): iopoll: Add dealy to read poll iopoll: Add readl_poll_sleep_timeout clk: rk3399: Add enable/disable clks clk: rk3399: Enable/Disable the PCIEPHY clk pci: Add Rockchip PCIe controller driver pci: Add Rockchip PCIe PHY controller driver rockchip: Enable PCIe/M.2 on rk3399 board w/ M.2 rockchip: Enable PCIe/M.2 on rock960 board arch/arm/dts/rk3399-u-boot.dtsi | 1 + board/vamrs/rock960_rk3399/rock960-rk3399.c | 20 + configs/nanopc-t4-rk3399_defconfig | 4 + configs/roc-pc-mezzanine-rk3399_defconfig | 4 + configs/rock960-rk3399_defconfig| 5 + drivers/clk/rockchip/clk_rk3399.c | 154 ++ drivers/pci/Kconfig | 8 + drivers/pci/Makefile| 1 + drivers/pci/pcie_rockchip.c | 491 drivers/pci/pcie_rockchip.h | 142 ++ drivers/pci/pcie_rockchip_phy.c | 205 include/linux/iopoll.h | 23 +- 12 files changed, 1049 insertions(+), 9 deletions(-) create mode 100644 drivers/pci/pcie_rockchip.c create mode 100644 drivers/pci/pcie_rockchip.h create mode 100644 drivers/pci/pcie_rockchip_phy.c -- 2.17.1
[PATCH v2 1/8] iopoll: Add dealy to read poll
Some drivers and other bsp code not only poll the
register with timeout but also required to delay
on each transaction.
This patch add that requirement by adding sleep_us
variable so-that read_poll_timeout now support
delay as well.
Cc: Tom Rini
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
include/linux/iopoll.h | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/include/linux/iopoll.h b/include/linux/iopoll.h
index ab0ae1969a..0bbd757939 100644
--- a/include/linux/iopoll.h
+++ b/include/linux/iopoll.h
@@ -16,6 +16,7 @@
* @addr: Address to poll
* @val: Variable to read the value into
* @cond: Break condition (usually involving @val)
+ * @sleep_us: Maximum time to sleep in us
* @timeout_us: Timeout in us, 0 means never timeout
*
* Returns 0 on success and -ETIMEDOUT upon a timeout. In either
@@ -24,7 +25,7 @@
* When available, you'll probably want to use one of the specialized
* macros defined below rather than this macro directly.
*/
-#define readx_poll_timeout(op, addr, val, cond, timeout_us)\
+#define readx_poll_timeout(op, addr, val, cond, sleep_us, timeout_us) \
({ \
unsigned long timeout = timer_get_us() + timeout_us; \
for (;;) { \
@@ -35,33 +36,34 @@
(val) = op(addr); \
break; \
} \
+ if (sleep_us) \
+ udelay(sleep_us); \
} \
(cond) ? 0 : -ETIMEDOUT; \
})
-
#define readb_poll_timeout(addr, val, cond, timeout_us) \
- readx_poll_timeout(readb, addr, val, cond, timeout_us)
+ readx_poll_timeout(readb, addr, val, cond, false, timeout_us)
#define readw_poll_timeout(addr, val, cond, timeout_us) \
- readx_poll_timeout(readw, addr, val, cond, timeout_us)
+ readx_poll_timeout(readw, addr, val, cond, false, timeout_us)
#define readl_poll_timeout(addr, val, cond, timeout_us) \
- readx_poll_timeout(readl, addr, val, cond, timeout_us)
+ readx_poll_timeout(readl, addr, val, cond, false, timeout_us)
#define readq_poll_timeout(addr, val, cond, timeout_us) \
- readx_poll_timeout(readq, addr, val, cond, timeout_us)
+ readx_poll_timeout(readq, addr, val, cond, false, timeout_us)
#define readb_relaxed_poll_timeout(addr, val, cond, timeout_us) \
- readx_poll_timeout(readb_relaxed, addr, val, cond, timeout_us)
+ readx_poll_timeout(readb_relaxed, addr, val, cond, false, timeout_us)
#define readw_relaxed_poll_timeout(addr, val, cond, timeout_us) \
- readx_poll_timeout(readw_relaxed, addr, val, cond, timeout_us)
+ readx_poll_timeout(readw_relaxed, addr, val, cond, false, timeout_us)
#define readl_relaxed_poll_timeout(addr, val, cond, timeout_us) \
- readx_poll_timeout(readl_relaxed, addr, val, cond, timeout_us)
+ readx_poll_timeout(readl_relaxed, addr, val, cond, false, timeout_us)
#define readq_relaxed_poll_timeout(addr, val, cond, timeout_us) \
- readx_poll_timeout(readq_relaxed, addr, val, cond, timeout_us)
+ readx_poll_timeout(readq_relaxed, addr, val, cond, false, timeout_us)
#endif /* _LINUX_IOPOLL_H */
--
2.17.1
[PATCH v2 4/8] clk: rk3399: Enable/Disable the PCIEPHY clk
Enable/Disable the PCIEPHY clk for rk3399.
CLK is clear in both enable and disable functionality.
Signed-off-by: Jagan Teki
---
Changes for v2:
- clear the clk in enable
drivers/clk/rockchip/clk_rk3399.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
b/drivers/clk/rockchip/clk_rk3399.c
index df70e9fa88..7feba92f9e 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1136,6 +1136,9 @@ static int rk3399_clk_enable(struct clk *clk)
case HCLK_HOST1_ARB:
rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
break;
+ case SCLK_PCIEPHY_REF:
+ rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+ break;
default:
debug("%s: unsupported clk %ld\n", __func__, clk->id);
return -ENOENT;
@@ -1209,6 +1212,9 @@ static int rk3399_clk_disable(struct clk *clk)
case HCLK_HOST1_ARB:
rk_setreg(&priv->cru->clksel_con[20], BIT(8));
break;
+ case SCLK_PCIEPHY_REF:
+ rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+ break;
default:
debug("%s: unsupported clk %ld\n", __func__, clk->id);
return -ENOENT;
--
2.17.1
[PATCH v2 2/8] iopoll: Add readl_poll_sleep_timeout
Add readl poll API with sleep and timeout support. Cc: Tom Rini Signed-off-by: Jagan Teki --- Changes for v2: - none include/linux/iopoll.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/iopoll.h b/include/linux/iopoll.h index 0bbd757939..e087f23271 100644 --- a/include/linux/iopoll.h +++ b/include/linux/iopoll.h @@ -42,6 +42,9 @@ (cond) ? 0 : -ETIMEDOUT; \ }) +#define readl_poll_sleep_timeout(addr, val, cond, sleep_us, timeout_us) \ + readx_poll_timeout(readl, addr, val, cond, sleep_us, timeout_us) + #define readb_poll_timeout(addr, val, cond, timeout_us) \ readx_poll_timeout(readb, addr, val, cond, false, timeout_us) -- 2.17.1
[PATCH v2 3/8] clk: rk3399: Add enable/disable clks
Yes, most of the high speed peripheral clocks
in rk3399 enabled by default.
But it would be better to handle them via clk
enable/disable API for handling proper reset
conditions like 'usb reset' over command line.
So, enable USB, GMAC clock via enable/disable ops.
Signed-off-by: Jagan Teki
---
Changes for v2:
- new patch
drivers/clk/rockchip/clk_rk3399.c | 148 ++
1 file changed, 148 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
b/drivers/clk/rockchip/clk_rk3399.c
index d822acace1..df70e9fa88 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1071,12 +1071,160 @@ static int __maybe_unused rk3399_clk_set_parent(struct
clk *clk,
return -ENOENT;
}
+static int rk3399_clk_enable(struct clk *clk)
+{
+ struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case SCLK_MAC:
+ rk_clrreg(&priv->cru->clkgate_con[5], BIT(5));
+ break;
+ case SCLK_MAC_RX:
+ rk_clrreg(&priv->cru->clkgate_con[5], BIT(8));
+ break;
+ case SCLK_MAC_TX:
+ rk_clrreg(&priv->cru->clkgate_con[5], BIT(9));
+ break;
+ case SCLK_MACREF:
+ rk_clrreg(&priv->cru->clkgate_con[5], BIT(7));
+ break;
+ case SCLK_MACREF_OUT:
+ rk_clrreg(&priv->cru->clkgate_con[5], BIT(6));
+ break;
+ case ACLK_GMAC:
+ rk_clrreg(&priv->cru->clkgate_con[32], BIT(0));
+ break;
+ case PCLK_GMAC:
+ rk_clrreg(&priv->cru->clkgate_con[32], BIT(2));
+ break;
+ case SCLK_USB3OTG0_REF:
+ rk_clrreg(&priv->cru->clksel_con[12], BIT(1));
+ break;
+ case SCLK_USB3OTG1_REF:
+ rk_clrreg(&priv->cru->clksel_con[12], BIT(2));
+ break;
+ case SCLK_USB3OTG0_SUSPEND:
+ rk_clrreg(&priv->cru->clkgate_con[12], BIT(3));
+ break;
+ case SCLK_USB3OTG1_SUSPEND:
+ rk_clrreg(&priv->cru->clkgate_con[12], BIT(4));
+ break;
+ case ACLK_USB3OTG0:
+ rk_clrreg(&priv->cru->clkgate_con[30], BIT(1));
+ break;
+ case ACLK_USB3OTG1:
+ rk_clrreg(&priv->cru->clkgate_con[30], BIT(2));
+ break;
+ case ACLK_USB3_RKSOC_AXI_PERF:
+ rk_clrreg(&priv->cru->clkgate_con[30], BIT(3));
+ break;
+ case ACLK_USB3:
+ rk_clrreg(&priv->cru->clkgate_con[12], BIT(0));
+ break;
+ case ACLK_USB3_GRF:
+ rk_clrreg(&priv->cru->clkgate_con[30], BIT(4));
+ break;
+ case HCLK_HOST0:
+ rk_clrreg(&priv->cru->clksel_con[20], BIT(5));
+ break;
+ case HCLK_HOST0_ARB:
+ rk_clrreg(&priv->cru->clksel_con[20], BIT(6));
+ break;
+ case HCLK_HOST1:
+ rk_clrreg(&priv->cru->clksel_con[20], BIT(7));
+ break;
+ case HCLK_HOST1_ARB:
+ rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
+ break;
+ default:
+ debug("%s: unsupported clk %ld\n", __func__, clk->id);
+ return -ENOENT;
+ }
+
+ return 0;
+}
+
+static int rk3399_clk_disable(struct clk *clk)
+{
+ struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case SCLK_MAC:
+ rk_setreg(&priv->cru->clkgate_con[5], BIT(5));
+ break;
+ case SCLK_MAC_RX:
+ rk_setreg(&priv->cru->clkgate_con[5], BIT(8));
+ break;
+ case SCLK_MAC_TX:
+ rk_setreg(&priv->cru->clkgate_con[5], BIT(9));
+ break;
+ case SCLK_MACREF:
+ rk_setreg(&priv->cru->clkgate_con[5], BIT(7));
+ break;
+ case SCLK_MACREF_OUT:
+ rk_setreg(&priv->cru->clkgate_con[5], BIT(6));
+ break;
+ case ACLK_GMAC:
+ rk_setreg(&priv->cru->clkgate_con[32], BIT(0));
+ break;
+ case PCLK_GMAC:
+ rk_setreg(&priv->cru->clkgate_con[32], BIT(2));
+ break;
+ case SCLK_USB3OTG0_REF:
+ rk_setreg(&priv->cru->clksel_con[12], BIT(1));
+ break;
+ case SCLK_USB3OTG1_REF:
+ rk_setreg(&priv->cru->clksel_con[12], BIT(2));
+ break;
+ case SCLK_USB3OTG0_SUSPEND:
+ rk_setreg(&priv->cru->clkgate_con[12], BIT(3));
+ break;
+ case SCLK_USB3OTG1_SUSPEND:
+ rk_setreg(&priv->cru->clkgate_con[12], BIT(4));
+ break;
+ case ACLK_USB3OTG0:
+ rk_setreg(&priv->cru->clkgate_con[30], BIT(1));
+ break;
+ case ACLK_USB3OTG1:
+ rk_setreg(&priv->cru->clkgate_con[30], BIT(2));
+ break;
+ c
[PATCH v2 6/8] pci: Add Rockchip PCIe PHY controller driver
Yes, it is possible to have a dedicated UCLASS PHY driver
for this Rockchip PCIe PHY but there are some issues on
Generic PHY framework to support the same.
The Generic PHY framework is unable to get the PHY if
the PHY parent is of a different uclass.
Say if we try to get the PCIe PHY then the phy-uclass
will look for PHY in the first instance if it is not
in the root node it will try to probe the parent by
assuming that the actual PHY is inside the parent PHY
of UCLASS_PHY. But, in rk3399 hardware representation
PHY like emmc, usb and pcie are part of syscon which
is completely a different of UCLASS_SYSCON.
Example:
grf: syscon@ff77 {
compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
reg = <0x0 0xff77 0x0 0x1>;
#address-cells = <1>;
#size-cells = <1>;
pcie_phy: pcie-phy {
compatible = "rockchip,rk3399-pcie-phy";
clocks = <&cru SCLK_PCIEPHY_REF>;
clock-names = "refclk";
#phy-cells = <1>;
resets = <&cru SRST_PCIEPHY>;
drive-impedance-ohm = <50>;
reset-names = "phy";
status = "disabled";
};
};
Due to this limitation, this patch adds a separate PHY
driver for Rockchip PCIe. This might be removed in future
once Generic PHY supports this limitation.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/pci/Makefile| 2 +-
drivers/pci/pcie_rockchip.c | 50 ++--
drivers/pci/pcie_rockchip.h | 63 ++
drivers/pci/pcie_rockchip_phy.c | 205
4 files changed, 306 insertions(+), 14 deletions(-)
create mode 100644 drivers/pci/pcie_rockchip_phy.c
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 493e9354dd..955351c5c2 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -43,4 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
-obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o
+obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o pcie_rockchip_phy.o
diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c
index 3f06f783ca..82a8396e42 100644
--- a/drivers/pci/pcie_rockchip.c
+++ b/drivers/pci/pcie_rockchip.c
@@ -159,6 +159,8 @@ static int rockchip_pcie_atr_init(struct rockchip_pcie
*priv)
static int rockchip_pcie_init_port(struct udevice *dev)
{
struct rockchip_pcie *priv = dev_get_priv(dev);
+ struct rockchip_pcie_phy *phy = pcie_get_phy(priv);
+ struct rockchip_pcie_phy_ops *ops = phy_get_ops(phy);
u32 cr, val, status;
int ret;
@@ -183,29 +185,35 @@ static int rockchip_pcie_init_port(struct udevice *dev)
return ret;
}
+ ret = ops->init(phy);
+ if (ret) {
+ dev_err(dev, "failed to init phy (ret=%d)\n", ret);
+ goto err_exit_phy;
+ }
+
ret = reset_assert(&priv->core_rst);
if (ret) {
dev_err(dev, "failed to assert core reset (ret=%d)\n", ret);
- return ret;
+ goto err_exit_phy;
}
ret = reset_assert(&priv->mgmt_rst);
if (ret) {
dev_err(dev, "failed to assert mgmt reset (ret=%d)\n", ret);
- return ret;
+ goto err_exit_phy;
}
ret = reset_assert(&priv->mgmt_sticky_rst);
if (ret) {
dev_err(dev, "failed to assert mgmt-sticky reset (ret=%d)\n",
ret);
- return ret;
+ goto err_exit_phy;
}
ret = reset_assert(&priv->pipe_rst);
if (ret) {
dev_err(dev, "failed to assert pipe reset (ret=%d)\n", ret);
- return ret;
+ goto err_exit_phy;
}
udelay(10);
@@ -213,19 +221,19 @@ static int rockchip_pcie_init_port(struct udevice *dev)
ret = reset_deassert(&priv->pm_rst);
if (ret) {
dev_err(dev, "failed to deassert pm reset (ret=%d)\n", ret);
- return ret;
+ goto err_exit_phy;
}
ret = reset_deassert(&priv->aclk_rst);
if (ret) {
dev_err(dev, "failed to deassert aclk reset (ret=%d)\n", ret);
- return ret;
+ goto err_exit_phy;
}
ret = reset_deassert(&priv->pclk_rst);
if (ret) {
dev_err(dev, "failed to deassert pclk reset (ret=%d)\n", ret);
- return ret;
+ goto err_exit_phy;
}
/* Select GEN1 for now */
@@ -234,29 +242,35 @@ static int rockchip_pcie_init_port(struct udevice *dev)
cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG);
+ ret = ops->power_on(phy);
+ if (ret) {
+ dev_err(dev, "failed to power on phy (ret=%d)\n", ret);
+ goto err_power_off_phy;
+ }
[PATCH v2 5/8] pci: Add Rockchip PCIe controller driver
Add Rockchip PCIe controller driver for rk3399 platform.
Driver support Gen1 by operating as a Root complex.
Thanks to Patrick for initial work.
Signed-off-by: Patrick Wildt
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v2:
- simplify bdf in rd_conf, wr_conf
- collect kever r-o-b
drivers/pci/Kconfig | 8 +
drivers/pci/Makefile| 1 +
drivers/pci/pcie_rockchip.c | 467
drivers/pci/pcie_rockchip.h | 79 ++
4 files changed, 555 insertions(+)
create mode 100644 drivers/pci/pcie_rockchip.c
create mode 100644 drivers/pci/pcie_rockchip.h
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 437cd9a055..3dba84103b 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -197,4 +197,12 @@ config PCIE_MEDIATEK
Say Y here if you want to enable Gen2 PCIe controller,
which could be found on MT7623 SoC family.
+config PCIE_ROCKCHIP
+ bool "Enable Rockchip PCIe driver"
+ select DM_PCI
+ default y if ROCKCHIP_RK3399
+ help
+ Say Y here if you want to enable PCIe controller support on
+ Rockchip SoCs.
+
endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index c051ecc9f3..493e9354dd 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
+obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o
diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c
new file mode 100644
index 00..3f06f783ca
--- /dev/null
+++ b/drivers/pci/pcie_rockchip.c
@@ -0,0 +1,467 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Rockchip AXI PCIe host controller driver
+ *
+ * Copyright (c) 2016 Rockchip, Inc.
+ * Copyright (c) 2020 Amarula Solutions(India)
+ * Copyright (c) 2020 Jagan Teki
+ * Copyright (c) 2019 Patrick Wildt
+ * Copyright (c) 2018 Mark Kettenis
+ *
+ * Bits taken from Linux Rockchip PCIe host controller.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie_rockchip.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int rockchip_pcie_off_conf(pci_dev_t bdf, uint offset)
+{
+ unsigned int bus = PCI_BUS(bdf);
+ unsigned int dev = PCI_DEV(bdf);
+ unsigned int func = PCI_FUNC(bdf);
+
+ return (bus << 20) | (dev << 15) | (func << 12) | (offset & ~0x3);
+}
+
+static int rockchip_pcie_rd_conf(const struct udevice *udev, pci_dev_t bdf,
+uint offset, ulong *valuep,
+enum pci_size_t size)
+{
+ struct rockchip_pcie *priv = dev_get_priv(udev);
+ unsigned int bus = PCI_BUS(bdf);
+ unsigned int dev = PCI_DEV(bdf);
+ int where = rockchip_pcie_off_conf(bdf, offset);
+ ulong value;
+
+ if (bus == priv->first_busno && dev == 0) {
+ value = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + where);
+ *valuep = pci_conv_32_to_size(value, offset, size);
+ return 0;
+ }
+
+ if ((bus == priv->first_busno + 1) && dev == 0) {
+ value = readl(priv->axi_base + where);
+ *valuep = pci_conv_32_to_size(value, offset, size);
+ return 0;
+ }
+
+ *valuep = pci_get_ff(size);
+
+ return 0;
+}
+
+static int rockchip_pcie_wr_conf(struct udevice *udev, pci_dev_t bdf,
+uint offset, ulong value,
+enum pci_size_t size)
+{
+ struct rockchip_pcie *priv = dev_get_priv(udev);
+ unsigned int bus = PCI_BUS(bdf);
+ unsigned int dev = PCI_DEV(bdf);
+ int where = rockchip_pcie_off_conf(bdf, offset);
+ ulong old;
+
+ if (bus == priv->first_busno && dev == 0) {
+ old = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + where);
+ value = pci_conv_size_to_32(old, value, offset, size);
+ writel(value, priv->apb_base + PCIE_RC_NORMAL_BASE + where);
+ return 0;
+ }
+
+ if ((bus == priv->first_busno + 1) && dev == 0) {
+ old = readl(priv->axi_base + where);
+ value = pci_conv_size_to_32(old, value, offset, size);
+ writel(value, priv->axi_base + where);
+ return 0;
+ }
+
+ return 0;
+}
+
+static int rockchip_pcie_atr_init(struct rockchip_pcie *priv)
+{
+ struct udevice *ctlr = pci_get_controller(priv->dev);
+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+ u64 addr, size, offset;
+ u32 type;
+ int i, region;
+
+ /* Use region 0 to map PCI configuration space. */
+ writel(25 - 1, priv->apb_base + PCIE_ATR_OB_ADDR0(0));
+ writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(0));
+ wr
[PATCH v2 8/8] rockchip: Enable PCIe/M.2 on rock960 board
Due to some on board limitation rock960 PCIe
works only with 1.8V IO domain.
So, this patch enables grf io_sel explicitly
to make PCIe/M.2 to work.
Cc: Tom Cubie
Cc: Manivannan Sadhasivam
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
board/vamrs/rock960_rk3399/rock960-rk3399.c | 20
configs/rock960-rk3399_defconfig| 5 +
2 files changed, 25 insertions(+)
diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c
b/board/vamrs/rock960_rk3399/rock960-rk3399.c
index 68a127b9ac..98d62e89ca 100644
--- a/board/vamrs/rock960_rk3399/rock960-rk3399.c
+++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c
@@ -2,3 +2,23 @@
/*
* Copyright (C) 2018 Manivannan Sadhasivam
*/
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ struct rk3399_grf_regs *grf =
+ syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ /* BT565 is in 1.8v domain */
+ rk_setreg(&grf->io_vsel, BIT(0));
+
+ return 0;
+}
+#endif
diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
index c4e954731a..cb1ec3c26b 100644
--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEBUG_UART_BASE=0xFF1A
CONFIG_DEBUG_UART_CLOCK=2400
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
+CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
@@ -19,6 +20,7 @@ CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
@@ -36,10 +38,13 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_DM_ETH=y
+CONFIG_NVME=y
+CONFIG_PCI=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_DM_RESET=y
CONFIG_BAUDRATE=150
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
--
2.17.1
[PATCH v2 7/8] rockchip: Enable PCIe/M.2 on rk3399 board w/ M.2
Enable PCIe/M.2 support on
- NanoPC-T4
- ROC-RK3399-PC Mezzanine boards.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
arch/arm/dts/rk3399-u-boot.dtsi | 1 +
configs/nanopc-t4-rk3399_defconfig| 4
configs/roc-pc-mezzanine-rk3399_defconfig | 4
3 files changed, 9 insertions(+)
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index ef57c36e73..a79a2d23d8 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -8,6 +8,7 @@
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc;
+ pci0 = &pcie0;
};
cic: syscon@ff62 {
diff --git a/configs/nanopc-t4-rk3399_defconfig
b/configs/nanopc-t4-rk3399_defconfig
index 607a00dbf7..032256fd76 100644
--- a/configs/nanopc-t4-rk3399_defconfig
+++ b/configs/nanopc-t4-rk3399_defconfig
@@ -18,6 +18,7 @@ CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
@@ -34,10 +35,13 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME=y
+CONFIG_PCI=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_DM_RESET=y
CONFIG_BAUDRATE=150
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig
b/configs/roc-pc-mezzanine-rk3399_defconfig
index 5a694edc03..0b853805f3 100644
--- a/configs/roc-pc-mezzanine-rk3399_defconfig
+++ b/configs/roc-pc-mezzanine-rk3399_defconfig
@@ -19,6 +19,7 @@ CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
@@ -36,11 +37,14 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME=y
+CONFIG_PCI=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_DM_RESET=y
CONFIG_BAUDRATE=150
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_SPI=y
--
2.17.1
Re: [PATCH] xilinx: Enable MTD and UBIFS for zynq and zynqmp
st 8. 4. 2020 v 10:39 odesílatel Michal Simek napsal: > > Both of them have nand controller that's why it is good to enable it > because these configurations are also covered by testing. > > Signed-off-by: Michal Simek > --- > > configs/xilinx_zynq_virt_defconfig | 5 + > configs/xilinx_zynqmp_virt_defconfig | 5 + > 2 files changed, 10 insertions(+) > > diff --git a/configs/xilinx_zynq_virt_defconfig > b/configs/xilinx_zynq_virt_defconfig > index 54cbd3e12b65..6af4565451a9 100644 > --- a/configs/xilinx_zynq_virt_defconfig > +++ b/configs/xilinx_zynq_virt_defconfig > @@ -32,12 +32,17 @@ CONFIG_CMD_FPGA_LOADP=y > CONFIG_CMD_GPIO=y > CONFIG_CMD_I2C=y > CONFIG_CMD_MMC=y > +CONFIG_CMD_MTD=y > CONFIG_CMD_NAND_LOCK_UNLOCK=y > CONFIG_CMD_USB=y > # CONFIG_CMD_SETEXPR is not set > CONFIG_CMD_TFTPPUT=y > CONFIG_CMD_CACHE=y > CONFIG_CMD_EXT4_WRITE=y > +CONFIG_CMD_MTDPARTS=y > +CONFIG_CMD_MTDPARTS_SPREAD=y > +CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y > +CONFIG_CMD_UBI=y > CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" > CONFIG_OF_LIST="zynq-zc702 zynq-zc706 zynq-zc770-xm010 zynq-zc770-xm011 > zynq-zc770-xm011-x16 zynq-zc770-xm012 zynq-zc770-xm013 zynq-cc108 > zynq-microzed zynq-minized zynq-picozed zynq-zed zynq-zturn zynq-zybo > zynq-zybo-z7 zynq-dlc20-rev1.0" > CONFIG_ENV_IS_IN_SPI_FLASH=y > diff --git a/configs/xilinx_zynqmp_virt_defconfig > b/configs/xilinx_zynqmp_virt_defconfig > index 45360f873134..279483f1cb7b 100644 > --- a/configs/xilinx_zynqmp_virt_defconfig > +++ b/configs/xilinx_zynqmp_virt_defconfig > @@ -40,6 +40,7 @@ CONFIG_CMD_GPIO=y > CONFIG_CMD_GPT=y > CONFIG_CMD_I2C=y > CONFIG_CMD_MMC=y > +CONFIG_CMD_MTD=y > CONFIG_CMD_NAND_LOCK_UNLOCK=y > CONFIG_CMD_POWEROFF=y > CONFIG_CMD_SDRAM=y > @@ -50,6 +51,10 @@ CONFIG_CMD_TFTPPUT=y > CONFIG_CMD_TIME=y > CONFIG_CMD_TIMER=y > CONFIG_CMD_EXT4_WRITE=y > +CONFIG_CMD_MTDPARTS=y > +CONFIG_CMD_MTDPARTS_SPREAD=y > +CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y > +CONFIG_CMD_UBI=y > CONFIG_SPL_OF_CONTROL=y > CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC" > CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA > zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA > zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA > zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 > zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 > zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 > zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC > zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB > zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA" > -- > 2.26.0 > Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] ARM: zynq: Setup stack size via Kconfig
čt 16. 4. 2020 v 14:21 odesílatel Michal Simek napsal:
>
> Stack size has been introduced by commit a69814c815b9 ("arm64: zynqmp:
> Set initrd_high to as high as possible") and commit 085201c246ee ("arm64:
> versal: Set initrd_high to as high as possible")
> to support setting up initrd_high as high as possible.
> The same change should happen for Zynq because the code is moved to xilinx
> common location.
>
> Signed-off-by: Michal Simek
> ---
>
> arch/arm/Kconfig | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index bbb1e2738bfe..2140dd27f4ec 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -475,7 +475,7 @@ config TPL_USE_ARCH_MEMSET
>
> config SET_STACK_SIZE
> bool "Enable an option to set max stack size that can be used"
> - default y if ARCH_VERSAL || ARCH_ZYNQMP
> + default y if ARCH_VERSAL || ARCH_ZYNQMP || ARCH_ZYNQ
> help
> This will enable an option to set max stack size that can be
> used by U-Boot.
> @@ -484,6 +484,7 @@ config STACK_SIZE
> hex "Define max stack size that can be used by U-Boot"
> depends on SET_STACK_SIZE
> default 0x400 if ARCH_VERSAL || ARCH_ZYNQMP
> + default 0x100 if ARCH_ZYNQ
> help
> Define Max stack size that can be used by U-Boot so that the
> initrd_high will be calculated as base stack pointer minus this
> --
> 2.26.0
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] xilinx: Introduce board_late_init_xilinx()
st 8. 4. 2020 v 10:50 odesílatel Michal Simek napsal:
>
> This function should keep common shared late configurations for Xilinx
> SoCs.
>
> Signed-off-by: Michal Simek
> ---
>
> board/xilinx/common/board.c | 8
> board/xilinx/common/board.h | 12
> board/xilinx/versal/board.c | 5 ++---
> board/xilinx/zynq/board.c| 5 ++---
> board/xilinx/zynqmp/zynqmp.c | 5 ++---
> 5 files changed, 26 insertions(+), 9 deletions(-)
> create mode 100644 board/xilinx/common/board.h
>
> diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
> index e83c692f2174..7c191e53fb71 100644
> --- a/board/xilinx/common/board.c
> +++ b/board/xilinx/common/board.c
> @@ -8,6 +8,7 @@
> #include
> #include
> #include
> +#include "board.h"
>
> int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
> {
> @@ -71,3 +72,10 @@ void *board_fdt_blob_setup(void)
> return NULL;
> }
> #endif
> +
> +int board_late_init_xilinx(void)
> +{
> + env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
> +
> + return 0;
> +}
> diff --git a/board/xilinx/common/board.h b/board/xilinx/common/board.h
> new file mode 100644
> index ..180dfbca1082
> --- /dev/null
> +++ b/board/xilinx/common/board.h
> @@ -0,0 +1,12 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * (C) Copyright 2020 Xilinx, Inc.
> + * Michal Simek
> + */
> +
> +#ifndef _BOARD_XILINX_COMMON_BOARD_H
> +#define _BOARD_XILINX_COMMON_BOARD_H
> +
> +int board_late_init_xilinx(void);
> +
> +#endif /* BOARD_XILINX_COMMON_BOARD_H */
> diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
> index 75aedb092922..908ea87163f8 100644
> --- a/board/xilinx/versal/board.c
> +++ b/board/xilinx/versal/board.c
> @@ -17,6 +17,7 @@
> #include
> #include
> #include
> +#include "../common/board.h"
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -204,9 +205,7 @@ int board_late_init(void)
> initrd_hi = round_down(initrd_hi, SZ_16M);
> env_set_addr("initrd_high", (void *)initrd_hi);
>
> - env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
> -
> - return 0;
> + return board_late_init_xilinx();
> }
>
> int dram_init_banksize(void)
> diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
> index 420a5ca66311..2164eac8d518 100644
> --- a/board/xilinx/zynq/board.c
> +++ b/board/xilinx/zynq/board.c
> @@ -17,6 +17,7 @@
> #include
> #include
> #include
> +#include "../common/board.h"
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -76,9 +77,7 @@ int board_late_init(void)
>
> env_set("boot_targets", new_targets);
>
> - env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
> -
> - return 0;
> + return board_late_init_xilinx();
> }
>
> #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
> diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
> index 3c92b1a5825f..b2172356ad0a 100644
> --- a/board/xilinx/zynqmp/zynqmp.c
> +++ b/board/xilinx/zynqmp/zynqmp.c
> @@ -27,6 +27,7 @@
> #include
> #include
> #include
> +#include "../common/board.h"
>
> #include "pm_cfg_obj.h"
>
> @@ -695,11 +696,9 @@ int board_late_init(void)
> initrd_hi = round_down(initrd_hi, SZ_16M);
> env_set_addr("initrd_high", (void *)initrd_hi);
>
> - env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
> -
> reset_reason();
>
> - return 0;
> + return board_late_init_xilinx();
> }
> #endif
>
> --
> 2.26.0
>
Applied but also fix antminer and topic Makefiles.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] clk: versal: Fix watchdog clock issue
po 13. 4. 2020 v 9:53 odesílatel Michal Simek napsal:
>
> From: T Karthik Reddy
>
> Enable mux based clocks to populate LPD_LSBUS clock to xilinx_wwdt
> driver. Skip reading clock rate for the mux based clocks with
> parent clock id is zero.
>
> Signed-off-by: T Karthik Reddy
> Signed-off-by: Ashok Reddy Soma
> Signed-off-by: Michal Simek
> ---
>
> drivers/clk/clk_versal.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
> index d3673a5c8b81..075a08380d84 100644
> --- a/drivers/clk/clk_versal.c
> +++ b/drivers/clk/clk_versal.c
> @@ -503,6 +503,9 @@ static u64 versal_clock_calc(u32 clk_id)
> NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
> return versal_clock_ref(clk_id);
>
> + if (!parent_id)
> + return 0;
> +
> clk_rate = versal_clock_calc(parent_id);
>
> if (versal_clock_div(clk_id)) {
> @@ -526,7 +529,7 @@ static int versal_clock_get_rate(u32 clk_id, u64
> *clk_rate)
> NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_OUT &&
> ((clk_id >> NODE_CLASS_SHIFT) &
> NODE_CLASS_MASK) == NODE_CLASS_CLOCK) {
> - if (!versal_clock_gate(clk_id))
> + if (!versal_clock_gate(clk_id) && !versal_clock_mux(clk_id))
> return -EINVAL;
> *clk_rate = versal_clock_calc(clk_id);
> return 0;
> --
> 2.26.0
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] xilinx: zynqmp: Fix MIO 18 configuration on zcu104 revC
st 8. 4. 2020 v 13:31 odesílatel Michal Simek napsal: > > Without this change QSPI is not detected on zcu104 revC. > > Signed-off-by: Michal Simek > --- > > board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c > b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c > index 4805e5a3b914..383e3d0c7e13 100644 > --- a/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c > +++ b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c > @@ -363,6 +363,7 @@ static unsigned long psu_mio_init_data(void) > psu_mask_write(0xFF18000C, 0x00FEU, 0x0002U); > psu_mask_write(0xFF180010, 0x00FEU, 0x0002U); > psu_mask_write(0xFF180014, 0x00FEU, 0x0002U); > + psu_mask_write(0xFF180018, 0x00FEU, 0x0002U); > psu_mask_write(0xFF180040, 0x00FEU, 0x0040U); > psu_mask_write(0xFF180044, 0x00FEU, 0x0040U); > psu_mask_write(0xFF180048, 0x00FEU, 0x00C0U); > @@ -408,7 +409,7 @@ static unsigned long psu_mio_init_data(void) > psu_mask_write(0xFF18012C, 0x00FEU, 0x0002U); > psu_mask_write(0xFF180130, 0x00FEU, 0x00C0U); > psu_mask_write(0xFF180134, 0x00FEU, 0x00C0U); > - psu_mask_write(0xFF180204, 0x7B3F003FU, 0x5224U); > + psu_mask_write(0xFF180204, 0x7B3F007FU, 0x5224U); > psu_mask_write(0xFF180208, 0xE000U, 0x00B02000U); > psu_mask_write(0xFF18020C, 0x3FFFU, 0x0FC0U); > psu_mask_write(0xFF180138, 0x03FFU, 0x03FFU); > -- > 2.26.0 > Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] arm64: zynqmp: Add label to GPIO lines for boot mode and POR
po 13. 4. 2020 v 10:00 odesílatel Michal Simek napsal: > > From: Saeed Nowshadi > > Add label to GPIO lines controlling boot mode and POR EMIO pins so System > Controller can assert those lines on Versal. > > Signed-off-by: Saeed Nowshadi > Signed-off-by: Michal Simek > --- > > arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts > b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts > index 39b5d7fff9ac..65cf5914945d 100644 > --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts > +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts > @@ -162,9 +162,9 @@ > "", "", "", "", "", /* 65 - 69 */ > "", "", "", "", "", /* 70 - 74 */ > "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO > start */ > - "", "", /* 78 - 79 */ > - "", "", "", "", "", /* 80 - 84 */ > - "", "", "", "", "", /* 85 -89 */ > + "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 > */ > + "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", > "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */ > + "", "", "", "", "", /* 85 - 89 */ > "", "", "", "", "", /* 90 - 94 */ > "", "", "", "", "", /* 95 - 99 */ > "", "", "", "", "", /* 100 - 104 */ > -- > 2.26.0 > Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH 1/2] xilinx: Move initrd_high setup to common location
po 13. 4. 2020 v 10:01 odesílatel Michal Simek napsal:
>
> Moving to common location initrd_high is also setup for Zynq which hasn't
> done in run time code.
>
> Signed-off-by: Michal Simek
> ---
>
> board/xilinx/common/board.c | 7 +++
> board/xilinx/versal/board.c | 6 --
> board/xilinx/zynqmp/zynqmp.c | 6 --
> include/configs/zynq-common.h | 1 -
> 4 files changed, 7 insertions(+), 13 deletions(-)
>
> diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
> index 7c191e53fb71..294a59df77da 100644
> --- a/board/xilinx/common/board.c
> +++ b/board/xilinx/common/board.c
> @@ -8,6 +8,7 @@
> #include
> #include
> #include
> +#include
> #include "board.h"
>
> int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
> @@ -75,7 +76,13 @@ void *board_fdt_blob_setup(void)
>
> int board_late_init_xilinx(void)
> {
> + ulong initrd_hi;
> +
> env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
>
> + initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
> + initrd_hi = round_down(initrd_hi, SZ_16M);
> + env_set_addr("initrd_high", (void *)initrd_hi);
> +
> return 0;
> }
> diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
> index 908ea87163f8..2900dfb44e93 100644
> --- a/board/xilinx/versal/board.c
> +++ b/board/xilinx/versal/board.c
> @@ -16,7 +16,6 @@
> #include
> #include
> #include
> -#include
> #include "../common/board.h"
>
> DECLARE_GLOBAL_DATA_PTR;
> @@ -94,7 +93,6 @@ int board_late_init(void)
> const char *mode;
> char *new_targets;
> char *env_targets;
> - ulong initrd_hi;
>
> if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
> debug("Saved variables - Skipping\n");
> @@ -201,10 +199,6 @@ int board_late_init(void)
>
> env_set("boot_targets", new_targets);
>
> - initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
> - initrd_hi = round_down(initrd_hi, SZ_16M);
> - env_set_addr("initrd_high", (void *)initrd_hi);
> -
> return board_late_init_xilinx();
> }
>
> diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
> index b2172356ad0a..66a43974e68d 100644
> --- a/board/xilinx/zynqmp/zynqmp.c
> +++ b/board/xilinx/zynqmp/zynqmp.c
> @@ -26,7 +26,6 @@
> #include
> #include
> #include
> -#include
> #include "../common/board.h"
>
> #include "pm_cfg_obj.h"
> @@ -565,7 +564,6 @@ int board_late_init(void)
> char *new_targets;
> char *env_targets;
> int ret;
> - ulong initrd_hi;
>
> #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
> usb_ether_init();
> @@ -692,10 +690,6 @@ int board_late_init(void)
>
> env_set("boot_targets", new_targets);
>
> - initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
> - initrd_hi = round_down(initrd_hi, SZ_16M);
> - env_set_addr("initrd_high", (void *)initrd_hi);
> -
> reset_reason();
>
> return board_late_init_xilinx();
> diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
> index 1eaf65b0a2a1..4ccc31e37655 100644
> --- a/include/configs/zynq-common.h
> +++ b/include/configs/zynq-common.h
> @@ -198,7 +198,6 @@
> #ifndef CONFIG_EXTRA_ENV_SETTINGS
> #define CONFIG_EXTRA_ENV_SETTINGS \
> "fdt_high=0x2000\0" \
> - "initrd_high=0x2000\0" \
> "scriptaddr=0x2\0" \
> "script_size_f=0x4\0" \
> "fdt_addr_r=0x1f0\0"\
> --
> 2.26.0
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH 2/2] xilinx: Move bootmode detection to separate function
po 13. 4. 2020 v 10:01 odesílatel Michal Simek napsal:
>
> Create special function for reading bootmode on Versal and ZynqMP.
> Zynq is using specific function (without mask) already.
> Future patches will be calling this function from different location too.
>
> Signed-off-by: Michal Simek
> ---
>
> board/xilinx/versal/board.c | 23 ---
> board/xilinx/zynqmp/zynqmp.c | 28 +++-
> 2 files changed, 35 insertions(+), 16 deletions(-)
>
> diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
> index 2900dfb44e93..483e3ce2f79a 100644
> --- a/board/xilinx/versal/board.c
> +++ b/board/xilinx/versal/board.c
> @@ -82,9 +82,23 @@ int board_early_init_r(void)
> return 0;
> }
>
> -int board_late_init(void)
> +static u8 versal_get_bootmode(void)
> {
> + u8 bootmode;
> u32 reg = 0;
> +
> + reg = readl(&crp_base->boot_mode_usr);
> +
> + if (reg >> BOOT_MODE_ALT_SHIFT)
> + reg >>= BOOT_MODE_ALT_SHIFT;
> +
> + bootmode = reg & BOOT_MODES_MASK;
> +
> + return bootmode;
> +}
> +
> +int board_late_init(void)
> +{
> u8 bootmode;
> struct udevice *dev;
> int bootseq = -1;
> @@ -99,12 +113,7 @@ int board_late_init(void)
> return 0;
> }
>
> - reg = readl(&crp_base->boot_mode_usr);
> -
> - if (reg >> BOOT_MODE_ALT_SHIFT)
> - reg >>= BOOT_MODE_ALT_SHIFT;
> -
> - bootmode = reg & BOOT_MODES_MASK;
> + bootmode = versal_get_bootmode();
>
> puts("Bootmode: ");
> switch (bootmode) {
> diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
> index 66a43974e68d..a2a0d563318e 100644
> --- a/board/xilinx/zynqmp/zynqmp.c
> +++ b/board/xilinx/zynqmp/zynqmp.c
> @@ -552,9 +552,26 @@ static int set_fdtfile(void)
> return 0;
> }
>
> -int board_late_init(void)
> +static u8 zynqmp_get_bootmode(void)
> {
> + u8 bootmode;
> u32 reg = 0;
> + int ret;
> +
> + ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
> + if (ret)
> + return -EINVAL;
> +
> + if (reg >> BOOT_MODE_ALT_SHIFT)
> + reg >>= BOOT_MODE_ALT_SHIFT;
> +
> + bootmode = reg & BOOT_MODES_MASK;
> +
> + return bootmode;
> +}
> +
> +int board_late_init(void)
> +{
> u8 bootmode;
> struct udevice *dev;
> int bootseq = -1;
> @@ -578,14 +595,7 @@ int board_late_init(void)
> if (ret)
> return ret;
>
> - ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
> - if (ret)
> - return -EINVAL;
> -
> - if (reg >> BOOT_MODE_ALT_SHIFT)
> - reg >>= BOOT_MODE_ALT_SHIFT;
> -
> - bootmode = reg & BOOT_MODES_MASK;
> + bootmode = zynqmp_get_bootmode();
>
> puts("Bootmode: ");
> switch (bootmode) {
> --
> 2.26.0
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] ARM: zynq: Change SYS_MALLOC_LEN in zynq_cse_nand_defconfig
po 20. 4. 2020 v 7:43 odesílatel Michal Simek napsal: > > From: T Karthik Reddy > > nand_scan_tail() function allocates memory dynamically for > struct nand_buffers which needs ~21kbytes of memory. But the > memory alloted with CONFIG_SYS_MALLOC_LEN is 4k which is insufficient. > Increase CONFIG_SYS_MALLOC_LEN to 32Kbytes from which struct > nand_buffers uses ~21kbytes & remaining memory is used for other. > > Signed-off-by: T Karthik Reddy > Signed-off-by: Michal Simek > --- > > configs/zynq_cse_nand_defconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig > index 2b58c461c390..80a427d905d3 100644 > --- a/configs/zynq_cse_nand_defconfig > +++ b/configs/zynq_cse_nand_defconfig > @@ -4,7 +4,7 @@ CONFIG_SYS_ICACHE_OFF=y > CONFIG_SYS_DCACHE_OFF=y > CONFIG_ARCH_ZYNQ=y > CONFIG_SYS_TEXT_BASE=0x10 > -CONFIG_SYS_MALLOC_LEN=0x1000 > +CONFIG_SYS_MALLOC_LEN=0x8000 > CONFIG_ENV_SIZE=0x190 > CONFIG_SPL_STACK_R_ADDR=0x20 > CONFIG_SPL=y > -- > 2.26.0 > Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] arm64: zynqmp: Fix irps5401 device nodes
po 13. 4. 2020 v 10:05 odesílatel Michal Simek napsal:
>
> - Do not use irps54012 as device node which is not correct.
> - Fix addresses of irps5401/u180 on zcu104 revisions.
> - Remove clock-cells property. It is PMIC without any clock output.
> - Define irps5401 nodes in zynqmp-e-a2197
>
> Signed-off-by: Michal Simek
> ---
>
> arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 16 +---
> arch/arm/dts/zynqmp-zcu104-revA.dts | 10 --
> arch/arm/dts/zynqmp-zcu104-revC.dts | 10 --
> arch/arm/dts/zynqmp-zcu111-revA.dts | 9 +++--
> arch/arm/dts/zynqmp-zcu208-revA.dts | 6 ++
> arch/arm/dts/zynqmp-zcu216-revA.dts | 6 ++
> 6 files changed, 28 insertions(+), 29 deletions(-)
>
> diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
> b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
> index 65cf5914945d..bf982e221830 100644
> --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
> +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
> @@ -198,9 +198,6 @@
> #size-cells = <0>;
> reg = <0>;
> /* u152 IR35215 0x16/0x46 vcc_soc */
> - /* u160 IRPS5401 0x17/0x47 */
> - /* u167 IRPS5401 0x1c/0x4c */
> - /* u175 IRPS5401 0x1d/0x4d */
> /* u179 ir38164 0x19/0x49 vcco_500 */
> /* u181 ir38164 0x1a/0x4a vcco_501 */
> /* u183 ir38164 0x1b/0x4b vcco_502 */
> @@ -209,6 +206,19 @@
> /* u189 ir38164 0x20/0x50 mgtyavtt */
> /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */
> /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */
> +
> + irps5401_47: irps5401@47 { /* IRPS5401 - u160 */
> + compatible = "infineon,irps5401";
> + reg = <0x47>; /* pmbus / i2c 0x17 */
> + };
> + irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */
> + compatible = "infineon,irps5401";
> + reg = <0x4c>; /* pmbus / i2c 0x1c */
> + };
> + irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */
> + compatible = "infineon,irps5401";
> + reg = <0x4d>; /* pmbus / i2c 0x1d */
> + };
> };
> i2c@1 { /* PMBUS1_INA226 */
> #address-cells = <1>;
> diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts
> b/arch/arm/dts/zynqmp-zcu104-revA.dts
> index 3ceb39dce02b..a4bd6b800a18 100644
> --- a/arch/arm/dts/zynqmp-zcu104-revA.dts
> +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
> @@ -147,15 +147,13 @@
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <2>;
> - irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
> - #clock-cells = <0>;
> + irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
> compatible = "infineon,irps5401";
> - reg = <0x43>;
> + reg = <0x43>; /* pmbus / i2c 0x13 */
> };
> - irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
> - #clock-cells = <0>;
> + irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
> compatible = "infineon,irps5401";
> - reg = <0x4d>;
> + reg = <0x44>; /* pmbus / i2c 0x14 */
> };
> };
>
> diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts
> b/arch/arm/dts/zynqmp-zcu104-revC.dts
> index 7dad4523deb0..d4b3769a27cc 100644
> --- a/arch/arm/dts/zynqmp-zcu104-revC.dts
> +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
> @@ -172,15 +172,13 @@
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <2>;
> - irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
> - #clock-cells = <0>;
> + irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
> compatible = "infineon,irps5401";
> - reg = <0x43>;
> + reg = <0x43>; /* pmbus / i2c 0x13 */
> };
> - irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
> - #clock-cells = <0>;
> + irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
> compatible = "infineon,irps5401";
> - reg = <0x4d>;
> + reg = <0x44>; /* pmbus / i2c 0x1
Re: [PATCH] ARM: zynq: Add nand controller node in zynq-ces-nand dt
čt 16. 4. 2020 v 14:22 odesílatel Michal Simek napsal:
>
> From: T Karthik Reddy
>
> Add memory-controller@e000e000 node in zynq-ces-nand.dts as
> zynq_nand driver utilizes flash@e100 node. Without this
> dt node mini nand u-boot does not probe.
>
> Signed-off-by: T Karthik Reddy
> Signed-off-by: Michal Simek
> ---
>
> arch/arm/dts/zynq-cse-nand.dts | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts
> index 1e16d7fab97d..32cb3bffcb94 100644
> --- a/arch/arm/dts/zynq-cse-nand.dts
> +++ b/arch/arm/dts/zynq-cse-nand.dts
> @@ -38,6 +38,21 @@
> #size-cells = <1>;
> ranges;
>
> + smcc: memory-controller@e000e000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + clock-names = "memclk", "apb_pclk";
> + clocks = <&clkc 11>, <&clkc 44>;
> + compatible = "arm,pl353-smc-r2p1", "arm,primecell";
> + ranges;
> + reg = <0xe000e000 0x1000>;
> +
> + nand0: flash@e100 {
> + compatible = "arm,pl353-nand-r2p1";
> + reg = <0xe100 0x100>;
> + };
> + };
> +
> slcr: slcr@f800 {
> u-boot,dm-pre-reloc;
> #address-cells = <1>;
> --
> 2.26.0
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] xilinx: Make Xilinx custom distro boot commands more verbose
po 20. 4. 2020 v 10:47 odesílatel Michal Simek napsal:
>
> Extend description of Xilinx custom boot commands to make clear what runs
> and what failed.
>
> Signed-off-by: Michal Simek
> ---
>
> include/configs/xilinx_versal.h | 12
> include/configs/xilinx_zynqmp.h | 9 ++---
> include/configs/zynq-common.h | 12
> 3 files changed, 22 insertions(+), 11 deletions(-)
>
> diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h
> index dec5001b5fe4..0c259a181f10 100644
> --- a/include/configs/xilinx_versal.h
> +++ b/include/configs/xilinx_versal.h
> @@ -109,7 +109,8 @@
> #define BOOTENV_DEV_XSPI(devtypeu, devtypel, instance) \
> "bootcmd_xspi0=sf probe 0 0 0 && " \
> "sf read $scriptaddr $script_offset_f $script_size_f && " \
> - "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
> + "echo XSPI: Trying to boot script at ${scriptaddr} && " \
> + "source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...;\0"
>
> #define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \
> "xspi "
> @@ -117,7 +118,8 @@
> #define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na)
>
> #define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \
> - "bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED:
> continuing...;\0"
> + "bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \
> + "source ${scriptaddr}; echo JTAG: SCRIPT FAILED:
> continuing...;\0"
>
> #define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \
> "jtag "
> @@ -126,8 +128,10 @@
>
> #define BOOTENV_DEV_DFU_USB(devtypeu, devtypel, instance) \
> "bootcmd_dfu_usb=setenv dfu_alt_info boot.scr ram $scriptaddr " \
> - "$script_size_f; dfu 0 ram 0 && source $scriptaddr; " \
> - "echo SCRIPT FAILED: continuing...;\0"
> + "$script_size_f; dfu 0 ram 0 && " \
> + "echo DFU: Trying to boot script at ${scriptaddr} && " \
> + "source ${scriptaddr}; " \
> + "echo DFU: SCRIPT FAILED: continuing...;\0"
>
> #define BOOTENV_DEV_NAME_DFU_USB(devtypeu, devtypel, instance) \
> "dfu_usb "
> diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
> index 010738363d13..eddc2b402006 100644
> --- a/include/configs/xilinx_zynqmp.h
> +++ b/include/configs/xilinx_zynqmp.h
> @@ -160,7 +160,8 @@
> #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
> "bootcmd_" #devtypel #instance "=sf probe " #instance " 0 0 && " \
>"sf read $scriptaddr $script_offset_f $script_size_f
> && " \
> - "source ${scriptaddr}; echo SCRIPT FAILED:
> continuing...;\0"
> + "echo QSPI: Trying to boot script at ${scriptaddr} &&
> " \
> + "source ${scriptaddr}; echo QSPI: SCRIPT FAILED:
> continuing...;\0"
>
> #define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
> #devtypel #instance " "
> @@ -168,7 +169,8 @@
> #define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
> "bootcmd_" #devtypel #instance "= nand info && " \
>"nand read $scriptaddr $script_offset_f $script_size_f
> && " \
> - "source ${scriptaddr}; echo SCRIPT FAILED:
> continuing...;\0"
> + "echo NAND: Trying to boot script at ${scriptaddr} &&
> " \
> + "source ${scriptaddr}; echo NAND: SCRIPT FAILED:
> continuing...;\0"
>
> #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
> #devtypel #instance " "
> @@ -176,7 +178,8 @@
> #define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na)
>
> #define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \
> - "bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED:
> continuing...;\0"
> + "bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \
> + "source ${scriptaddr}; echo JTAG: SCRIPT FAILED:
> continuing...;\0"
>
> #define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \
> "jtag "
> diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
> index 4ccc31e37655..a93172b02cd6 100644
> --- a/include/configs/zynq-common.h
> +++ b/include/configs/zynq-common.h
> @@ -152,7 +152,8 @@
> #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
> "bootcmd_qspi=sf probe 0 0 0 && " \
> "sf read ${scriptaddr} ${script_offset_f}
> ${script_size_f} && " \
> - "source ${scriptaddr}; echo SCRIPT FAILED:
> continuing...;\0"
> + "echo QSPI: Trying to boot script at ${scriptaddr} && "
> \
> + "source ${scriptaddr}; echo QSPI: SCRIPT FAILED:
> continuing...;\0"
>
> #define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
> "qspi "
> @@ -160,7 +161,8 @@
> #define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
> "bootcmd_nand=nand info && " \
> "nan
Re: [PATCH] ARM: zynq: Fix invalid check on NAND_CMD_NONE.
pá 24. 4. 2020 v 12:25 odesílatel Michal Simek napsal: > > From: Patrick van Gelder > > The end_cmd field in the variables cmd_phase_addr and data_phase_addr > contains the value 0xFF when the end_cmd equals NAND_CMD_NONE. This > should be 0x00. > > This is caused by comparing NAND_CMD_NONE (int) with end_cmd (u8). > end_cmd will be promoted by the int value -1 and therefore is not equal > to 0xFF. Solved by casting NAND_CMD_NONE to u8 which will avoid int > promotion. > > Signed-off-by: Patrick van Gelder > Reviewed-by: T Karthik Reddy > Signed-off-by: Michal Simek > --- > > drivers/mtd/nand/raw/zynq_nand.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mtd/nand/raw/zynq_nand.c > b/drivers/mtd/nand/raw/zynq_nand.c > index 0aea83dac0e6..394129741831 100644 > --- a/drivers/mtd/nand/raw/zynq_nand.c > +++ b/drivers/mtd/nand/raw/zynq_nand.c > @@ -845,7 +845,7 @@ static void zynq_nand_cmd_function(struct mtd_info *mtd, > unsigned int command, > if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE) > end_cmd_valid = 1; > > - if (curr_cmd->end_cmd == NAND_CMD_NONE) > + if (curr_cmd->end_cmd == (u8)NAND_CMD_NONE) > end_cmd = 0x0; > else > end_cmd = curr_cmd->end_cmd; > -- > 2.26.2 > Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
[GIT PULL] Xilinx fixes for v2020.07-rc2
Hi Tom, Please pull these patches to your tree. Travis looks good. https://travis-ci.org/github/michalsimek/u-boot/builds/680070323 Gitlab CI too https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze/pipelines/2952 I have tried to merge with your latest branch and there is small conflict because of defconfig resync. It is easy to resolve like this. diff --cc configs/zynq_cse_nand_defconfig index 80a427d905d3,19491c9e47eb.. --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@@ -4,8 -4,8 +4,8 @@@ CONFIG_SYS_ICACHE_OFF= CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x10 - CONFIG_SYS_MALLOC_LEN=0x8000 CONFIG_ENV_SIZE=0x190 -CONFIG_SYS_MALLOC_LEN=0x1000 ++CONFIG_SYS_MALLOC_LEN=0x8000 CONFIG_SPL_STACK_R_ADDR=0x20 CONFIG_SPL=y CONFIG_SYS_CUSTOM_LDSCRIPT=y Thanks, Michal The following changes since commit d202f67db0771247de562af5d6a5df778702857b: Merge branch '2020-04-25-master-imports' (2020-04-25 08:20:22 -0400) are available in the Git repository at: g...@gitlab.denx.de:u-boot/custodians/u-boot-microblaze.git tags/xilinx-for-v2020.07-rc2 for you to fetch changes up to 27d706937a5c72f0414a540ca20fd36b4b72bda7: ARM: zynq: Fix invalid check on NAND_CMD_NONE. (2020-04-27 14:21:18 +0200) Xilinx changes for v2020.07-rc2 mmc: - Fix dt property handling via generic function clk: - Fix versal watchdog clock setting nand: - Fix zynq nand command comparison xilinx: - Enable ubifs - Sync board_late_init configurations with initrd_high setup - Make custom distro boot more verbose zynq: - Kconfig alignments - Fix nand cse configuration zynqmp: - Fix zcu104 low level qspi configuration - Small DT updates Benedikt Grassl (1): mmc: zynq: parse dt when probing Michal Simek (8): xilinx: Enable MTD and UBIFS for zynq and zynqmp ARM: zynq: Setup stack size via Kconfig xilinx: Introduce board_late_init_xilinx() xilinx: zynqmp: Fix MIO 18 configuration on zcu104 revC xilinx: Move initrd_high setup to common location xilinx: Move bootmode detection to separate function arm64: zynqmp: Fix irps5401 device nodes xilinx: Make Xilinx custom distro boot commands more verbose Patrick van Gelder (1): ARM: zynq: Fix invalid check on NAND_CMD_NONE. Saeed Nowshadi (1): arm64: zynqmp: Add label to GPIO lines for boot mode and POR T Karthik Reddy (3): clk: versal: Fix watchdog clock issue ARM: zynq: Add nand controller node in zynq-ces-nand dt ARM: zynq: Change SYS_MALLOC_LEN in zynq_cse_nand_defconfig arch/arm/Kconfig | 3 ++- arch/arm/dts/zynq-cse-nand.dts| 15 +++ arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 22 -- arch/arm/dts/zynqmp-zcu104-revA.dts | 10 -- arch/arm/dts/zynqmp-zcu104-revC.dts | 10 -- arch/arm/dts/zynqmp-zcu111-revA.dts | 9 +++-- arch/arm/dts/zynqmp-zcu208-revA.dts | 6 ++ arch/arm/dts/zynqmp-zcu216-revA.dts | 6 ++ board/bitmain/antminer_s9/Makefile| 1 + board/topic/zynq/Makefile | 1 + board/xilinx/common/board.c | 15 +++ board/xilinx/common/board.h | 12 board/xilinx/versal/board.c | 34 ++ board/xilinx/zynq/board.c | 5 ++--- board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c | 3 ++- board/xilinx/zynqmp/zynqmp.c | 39 +-- configs/xilinx_zynq_virt_defconfig| 5 + configs/xilinx_zynqmp_virt_defconfig | 5 + configs/zynq_cse_nand_defconfig | 2 +- drivers/clk/clk_versal.c | 5 - drivers/mmc/sdhci.c | 3 +-- drivers/mmc/zynq_sdhci.c | 15 ++- drivers/mtd/nand/raw/zynq_nand.c | 2 +- include/configs/xilinx_versal.h | 12 include/configs/xilinx_zynqmp.h | 9 ++--- include/configs/zynq-common.h | 13 - include/sdhci.h | 1 - 27 files changed, 165 insertions(+), 98 deletions(-) create mode 100644 board/xilinx/common/board.h
[PATCH] mmc: stm32_sdmmc2: change the displayed config name
Change the mmc displayed name in U-Boot for stm32_sdmmc2 driver to “STM32 SD/MMC”. This stm32_sdmmc2 driver is for version 2 of the ST HW IP SDMMC but the displayed name "STM32 SDMMC2" is confusing for user, between the instance of SDMMC and the device identifier of MMC. For example on EV1 board, we have: STM32MP1> mmc list STM32 SDMMC2: 0 (SD) STM32 SDMMC2: 1 (eMMC) Changed to more clear: STM32MP1> mmc list STM32 SD/MMC: 0 (SD) STM32 SD/MMC: 1 (eMMC) Signed-off-by: Patrick Delaunay --- drivers/mmc/stm32_sdmmc2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 6f3b2ad653..fa6fc94ad9 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -674,7 +674,7 @@ static int stm32_sdmmc2_probe(struct udevice *dev) cfg->f_max = dev_read_u32_default(dev, "max-frequency", 5200); cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - cfg->name = "STM32 SDMMC2"; + cfg->name = "STM32 SD/MMC"; cfg->host_caps = 0; if (cfg->f_max > 2500) -- 2.17.1
Re: [PATCH v2 1/3] net: phy: Add helper routines to set and clear bits
On 28. 04. 20 21:26, Dan Murphy wrote:
> Add phy_set/clear_bit helper routines so that ported drivers from the
> kernel can use these functions.
>
> Signed-off-by: Dan Murphy
> ---
> include/phy.h | 80 +++
> 1 file changed, 80 insertions(+)
>
> diff --git a/include/phy.h b/include/phy.h
> index b5de14cbfc29..1a875b96edb7 100644
> --- a/include/phy.h
> +++ b/include/phy.h
> @@ -170,6 +170,12 @@ struct fixed_link {
> int asym_pause;
> };
>
> +/**
> + * phy_read - Convenience function for reading a given PHY register
> + * @phydev: the phy_device struct
> + * @devad: The MMD to read from
> + * @regnum: register number to read
> + */
> static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
> {
> struct mii_dev *bus = phydev->bus;
> @@ -182,6 +188,13 @@ static inline int phy_read(struct phy_device *phydev,
> int devad, int regnum)
> return bus->read(bus, phydev->addr, devad, regnum);
> }
>
> +/**
> + * phy_write - Convenience function for writing a given PHY register
> + * @phydev: the phy_device struct
> + * @devad: The MMD to read from
> + * @regnum: register number to write
> + * @val: value to write to @regnum
> + */
> static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
> u16 val)
> {
> @@ -209,6 +222,13 @@ static inline void phy_mmd_start_indirect(struct
> phy_device *phydev, int devad,
> (devad | MII_MMD_CTRL_NOINCR));
> }
>
> +/**
> + * phy_read_mmd - Convenience function for reading a register
> + * from an MMD on a given PHY.
> + * @phydev: The phy_device struct
> + * @devad: The MMD to read from
> + * @regnum: The register on the MMD to read
> + */
> static inline int phy_read_mmd(struct phy_device *phydev, int devad,
> int regnum)
> {
> @@ -233,6 +253,14 @@ static inline int phy_read_mmd(struct phy_device
> *phydev, int devad,
> return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA);
> }
>
> +/**
> + * phy_write_mmd - Convenience function for writing a register
> + * on an MMD on a given PHY.
> + * @phydev: The phy_device struct
> + * @devad: The MMD to read from
> + * @regnum: The register on the MMD to read
> + * @val: value to write to @regnum
> + */
> static inline int phy_write_mmd(struct phy_device *phydev, int devad,
> int regnum, u16 val)
> {
> @@ -257,6 +285,58 @@ static inline int phy_write_mmd(struct phy_device
> *phydev, int devad,
> return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val);
> }
>
> +/**
> + * phy_set_bits_mmd - Convenience function for setting bits in a register
> + * on MMD
> + * @phydev: the phy_device struct
> + * @devad: the MMD containing register to modify
> + * @regnum: register number to modify
> + * @val: bits to set
> + */
> +static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad,
> +u32 regnum, u16 val)
> +{
> + int value, ret;
> +
> + value = phy_read_mmd(phydev, devad, regnum);
> + if (value < 0)
> + return value;
> +
> + value |= val;
> +
> + ret = phy_write_mmd(phydev, devad, regnum, value);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +
> +/**
> + * phy_clear_bits_mmd - Convenience function for clearing bits in a register
> + * on MMD
> + * @phydev: the phy_device struct
> + * @devad: the MMD containing register to modify
> + * @regnum: register number to modify
> + * @val: bits to clear
> + */
> +static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad,
> + u32 regnum, u16 val)
> +{
> + int value, ret;
> +
> + value = phy_read_mmd(phydev, devad, regnum);
> + if (value < 0)
> + return value;
> +
> + value &= ~val;
> +
> + ret = phy_write_mmd(phydev, devad, regnum, value);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +
> #ifdef CONFIG_PHYLIB_10G
> extern struct phy_driver gen10g_driver;
>
>
Better would be to have one patch just with adding missing kernel-doc.
It is not described in commit message too.
And second to add that functions.
And there are errors there.
[u-boot](debian)$ ./scripts/kernel-doc -v -man include/phy.h > /dev/null
include/phy.h:174: info: Scanning doc for phy_read
include/phy.h:180: warning: No description found for return value of
'phy_read'
include/phy.h:192: info: Scanning doc for phy_write
include/phy.h:200: warning: No description found for return value of
'phy_write'
include/phy.h:226: info: Scanning doc for phy_read_mmd
include/phy.h:234: warning: No description found for return value of
'phy_read_mmd'
include/phy.h:257: info: Scanning doc for phy_write_mmd
include/phy.h:266: warning: No description found for return value of
'phy_write_mmd'
include/phy.h:289: info: Scanning doc for phy_set_bits_mmd
include/phy.h:298: warning: No description f
Re: [PATCH v2 2/3] net: phy: Add support for TI PHY init
On 28. 04. 20 21:26, Dan Murphy wrote: > ti_phy_init function was allocated to the DP83867 PHY. This function > name is to generic for a specific PHY. The function can be moved to a > TI specific file that can register all TI PHYs that are defined in the > defconfig. The ti_phy_init file will contain all TI PHYs initialization > so that only phy_ti_init can be called from the framework. > > In addition to the above the config flag for the DP83867 needs to be changed > in the Kconfig and dependent defconfig files. The config flag that was > used for the DP83867 was also generic in nature so a more specific > config flag for the DP83867 was created. > > Signed-off-by: Dan Murphy > --- > configs/am65x_evm_a53_defconfig | 2 +- > configs/am65x_hs_evm_a53_defconfig | 2 +- > configs/dra7xx_evm_defconfig | 2 +- > configs/dra7xx_hs_evm_defconfig | 2 +- > configs/dra7xx_hs_evm_usb_defconfig | 2 +- > configs/j721e_evm_a72_defconfig | 2 +- > configs/j721e_hs_evm_a72_defconfig | 2 +- > configs/k2g_evm_defconfig| 2 +- > configs/xilinx_versal_virt_defconfig | 2 +- > configs/xilinx_zynqmp_virt_defconfig | 2 +- > drivers/net/phy/Kconfig | 15 +++ > drivers/net/phy/Makefile | 3 ++- > drivers/net/phy/dp83867.c| 3 ++- > drivers/net/phy/ti_phy_init.c| 18 ++ > drivers/net/phy/ti_phy_init.h| 15 +++ > 15 files changed, 62 insertions(+), 12 deletions(-) > create mode 100644 drivers/net/phy/ti_phy_init.c > create mode 100644 drivers/net/phy/ti_phy_init.h > > diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig > index 542bbd992c53..c8cc9b2f7d8d 100644 > --- a/configs/am65x_evm_a53_defconfig > +++ b/configs/am65x_evm_a53_defconfig > @@ -101,7 +101,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT > CONFIG_SPI_FLASH_STMICRO=y > # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set > CONFIG_SPI_FLASH_MTD=y > -CONFIG_PHY_TI=y > +CONFIG_PHY_TI_DP83867=y > CONFIG_PHY_FIXED=y > CONFIG_DM_ETH=y > CONFIG_E1000=y > diff --git a/configs/am65x_hs_evm_a53_defconfig > b/configs/am65x_hs_evm_a53_defconfig > index 9f43cee39611..738bd01b059f 100644 > --- a/configs/am65x_hs_evm_a53_defconfig > +++ b/configs/am65x_hs_evm_a53_defconfig > @@ -103,7 +103,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT > CONFIG_SPI_FLASH_STMICRO=y > # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set > CONFIG_SPI_FLASH_MTD=y > -CONFIG_PHY_TI=y > +CONFIG_PHY_TI_DP83867=y > CONFIG_PHY_FIXED=y > CONFIG_DM_ETH=y > CONFIG_E1000=y > diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig > index 4d765da4e052..9ad462cdc6de 100644 > --- a/configs/dra7xx_evm_defconfig > +++ b/configs/dra7xx_evm_defconfig > @@ -86,7 +86,7 @@ CONFIG_DM_SPI_FLASH=y > CONFIG_SF_DEFAULT_MODE=0 > CONFIG_SF_DEFAULT_SPEED=7680 > CONFIG_SPI_FLASH_SPANSION=y > -CONFIG_PHY_TI=y > +CONFIG_PHY_TI_DP83867=y > CONFIG_DM_ETH=y > CONFIG_PHY_GIGE=y > CONFIG_MII=y > diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig > index c25d4ce5c142..9aa452460765 100644 > --- a/configs/dra7xx_hs_evm_defconfig > +++ b/configs/dra7xx_hs_evm_defconfig > @@ -89,7 +89,7 @@ CONFIG_DM_SPI_FLASH=y > CONFIG_SF_DEFAULT_MODE=0 > CONFIG_SF_DEFAULT_SPEED=7680 > CONFIG_SPI_FLASH_SPANSION=y > -CONFIG_PHY_TI=y > +CONFIG_PHY_TI_DP83867=y > CONFIG_DM_ETH=y > CONFIG_PHY_GIGE=y > CONFIG_MII=y > diff --git a/configs/dra7xx_hs_evm_usb_defconfig > b/configs/dra7xx_hs_evm_usb_defconfig > index 8e74496b2ccd..d282468212e9 100644 > --- a/configs/dra7xx_hs_evm_usb_defconfig > +++ b/configs/dra7xx_hs_evm_usb_defconfig > @@ -87,7 +87,7 @@ CONFIG_SF_DEFAULT_MODE=0 > CONFIG_SF_DEFAULT_SPEED=7680 > CONFIG_SPI_FLASH_BAR=y > CONFIG_SPI_FLASH_SPANSION=y > -CONFIG_PHY_TI=y > +CONFIG_PHY_TI_DP83867=y > CONFIG_DM_ETH=y > CONFIG_PHY_GIGE=y > CONFIG_MII=y > diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig > index e9e82bb4309d..29ae8d720753 100644 > --- a/configs/j721e_evm_a72_defconfig > +++ b/configs/j721e_evm_a72_defconfig > @@ -124,7 +124,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT > CONFIG_SPI_FLASH_STMICRO=y > # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set > CONFIG_SPI_FLASH_MTD=y > -CONFIG_PHY_TI=y > +CONFIG_PHY_TI_DP83867=y > CONFIG_PHY_FIXED=y > CONFIG_DM_ETH=y > CONFIG_TI_AM65_CPSW_NUSS=y > diff --git a/configs/j721e_hs_evm_a72_defconfig > b/configs/j721e_hs_evm_a72_defconfig > index a723e2718e5e..7174fda72a01 100644 > --- a/configs/j721e_hs_evm_a72_defconfig > +++ b/configs/j721e_hs_evm_a72_defconfig > @@ -114,7 +114,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT > CONFIG_SPI_FLASH_STMICRO=y > # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set > CONFIG_SPI_FLASH_MTD=y > -CONFIG_PHY_TI=y > +CONFIG_PHY_TI_DP83867=y > CONFIG_PHY_FIXED=y > CONFIG_DM_ETH=y > CONFIG_TI_AM65_CPSW_NUSS=y > diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig > index 5abf5faa450e..14cf1b997d91 100644 > --- a/configs/k2g_
Re: [PATCH v2 3/3] net: phy: Add DP8382x phy registration to TI PHY init
On 28. 04. 20 21:26, Dan Murphy wrote:
> Add the DP8382X generic PHY registration to the TI PHY init file.
>
> Signed-off-by: Dan Murphy
> ---
> drivers/net/phy/ti_phy_init.c | 91 +++
> 1 file changed, 91 insertions(+)
>
> diff --git a/drivers/net/phy/ti_phy_init.c b/drivers/net/phy/ti_phy_init.c
> index 277b29a26342..47f32a528361 100644
> --- a/drivers/net/phy/ti_phy_init.c
> +++ b/drivers/net/phy/ti_phy_init.c
> @@ -7,12 +7,103 @@
> * Copyright (C) 2019-20 Texas Instruments Inc.
> */
>
> +
Useless change.
> +#include
> #include "ti_phy_init.h"
>
> +#define DP83822_PHY_ID 0x2000a240
> +#define DP83825S_PHY_ID 0x2000a140
> +#define DP83825I_PHY_ID 0x2000a150
> +#define DP83825CM_PHY_ID 0x2000a160
> +#define DP83825CS_PHY_ID 0x2000a170
> +#define DP83826C_PHY_ID 0x2000a130
> +#define DP83826NC_PHY_ID 0x2000a110
nit: Can't see value to have these macros here.
> +
> +#ifdef CONFIG_PHY_TI_GENERIC
> +static struct phy_driver dp83822_driver = {
> + .name = "TI DP83822",
> + .uid = DP83822_PHY_ID,
> + .mask = 0xfff0,
> + .features = PHY_BASIC_FEATURES,
> + .config = &genphy_config_aneg,
> + .startup = &genphy_startup,
> + .shutdown = &genphy_shutdown,
> +};
> +
> +static struct phy_driver dp83825s_driver = {
> + .name = "TI DP83825S",
> + .uid = DP83825S_PHY_ID,
> + .mask = 0xfff0,
> + .features = PHY_BASIC_FEATURES,
> + .config = &genphy_config_aneg,
> + .startup = &genphy_startup,
> + .shutdown = &genphy_shutdown,
> +};
> +
> +static struct phy_driver dp83825i_driver = {
> + .name = "TI DP83825I",
> + .uid = DP83825I_PHY_ID,
> + .mask = 0xfff0,
> + .features = PHY_BASIC_FEATURES,
> + .config = &genphy_config_aneg,
> + .startup = &genphy_startup,
> + .shutdown = &genphy_shutdown,
> +};
> +
> +static struct phy_driver dp83825m_driver = {
> + .name = "TI DP83825M",
> + .uid = DP83825CM_PHY_ID,
> + .mask = 0xfff0,
> + .features = PHY_BASIC_FEATURES,
> + .config = &genphy_config_aneg,
> + .startup = &genphy_startup,
> + .shutdown = &genphy_shutdown,
> +};
> +
> +static struct phy_driver dp83825cs_driver = {
> + .name = "TI DP83825CS",
> + .uid = DP83825CS_PHY_ID,
> + .mask = 0xfff0,
> + .features = PHY_BASIC_FEATURES,
> + .config = &genphy_config_aneg,
> + .startup = &genphy_startup,
> + .shutdown = &genphy_shutdown,
> +};
> +
> +static struct phy_driver dp83826c_driver = {
> + .name = "TI DP83826C",
> + .uid = DP83826C_PHY_ID,
> + .mask = 0xfff0,
> + .features = PHY_BASIC_FEATURES,
> + .config = &genphy_config_aneg,
> + .startup = &genphy_startup,
> + .shutdown = &genphy_shutdown,
> +};
> +static struct phy_driver dp83826nc_driver = {
> + .name = "TI DP83826NC",
> + .uid = DP83826NC_PHY_ID,
> + .mask = 0xfff0,
> + .features = PHY_BASIC_FEATURES,
> + .config = &genphy_config_aneg,
> + .startup = &genphy_startup,
> + .shutdown = &genphy_shutdown,
> +};
> +#endif /* CONFIG_PHY_TI_GENERIC */
> +
> int phy_ti_init(void)
> {
> #ifdef CONFIG_PHY_TI_DP83867
> phy_dp83867_init();
> #endif
> +
> +#ifdef CONFIG_PHY_TI_GENERIC
> + phy_register(&dp83822_driver);
> + phy_register(&dp83825s_driver);
> + phy_register(&dp83825i_driver);
> + phy_register(&dp83825m_driver);
> + phy_register(&dp83825cs_driver);
> + phy_register(&dp83826c_driver);
> + phy_register(&dp83826nc_driver);
> +#endif
> return 0;
> }
>
When you remove that additional empty line feel free to add my
Acked-by: Michal Simek
Thanks,
Michal
Re: [PATCH v2 5/5] doc: add bind/unbind command documentation
On 4/29/20 8:04 PM, Simon Glass wrote:
> Hi Patrice,
>
> On Wed, 29 Apr 2020 at 06:20, Patrice Chotard wrote:
>> Add documentation in doc/drivel-model for the bind/unbind command.
>> Part of this documentation is extracted from original patch commit
>> message:
>> commit 49c752c93a78 ("cmd: Add bind/unbind commands to bind a device to a
>> driver from the command line")
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> Changes in v2: None
>>
>> doc/driver-model/bind.rst | 32
>> doc/driver-model/index.rst | 1 +
>> 2 files changed, 33 insertions(+)
>> create mode 100644 doc/driver-model/bind.rst
>>
>> diff --git a/doc/driver-model/bind.rst b/doc/driver-model/bind.rst
>> new file mode 100644
>> index 00..df6b5f143b
>> --- /dev/null
>> +++ b/doc/driver-model/bind.rst
>> @@ -0,0 +1,32 @@
>> +.. SPDX-License-Identifier: GPL-2.0+
>> +.. sectionauthor:: Patrice Chotard
>> +
>> +Binding/unbiding a driver
> unbinding
>
>> +=
>> +
>> +This documents aims to describe the bind and unbind commands.
> document
>
>> +
>> +For debug purpose, it should be useful to bind or unbind a driver from
> For debugging
>
>> +the U-boot command line.
>> +
>> +The unbind command calls the remove device driver callback and unbind the
>> +device from its driver.
>> +
>> +The bind command binds a device to its driver.
>> +
>> +In some cases it can be useful to be able to bind a device to a driver from
>> +the command line.
>> +The obvious example is for versatile devices such as USB gadget.
>> +Another use case is when the devices are not yet ready at startup and
>> +require some setup before the drivers are bound (ex: FPGA which bitsream is
>> +fetched from a mass storage or ethernet)
>> +
>> +usage example:
>> +
>> +bind usb_dev_generic 0 usb_ether
>> +unbind usb_dev_generic 0 usb_ether
> can you mention what the two parameters are and how to find them?
I will fix typos and update the documentation with these informations.
Thanks
Patrice
>
>> +or
>> +unbind eth 1
>> +
>> +bind /ocp/omap_dwc3@4838/usb@4839 usb_ether
>> +unbind /ocp/omap_dwc3@4838/usb@4839
>> diff --git a/doc/driver-model/index.rst b/doc/driver-model/index.rst
>> index b9df221627..37ef3721df 100644
>> --- a/doc/driver-model/index.rst
>> +++ b/doc/driver-model/index.rst
>> @@ -6,6 +6,7 @@ Driver Model
>> .. toctree::
>> :maxdepth: 2
>>
>> + bind
>> debugging
>> design
>> ethernet
>> --
>> 2.17.1
>>
> Regards,
> Simon
Re: [PATCH v2 4/5] test/py: Update test_bind
Hi Simon On 4/29/20 8:04 PM, Simon Glass wrote: > On Wed, 29 Apr 2020 at 06:20, Patrice Chotard wrote: >> As bind-test is now binded at sandbox startup and no more by >> test_bind.py, bind-test nodes are not located at the end of >> "dm tree" output, but can be located everywwhere in the tree, so > everywhere will be fixed Thanks Patrice > >> bind-test output could either be: >> >> simple_bus0 [ ] generic_simple_bus|-- bind-test >> phy 0 [ ] phy_sandbox | |-- bind-test-child1 >> simple_bus1 [ ] generic_simple_bus| `-- bind-test-child2 >> >> or: >> >> simple_bus5 [ ] generic_simple_bus`-- bind-test >> phy 2 [ ] phy_sandbox |-- bind-test-child1 >> simple_bus6 [ ] generic_simple_bus`-- bind-test-child2 >> >> in_tree() function need to be updated to take care of that change. >> >> Signed-off-by: Patrice Chotard >> --- >> >> Changes in v2: None >> >> test/py/tests/test_bind.py | 15 +-- >> 1 file changed, 9 insertions(+), 6 deletions(-) > Reviewed-by: Simon Glass
[PATCH v3 3/5] sandbox: dts: Add compatible string for bind-test node
Usage of lists_bind_fdt() in bind command imposes to add
a compatible string for bind-test node.
The other impact, is that bind-test node is binded at sandbox
start, so no need to bind it in test_bind_unbind_with_node() test
Signed-off-by: Patrice Chotard
Reviewed-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/sandbox/dts/test.dts | 1 +
test/py/tests/test_bind.py | 3 ---
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index df9f1835c9..7c6b14887f 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -131,6 +131,7 @@
};
bind-test {
+ compatible = "simple-bus";
bind-test-child1 {
compatible = "sandbox,phy";
#phy-cells = <1>;
diff --git a/test/py/tests/test_bind.py b/test/py/tests/test_bind.py
index 20c6050342..0b7cd9a808 100644
--- a/test/py/tests/test_bind.py
+++ b/test/py/tests/test_bind.py
@@ -25,9 +25,6 @@ def in_tree(response, name, uclass, drv, depth, last_child):
@pytest.mark.buildconfigspec('cmd_bind')
def test_bind_unbind_with_node(u_boot_console):
- #bind /bind-test. Device should come up as well as its children
- response = u_boot_console.run_command('bind /bind-test
generic_simple_bus')
- assert response == ''
tree = u_boot_console.run_command('dm tree')
assert in_tree(tree, 'bind-test', 'simple_bus', 'generic_simple_bus',
0, True)
assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, False)
--
2.17.1
[PATCH v3 1/5] cmd: bind: allow to bind driver with driver data
Initial implementation invokes device_bind_with_driver_data()
with driver_data parameter equal to 0.
For driver with driver data, the bind command can't bind
correctly this driver or even worse causes data abort as shown below:
As example, for debug purpose on STM32MP1 platform, ethernet (dwc_eth_qos.c)
driver needed to be unbinded/binded. This driver is using driver data:
static const struct udevice_id eqos_ids[] = {
{
.compatible = "nvidia,tegra186-eqos",
.data = (ulong)&eqos_tegra186_config
},
{
.compatible = "snps,dwmac-4.20a",
.data = (ulong)&eqos_stm32_config
},
{ }
};
After unbinding/binding this driver and probing it (with the dhcp command),
we got a prefetch abort as below:
STM32MP> unbind eth ethernet@5800a000
STM32MP> bind /soc/ethernet@5800a000 eth_eqos
STM32MP> dhcp
prefetch abort
pc : [<4310801c>] lr : []
reloc pc : [<035ba01c>]lr : []
sp : fdaf19b0 ip : ffcea83c fp : 0001
r10: ffcfd4a0 r9 : fdaffed0 r8 :
r7 : ffcff304 r6 : fdc63220 r5 : r4 : fdc5b108
r3 : 43108020 r2 : 3d39 r1 : ffcea544 r0 : fdc63220
Flags: nZCv IRQs off FIQs off Mode SVC_32
Code: data abort
pc : [] lr : []
reloc pc : []lr : []
sp : fdaf18b8 ip : fp : 0001
r10: ffcd69b2 r9 : fdaffed0 r8 : ffcd69aa
r7 : r6 : 0008 r5 : 4310801c r4 : fffc
r3 : 0001 r2 : 0028 r1 : r0 : 0006
Flags: NzCv IRQs on FIQs on Mode SVC_32 (T)
Code: 2f00 d1e9 2c00 dce9 (f855) 2024
Resetting CPU ...
Signed-off-by: Patrice Chotard
Cc: Jean-Jacques Hiblot
Reviewed-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- add a bind command test
- add bind command documentation in doc/driver/model/bind.rst
- simplify patch 1 by using lists_bind_fdt()
cmd/bind.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/cmd/bind.c b/cmd/bind.c
index 44a5f17f0d..0aefc531d8 100644
--- a/cmd/bind.c
+++ b/cmd/bind.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include
static int bind_by_class_index(const char *uclass, int index,
@@ -150,8 +151,8 @@ static int bind_by_node_path(const char *path, const char
*drv_name)
}
ofnode = ofnode_path(path);
- ret = device_bind_with_driver_data(parent, drv, ofnode_get_name(ofnode),
- 0, ofnode, &dev);
+ ret = lists_bind_fdt(parent, ofnode, &dev, false);
+
if (!dev || ret) {
printf("Unable to bind. err:%d\n", ret);
return ret;
--
2.17.1
[PATCH v3 5/5] doc: add bind/unbind command documentation
Add documentation in doc/drivel-model for the bind/unbind command.
Part of this documentation is extracted from original patch commit
message:
commit 49c752c93a78 ("cmd: Add bind/unbind commands to bind a device to a
driver from the command line")
Signed-off-by: Patrice Chotard
---
Changes in v3:
- fix typo
- add bind/unbind parameters description and how to find them
Changes in v2: None
doc/driver-model/bind.rst | 49 ++
doc/driver-model/index.rst | 1 +
2 files changed, 50 insertions(+)
create mode 100644 doc/driver-model/bind.rst
diff --git a/doc/driver-model/bind.rst b/doc/driver-model/bind.rst
new file mode 100644
index 00..dfe8fd57dd
--- /dev/null
+++ b/doc/driver-model/bind.rst
@@ -0,0 +1,49 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Patrice Chotard
+
+Binding/unbinding a driver
+=
+
+This document aims to describe the bind and unbind commands.
+
+For debugging purpose, it should be useful to bind or unbind a driver from
+the U-boot command line.
+
+The unbind command calls the remove device driver callback and unbind the
+device from its driver.
+
+The bind command binds a device to its driver.
+
+In some cases it can be useful to be able to bind a device to a driver from
+the command line.
+The obvious example is for versatile devices such as USB gadget.
+Another use case is when the devices are not yet ready at startup and
+require some setup before the drivers are bound (ex: FPGA which bitsream is
+fetched from a mass storage or ethernet)
+
+usage:
+
+bind
+bind
+
+unbind
+unbind
+unbind
+
+Where:
+ - is the node's device tree path
+ - is one of the class available in the list given by the "dm uclass"
+ command or first column of "dm tree" command.
+ - is the index of the parent's node (second column of "dm tree"
output).
+ - is the driver name to bind given by the "dm drivers" command or
the by
+ the fourth column of "dm tree" output.
+
+example:
+
+bind usb_dev_generic 0 usb_ether
+unbind usb_dev_generic 0 usb_ether
+or
+unbind eth 1
+
+bind /ocp/omap_dwc3@4838/usb@4839 usb_ether
+unbind /ocp/omap_dwc3@4838/usb@4839
diff --git a/doc/driver-model/index.rst b/doc/driver-model/index.rst
index b9df221627..37ef3721df 100644
--- a/doc/driver-model/index.rst
+++ b/doc/driver-model/index.rst
@@ -6,6 +6,7 @@ Driver Model
.. toctree::
:maxdepth: 2
+ bind
debugging
design
ethernet
--
2.17.1
[PATCH v3 2/5] sandbox: phy: add driver_data for bind test cmd
Add driver data to existing compatible string "sandbox,phy".
Add an additional compatible string without driver_data
This will verify that bind command parses, finds and passes the
correct driver data to device_bind_with_driver_data() by using
driver_data in the second sandbox_phy_ids table entry.
In sandbox_phy_bind() a check is added to validate driver_data
content.
Signed-off-by: Patrice Chotard
Reviewed-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/phy/sandbox-phy.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/sandbox-phy.c b/drivers/phy/sandbox-phy.c
index 84ff5c6275..5f36da7692 100644
--- a/drivers/phy/sandbox-phy.c
+++ b/drivers/phy/sandbox-phy.c
@@ -8,6 +8,8 @@
#include
#include
+#define DRIVER_DATA 0x12345678
+
struct sandbox_phy_priv {
bool initialized;
bool on;
@@ -71,6 +73,14 @@ static int sandbox_phy_exit(struct phy *phy)
return 0;
}
+static int sandbox_phy_bind(struct udevice *dev)
+{
+ if (dev_get_driver_data(dev) != DRIVER_DATA)
+ return -ENODATA;
+
+ return 0;
+}
+
static int sandbox_phy_probe(struct udevice *dev)
{
struct sandbox_phy_priv *priv = dev_get_priv(dev);
@@ -90,13 +100,19 @@ static struct phy_ops sandbox_phy_ops = {
};
static const struct udevice_id sandbox_phy_ids[] = {
- { .compatible = "sandbox,phy" },
+ { .compatible = "sandbox,phy_no_driver_data",
+ },
+
+ { .compatible = "sandbox,phy",
+ .data = DRIVER_DATA
+ },
{ }
};
U_BOOT_DRIVER(phy_sandbox) = {
.name = "phy_sandbox",
.id = UCLASS_PHY,
+ .bind = sandbox_phy_bind,
.of_match = sandbox_phy_ids,
.ops= &sandbox_phy_ops,
.probe = sandbox_phy_probe,
--
2.17.1
[PATCH v3 4/5] test/py: Update test_bind
As bind-test is now binded at sandbox startup and no more by
test_bind.py, bind-test nodes are not located at the end of
"dm tree" output, but can be located everywhere in the tree, so
bind-test output could either be:
simple_bus0 [ ] generic_simple_bus|-- bind-test
phy 0 [ ] phy_sandbox | |-- bind-test-child1
simple_bus1 [ ] generic_simple_bus| `-- bind-test-child2
or:
simple_bus5 [ ] generic_simple_bus`-- bind-test
phy 2 [ ] phy_sandbox |-- bind-test-child1
simple_bus6 [ ] generic_simple_bus`-- bind-test-child2
in_tree() function need to be updated to take care of that change.
Signed-off-by: Patrice Chotard
Reviewed-by: Simon Glass
---
Changes in v3:
- fix typo
Changes in v2: None
test/py/tests/test_bind.py | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/test/py/tests/test_bind.py b/test/py/tests/test_bind.py
index 0b7cd9a808..4753c7ea7b 100644
--- a/test/py/tests/test_bind.py
+++ b/test/py/tests/test_bind.py
@@ -7,13 +7,16 @@ import re
def in_tree(response, name, uclass, drv, depth, last_child):
lines = [x.strip() for x in response.splitlines()]
- leaf = ' ' * 4 * depth;
- if not last_child:
- leaf = leaf + r'\|'
- else:
- leaf = leaf + '`'
+ leaf = ''
+ if depth != 0:
+ leaf = ' ' + '' * (depth - 1) ;
+ if not last_child:
+ leaf = leaf + r'\|'
+ else:
+leaf = leaf + '`'
+
leaf = leaf + '-- ' + name
- line = (r' *{:10.10}[0-9]* \[ [ +] \] {:20.20} {}$'
+ line = (r' *{:10.10}[0-9]* \[ [ +] \] {:20.20} [` |]{}$'
.format(uclass, drv, leaf))
prog = re.compile(line)
for l in lines:
--
2.17.1
[PATCH v3 0/5] cmd: bind allow to bind driver with driver_data
- fix the bind command - add a bind command test - add bind command documentation Changes in v3: - fix typo - add bind/unbind parameters description and how to find them Changes in v2: - add a bind command test - add bind command documentation in doc/driver/model/bind.rst - simplify patch 1 by using lists_bind_fdt() Patrice Chotard (5): cmd: bind: allow to bind driver with driver data sandbox: phy: add driver_data for bind test cmd sandbox: dts: Add compatible string for bind-test node test/py: Update test_bind doc: add bind/unbind command documentation arch/sandbox/dts/test.dts | 1 + cmd/bind.c | 5 ++-- doc/driver-model/bind.rst | 49 ++ doc/driver-model/index.rst | 1 + drivers/phy/sandbox-phy.c | 18 +- test/py/tests/test_bind.py | 18 +++--- 6 files changed, 80 insertions(+), 12 deletions(-) create mode 100644 doc/driver-model/bind.rst -- 2.17.1
Re: [PATCH v2 5/7] spl: fit: enable signing a generated u-boot.itb
Heiko, This patch will cause build fail on sandbox_spl_defconfig: dtc: option requires an argument -- 'p' Thanks, - Kever On 2020/4/21 上午8:23, Heiko Stuebner wrote: From: Heiko Stuebner With SPL_FIT_SIGNATURE enabled we will likely want a generated u-boot.itb to be signed and the key stores so that the spl can reach it. So add a SPL_FIT_SIGNATURE_KEY_DIR option and suitable hooks into the Makefile to have mkimage sign the .itb and store the used key into the spl dtb file. The added dependencies should make sure that the u-boot.itb gets generated before the spl-binary gets build, so that there is the necessary space for the key to get included. Signed-off-by: Heiko Stuebner Reviewed-by: Philipp Tomsich --- Kconfig | 8 Makefile | 11 ++- 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/Kconfig b/Kconfig index 4051746319..15a783a67d 100644 --- a/Kconfig +++ b/Kconfig @@ -451,6 +451,14 @@ config SPL_FIT_SIGNATURE select SPL_RSA_VERIFY select IMAGE_SIGN_INFO +config SPL_FIT_SIGNATURE_KEY_DIR + string "key directory for signing U-Boot FIT image" + depends on SPL_FIT_SIGNATURE + default "keys" + help + The directory to give to mkimage to retrieve keys from when + generating a signed U-Boot FIT image. + config SPL_LOAD_FIT bool "Enable SPL loading U-Boot as a FIT (basic fitImage features)" select SPL_FIT diff --git a/Makefile b/Makefile index 26307fd4a6..8e7a7cb50e 100644 --- a/Makefile +++ b/Makefile @@ -1394,6 +1394,14 @@ MKIMAGEFLAGS_u-boot.itb = else MKIMAGEFLAGS_u-boot.itb = -E endif +ifdef CONFIG_SPL_FIT_SIGNATURE +ifdef CONFIG_SPL_OF_CONTROL +MKIMAGEFLAGS_u-boot.itb += -K dts/dt-spl.dtb -r +ifneq ($(CONFIG_SPL_FIT_SIGNATURE_KEY_DIR),"") +MKIMAGEFLAGS_u-boot.itb += -k $(CONFIG_SPL_FIT_SIGNATURE_KEY_DIR) +endif +endif +endif u-boot.itb: u-boot-nodtb.bin \ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \ @@ -1913,7 +1921,8 @@ spl/u-boot-spl.bin: spl/u-boot-spl spl/u-boot-spl: tools prepare \ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \ - $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb) + $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb) \ + $(if $(CONFIG_SPL_FIT_GENERATOR),u-boot.itb FORCE) $(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.spl all spl/sunxi-spl.bin: spl/u-boot-spl
Re: [PATCH v3 0/9] rockchip: rk3328: sync dts and add ROC-RK3328-CC board
On 2020/4/27 下午2:52, Chen-Yu Tsai wrote:
From: Chen-Yu Tsai
Hi everyone,
This is v3 of my ROC-RK3328-CC series. Changes from v2 are mainly
fixing USB functionality on RK3328 in U-boot. This includes restoring
the U-Boot specific "hnp-srp-disable" property for dwc2, moving the
dwc2 device node after the ehci/ohci ones, and making vbus controllable
and tied only to the XHCI controller. Because of this, I dropped review
and tested tags from the DTS sync and new board patches.
Changes from v1 are mainly dropping the custom board target, and dealing
with the pinmuxing through proper use of DM regulators / GPIO / pinctrl
in SPL.
This series adds proper support for Firefly / Libre Computer ROC-RK3328-CC
single board computer.
The ROC-RK3328-CC from Firefly and Libre Computer Project is a credit
card size development board based on the Rockchip RK3328 SoC, with:
- 1/2/4 GB DDR4 DRAM
- eMMC connector for optional module
- micro SD card slot
- 1 x USB 3.0 host port
- 2 x USB 2.0 host port
- 1 x USB 2.0 OTG port
- HDMI video output
- TRRS connector with audio and composite video output
- gigabit Ethernet
- consumer IR receiver
- debug UART pins
Originally I started with Loic's patches, and syncing the device tree
files from Linux. That didn't get very far, with SPL failing to detect
the SD card. Examining the schematics and internal state of GRF and
GPIOs, I realized that the logic for the SD card power enable switch
is opposite that of what the SD card controller's SDMMC0_PWREN pin
would use. Instead, directly using the GPIO is required.
To deal with this, DM regulator and GPIO are enabled in SPL, and
various device nodes are marked with u-boot,dm-spl to have them work.
pinctrl properties are not stripped, so as to have the SDMMC0_PWREN
pin muxed over to GPIO.
Along the way, there are some clean-ups of existing dts files, moving
U-boot only features to -u-boot.dtsi files, and then a wholesale sync
from Linux. Only boards already existing in U-boot are synced. DT
binding header files are synced separately as there is already one
patch floating around. The DT sync also includes clean-up changes only
recently posted, and likely won't make it in for at least a few weeks.
Please have a look, and test if possible. I cc-ed a couple people that
showed interest in this board on mailing lists recently.
Regards
ChenYu
Chen-Yu Tsai (9):
rockchip: dts: rk3328-evb: Move vcc5v0-host-xhci-drv to -u-boot.dtsi
rockchip: dts: rk3328-evb: Move gmac2io related nodes to -u-boot.dtsi
rockchip: dts: rk3328: Move OTG node's hnp-srp-disable to
rk3328-u-boot.dtsi
dt-bindings: clock: rk3328: sync from upstream Linux kernel
dt-bindings: power: rk3328-power: sync from upstream Linux kernel
rockchip: rk3328: Disable generic PHY support
rockchip: dts: rk3328: Sync device tree files from Linux
rockchip: rk3328: Add support for ROC-RK3328-CC board
rockchip: dts: rock64: Fix XHCI usage
arch/arm/dts/Makefile |1 +
arch/arm/dts/rk3328-evb-u-boot.dtsi | 39 +
arch/arm/dts/rk3328-evb.dts | 220 +--
arch/arm/dts/rk3328-roc-cc-u-boot.dtsi| 47 +
.../{rk3328-rock64.dts => rk3328-roc-cc.dts} | 135 +-
arch/arm/dts/rk3328-rock64-u-boot.dtsi| 11 +
arch/arm/dts/rk3328-rock64.dts| 132 +-
arch/arm/dts/rk3328-u-boot.dtsi |4 +
arch/arm/dts/rk3328.dtsi | 1415 +++--
board/rockchip/evb_rk3328/MAINTAINERS |7 +
configs/evb-rk3328_defconfig |1 -
...3328_defconfig => roc-cc-rk3328_defconfig} | 19 +-
configs/rock64-rk3328_defconfig |1 -
doc/README.rockchip |4 +-
include/dt-bindings/clock/rk3328-cru.h| 212 +--
include/dt-bindings/power/rk3328-power.h | 19 +
16 files changed, 1514 insertions(+), 753 deletions(-)
create mode 100644 arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
copy arch/arm/dts/{rk3328-rock64.dts => rk3328-roc-cc.dts} (68%)
copy configs/{rock64-rk3328_defconfig => roc-cc-rk3328_defconfig} (81%)
create mode 100644 include/dt-bindings/power/rk3328-power.h
Applied to u-boot-rockchip/master,
Thanks,
- Kever
Re: [PATCH v3 8/9] rockchip: rk3328: Add support for ROC-RK3328-CC board
On 2020/4/27 下午2:52, Chen-Yu Tsai wrote: --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -5,6 +5,13 @@ F: board/rockchip/evb_rk3328 F: include/configs/evb_rk3328.h F: configs/evb-rk3328_defconfig +ROC-RK3328-CC +M: Loic Devulder +M: Chen-Yu Tsai +S: Maintained +F: configs/roc-rk3328-cc_defconfig This need to be roc-cc-rk3328_defconfig, or else there will be warning: WARNING: no status info for 'roc-cc-rk3328' WARNING: no maintainers for 'roc-cc-rk3328' I will update it before merge. Thanks, - Kever +F: arch/arm/dts/rk3328-roc-cc-u-boot.dtsi +
Re: [PATCH] rk3399: Enable SF distro bootcmd
Hi Jagan, Previous patch will be drop and replace by this one, right? rockchip: Enable SF distro bootcmd On 2020/4/30 上午3:39, Jagan Teki wrote: Enable SPI flash(SF) distro boot command in rk3399. This distro boot will read the boot script at specific location at the flash and start sourcing the same. Included the SF device at the last of the target devices list since all the rest of the devices on the list have more possibility to boot the distribution due to the size of the SPI flash is concern. Cc: Kever Yang Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Thanks, - Kever --- include/configs/rk3399_common.h | 1 + include/configs/rockchip-common.h | 15 +++ 2 files changed, 16 insertions(+) diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 01a9174bd2..f0ae6e67a7 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -60,6 +60,7 @@ #endif #include +#include #define CONFIG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index b55e09a9ca..bf8c60d6dd 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -41,11 +41,26 @@ #define BOOT_TARGET_DHCP(func) #endif +#if CONFIG_IS_ENABLED(CMD_SF) + #define BOOT_TARGET_SF(func)func(SF, sf, 0) +#else + #define BOOT_TARGET_SF(func) +#endif + +#ifdef CONFIG_ROCKCHIP_RK3399 +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_MMC(func) \ + BOOT_TARGET_USB(func) \ + BOOT_TARGET_PXE(func) \ + BOOT_TARGET_DHCP(func) \ + BOOT_TARGET_SF(func) +#else #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_MMC(func) \ BOOT_TARGET_USB(func) \ BOOT_TARGET_PXE(func) \ BOOT_TARGET_DHCP(func) +#endif #ifdef CONFIG_ARM64 #define ROOT_UUID "B921B045-1DF0-41C3-AF44-4C6F280D3FAE;\0"
Re: [PATCH 5/8] configs: slimbootloader: Add x86_64 slimbootloader config
On Mon, Apr 27, 2020 at 4:32 AM Simon Glass wrote: > > Hi Aiden, > > On Tue, 21 Apr 2020 at 18:45, wrote: > > > > From: Aiden Park > > > > Add slimbootloader-x86_64_defconfig for 64-bit slimbootloader board. > > > > Signed-off-by: Aiden Park > > --- > > configs/slimbootloader-x86_64_defconfig | 24 > > 1 file changed, 24 insertions(+) > > create mode 100644 configs/slimbootloader-x86_64_defconfig > > How about slimbootloader64? > > We always know it is x86. Agreed with Simon, Aiden, please also make sure the defconfig file is written with all options in the correct order. You can do it like this: $ make slimbootloader64_defconfig $ make savedefconfig $ cp defconfig configs/slimbootloader64_defconfig Regards, Bin
Re: [PATCH 1/8] x86: Add a new X86_RUN_64BIT_ONLY to Kconfig
Hi Aiden, On Wed, Apr 29, 2020 at 1:44 PM Park, Aiden wrote: > > Hi Simon, > > > -Original Message- > > From: Simon Glass > > Sent: Sunday, April 26, 2020 1:16 PM > > To: Park, Aiden > > Cc: Bin Meng ; U-Boot Mailing List > b...@lists.denx.de> > > Subject: Re: [PATCH 1/8] x86: Add a new X86_RUN_64BIT_ONLY to Kconfig > > > > Hi Aiden, > > > > On Tue, 21 Apr 2020 at 18:45, wrote: > > > > > > From: Aiden Park > > > > > > This will build U-Boot as a pure 64-bit binary with no SPL. > > > It can be used with a pre-stage boot firmware which has already done > > > 16-bit, 32-bit and 64-bit init. > > > > > > Signed-off-by: Aiden Park > > > --- > > > arch/x86/Kconfig | 8 > > > 1 file changed, 8 insertions(+) > > > > > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index > > > c8eae24c07..89add17e69 100644 > > > --- a/arch/x86/Kconfig > > > +++ b/arch/x86/Kconfig > > > @@ -40,6 +40,14 @@ config X86_RUN_64BIT > > > runs through the 16-bit and 32-bit init, then switches to 64-bit > > > mode and jumps to U-Boot proper. > > > > > > +config X86_RUN_64BIT_ONLY > > > > Perhaps X86_RUN_64BIT_NO_SPL? Bin might hav a better idea. > > > I considered X64_RUN_64BIT_NO_SPL, X64_RUN_64BIT_PURE and > X64_RUN_64BIT_NATIVE. > Hi Bin, can you recommend better naming? Cannot figure out a better name :) Let's use it. Reviewed-by: Bin Meng Regards, Bin
Re: [PATCH 8/8] doc: slimbootloader: Update 64-bit build instruction
On Wed, Apr 22, 2020 at 8:45 AM wrote: > > From: Aiden Park > > Add steps to build 64-bit Slim Bootloader and U-Boot. > > Signed-off-by: Aiden Park > --- > doc/board/intel/slimbootloader.rst | 29 + > 1 file changed, 29 insertions(+) > Reviewed-by: Bin Meng
Re: [PATCH v3 8/9] rockchip: rk3328: Add support for ROC-RK3328-CC board
On Thu, Apr 30, 2020 at 5:08 PM Kever Yang wrote: > > > On 2020/4/27 下午2:52, Chen-Yu Tsai wrote: > > --- a/board/rockchip/evb_rk3328/MAINTAINERS > > +++ b/board/rockchip/evb_rk3328/MAINTAINERS > > @@ -5,6 +5,13 @@ F: board/rockchip/evb_rk3328 > > F: include/configs/evb_rk3328.h > > F: configs/evb-rk3328_defconfig > > > > +ROC-RK3328-CC > > +M: Loic Devulder > > +M: Chen-Yu Tsai > > +S: Maintained > > +F: configs/roc-rk3328-cc_defconfig > > This need to be roc-cc-rk3328_defconfig, or else there will be warning: > > WARNING: no status info for 'roc-cc-rk3328' > WARNING: no maintainers for 'roc-cc-rk3328' > > I will update it before merge. Sorry about that, and thanks for fixing it up. ChenYu > Thanks, > > - Kever > > > +F: arch/arm/dts/rk3328-roc-cc-u-boot.dtsi > > + > >
[RFC PATCH 0/2] Move FSP configuration to devicetree
This patch series moves the configuration of FPS-S and FSP-M for Apollo Lake based SoCs from the code to the devicetree. In order to make the FSP configuration easy to extend and maintain new binding structs for FSP-M and FSP-S are introduced. These structs contain the information of which devicetree settings need to be copied to which offset in the FSP config structure. The actual code handling these structs is rather small, and generic for both FSP-S and FSP-M. This patch series replaces the previous sent patches: "arch: x86: apl: Read FSP-M configuration from device-tree" [1] "Move FSP-S configuration to device-tree" [2] Changes to [1] and [2]: - No default settings within U-Boot, the default settings in FSP are used directly - The code for copying the data was simplified, and the information of what needs to be copied was moved to newly introduced structures [1]: https://lists.denx.de/pipermail/u-boot/2020-April/405852.html [2]: https://lists.denx.de/pipermail/u-boot/2020-April/406590.html Bernhard Messerklinger (2): arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled arch: x86: apl: Use devicetree for FSP configuration arch/x86/cpu/apollolake/Makefile |1 + arch/x86/cpu/apollolake/fsp_bindings.c| 2096 + arch/x86/cpu/apollolake/fsp_m.c | 164 +- arch/x86/cpu/apollolake/fsp_s.c | 404 +--- arch/x86/dts/chromebook_coral.dts | 72 +- .../asm/arch-apollolake/fsp/fsp_m_upd.h | 168 ++ .../asm/arch-apollolake/fsp/fsp_s_upd.h | 202 ++ .../asm/arch-apollolake/fsp_bindings.h| 74 + .../fsp/fsp2/apollolake/fsp-m.txt | 320 +++ .../fsp/fsp2/apollolake/fsp-s.txt | 483 10 files changed, 3432 insertions(+), 552 deletions(-) create mode 100644 arch/x86/cpu/apollolake/fsp_bindings.c create mode 100644 arch/x86/include/asm/arch-apollolake/fsp_bindings.h create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt -- 2.26.0
[RFC PATCH 1/2] arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/fsp_s.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 17cf1682ad..8f1d6f3008 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -327,16 +327,17 @@ int fsps_update_config(struct udevice *dev, ulong
rom_offset,
{
struct fsp_s_config *cfg = &upd->config;
struct apl_config *apl;
+#ifdef CONFIG_HAVE_VBT
struct binman_entry vbt;
- void *buf;
+ void *vbt_buf;
int ret;
ret = binman_entry_find("intel-vbt", &vbt);
if (ret)
return log_msg_ret("Cannot find VBT", ret);
vbt.image_pos += rom_offset;
- buf = malloc(vbt.size);
- if (!buf)
+ vbt_buf = malloc(vbt.size);
+ if (!vbt_buf)
return log_msg_ret("Alloc VBT", -ENOMEM);
/*
@@ -344,16 +345,13 @@ int fsps_update_config(struct udevice *dev, ulong
rom_offset,
* memory-mapped SPI at present.
*/
bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
- memcpy(buf, (void *)vbt.image_pos, vbt.size);
+ memcpy(vbt_buf, (void *)vbt.image_pos, vbt.size);
bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
- if (*(u32 *)buf != VBT_SIGNATURE)
+ if (*(u32 *)vbt_buf != VBT_SIGNATURE)
return log_msg_ret("VBT signature", -EINVAL);
- cfg->graphics_config_ptr = (ulong)buf;
- apl = malloc(sizeof(*apl));
- if (!apl)
- return log_msg_ret("config", -ENOMEM);
- get_config(dev, apl);
+ cfg->graphics_config_ptr = (ulong)vbt_buf;
+#endif
cfg->ish_enable = 0;
cfg->enable_sata = 0;
--
2.26.0
Re: [RFC PATCH v2 0/2] Move FSP-S configuration to device-tree
Hi Bin, Simon, >This patch series moves the configuration of FPS-S for Apollo Lake >based SoCs from the code to the device-tree. > >This is similar to the previous patch series for FSP-M. >If wanted, I can also send FSP-M and FSP-S patch as a single series. > Please drop this series. This series is superseded by: "Move FSP configuration to devicetree" [1] [1]: https://lists.denx.de/pipermail/u-boot/2020-April/409505.html >Changes in v2: >Remove FSP-M binding file > >Bernhard Messerklinger (2): > arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled > arch: x86: apl: Read FSP-S configuration from device-tree > > arch/x86/cpu/apollolake/fsp_s.c | 1084 >+++-- > arch/x86/dts/chromebook_coral.dts | 35 +- > .../asm/arch-apollolake/fsp/fsp_s_upd.h | 268 > .../fsp/fsp2/apollolake/fsp-s.txt | 485 > 4 files changed, 1497 insertions(+), 375 deletions(-) > create mode 100644 >doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt > >-- >2.26.0 > > Regards, Bernhard
[PATCH] dt-bindings: vendor-prefixes: Add U-Boot bootloader prefix
List U-Boot project in vendor prefixes. For more information take a look at: https://en.wikipedia.org/wiki/Das_U-Boot Source code is available here: https://gitlab.denx.de/u-boot/u-boot Signed-off-by: Michal Simek --- The patch was created based on discussion with Rob https://lore.kernel.org/linux-devicetree/CAL_Jsq+ehJSK7sjqmKtWOVjr-QZ3LDB+ywCO85uF8WJ+cB=a...@mail.gmail.com/ --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index d3891386d671..2becc5ced47c 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1045,6 +1045,8 @@ patternProperties: description: Tyan Computer Corporation "^u-blox,.*": description: u-blox + "^u-boot,.*": +description: U-Boot bootloader "^ucrobotics,.*": description: uCRobotics "^ubnt,.*": -- 2.26.2
Re: [PATCH v4 1/9] x86: fsp: Allow skipping init code when chain loading
On Sun, Apr 26, 2020 at 11:13 PM Simon Glass wrote: > > It is useful to be able to boot the same x86 image on a device with or > without a first-stage bootloader. For example, with chromebook_coral, it > is helpful for testing to be able to boot the same U-Boot (complete with > FSP) on bare metal and from coreboot. It allows checking of things like > CPU speed, comparing registers, ACPI tables and the like. > > When U-Boot is not the first-stage bootloader much of this code is not > needed and can break booting. Add checks for this to the FSP code. > > Rather than checking for the amount of available SDRAM, just use 1GB in > this situation, which should be safe. Using 2GB may run into a memory > hole on some SoCs. > > Signed-off-by: Simon Glass > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > arch/x86/lib/fsp/fsp_dram.c | 8 > arch/x86/lib/fsp/fsp_graphics.c | 3 +++ > arch/x86/lib/fsp2/fsp_dram.c| 10 ++ > arch/x86/lib/fsp2/fsp_init.c| 2 +- > 4 files changed, 22 insertions(+), 1 deletion(-) > Reviewed-by: Bin Meng
Re: [RFC PATCH v3] arch: x86: apl: Read FSP-M configuration from device-tree
Hi Bin, Simon, > >Move FSP-M configuration to the device-tree like it's already done >for >other SoCs (Baytrail). > >Signed-off-by: Bernhard Messerklinger > >--- >With this patch I moved the FSP-M configuration to the device-tree >based >on the Baytrail boards. > >Changes in v3: >Added doc binding file >Added fspm prefix to some variables > >Changes in v2: >Added commit notes > ... Please drop this series. This series is superseded by: "Move FSP configuration to devicetree" [1] [1]: https://lists.denx.de/pipermail/u-boot/2020-April/409505.html Regards, Bernhard
Re: [PATCH v3 5/5] doc: add bind/unbind command documentation
On 30.04.20 10:52, Patrice Chotard wrote:
> Add documentation in doc/drivel-model for the bind/unbind command.
> Part of this documentation is extracted from original patch commit
> message:
> commit 49c752c93a78 ("cmd: Add bind/unbind commands to bind a device to a
> driver from the command line")
>
> Signed-off-by: Patrice Chotard
> ---
>
> Changes in v3:
> - fix typo
> - add bind/unbind parameters description and how to find them
>
> Changes in v2: None
>
> doc/driver-model/bind.rst | 49 ++
> doc/driver-model/index.rst | 1 +
> 2 files changed, 50 insertions(+)
> create mode 100644 doc/driver-model/bind.rst
>
> diff --git a/doc/driver-model/bind.rst b/doc/driver-model/bind.rst
> new file mode 100644
> index 00..dfe8fd57dd
> --- /dev/null
> +++ b/doc/driver-model/bind.rst
> @@ -0,0 +1,49 @@
> +.. SPDX-License-Identifier: GPL-2.0+
> +.. sectionauthor:: Patrice Chotard
> +
> +Binding/unbinding a driver
> +=
The title underline is too short.
Please, use 'make htmldocs' for testing.
Best regards
Heinrich
> +
> +This document aims to describe the bind and unbind commands.
> +
> +For debugging purpose, it should be useful to bind or unbind a driver from
> +the U-boot command line.
> +
> +The unbind command calls the remove device driver callback and unbind the
> +device from its driver.
> +
> +The bind command binds a device to its driver.
> +
> +In some cases it can be useful to be able to bind a device to a driver from
> +the command line.
> +The obvious example is for versatile devices such as USB gadget.
> +Another use case is when the devices are not yet ready at startup and
> +require some setup before the drivers are bound (ex: FPGA which bitsream is
> +fetched from a mass storage or ethernet)
> +
> +usage:
> +
> +bind
> +bind
> +
> +unbind
> +unbind
> +unbind
> +
> +Where:
> + - is the node's device tree path
> + - is one of the class available in the list given by the "dm uclass"
> + command or first column of "dm tree" command.
> + - is the index of the parent's node (second column of "dm tree"
> output).
> + - is the driver name to bind given by the "dm drivers" command or
> the by
> + the fourth column of "dm tree" output.
> +
> +example:
> +
> +bind usb_dev_generic 0 usb_ether
> +unbind usb_dev_generic 0 usb_ether
> +or
> +unbind eth 1
> +
> +bind /ocp/omap_dwc3@4838/usb@4839 usb_ether
> +unbind /ocp/omap_dwc3@4838/usb@4839
> diff --git a/doc/driver-model/index.rst b/doc/driver-model/index.rst
> index b9df221627..37ef3721df 100644
> --- a/doc/driver-model/index.rst
> +++ b/doc/driver-model/index.rst
> @@ -6,6 +6,7 @@ Driver Model
> .. toctree::
> :maxdepth: 2
>
> + bind
> debugging
> design
> ethernet
>
Re: [PATCH v4 3/9] x86: cpu: Skip init code when chain loading
On Sun, Apr 26, 2020 at 11:13 PM Simon Glass wrote: > > When U-Boot is not the first-stage bootloader the interrupt and cache init > must be skipped, as well as init for various peripherals. Update the code > to add checks for this. > > Signed-off-by: Simon Glass > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: > - Drop the other check in interrupt_init() which is not needed now > > arch/x86/cpu/cpu.c| 4 +++- > arch/x86/cpu/i386/interrupt.c | 6 -- > arch/x86/lib/init_helpers.c | 3 +++ > 3 files changed, 10 insertions(+), 3 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH v4 2/9] x86: apl: Skip init code when chain loading
On Sun, Apr 26, 2020 at 11:13 PM Simon Glass wrote: > > When U-Boot is not the first-stage bootloader the FSP-S init must be > skipped. Update it to add a check. > > Signed-off-by: Simon Glass > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > arch/x86/cpu/apollolake/fsp_s.c | 2 ++ > 1 file changed, 2 insertions(+) > Reviewed-by: Bin Meng
Re: [PATCH v4 5/9] board: Add a gd flag for chain loading
On Sun, Apr 26, 2020 at 11:13 PM Simon Glass wrote: > > When U-Boot is run from another boot loader, much of the low-level init > needs to be skipped. > > Add a flag for this and adjust ll_boot_init() to use it. > > Signed-off-by: Simon Glass > --- > > Changes in v4: > - Rename flag to GD_FLG_SKIP_LL_INIT > > Changes in v3: > - Add a new patch with a gd flag for chain loading > > Changes in v2: None > > include/asm-generic/global_data.h | 1 + > include/init.h| 2 +- > 2 files changed, 2 insertions(+), 1 deletion(-) > Reviewed-by: Bin Meng
Re: [PATCH v4 7/9] x86: Add a way to detect running from coreboot
On Sun, Apr 26, 2020 at 11:13 PM Simon Glass wrote: > > If U-Boot is running from coreboot we need to skip low-level init. Add > an way to detect this and to set the gd flag. > > Signed-off-by: Simon Glass > --- > > Changes in v4: > - Rename flag to GD_FLG_SKIP_LL_INIT > - Split this patch into two > > Changes in v3: > - Add new patch to detect running from coreboot > > Changes in v2: None > > arch/x86/cpu/i386/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > Reviewed-by: Bin Meng
Re: [PATCH v4 6/9] x86: Move coreboot-table detection into common code
Hi Simon,
On Sun, Apr 26, 2020 at 11:13 PM Simon Glass wrote:
>
> To support detecting booting from coreboot, move the code which locates
> the coreboot tables into a common place. Adjust the algorithm slightly to
> use a word comparison instead of string, since it is faster.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v4:
> - Add new patch to move coreboot-table detection into common code
>
> Changes in v3: None
> Changes in v2: None
>
> arch/x86/cpu/coreboot/tables.c | 24 +---
> arch/x86/cpu/i386/cpu.c| 25 +
> arch/x86/include/asm/coreboot_tables.h | 7 +++
> 3 files changed, 41 insertions(+), 15 deletions(-)
>
> diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c
> index 37e0424b5e..0f04c4f8e9 100644
> --- a/arch/x86/cpu/coreboot/tables.c
> +++ b/arch/x86/cpu/coreboot/tables.c
> @@ -115,20 +115,11 @@ __weak void cb_parse_unhandled(u32 tag, unsigned char
> *ptr)
>
> static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
> {
> + unsigned char *ptr = addr;
This variable is not necessary
> struct cb_header *header;
> - unsigned char *ptr = (unsigned char *)addr;
> int i;
>
> - for (i = 0; i < len; i += 16, ptr += 16) {
> - header = (struct cb_header *)ptr;
> - if (!strncmp((const char *)header->signature, "LBIO", 4))
> - break;
> - }
> -
> - /* We walked the entire space and didn't find anything. */
> - if (i >= len)
> - return -1;
> -
> + header = (struct cb_header *)ptr;
and assign addr to header directly
> if (!header->table_bytes)
> return 0;
>
> @@ -231,10 +222,13 @@ static int cb_parse_header(void *addr, int len, struct
> sysinfo_t *info)
>
> int get_coreboot_info(struct sysinfo_t *info)
> {
> - int ret = cb_parse_header((void *)0x, 0x1000, info);
> + long addr;
> + int ret;
>
> - if (ret != 1)
> - ret = cb_parse_header((void *)0x000f, 0x1000, info);
> + addr = locate_coreboot_table();
> + if (addr < 0)
> + return addr;
> + ret = cb_parse_header((void *)addr, 0x1000, info);
>
> - return (ret == 1) ? 0 : -1;
> + return ret == 1 ? 0 : -ENOENT;
> }
> diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
> index c8da7f10e9..e52fd686d9 100644
> --- a/arch/x86/cpu/i386/cpu.c
> +++ b/arch/x86/cpu/i386/cpu.c
> @@ -447,6 +447,31 @@ int x86_cpu_init_f(void)
> return 0;
> }
>
> +long detect_coreboot_table_at(ulong start, ulong size)
> +{
> + u32 *ptr, *end;
> +
> + size /= 4;
> + for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
> + if (*ptr == 0x4f49424c) /* "LBIO" */
> + return (long)ptr;
> + }
> +
> + return -ENOENT;
> +}
> +
> +long locate_coreboot_table(void)
> +{
> + long addr;
> +
> + /* We look for LBIO in the first 4K of RAM and again at 60KB */
It should be 960KB
> + addr = detect_coreboot_table_at(0x0, 0x1000);
> + if (addr < 0)
> + addr = detect_coreboot_table_at(0xf, 0x1000);
> +
> + return addr;
> +}
> +
Looks good otherwise:
Reviewed-by: Bin Meng
Regards,
Bin
Re: [PATCH v4 4/9] pci: Avoid auto-config when chain loading
On Sun, Apr 26, 2020 at 11:13 PM Simon Glass wrote: > > When U-Boot is not the first-stage bootloader we don't want to > re-configure the PCI devices, since this has already been done. Add a > check to avoid this. > > Signed-off-by: Simon Glass > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: > - Drop patch 'dm: Avoid initing built-in devices when chain loading' > > drivers/pci/pci-uclass.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH v4 8/9] x86: Use the existing stack when chain-loading
On Sun, Apr 26, 2020 at 11:13 PM Simon Glass wrote: > > With chromebook_coral we normally run TPL->SPL->U-Boot. This is the > 'bare metal' case. > > When running from coreboot we put u-boot.bin in the RW_LEGACY portion > of the image, e.g. with: > >cbfstool image-coral.serial.bin add-flat-binary -r RW_LEGACY \ > -f /tmp/b/chromebook_coral/u-boot.bin -n altfw/u-boot \ > -c lzma -l 0x111 -e 0x111 > > In this case U-Boot is run from coreboot (actually Depthcharge, its > payload) so we cannot access CAR. Use the existing stack instead. > > Signed-off-by: Simon Glass > --- > > Changes in v4: > - Update to use locate_coreboot_table() > > Changes in v3: None > Changes in v2: None > > arch/x86/cpu/start_from_spl.S | 16 ++-- > 1 file changed, 14 insertions(+), 2 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH v4 9/9] x86: Add documentation for the chain-load feature
On Sun, Apr 26, 2020 at 11:13 PM Simon Glass wrote: > > Add a few notes about this feature, which is aimed for development. > > Signed-off-by: Simon Glass > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > doc/arch/x86.rst | 28 > 1 file changed, 28 insertions(+) > Reviewed-by: Bin Meng
'ls' or 'ext4ls' misses files on FS
HI! Did I miss anything myself? U-Boot: => ext4ls mmc 0:8 /home/root 4096 . 4096 .. 4096 .node_app_slot Linux: # ls -la /home/root/ total 76 drwxr-xr-x 3 root root 4096 Apr 30 09:27 . drwxr-xr-x 4 root root 4096 Apr 30 09:11 .. -rw--- 1 root root 4188 Apr 30 09:11 .bash_history drwxr-xr-x 2 root root 4096 Mar 8 2016 .node_app_slot -rw--- 1 root root24 Apr 30 09:27 .python-history -rw--- 1 root root 1250 Apr 29 2016 .viminfo -rw-r--r-- 1 root root 14054 Apr 29 2016 crashlog_1.tar.gz -rw-r--r-- 1 root root 14022 Apr 29 2016 crashlog_2.tar.gz -rw-r--r-- 1 root root 13972 Apr 29 2016 crashlog_3.tar.gz -- With Best Regards, Andy Shevchenko
Re: 'ls' or 'ext4ls' misses files on FS
On Thu, Apr 30, 2020 at 12:34 PM Andy Shevchenko wrote: > > HI! > > Did I miss anything myself? U-Boot v2020.04 > U-Boot: > => ext4ls mmc 0:8 /home/root >4096 . >4096 .. >4096 .node_app_slot > > Linux: (Some v3.10.98 based BSP) > # ls -la /home/root/ > total 76 > drwxr-xr-x 3 root root 4096 Apr 30 09:27 . > drwxr-xr-x 4 root root 4096 Apr 30 09:11 .. > -rw--- 1 root root 4188 Apr 30 09:11 .bash_history > drwxr-xr-x 2 root root 4096 Mar 8 2016 .node_app_slot > -rw--- 1 root root24 Apr 30 09:27 .python-history > -rw--- 1 root root 1250 Apr 29 2016 .viminfo > -rw-r--r-- 1 root root 14054 Apr 29 2016 crashlog_1.tar.gz > -rw-r--r-- 1 root root 14022 Apr 29 2016 crashlog_2.tar.gz > -rw-r--r-- 1 root root 13972 Apr 29 2016 crashlog_3.tar.gz > > -- > With Best Regards, > Andy Shevchenko -- With Best Regards, Andy Shevchenko
Re: [PATCH v3 5/5] doc: add bind/unbind command documentation
Hi Heinrich
On 4/30/20 11:31 AM, Heinrich Schuchardt wrote:
> On 30.04.20 10:52, Patrice Chotard wrote:
>> Add documentation in doc/drivel-model for the bind/unbind command.
>> Part of this documentation is extracted from original patch commit
>> message:
>> commit 49c752c93a78 ("cmd: Add bind/unbind commands to bind a device to a
>> driver from the command line")
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> Changes in v3:
>> - fix typo
>> - add bind/unbind parameters description and how to find them
>>
>> Changes in v2: None
>>
>> doc/driver-model/bind.rst | 49 ++
>> doc/driver-model/index.rst | 1 +
>> 2 files changed, 50 insertions(+)
>> create mode 100644 doc/driver-model/bind.rst
>>
>> diff --git a/doc/driver-model/bind.rst b/doc/driver-model/bind.rst
>> new file mode 100644
>> index 00..dfe8fd57dd
>> --- /dev/null
>> +++ b/doc/driver-model/bind.rst
>> @@ -0,0 +1,49 @@
>> +.. SPDX-License-Identifier: GPL-2.0+
>> +.. sectionauthor:: Patrice Chotard
>> +
>> +Binding/unbinding a driver
>> +=
> The title underline is too short.
>
> Please, use 'make htmldocs' for testing.
Thanks for the tips
Patrice
>
> Best regards
>
> Heinrich
>
>> +
>> +This document aims to describe the bind and unbind commands.
>> +
>> +For debugging purpose, it should be useful to bind or unbind a driver from
>> +the U-boot command line.
>> +
>> +The unbind command calls the remove device driver callback and unbind the
>> +device from its driver.
>> +
>> +The bind command binds a device to its driver.
>> +
>> +In some cases it can be useful to be able to bind a device to a driver from
>> +the command line.
>> +The obvious example is for versatile devices such as USB gadget.
>> +Another use case is when the devices are not yet ready at startup and
>> +require some setup before the drivers are bound (ex: FPGA which bitsream is
>> +fetched from a mass storage or ethernet)
>> +
>> +usage:
>> +
>> +bind
>> +bind
>> +
>> +unbind
>> +unbind
>> +unbind
>> +
>> +Where:
>> + - is the node's device tree path
>> + - is one of the class available in the list given by the "dm
>> uclass"
>> + command or first column of "dm tree" command.
>> + - is the index of the parent's node (second column of "dm tree"
>> output).
>> + - is the driver name to bind given by the "dm drivers" command or
>> the by
>> + the fourth column of "dm tree" output.
>> +
>> +example:
>> +
>> +bind usb_dev_generic 0 usb_ether
>> +unbind usb_dev_generic 0 usb_ether
>> +or
>> +unbind eth 1
>> +
>> +bind /ocp/omap_dwc3@4838/usb@4839 usb_ether
>> +unbind /ocp/omap_dwc3@4838/usb@4839
>> diff --git a/doc/driver-model/index.rst b/doc/driver-model/index.rst
>> index b9df221627..37ef3721df 100644
>> --- a/doc/driver-model/index.rst
>> +++ b/doc/driver-model/index.rst
>> @@ -6,6 +6,7 @@ Driver Model
>> .. toctree::
>> :maxdepth: 2
>>
>> + bind
>> debugging
>> design
>> ethernet
>>
Re: [PATCH v2 1/2] arm: dts: bcm283x: Allow UARTs to work before relocation
Hi all, On 29/04/2020 22:11, Simon Glass wrote: > Hi Tom, > > On Wed, 15 Apr 2020 at 13:59, Tom Rini wrote: >> >> On Tue, Apr 14, 2020 at 08:23:10PM -0600, Simon Glass wrote: >>> Hi, >>> >>> On Sun, 22 Mar 2020 at 21:16, Simon Glass wrote: At present the pinctrl nodes are not enabled in pre-relocation U-Boot so the UARTs do not correctly select the pinconfig to enable the UART pins. Fix this so that the U-Boot banner is printed. This fixes serial output on rpi_3b_32b with the following config.txt options: enable_uart=1 gpu_freq=250 Signed-off-by: Simon Glass Fixes: 9821636b64 (bcm2835_pinctrl: Probe pre-reloc) --- Changes in v2: - Update commit message arch/arm/dts/bcm283x-u-boot.dtsi | 8 1 file changed, 8 insertions(+) >>> >>> Any thoughts on this series? At present all my lab tests fail. >> >> I don't know if the problem is my firmware is too old (and so works) or >> your firmware is too old (and so fails) or if there's some >> phase-of-the-moon problem. So while I'd like to know _why_ my 3B is >> fine and yours is not, we should just take this I suppose. > > It should not harm anything. > > For now I am unable to run rpi tests on mainline. > Sorry for being silent for such a long time. I'll have a look and provide a PR. Regards, Matthias
Re: [PATCH] rk3399: Enable SF distro bootcmd
On Thu, Apr 30, 2020 at 2:41 PM Kever Yang wrote: > > Hi Jagan, > > Previous patch will be drop and replace by this one, right? > > rockchip: Enable SF distro bootcmd Yes, I'll apply this via the spi tree since it has SF distro changes already.
Re: [PATCH v4 6/9] x86: Move coreboot-table detection into common code
Hi Simon,
On Thu, Apr 30, 2020 at 5:33 PM Bin Meng wrote:
>
> Hi Simon,
>
> On Sun, Apr 26, 2020 at 11:13 PM Simon Glass wrote:
> >
> > To support detecting booting from coreboot, move the code which locates
> > the coreboot tables into a common place. Adjust the algorithm slightly to
> > use a word comparison instead of string, since it is faster.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > Changes in v4:
> > - Add new patch to move coreboot-table detection into common code
> >
> > Changes in v3: None
> > Changes in v2: None
> >
> > arch/x86/cpu/coreboot/tables.c | 24 +---
> > arch/x86/cpu/i386/cpu.c| 25 +
> > arch/x86/include/asm/coreboot_tables.h | 7 +++
> > 3 files changed, 41 insertions(+), 15 deletions(-)
> >
> > diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c
> > index 37e0424b5e..0f04c4f8e9 100644
> > --- a/arch/x86/cpu/coreboot/tables.c
> > +++ b/arch/x86/cpu/coreboot/tables.c
> > @@ -115,20 +115,11 @@ __weak void cb_parse_unhandled(u32 tag, unsigned char
> > *ptr)
> >
> > static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
> > {
> > + unsigned char *ptr = addr;
>
> This variable is not necessary
No, I was wrong.
>
> > struct cb_header *header;
> > - unsigned char *ptr = (unsigned char *)addr;
> > int i;
> >
> > - for (i = 0; i < len; i += 16, ptr += 16) {
> > - header = (struct cb_header *)ptr;
> > - if (!strncmp((const char *)header->signature, "LBIO", 4))
> > - break;
> > - }
> > -
> > - /* We walked the entire space and didn't find anything. */
> > - if (i >= len)
> > - return -1;
> > -
> > + header = (struct cb_header *)ptr;
>
> and assign addr to header directly
Ignore this.
>
> > if (!header->table_bytes)
> > return 0;
> >
> > @@ -231,10 +222,13 @@ static int cb_parse_header(void *addr, int len,
> > struct sysinfo_t *info)
> >
> > int get_coreboot_info(struct sysinfo_t *info)
> > {
> > - int ret = cb_parse_header((void *)0x, 0x1000, info);
> > + long addr;
> > + int ret;
> >
> > - if (ret != 1)
> > - ret = cb_parse_header((void *)0x000f, 0x1000, info);
> > + addr = locate_coreboot_table();
> > + if (addr < 0)
> > + return addr;
> > + ret = cb_parse_header((void *)addr, 0x1000, info);
> >
> > - return (ret == 1) ? 0 : -1;
> > + return ret == 1 ? 0 : -ENOENT;
> > }
> > diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
> > index c8da7f10e9..e52fd686d9 100644
> > --- a/arch/x86/cpu/i386/cpu.c
> > +++ b/arch/x86/cpu/i386/cpu.c
> > @@ -447,6 +447,31 @@ int x86_cpu_init_f(void)
> > return 0;
> > }
> >
> > +long detect_coreboot_table_at(ulong start, ulong size)
> > +{
> > + u32 *ptr, *end;
> > +
> > + size /= 4;
> > + for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
> > + if (*ptr == 0x4f49424c) /* "LBIO" */
> > + return (long)ptr;
> > + }
> > +
> > + return -ENOENT;
> > +}
> > +
> > +long locate_coreboot_table(void)
> > +{
> > + long addr;
> > +
> > + /* We look for LBIO in the first 4K of RAM and again at 60KB */
>
> It should be 960KB
I can fix this comments when applying.
>
> > + addr = detect_coreboot_table_at(0x0, 0x1000);
> > + if (addr < 0)
> > + addr = detect_coreboot_table_at(0xf, 0x1000);
> > +
> > + return addr;
> > +}
> > +
>
> Looks good otherwise:
>
> Reviewed-by: Bin Meng
Regards,
Bin
Re: [PATCH v4 0/9] x86: Improve support for chain-loading U-Boot
Hi Simon, On Sun, Apr 26, 2020 at 11:13 PM Simon Glass wrote: > > This little series adds a few checks into the code to allow better > operation when booting a build from a previous-state loader such as > coreboot. > > At present we have a 'coreboot' target but this runs very different code > from the bare-metal targets, such as coral. There is very little in common > between them. > > It is useful to be able to boot the same U-Boot on a device, with or > without a first-stage bootloader. For example, with chromebook_coral, it > is helpful for testing to be able to boot the same U-Boot (complete with > FSP) on bare metal and from coreboot. It allows checking of things like > CPU speed, comparing registers, ACPI tables and the like. > > This series allows U-Boot to detect that it ran from coreboot and > automatically do the right thing. > > This series makes the most important changes to allow the same u-boot.bin > for coral to boot after coreboot (by itself) or bare metal (via TPL->SPL). > > Changes in v4: > - Rename flag to GD_FLG_SKIP_LL_INIT > - Add new patch to move coreboot-table detection into common code > - Rename flag to GD_FLG_SKIP_LL_INIT > - Split this patch into two > - Update to use locate_coreboot_table() v4 series applied to u-boot-x86/master, thanks! Regards, Bin
Re: [PATCH v2 1/2] drivers: gpio: add broadcom iproc gpio driver support
On Wed, Apr 29, 2020 at 11:34 PM Simon Glass wrote:
>
> Hi Rayagonda,
>
> On Wed, 29 Apr 2020 at 00:21, Rayagonda Kokatanur
> wrote:
> >
> > Add gpio driver support for Broadcom iproc-based socs.
> >
> > Signed-off-by: Rayagonda Kokatanur
> > Signed-off-by: Sheetal Tigadoli
> > ---
> > drivers/gpio/Kconfig | 10 ++
> > drivers/gpio/Makefile | 1 +
> > drivers/gpio/iproc_gpio.c | 259 ++
> > 3 files changed, 270 insertions(+)
> > create mode 100644 drivers/gpio/iproc_gpio.c
> >
>
> Minor nits below
>
> > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> > index 2081520f42..a04b4af1b5 100644
> > --- a/drivers/gpio/Kconfig
> > +++ b/drivers/gpio/Kconfig
> > @@ -135,6 +135,16 @@ config IMX_RGPIO2P
> > help
> > This driver supports i.MX7ULP Rapid GPIO2P controller.
> >
> > +config IPROC_GPIO
> > + bool "Broadcom iProc GPIO driver(without pinconf)"
> > + default n
> > + help
> > + The Broadcom iProc based SoCs- Cygnus, NS2, NS3, NSP and Stingray,
> > + use same GPIO Controller IP hence this driver could be used for
> > all.
>
> use the same
>
> > +
> > + The Broadcom iProc based SoCs have multiple GPIO controllers and
> > only
> > + the always-ON GPIO controller (CRMU/AON) is supported by this
> > driver.
> > +
> > config HSDK_CREG_GPIO
> > bool "HSDK CREG GPIO griver"
> > depends on DM_GPIO
> > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> > index 7638259007..5dc5849477 100644
> > --- a/drivers/gpio/Makefile
> > +++ b/drivers/gpio/Makefile
> > @@ -19,6 +19,7 @@ obj-$(CONFIG_CORTINA_GPIO) += cortina_gpio.o
> > obj-$(CONFIG_INTEL_GPIO) += intel_gpio.o
> > obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o
> > obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o
> > +obj-$(CONFIG_IPROC_GPIO) += iproc_gpio.o
> > obj-$(CONFIG_KIRKWOOD_GPIO)+= kw_gpio.o
> > obj-$(CONFIG_KONA_GPIO)+= kona_gpio.o
> > obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o
> > diff --git a/drivers/gpio/iproc_gpio.c b/drivers/gpio/iproc_gpio.c
> > new file mode 100644
> > index 00..037f1a7de5
> > --- /dev/null
> > +++ b/drivers/gpio/iproc_gpio.c
> > @@ -0,0 +1,259 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2020 Broadcom
> > + */
> > +
> > +#include
> > +#include
> > +#include
>
> common.h always goes first
> > +#include
>
> put asm ones here
>
> > +#include
> > +#include
> > +#include
> > +#include
>
> put that just below dm.h
>
> See Include files here: https://www.denx.de/wiki/U-Boot/CodingStyle
>
> > +
> > +/*
> > + * There are five GPIO bank register. Each bank can configure max of 32
> > gpios.
> > + * BANK0 - gpios 0 to 31
> > + * BANK1 - gpios 32 to 63
> > + * BANK2 - gpios 64 to 95
> > + * BANK3 - gpios 96 to 127
> > + * BANK4 - gpios 128 to 150
> > + *
> > + * Offset difference between consecutive bank register is 0x200
> > + */
> > +#define IPROC_GPIO_PER_BANK 32
> > +#define IPROC_GPIO_SHIFT(n) ((n) % IPROC_GPIO_PER_BANK)
> > +#define IPROC_GPIO_BANK_OFFSET(n) (0x200 * ((n) / IPROC_GPIO_PER_BANK))
>
> Move this one to a function?
I will rewritten the macro, please have a look and let me know.
>
> > +#define IPROC_GPIO_REG(pin, reg)(IPROC_GPIO_BANK_OFFSET(pin) + (reg))
> > +
> > +#define IPROC_GPIO_DATA_IN_OFFSET 0x00
> > +#define IPROC_GPIO_DATA_OUT_OFFSET 0x04
> > +#define IPROC_GPIO_OUT_EN_OFFSET0x08
> > +
> > +struct iproc_gpio_pctrl_map {
>
> Needs struct comment talking about members
>
> > + u32 gpio_pin;
> > + u32 pctrl_pin;
> > + u32 npins;
> > + struct list_head node;
> > +};
> > +
> > +struct iproc_gpio_platdata {
>
> Needs struct comment talking about members
>
> > + struct udevice *pinctrl_dev;
> > + struct list_head gpiomap;
> > + /* register base for this bank */
> > + void __iomem *base;
> > + char *name;
> > + u32 ngpios;
> > +};
> > +
> > +/**
> > + * iproc_gpio_set_bit - set or clear one bit (corresponding to the GPIO
> > pin)
> > + * in a iproc GPIO register
> > + *
> > + * @iproc_gpio: Iproc GPIO device
> > + * @reg: register offset
> > + * @gpio: GPIO pin
> > + * @set: set or clear
> > + */
> > +static inline void iproc_gpio_set_bit(struct iproc_gpio_platdata *plat,
> > + u32 reg,
> > + u32 gpio, bool set)
> > +{
> > + u32 offset = IPROC_GPIO_REG(gpio, reg);
> > + u32 shift = IPROC_GPIO_SHIFT(gpio);
> > + u32 val;
> > +
> > + val = readl(plat->base + offset);
>
> You can use clrsetbits_le32()
>
> > + if (set)
> > + val |= BIT(shift);
> > + else
> > + val &= ~BIT(shift);
> > + writel(val, plat->base + offset);
> > +}
> > +
> > +static inline bool iproc_gpio_get_bit(struct iproc_gpio_platdata *plat,
> > +
Re: [PATCH] imx: spl: Fix build-time test for CONFIG_SPL_FS_FAT
Hello Jan, On Wed, 2020-04-29 at 19:23 +0200, Jan Kiszka wrote: > From: Jan Kiszka > > This was already changed in 0c3a9ed409a5 but apparently missed when > adding 9d86dbd9cf9d. I sent a very similar patch [1] as part of my "Fix spl_mmc_boot_mode() implementation for IMX" series [2] which tries to solve a few more issues in this particular function. [1]: http://patchwork.ozlabs.org/project/uboot/patch/20200423110753.51231-6-...@denx.de/ [2]: http://patchwork.ozlabs.org/project/uboot/list/?series=172241 > Signed-off-by: Jan Kiszka > --- > > Found by chance while working on other code. Not tested. > > arch/arm/mach-imx/spl.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c > index 49bb3b928d..bfdb3f3ada 100644 > --- a/arch/arm/mach-imx/spl.c > +++ b/arch/arm/mach-imx/spl.c > @@ -197,7 +197,7 @@ u32 spl_mmc_boot_mode(const u32 boot_device) > case SD1_BOOT: > case SD2_BOOT: > case SD3_BOOT: > -#if defined(CONFIG_SPL_FAT_SUPPORT) > +#if defined(CONFIG_SPL_FS_FAT) > return MMCSD_MODE_FS; > #else > return MMCSD_MODE_RAW; > @@ -206,7 +206,7 @@ u32 spl_mmc_boot_mode(const u32 boot_device) > case MMC1_BOOT: > case MMC2_BOOT: > case MMC3_BOOT: > -#if defined(CONFIG_SPL_FAT_SUPPORT) > +#if defined(CONFIG_SPL_FS_FAT) > return MMCSD_MODE_FS; > #elif defined(CONFIG_SUPPORT_EMMC_BOOT) > return MMCSD_MODE_EMMCBOOT; > -- > 2.16.4 Regards, -- Harald
[PATCH v4 2/5] sandbox: phy: add driver_data for bind test cmd
Add driver data to existing compatible string "sandbox,phy".
Add an additional compatible string without driver_data
This will verify that bind command parses, finds and passes the
correct driver data to device_bind_with_driver_data() by using
driver_data in the second sandbox_phy_ids table entry.
In sandbox_phy_bind() a check is added to validate driver_data
content.
Signed-off-by: Patrice Chotard
Reviewed-by: Simon Glass
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/phy/sandbox-phy.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/sandbox-phy.c b/drivers/phy/sandbox-phy.c
index 84ff5c6275..5f36da7692 100644
--- a/drivers/phy/sandbox-phy.c
+++ b/drivers/phy/sandbox-phy.c
@@ -8,6 +8,8 @@
#include
#include
+#define DRIVER_DATA 0x12345678
+
struct sandbox_phy_priv {
bool initialized;
bool on;
@@ -71,6 +73,14 @@ static int sandbox_phy_exit(struct phy *phy)
return 0;
}
+static int sandbox_phy_bind(struct udevice *dev)
+{
+ if (dev_get_driver_data(dev) != DRIVER_DATA)
+ return -ENODATA;
+
+ return 0;
+}
+
static int sandbox_phy_probe(struct udevice *dev)
{
struct sandbox_phy_priv *priv = dev_get_priv(dev);
@@ -90,13 +100,19 @@ static struct phy_ops sandbox_phy_ops = {
};
static const struct udevice_id sandbox_phy_ids[] = {
- { .compatible = "sandbox,phy" },
+ { .compatible = "sandbox,phy_no_driver_data",
+ },
+
+ { .compatible = "sandbox,phy",
+ .data = DRIVER_DATA
+ },
{ }
};
U_BOOT_DRIVER(phy_sandbox) = {
.name = "phy_sandbox",
.id = UCLASS_PHY,
+ .bind = sandbox_phy_bind,
.of_match = sandbox_phy_ids,
.ops= &sandbox_phy_ops,
.probe = sandbox_phy_probe,
--
2.17.1
[PATCH v4 3/5] sandbox: dts: Add compatible string for bind-test node
Usage of lists_bind_fdt() in bind command imposes to add
a compatible string for bind-test node.
The other impact, is that bind-test node is binded at sandbox
start, so no need to bind it in test_bind_unbind_with_node() test
Signed-off-by: Patrice Chotard
Reviewed-by: Simon Glass
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/sandbox/dts/test.dts | 1 +
test/py/tests/test_bind.py | 3 ---
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index df9f1835c9..7c6b14887f 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -131,6 +131,7 @@
};
bind-test {
+ compatible = "simple-bus";
bind-test-child1 {
compatible = "sandbox,phy";
#phy-cells = <1>;
diff --git a/test/py/tests/test_bind.py b/test/py/tests/test_bind.py
index 20c6050342..0b7cd9a808 100644
--- a/test/py/tests/test_bind.py
+++ b/test/py/tests/test_bind.py
@@ -25,9 +25,6 @@ def in_tree(response, name, uclass, drv, depth, last_child):
@pytest.mark.buildconfigspec('cmd_bind')
def test_bind_unbind_with_node(u_boot_console):
- #bind /bind-test. Device should come up as well as its children
- response = u_boot_console.run_command('bind /bind-test
generic_simple_bus')
- assert response == ''
tree = u_boot_console.run_command('dm tree')
assert in_tree(tree, 'bind-test', 'simple_bus', 'generic_simple_bus',
0, True)
assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, False)
--
2.17.1
[PATCH v4 5/5] doc: add bind/unbind command documentation
Add documentation in doc/drivel-model for the bind/unbind command.
Part of this documentation is extracted from original patch commit
message:
commit 49c752c93a78 ("cmd: Add bind/unbind commands to bind a device to a
driver from the command line")
Signed-off-by: Patrice Chotard
---
Changes in v4:
- fix make htmldocs error "Title underline too short"
Changes in v3:
- fix typo
- add bind/unbind parameters description and how to find them
Changes in v2: None
doc/driver-model/bind.rst | 49 ++
doc/driver-model/index.rst | 1 +
2 files changed, 50 insertions(+)
create mode 100644 doc/driver-model/bind.rst
diff --git a/doc/driver-model/bind.rst b/doc/driver-model/bind.rst
new file mode 100644
index 00..e3e9cb4d3c
--- /dev/null
+++ b/doc/driver-model/bind.rst
@@ -0,0 +1,49 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Patrice Chotard
+
+Binding/unbinding a driver
+==
+
+This document aims to describe the bind and unbind commands.
+
+For debugging purpose, it should be useful to bind or unbind a driver from
+the U-boot command line.
+
+The unbind command calls the remove device driver callback and unbind the
+device from its driver.
+
+The bind command binds a device to its driver.
+
+In some cases it can be useful to be able to bind a device to a driver from
+the command line.
+The obvious example is for versatile devices such as USB gadget.
+Another use case is when the devices are not yet ready at startup and
+require some setup before the drivers are bound (ex: FPGA which bitsream is
+fetched from a mass storage or ethernet)
+
+usage:
+
+bind
+bind
+
+unbind
+unbind
+unbind
+
+Where:
+ - is the node's device tree path
+ - is one of the class available in the list given by the "dm uclass"
+ command or first column of "dm tree" command.
+ - is the index of the parent's node (second column of "dm tree"
output).
+ - is the driver name to bind given by the "dm drivers" command or
the by
+ the fourth column of "dm tree" output.
+
+example:
+
+bind usb_dev_generic 0 usb_ether
+unbind usb_dev_generic 0 usb_ether
+or
+unbind eth 1
+
+bind /ocp/omap_dwc3@4838/usb@4839 usb_ether
+unbind /ocp/omap_dwc3@4838/usb@4839
diff --git a/doc/driver-model/index.rst b/doc/driver-model/index.rst
index b9df221627..37ef3721df 100644
--- a/doc/driver-model/index.rst
+++ b/doc/driver-model/index.rst
@@ -6,6 +6,7 @@ Driver Model
.. toctree::
:maxdepth: 2
+ bind
debugging
design
ethernet
--
2.17.1
[PATCH v4 1/5] cmd: bind: allow to bind driver with driver data
Initial implementation invokes device_bind_with_driver_data()
with driver_data parameter equal to 0.
For driver with driver data, the bind command can't bind
correctly this driver or even worse causes data abort as shown below:
As example, for debug purpose on STM32MP1 platform, ethernet (dwc_eth_qos.c)
driver needed to be unbinded/binded. This driver is using driver data:
static const struct udevice_id eqos_ids[] = {
{
.compatible = "nvidia,tegra186-eqos",
.data = (ulong)&eqos_tegra186_config
},
{
.compatible = "snps,dwmac-4.20a",
.data = (ulong)&eqos_stm32_config
},
{ }
};
After unbinding/binding this driver and probing it (with the dhcp command),
we got a prefetch abort as below:
STM32MP> unbind eth ethernet@5800a000
STM32MP> bind /soc/ethernet@5800a000 eth_eqos
STM32MP> dhcp
prefetch abort
pc : [<4310801c>] lr : []
reloc pc : [<035ba01c>]lr : []
sp : fdaf19b0 ip : ffcea83c fp : 0001
r10: ffcfd4a0 r9 : fdaffed0 r8 :
r7 : ffcff304 r6 : fdc63220 r5 : r4 : fdc5b108
r3 : 43108020 r2 : 3d39 r1 : ffcea544 r0 : fdc63220
Flags: nZCv IRQs off FIQs off Mode SVC_32
Code: data abort
pc : [] lr : []
reloc pc : []lr : []
sp : fdaf18b8 ip : fp : 0001
r10: ffcd69b2 r9 : fdaffed0 r8 : ffcd69aa
r7 : r6 : 0008 r5 : 4310801c r4 : fffc
r3 : 0001 r2 : 0028 r1 : r0 : 0006
Flags: NzCv IRQs on FIQs on Mode SVC_32 (T)
Code: 2f00 d1e9 2c00 dce9 (f855) 2024
Resetting CPU ...
Signed-off-by: Patrice Chotard
Cc: Jean-Jacques Hiblot
Reviewed-by: Simon Glass
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- add a bind command test
- add bind command documentation in doc/driver/model/bind.rst
- simplify patch 1 by using lists_bind_fdt()
cmd/bind.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/cmd/bind.c b/cmd/bind.c
index 44a5f17f0d..0aefc531d8 100644
--- a/cmd/bind.c
+++ b/cmd/bind.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include
static int bind_by_class_index(const char *uclass, int index,
@@ -150,8 +151,8 @@ static int bind_by_node_path(const char *path, const char
*drv_name)
}
ofnode = ofnode_path(path);
- ret = device_bind_with_driver_data(parent, drv, ofnode_get_name(ofnode),
- 0, ofnode, &dev);
+ ret = lists_bind_fdt(parent, ofnode, &dev, false);
+
if (!dev || ret) {
printf("Unable to bind. err:%d\n", ret);
return ret;
--
2.17.1
[PATCH v4 0/5] cmd: bind allow to bind driver with driver_data
- fix the bind command - add a bind command test - add bind command documentation Changes in v4: - fix make htmldocs error "Title underline too short" Changes in v3: - fix typo - fix typo - add bind/unbind parameters description and how to find them Changes in v2: - add a bind command test - add bind command documentation in doc/driver/model/bind.rst - simplify patch 1 by using lists_bind_fdt() Patrice Chotard (5): cmd: bind: allow to bind driver with driver data sandbox: phy: add driver_data for bind test cmd sandbox: dts: Add compatible string for bind-test node test/py: Update test_bind doc: add bind/unbind command documentation arch/sandbox/dts/test.dts | 1 + cmd/bind.c | 5 ++-- doc/driver-model/bind.rst | 49 ++ doc/driver-model/index.rst | 1 + drivers/phy/sandbox-phy.c | 18 +- test/py/tests/test_bind.py | 18 +++--- 6 files changed, 80 insertions(+), 12 deletions(-) create mode 100644 doc/driver-model/bind.rst -- 2.17.1
Re: [PATCH v1 1/3] drivers: pinctrl-single: handle different register width
On Wed, Apr 29, 2020 at 11:34 PM Simon Glass wrote:
>
> Hi Rayagonda,
>
> +Stephen Warren
>
> On Wed, 29 Apr 2020 at 10:35, Rayagonda Kokatanur
> wrote:
> >
> > Add support to use different register read/write api's
> > based on register width.
> >
> > Signed-off-by: Rayagonda Kokatanur
> > ---
> > drivers/pinctrl/pinctrl-single.c | 98
> > 1 file changed, 74 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/pinctrl/pinctrl-single.c
> > b/drivers/pinctrl/pinctrl-single.c
> > index 738f5bd636..aed113b083 100644
> > --- a/drivers/pinctrl/pinctrl-single.c
> > +++ b/drivers/pinctrl/pinctrl-single.c
> > @@ -10,12 +10,24 @@
> > #include
> > #include
> >
> > +/**
> > + * struct single_pdata - pinctrl device instance
> > + * @base first configuration register
> > + * @offset index of last configuration register
> > + * @mask configuration-value mask bits
> > + * @width configuration register bit width
> > + * @bits_per_mux
> > + * @read register read function to use
> > + * @write register write function to use
> > + */
> > struct single_pdata {
> > fdt_addr_t base;/* first configuration register */
> > int offset; /* index of last configuration register */
> > u32 mask; /* configuration-value mask bits */
> > int width; /* configuration register bit width */
> > bool bits_per_mux;
> > + u32 (*read)(phys_addr_t reg);
> > + void (*write)(u32 val, phys_addr_t reg);
>
> Can't we just have a read & write function with a switch statement?
> Why do we need function pointers?
I referred to the linux pinctrl-single.c and kept code similar to linux.
Please let me know.
>
> Regards,
> Simon
[PATCH v4 4/5] test/py: Update test_bind
As bind-test is now binded at sandbox startup and no more by
test_bind.py, bind-test nodes are not located at the end of
"dm tree" output, but can be located everywhere in the tree, so
bind-test output could either be:
simple_bus0 [ ] generic_simple_bus|-- bind-test
phy 0 [ ] phy_sandbox | |-- bind-test-child1
simple_bus1 [ ] generic_simple_bus| `-- bind-test-child2
or:
simple_bus5 [ ] generic_simple_bus`-- bind-test
phy 2 [ ] phy_sandbox |-- bind-test-child1
simple_bus6 [ ] generic_simple_bus`-- bind-test-child2
in_tree() function need to be updated to take care of that change.
Signed-off-by: Patrice Chotard
Reviewed-by: Simon Glass
---
Changes in v4: None
Changes in v3:
- fix typo
Changes in v2: None
test/py/tests/test_bind.py | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/test/py/tests/test_bind.py b/test/py/tests/test_bind.py
index 0b7cd9a808..4753c7ea7b 100644
--- a/test/py/tests/test_bind.py
+++ b/test/py/tests/test_bind.py
@@ -7,13 +7,16 @@ import re
def in_tree(response, name, uclass, drv, depth, last_child):
lines = [x.strip() for x in response.splitlines()]
- leaf = ' ' * 4 * depth;
- if not last_child:
- leaf = leaf + r'\|'
- else:
- leaf = leaf + '`'
+ leaf = ''
+ if depth != 0:
+ leaf = ' ' + '' * (depth - 1) ;
+ if not last_child:
+ leaf = leaf + r'\|'
+ else:
+leaf = leaf + '`'
+
leaf = leaf + '-- ' + name
- line = (r' *{:10.10}[0-9]* \[ [ +] \] {:20.20} {}$'
+ line = (r' *{:10.10}[0-9]* \[ [ +] \] {:20.20} [` |]{}$'
.format(uclass, drv, leaf))
prog = re.compile(line)
for l in lines:
--
2.17.1
Re: [PATCH] imx: spl: Fix build-time test for CONFIG_SPL_FS_FAT
On 30.04.20 12:06, Harald Seiler wrote: Hello Jan, On Wed, 2020-04-29 at 19:23 +0200, Jan Kiszka wrote: From: Jan Kiszka This was already changed in 0c3a9ed409a5 but apparently missed when adding 9d86dbd9cf9d. I sent a very similar patch [1] as part of my "Fix spl_mmc_boot_mode() implementation for IMX" series [2] which tries to solve a few more issues in this particular function. Oh, didn't check - then please ignore mine. Jan [1]: http://patchwork.ozlabs.org/project/uboot/patch/20200423110753.51231-6-...@denx.de/ [2]: http://patchwork.ozlabs.org/project/uboot/list/?series=172241 Signed-off-by: Jan Kiszka --- Found by chance while working on other code. Not tested. arch/arm/mach-imx/spl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 49bb3b928d..bfdb3f3ada 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -197,7 +197,7 @@ u32 spl_mmc_boot_mode(const u32 boot_device) case SD1_BOOT: case SD2_BOOT: case SD3_BOOT: -#if defined(CONFIG_SPL_FAT_SUPPORT) +#if defined(CONFIG_SPL_FS_FAT) return MMCSD_MODE_FS; #else return MMCSD_MODE_RAW; @@ -206,7 +206,7 @@ u32 spl_mmc_boot_mode(const u32 boot_device) case MMC1_BOOT: case MMC2_BOOT: case MMC3_BOOT: -#if defined(CONFIG_SPL_FAT_SUPPORT) +#if defined(CONFIG_SPL_FS_FAT) return MMCSD_MODE_FS; #elif defined(CONFIG_SUPPORT_EMMC_BOOT) return MMCSD_MODE_EMMCBOOT; -- 2.16.4 Regards,
Fwd: Re: ZynqMP boot: no messages from SPL other than "Debug uart enabled"
Hi Michal,
can you please try these files in SD boot mode?
Done, here are two logs, both in SD boot mode.
First, log.sd is with SD card inserted (with the image files that
apparently refuse to work other than the early UART message).
The other file, log.no-sd, is with no card inserted.
Cheers,
András
log.sd
Description: chemical/mdl-sdfile
** Xilinx System Debugger (XSDB) v2019.2
Build date : Nov 6 2019-22:12:26
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
xsdb% cd
xsdb% cd ../../home/u-boot
xsdb% pwd
C:/home/u-boot
xsdb% source script
attempting to launch hw_server
** Xilinx hw_server v2019.2
Build date : Nov 6 2019 at 22:12:23
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: hw_server application started
INFO: Use Ctrl-C to exit hw_server application
** Xilinx hw_server v2019.2
Build date : Nov 6 2019 at 22:12:23
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: hw_server application started
INFO: Use Ctrl-C to exit hw_server application
INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121
Downloading Program -- C:/home/u-boot/pmufw.elf
section, .vectors.reset: 0xffdc - 0xffdc0007
section, .vectors.sw_exception: 0xffdc0008 - 0xffdc000f
section, .vectors.interrupt: 0xffdc0010 - 0xffdc0017
section, .vectors.hw_exception: 0xffdc0020 - 0xffdc0027
section, .text: 0xffdc0050 - 0xffdd108b
section, .rodata: 0xffdd108c - 0xffdd31a3
section, .data: 0xffdd31a4 - 0xffdd749b
section, .sdata2: 0xffdd749c - 0xffdd749f
section, .sdata: 0xffdd74a0 - 0xffdd749f
section, .sbss: 0xffdd74a0 - 0xffdd749f
section, .bss: 0xffdd74a0 - 0xffddb4cb
section, .srdata: 0xffddb4cc - 0xffddbdef
section, .stack: 0xffddbdf0 - 0xffddcdef
section, .xpbr_serv_ext_tbl: 0xffddf6e0 - 0xffddfadf
100%0MB 0.2MB/s 00:00
Setting PC to Program Start Address 0xffdd02a0
Successfully downloaded C:/home/u-boot/pmufw.elf
Info: MicroBlaze PMU (target 13) Running
Info: Cortex-A53 #0 (target 9) Stopped at 0x (External Debug Request)
100%0MB 0.2MB/s 00:00
Successfully downloaded C:/home/u-boot/spl/u-boot-spl-dtb.bin
Info: Cortex-A53 #0 (target 9) Stopped at 0xfffcc484 (Breakpoint)
udelay() at lib/time.c: 178
178: couldn't open "/lib/time.c": no such file or directory
Info: Breakpoint 0 status:
target 9: {Address: 0xfffcc484 Type: Hardware}
xsdb% Info: Cortex-A53 #0 (target 9) Stopped at 0xfffcc484 (Breakpoint)
178: couldn't open "/lib/time.c": no such file or directory
xsdb%
[PATCH] board_r: Detect ifc-nor flash at run-time
From: Pankit Garg
CONFIG_MTD_NOR_FLASH flag needs to be enable for all
boot sources,as all flash drivers need to compile in
TFA Boot.Probe ifc nor flash only when there is nor
flash available on board.So needs to detect ifc-nor
flash at run-time for probing.
Signed-off-by: Pankit Garg
---
common/board_r.c | 8
1 file changed, 8 insertions(+)
diff --git a/common/board_r.c b/common/board_r.c
index 0bbeaa7594..2279736863 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -370,11 +370,19 @@ static int initr_binman(void)
}
#if defined(CONFIG_MTD_NOR_FLASH)
+__weak int is_flash_available(void)
+{
+ return 1;
+}
+
static int initr_flash(void)
{
ulong flash_size = 0;
bd_t *bd = gd->bd;
+ if (!is_flash_available())
+ return 0;
+
puts("Flash: ");
if (board_flash_wp_on())
--
2.17.1
[PATCH 0/8] Add dwc_eth_qos support for rockchip
Rockchip Socs can support two controllers "snps, dwmac-4.20a" and "snps, dwmac-3.50". In order to support two at gmac-rockchip.c, export public interface functions and struct data, it will be more general for others. David Wu (8): net: dwc_eth_qos: Use dev_ functions calls to get FDT data net: dwc_eth_qos: Fix the software reset net: dwc_eth_qos: Add option "snps,reset-gpio" phy-rst gpio for stm32 net: dwc_eth_qos: Move interface() to eqos_ops struct net: dwc_eth_qos: Make clk_rx and clk_tx optional net: dwc_eth_qos: Split eqos_start() to get link speed net: dwc_eth_qos: Export common struct and interface at head file net: gmac_rockchip: Add dwc_eth_qos support drivers/net/Kconfig | 2 +- drivers/net/dwc_eth_qos.c | 264 +--- drivers/net/gmac_rockchip.c | 160 ++ 3 files changed, 263 insertions(+), 163 deletions(-) -- 2.19.1
[PATCH 1/8] net: dwc_eth_qos: Use dev_ functions calls to get FDT data
It seems dev_ functions are more general than fdt_ functions.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 63f2086dec..a72132cacf 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1728,8 +1728,7 @@ static phy_interface_t eqos_get_interface_stm32(struct
udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
- NULL);
+ phy_mode = dev_read_string(dev, "phy-mode");
if (phy_mode)
interface = phy_get_interface_by_name(phy_mode);
@@ -1788,9 +1787,9 @@ static int eqos_probe(struct udevice *dev)
eqos->dev = dev;
eqos->config = (void *)dev_get_driver_data(dev);
- eqos->regs = devfdt_get_addr(dev);
+ eqos->regs = dev_read_addr(dev);
if (eqos->regs == FDT_ADDR_T_NONE) {
- pr_err("devfdt_get_addr() failed");
+ pr_err("dev_read_addr() failed");
return -ENODEV;
}
eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
--
2.19.1
[PATCH 3/8] net: dwc_eth_qos: Add option "snps, reset-gpio" phy-rst gpio for stm32
It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
gpio is used, adding this option makes reset function more general.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 40 ++-
1 file changed, 35 insertions(+), 5 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 16988f6bdc..06a8d924a7 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -298,6 +298,7 @@ struct eqos_priv {
struct eqos_tegra186_regs *tegra186_regs;
struct reset_ctl reset_ctl;
struct gpio_desc phy_reset_gpio;
+ u32 reset_delays[3];
struct clk clk_master_bus;
struct clk clk_rx;
struct clk clk_ptp_ref;
@@ -701,6 +702,15 @@ static int eqos_start_resets_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
+ ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
+ if (ret < 0) {
+ pr_err("dm_gpio_set_value(phy_reset, deassert) failed:
%d",
+ ret);
+ return ret;
+ }
+
+ udelay(eqos->reset_delays[0]);
+
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
if (ret < 0) {
pr_err("dm_gpio_set_value(phy_reset, assert) failed:
%d",
@@ -708,7 +718,7 @@ static int eqos_start_resets_stm32(struct udevice *dev)
return ret;
}
- udelay(2);
+ udelay(eqos->reset_delays[1]);
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
if (ret < 0) {
@@ -716,6 +726,8 @@ static int eqos_start_resets_stm32(struct udevice *dev)
ret);
return ret;
}
+
+ udelay(eqos->reset_delays[2]);
}
debug("%s: OK\n", __func__);
@@ -1065,16 +1077,16 @@ static int eqos_start(struct udevice *dev)
val |= EQOS_DMA_MODE_SWR;
writel(val, &eqos->dma_regs->mode);
limit = eqos->config->swr_wait / 10;
- while (limit--) {
+ do {
if (!(readl(&eqos->dma_regs->mode) & EQOS_DMA_MODE_SWR))
break;
mdelay(1);
- }
+ } while (limit--);
if (limit < 0) {
pr_err("EQOS_DMA_MODE_SWR stuck");
- goto err_stop_clks;
- return -ETIMEDOUT;
+ ret = -ETIMEDOUT;
+ goto err_stop_resets;
}
ret = eqos->config->ops->eqos_calibrate_pads(dev);
@@ -1712,11 +1724,29 @@ static int eqos_probe_resources_stm32(struct udevice
*dev)
if (ret)
pr_warn("gpio_request_by_name(phy reset) not provided
%d",
ret);
+ else
+ eqos->reset_delays[1] = 2;
eqos->phyaddr = ofnode_read_u32_default(phandle_args.node,
"reg", -1);
}
+ if (!dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
+ int reset_flags = GPIOD_IS_OUT;
+
+ if (dev_read_bool(dev, "snps,reset-active-low"))
+ reset_flags |= GPIOD_ACTIVE_LOW;
+
+ ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
+ &eqos->phy_reset_gpio, reset_flags);
+ if (ret == 0)
+ ret = dev_read_u32_array(dev, "snps,reset-delays-us",
+eqos->reset_delays, 3);
+ else
+ pr_warn("gpio_request_by_name(snps,reset-gpio) failed:
%d",
+ ret);
+ }
+
debug("%s: OK\n", __func__);
return 0;
--
2.19.1
[PATCH 4/8] net: dwc_eth_qos: Move interface() to eqos_ops struct
After moving to eqos_ops, if eqos_config is defined
outside, can not export interface() definition.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 06a8d924a7..fbd6caf85b 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -267,7 +267,6 @@ struct eqos_config {
int swr_wait;
int config_mac;
int config_mac_mdio;
- phy_interface_t (*interface)(struct udevice *dev);
struct eqos_ops *ops;
};
@@ -286,6 +285,7 @@ struct eqos_ops {
int (*eqos_disable_calibration)(struct udevice *dev);
int (*eqos_set_tx_clk_speed)(struct udevice *dev);
ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
+ phy_interface_t (*eqos_get_interface)(struct udevice *dev);
};
struct eqos_priv {
@@ -1105,7 +1105,7 @@ static int eqos_start(struct udevice *dev)
*/
if (!eqos->phy) {
eqos->phy = phy_connect(eqos->mii, eqos->phyaddr, dev,
- eqos->config->interface(dev));
+ eqos->config->ops->eqos_get_interface(dev));
if (!eqos->phy) {
pr_err("phy_connect() failed");
goto err_stop_resets;
@@ -1675,7 +1675,7 @@ static int eqos_probe_resources_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- interface = eqos->config->interface(dev);
+ interface = eqos->config->ops->eqos_get_interface(dev);
if (interface == PHY_INTERFACE_MODE_NONE) {
pr_err("Invalid PHY interface\n");
@@ -1918,7 +1918,8 @@ static struct eqos_ops eqos_tegra186_ops = {
.eqos_calibrate_pads = eqos_calibrate_pads_tegra186,
.eqos_disable_calibration = eqos_disable_calibration_tegra186,
.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186,
- .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
+ .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186,
+ .eqos_get_interface = eqos_get_interface_tegra186
};
static const struct eqos_config eqos_tegra186_config = {
@@ -1927,7 +1928,6 @@ static const struct eqos_config eqos_tegra186_config = {
.swr_wait = 10,
.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35,
- .interface = eqos_get_interface_tegra186,
.ops = &eqos_tegra186_ops
};
@@ -1945,7 +1945,8 @@ static struct eqos_ops eqos_stm32_ops = {
.eqos_calibrate_pads = eqos_calibrate_pads_stm32,
.eqos_disable_calibration = eqos_disable_calibration_stm32,
.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32,
- .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
+ .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32,
+ .eqos_get_interface = eqos_get_interface_stm32
};
static const struct eqos_config eqos_stm32_config = {
@@ -1954,7 +1955,6 @@ static const struct eqos_config eqos_stm32_config = {
.swr_wait = 50,
.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
- .interface = eqos_get_interface_stm32,
.ops = &eqos_stm32_ops
};
--
2.19.1
[PATCH 2/8] net: dwc_eth_qos: Fix the software reset
When using rgmii Gigabit mode, the wait_for_bit_le32()
reset method resulting in RX can not receive data, after
this patch, works well.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 21 +++--
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index a72132cacf..16988f6bdc 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1034,7 +1034,7 @@ static int eqos_write_hwaddr(struct udevice *dev)
static int eqos_start(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
- int ret, i;
+ int ret, i, limit;
ulong rate;
u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
ulong last_rx_desc;
@@ -1060,12 +1060,21 @@ static int eqos_start(struct udevice *dev)
eqos->reg_access_ok = true;
- ret = wait_for_bit_le32(&eqos->dma_regs->mode,
- EQOS_DMA_MODE_SWR, false,
- eqos->config->swr_wait, false);
- if (ret) {
+ /* DMA SW reset */
+ val = readl(&eqos->dma_regs->mode);
+ val |= EQOS_DMA_MODE_SWR;
+ writel(val, &eqos->dma_regs->mode);
+ limit = eqos->config->swr_wait / 10;
+ while (limit--) {
+ if (!(readl(&eqos->dma_regs->mode) & EQOS_DMA_MODE_SWR))
+ break;
+ mdelay(1);
+ }
+
+ if (limit < 0) {
pr_err("EQOS_DMA_MODE_SWR stuck");
- goto err_stop_resets;
+ goto err_stop_clks;
+ return -ETIMEDOUT;
}
ret = eqos->config->ops->eqos_calibrate_pads(dev);
--
2.19.1
[PATCH 6/8] net: dwc_eth_qos: Split eqos_start() to get link speed
Before enabling mac and mac working, we need to obtain
the current link speed to configure the clock, so split
eqos_start into two functions.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 56 ++-
1 file changed, 38 insertions(+), 18 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index b5d5156292..25b3449047 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1051,19 +1051,15 @@ static int eqos_write_hwaddr(struct udevice *dev)
return 0;
}
-static int eqos_start(struct udevice *dev)
+static int eqos_init(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
- int ret, i, limit;
+ int ret, limit;
ulong rate;
- u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
- ulong last_rx_desc;
+ u32 val;
debug("%s(dev=%p):\n", __func__, dev);
- eqos->tx_desc_idx = 0;
- eqos->rx_desc_idx = 0;
-
ret = eqos->config->ops->eqos_start_clks(dev);
if (ret < 0) {
pr_err("eqos_start_clks() failed: %d", ret);
@@ -1151,6 +1147,30 @@ static int eqos_start(struct udevice *dev)
goto err_shutdown_phy;
}
+ debug("%s: OK\n", __func__);
+ return 0;
+
+err_shutdown_phy:
+ phy_shutdown(eqos->phy);
+err_stop_resets:
+ eqos->config->ops->eqos_stop_resets(dev);
+err_stop_clks:
+ eqos->config->ops->eqos_stop_clks(dev);
+err:
+ pr_err("FAILED: %d", ret);
+ return ret;
+}
+
+static void eqos_enable(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
+ ulong last_rx_desc;
+ int i;
+
+ eqos->tx_desc_idx = 0;
+ eqos->rx_desc_idx = 0;
+
/* Configure MTL */
/* Enable Store and Forward mode for TX */
@@ -1352,19 +1372,19 @@ static int eqos_start(struct udevice *dev)
writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
eqos->started = true;
+}
- debug("%s: OK\n", __func__);
- return 0;
+static int eqos_start(struct udevice *dev)
+{
+ int ret;
-err_shutdown_phy:
- phy_shutdown(eqos->phy);
-err_stop_resets:
- eqos->config->ops->eqos_stop_resets(dev);
-err_stop_clks:
- eqos->config->ops->eqos_stop_clks(dev);
-err:
- pr_err("FAILED: %d", ret);
- return ret;
+ ret = eqos_init(dev);
+ if (ret)
+ return ret;
+
+ eqos_enable(dev);
+
+ return 0;
}
static void eqos_stop(struct udevice *dev)
--
2.19.1
[PATCH 7/8] net: dwc_eth_qos: Export common struct and interface at head file
Open structure data and interface, so that Soc using dw_eth_qos
controller can reference.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 81 +--
1 file changed, 9 insertions(+), 72 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 25b3449047..7f47e5f505 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -41,6 +41,7 @@
#include
#include
#include
+#include "dwc_eth_qos.h"
/* Core registers */
@@ -94,9 +95,6 @@ struct eqos_mac_regs {
#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT0
#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
@@ -109,8 +107,6 @@ struct eqos_mac_regs {
#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT16
#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
-#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
-#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT2
#define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
@@ -261,65 +257,6 @@ struct eqos_desc {
#define EQOS_DESC3_LD BIT(28)
#define EQOS_DESC3_BUF1V BIT(24)
-struct eqos_config {
- bool reg_access_always_ok;
- int mdio_wait;
- int swr_wait;
- int config_mac;
- int config_mac_mdio;
- struct eqos_ops *ops;
-};
-
-struct eqos_ops {
- void (*eqos_inval_desc)(void *desc);
- void (*eqos_flush_desc)(void *desc);
- void (*eqos_inval_buffer)(void *buf, size_t size);
- void (*eqos_flush_buffer)(void *buf, size_t size);
- int (*eqos_probe_resources)(struct udevice *dev);
- int (*eqos_remove_resources)(struct udevice *dev);
- int (*eqos_stop_resets)(struct udevice *dev);
- int (*eqos_start_resets)(struct udevice *dev);
- void (*eqos_stop_clks)(struct udevice *dev);
- int (*eqos_start_clks)(struct udevice *dev);
- int (*eqos_calibrate_pads)(struct udevice *dev);
- int (*eqos_disable_calibration)(struct udevice *dev);
- int (*eqos_set_tx_clk_speed)(struct udevice *dev);
- ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
- phy_interface_t (*eqos_get_interface)(struct udevice *dev);
-};
-
-struct eqos_priv {
- struct udevice *dev;
- const struct eqos_config *config;
- fdt_addr_t regs;
- struct eqos_mac_regs *mac_regs;
- struct eqos_mtl_regs *mtl_regs;
- struct eqos_dma_regs *dma_regs;
- struct eqos_tegra186_regs *tegra186_regs;
- struct reset_ctl reset_ctl;
- struct gpio_desc phy_reset_gpio;
- u32 reset_delays[3];
- struct clk clk_master_bus;
- struct clk clk_rx;
- struct clk clk_ptp_ref;
- struct clk clk_tx;
- struct clk clk_ck;
- struct clk clk_slave_bus;
- struct mii_dev *mii;
- struct phy_device *phy;
- int phyaddr;
- u32 max_speed;
- void *descs;
- struct eqos_desc *tx_descs;
- struct eqos_desc *rx_descs;
- int tx_desc_idx, rx_desc_idx;
- void *tx_dma_buf;
- void *rx_dma_buf;
- void *rx_pkt;
- bool started;
- bool reg_access_ok;
-};
-
/*
* TX and RX descriptors are 16 bytes. This causes problems with the cache
* maintenance on CPUs where the cache-line size exceeds the size of these
@@ -1007,7 +944,7 @@ static int eqos_adjust_link(struct udevice *dev)
return 0;
}
-static int eqos_write_hwaddr(struct udevice *dev)
+int eqos_write_hwaddr(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_platdata(dev);
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -1051,7 +988,7 @@ static int eqos_write_hwaddr(struct udevice *dev)
return 0;
}
-static int eqos_init(struct udevice *dev)
+int eqos_init(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
int ret, limit;
@@ -1161,7 +1098,7 @@ err:
return ret;
}
-static void eqos_enable(struct udevice *dev)
+void eqos_enable(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
@@ -1387,7 +1324,7 @@ static int eqos_start(struct udevice *dev)
return 0;
}
-static void eqos_stop(struct udevice *dev)
+void eqos_stop(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
int i;
@@ -1441,7 +1378,7 @@ static void eqos_stop(struct udevice *dev)
debug("%s: OK\n", __func__);
}
-static int eqos_send(struct udevice *dev, void *packet, int lengt
[PATCH 5/8] net: dwc_eth_qos: Make clk_rx and clk_tx optional
For others using, clk_rx and clk_tx may not be necessary,
and their clock names are different.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 65 +++
1 file changed, 31 insertions(+), 34 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index fbd6caf85b..b5d5156292 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -592,16 +592,20 @@ static int eqos_start_clks_stm32(struct udevice *dev)
goto err;
}
- ret = clk_enable(&eqos->clk_rx);
- if (ret < 0) {
- pr_err("clk_enable(clk_rx) failed: %d", ret);
- goto err_disable_clk_master_bus;
+ if (clk_valid(&eqos->clk_rx)) {
+ ret = clk_enable(&eqos->clk_rx);
+ if (ret < 0) {
+ pr_err("clk_enable(clk_rx) failed: %d", ret);
+ goto err_disable_clk_master_bus;
+ }
}
- ret = clk_enable(&eqos->clk_tx);
- if (ret < 0) {
- pr_err("clk_enable(clk_tx) failed: %d", ret);
- goto err_disable_clk_rx;
+ if (clk_valid(&eqos->clk_tx)) {
+ ret = clk_enable(&eqos->clk_tx);
+ if (ret < 0) {
+ pr_err("clk_enable(clk_tx) failed: %d", ret);
+ goto err_disable_clk_rx;
+ }
}
if (clk_valid(&eqos->clk_ck)) {
@@ -616,9 +620,11 @@ static int eqos_start_clks_stm32(struct udevice *dev)
return 0;
err_disable_clk_tx:
- clk_disable(&eqos->clk_tx);
+ if (clk_valid(&eqos->clk_tx))
+ clk_disable(&eqos->clk_tx);
err_disable_clk_rx:
- clk_disable(&eqos->clk_rx);
+ if (clk_valid(&eqos->clk_rx))
+ clk_disable(&eqos->clk_rx);
err_disable_clk_master_bus:
clk_disable(&eqos->clk_master_bus);
err:
@@ -647,8 +653,10 @@ static void eqos_stop_clks_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- clk_disable(&eqos->clk_tx);
- clk_disable(&eqos->clk_rx);
+ if (clk_valid(&eqos->clk_tx))
+ clk_disable(&eqos->clk_tx);
+ if (clk_valid(&eqos->clk_rx))
+ clk_disable(&eqos->clk_rx);
clk_disable(&eqos->clk_master_bus);
if (clk_valid(&eqos->clk_ck))
clk_disable(&eqos->clk_ck);
@@ -1691,20 +1699,16 @@ static int eqos_probe_resources_stm32(struct udevice
*dev)
ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
if (ret) {
pr_err("clk_get_by_name(master_bus) failed: %d", ret);
- goto err_probe;
+ return ret;
}
- ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
- if (ret) {
- pr_err("clk_get_by_name(rx) failed: %d", ret);
- goto err_free_clk_master_bus;
- }
+ ret = clk_get_by_name(dev, "mac_clk_rx", &eqos->clk_rx);
+ if (ret)
+ pr_warn("clk_get_by_name(rx) failed: %d", ret);
- ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
- if (ret) {
- pr_err("clk_get_by_name(tx) failed: %d", ret);
- goto err_free_clk_rx;
- }
+ ret = clk_get_by_name(dev, "mac_clk_tx", &eqos->clk_tx);
+ if (ret)
+ pr_warn("clk_get_by_name(tx) failed: %d", ret);
/* Get ETH_CLK clocks (optional) */
ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
@@ -1749,15 +1753,6 @@ static int eqos_probe_resources_stm32(struct udevice
*dev)
debug("%s: OK\n", __func__);
return 0;
-
-err_free_clk_rx:
- clk_free(&eqos->clk_rx);
-err_free_clk_master_bus:
- clk_free(&eqos->clk_master_bus);
-err_probe:
-
- debug("%s: returns %d\n", __func__, ret);
- return ret;
}
static phy_interface_t eqos_get_interface_stm32(struct udevice *dev)
@@ -1803,8 +1798,10 @@ static int eqos_remove_resources_stm32(struct udevice
*dev)
debug("%s(dev=%p):\n", __func__, dev);
- clk_free(&eqos->clk_tx);
- clk_free(&eqos->clk_rx);
+ if (clk_valid(&eqos->clk_tx))
+ clk_free(&eqos->clk_tx);
+ if (clk_valid(&eqos->clk_rx))
+ clk_free(&eqos->clk_rx);
clk_free(&eqos->clk_master_bus);
if (clk_valid(&eqos->clk_ck))
clk_free(&eqos->clk_ck);
--
2.19.1
[PATCH 8/8] net: gmac_rockchip: Add dwc_eth_qos support
Change the original data structure so that Rockchip's Soc
gmac controller can support the designware.c and dwc_eth_qos.c
drivers, a Soc can only support one.
Signed-off-by: David Wu
---
drivers/net/Kconfig | 2 +-
drivers/net/gmac_rockchip.c | 160 ++--
2 files changed, 135 insertions(+), 27 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4d1013c984..07d2b0787c 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -482,7 +482,7 @@ config PIC32_ETH
config GMAC_ROCKCHIP
bool "Rockchip Synopsys Designware Ethernet MAC"
- depends on DM_ETH && ETH_DESIGNWARE
+ depends on DM_ETH && (ETH_DESIGNWARE || DWC_ETH_QOS)
help
This driver provides Rockchip SoCs network support based on the
Synopsys Designware driver.
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index e152faf083..aa2bab4203 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -25,26 +25,39 @@
#include
#include
#include "designware.h"
+#include "dwc_eth_qos.h"
DECLARE_GLOBAL_DATA_PTR;
#define DELAY_ENABLE(soc, tx, rx) \
(((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE :
soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \
((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE :
soc##_RXCLK_DLY_ENA_GMAC_DISABLE))
+struct rockchip_eth_dev {
+ union {
+ struct eqos_priv eqos;
+ struct dw_eth_dev dw;
+ };
+};
+
/*
* Platform data for the gmac
*
* dw_eth_pdata: Required platform data for designware driver (must be first)
*/
struct gmac_rockchip_platdata {
- struct dw_eth_pdata dw_eth_pdata;
+ union {
+ struct dw_eth_pdata dw_eth_pdata;
+ struct eth_pdata eth_pdata;
+ };
+ bool has_gmac4;
bool clock_input;
int tx_delay;
int rx_delay;
};
struct rk_gmac_ops {
- int (*fix_mac_speed)(struct dw_eth_dev *priv);
+ const struct eqos_config config;
+ int (*fix_mac_speed)(struct rockchip_eth_dev *dev);
void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
};
@@ -55,6 +68,9 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice
*dev)
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
const char *string;
+ if (device_is_compatible(dev, "snps,dwmac-4.20a"))
+ pdata->has_gmac4 = true;
+
string = dev_read_string(dev, "clock_in_out");
if (!strcmp(string, "input"))
pdata->clock_input = true;
@@ -71,11 +87,15 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice
*dev)
if (pdata->rx_delay == -ENOENT)
pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
- return designware_eth_ofdata_to_platdata(dev);
+ if (!pdata->has_gmac4)
+ return designware_eth_ofdata_to_platdata(dev);
+
+ return 0;
}
-static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int px30_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct px30_grf *grf;
struct clk clk_speed;
int speed, ret;
@@ -115,8 +135,9 @@ static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
return 0;
}
-static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3228_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct rk322x_grf *grf;
int clk;
enum {
@@ -148,8 +169,9 @@ static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3288_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct rk3288_grf *grf;
int clk;
@@ -174,8 +196,9 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3308_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct rk3308_grf *grf;
struct clk clk_speed;
int speed, ret;
@@ -215,8 +238,9 @@ static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3328_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct rk3328_grf_regs *grf;
int clk;
enum {
@@ -248,8 +272,9 @@ static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3368_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct rk3368_g
[PATCH] sunxi: add support for Banana Pi P2 Zero board
Banana Pi P2 Zero is almost identic with Banana Pi M2 Zero with
additional eMMC and PoE functionality
This patch allows uboot to detect ethernet, usb, and eMMC during boot
Bootlog:
U-Boot SPL 2020.04 (Apr 30 2020 - 03:41:48 +0700)
DRAM: 512 MiB
Trying to boot from MMC1
U-Boot 2020.04 (Apr 30 2020 - 03:41:48 +0700) Allwinner Technology
CPU: Allwinner H3 (SUN8I 1680)
Model: Banana Pi BPI-P2-Zero
DRAM: 512 MiB
MMC: Device 'mmc@1c11000': seq 1 is in use by 'mmc@1c1'
mmc@1c0f000: 0, mmc@1c1: 2, mmc@1c11000: 1
Loading Environment from FAT... Unable to use mmc 1:1... In:serial
Out: serial
Err: serial
Net: phy interface0
eth0: ethernet@1c3
starting USB...
Bus usb@1c1a000: USB EHCI 1.00
scanning bus usb@1c1a000 for devices...
U-Boot SPL 2020.04 (Apr 30 2020 - 03:41:48 +0700)
DRAM: 512 MiB
Trying to boot from MMC1
U-Boot 2020.04 (Apr 30 2020 - 03:41:48 +0700) Allwinner Technology
CPU: Allwinner H3 (SUN8I 1680)
Model: Banana Pi BPI-P2-Zero
DRAM: 512 MiB
MMC: Device 'mmc@1c11000': seq 1 is in use by 'mmc@1c1'
mmc@1c0f000: 0, mmc@1c1: 2, mmc@1c11000: 1
Loading Environment from FAT... Unable to use mmc 1:1... In:serial
Out: serial
Err: serial
Net: phy interface0
eth0: ethernet@1c3
starting USB...
Bus usb@1c1a000: USB EHCI 1.00
scanning bus usb@1c1a000 for devices... 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found U-Boot script /boot.scr
515 bytes read in 2 ms (251 KiB/s)
## Executing script at 4310
21901 bytes read in 3 ms (7 MiB/s)
3966976 bytes read in 182 ms (20.8 MiB/s)
## Flattened Device Tree blob at 4100
Booting using the fdt blob at 0x4100
EHCI failed to shut down host controller.
Loading Device Tree to 49ff7000, end 49fff58c ... OK
Starting kernel ...
Signed-off-by: Mizan R
---
SHA1SUM for sun8i-h2-plus-bananapi-p2-zero.dts:
c682e1d9faba9d8c959ac526eef0962fc9ebd628
arch/arm/dts/sun8i-h2-plus-bananapi-p2-zero.dts
arch/arm/dts/Makefile | 1 +
.../dts/sun8i-h2-plus-bananapi-p2-zero.dts| 181 ++
board/sunxi/MAINTAINERS | 5 +
configs/bananapi_p2_zero_defconfig| 20 ++
4 files changed, 207 insertions(+)
create mode 100644 arch/arm/dts/sun8i-h2-plus-bananapi-p2-zero.dts
create mode 100644 configs/bananapi_p2_zero_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 820ee973..443d36f9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -516,6 +516,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \
sun8i-a83t-tbs-a711.dtb
dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h2-plus-bananapi-m2-zero.dtb \
+ sun8i-h2-plus-bananapi-p2-zero.dtb \
sun8i-h2-plus-libretech-all-h3-cc.dtb \
sun8i-h2-plus-orangepi-r1.dtb \
sun8i-h2-plus-orangepi-zero.dtb \
diff --git a/arch/arm/dts/sun8i-h2-plus-bananapi-p2-zero.dts
b/arch/arm/dts/sun8i-h2-plus-bananapi-p2-zero.dts
new file mode 100644
index ..b253e6e4
--- /dev/null
+++ b/arch/arm/dts/sun8i-h2-plus-bananapi-p2-zero.dts
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Mizan R
+ *
+ * Based on sun8i-h2-plus-bananapi-m2-zero.dts, which is:
+ * Copyright (C) 2017 Icenowy Zheng
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include
+#include
+
+/ {
+ model = "Banana Pi BPI-P2-Zero";
+ compatible = "sinovoip,bpi-p2-zero", "allwinner,sun8i-h2-plus";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ ethernet0 = &emac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+
+ pwr_led {
+ label = "bananapi-p2-zero:red:pwr";
+ linux,default-trigger = "heartbeat";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+ default-state = "on";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+
+ sw4 {
+ label = "power";
+ linux,code = ;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ reg_vdd_cpux: vdd-cpux-regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-cpux";
+ regulator-type = "voltage";
+
[RFC PATCH 2/2] arch: x86: apl: Use devicetree for FSP configuration
A the moment the FSP configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-M and FSP-S full configurable from devicetree by
adding binding properties for all FSP parameters.
Co-developed-by: Wolfgang Wallner
Signed-off-by: Wolfgang Wallner
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/Makefile |1 +
arch/x86/cpu/apollolake/fsp_bindings.c| 2096 +
arch/x86/cpu/apollolake/fsp_m.c | 164 +-
arch/x86/cpu/apollolake/fsp_s.c | 382 +--
arch/x86/dts/chromebook_coral.dts | 72 +-
.../asm/arch-apollolake/fsp/fsp_m_upd.h | 168 ++
.../asm/arch-apollolake/fsp/fsp_s_upd.h | 202 ++
.../asm/arch-apollolake/fsp_bindings.h| 74 +
.../fsp/fsp2/apollolake/fsp-m.txt | 320 +++
.../fsp/fsp2/apollolake/fsp-s.txt | 483
10 files changed, 3422 insertions(+), 540 deletions(-)
create mode 100644 arch/x86/cpu/apollolake/fsp_bindings.c
create mode 100644 arch/x86/include/asm/arch-apollolake/fsp_bindings.h
create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt
create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 578e15c4bf..3aa2a55676 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -10,6 +10,7 @@ obj-y += cpu_common.o
ifndef CONFIG_TPL_BUILD
obj-y += cpu.o
obj-y += punit.o
+obj-y += fsp_bindings.o
ifdef CONFIG_SPL_BUILD
obj-y += fsp_m.o
endif
diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c
b/arch/x86/cpu/apollolake/fsp_bindings.c
new file mode 100644
index 00..9c10e7328a
--- /dev/null
+++ b/arch/x86/cpu/apollolake/fsp_bindings.c
@@ -0,0 +1,2096 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 B&R Industrial Automation GmbH - http://www.br-automation.com
+ */
+
+#include
+#include
+#include
+
+static void read_u8_prop(ofnode node, u8 *dst, char *name, size_t count)
+{
+ u32 tmp;
+ const u8 *buf;
+ int ret;
+
+ if (count == 0) {
+ ret = ofnode_read_u32(node, name, &tmp);
+ if (ret == 0)
+ *dst = tmp;
+ } else {
+ buf = ofnode_read_u8_array_ptr(node, name, count);
+ if (buf)
+ memcpy(dst, buf, count);
+ }
+}
+
+static void read_u16_prop(ofnode node, u16 *dst, char *name, size_t count)
+{
+ u32 tmp;
+ u32 buf[32];
+ int ret;
+
+ if (ARRAY_SIZE(buf) < count) {
+ printf("ERROR: %s buffer to small!\n", __func__);
+ return;
+ }
+
+ if (count == 0) {
+ ret = ofnode_read_u32(node, name, &tmp);
+ if (ret == 0)
+ *dst = tmp;
+ } else {
+ ret = ofnode_read_u32_array(node, name, buf, count);
+ if (ret == 0)
+ for (int i = 0; i < count; i++)
+ dst[i] = buf[i];
+ }
+}
+
+static void read_u32_prop(ofnode node, u32 *dst, char *name, size_t count)
+{
+ if (count == 0)
+ ofnode_read_u32(node, name, dst);
+ else
+ ofnode_read_u32_array(node, name, dst, count);
+}
+
+static void read_string_prop(ofnode node, char *dst, char *name, int count)
+{
+ const char *string_buf;
+
+ if (count > 0) {
+ string_buf = ofnode_read_string(node, name);
+ if (string_buf) {
+ strncpy(dst, string_buf, count);
+ dst[count - 1] = '\0';
+ }
+ }
+}
+
+static void read_swizzle_prop(ofnode node, u8 *dst, char *name, int count)
+{
+ const struct lpddr4_chan_swizzle_cfg *sch;
+ /* Number of bytes to copy per DQS */
+ const size_t sz = DQ_BITS_PER_DQS;
+ const struct lpddr4_swizzle_cfg *swizzle_cfg;
+
+ swizzle_cfg = (const struct lpddr4_swizzle_cfg *)
+ ofnode_read_u8_array_ptr(node, name, count);
+
+ if (!swizzle_cfg)
+ return;
+ /*
+* CH0_DQB byte lanes in the bit swizzle configuration field are
+* not 1:1. The mapping within the swizzling field is:
+* indices [0:7] - byte lane 1 (DQS1) DQ[8:15]
+* indices [8:15] - byte lane 0 (DQS0) DQ[0:7]
+* indices [16:23] - byte lane 3 (DQS3) DQ[24:31]
+* indices [24:31] - byte lane 2 (DQS2) DQ[16:23]
+*/
+ sch = &swizzle_cfg->phys[LP4_PHYS_CH0B];
+ memcpy(&dst[0 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS1], sz);
+ memcpy(&dst[1 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS0], sz);
+ memcpy(&dst[2 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS3], sz);
+ memcpy(&dst[3 * DQ_BITS_PER_DQS], &sch->dqs[LP4_DQS2], sz);
+
+ /*
+* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1.
+
Re: ZynqMP boot: no messages from SPL other than "Debug uart enabled"
Hi Michal, Sorry I misunderstood your message, and I didn't spot the attached files. Now I booted with those two files, there's no output on the UARTs whatsoever. Is there anything else I can try? Cheers, András On 30/04/2020 12:33, Michal Simek wrote: Hi, On 30. 04. 20 12:19, Major A wrote: Hi Michal, can you please try these files in SD boot mode? Done, here are two logs, both in SD boot mode. First, log.sd is with SD card inserted (with the image files that apparently refuse to work other than the early UART message). The other file, log.no-sd, is with no card inserted. we don't understand each other. I sent you boot.bin and image.itb. Just copy them to SD card, switch board to sd boot mode and power it up. Thanks, Michal
Re: [PATCH v2 7/7] ddr: altera: arria10: Remove call to dram_init_banksize()
On Mon, Apr 20, 2020 at 4:46 PM Ley Foon Tan wrote:
>
> dram_init_banksize() is called in board_init_f() boot sequences
> in Uboot, remove it from SDRAM driver.
>
> Signed-off-by: Ley Foon Tan
> ---
> drivers/ddr/altera/sdram_arria10.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/ddr/altera/sdram_arria10.c
> b/drivers/ddr/altera/sdram_arria10.c
> index e4944ef95183..27fd393e6fe4 100644
> --- a/drivers/ddr/altera/sdram_arria10.c
> +++ b/drivers/ddr/altera/sdram_arria10.c
> @@ -660,9 +660,6 @@ static int ddr_calibration_sequence(struct
> altera_sdram_platdata *plat)
> else
> gd->ram_size = (u32)size;
>
> - /* setup the dram info within bd */
> - dram_init_banksize();
> -
> if (of_sdram_firewall_setup(gd->fdt_blob))
> puts("FW: Error Configuring Firewall\n");
>
Hi
Need to drop this patch, Found that dcache_enable() needs gd->bd->bi_dram[].
I will send v3.
Thanks.
Regards
Ley Foon
Re: [PATCH v1 3/3] drivers: pinctrl-single: add request api
Hi Simon, On Wed, Apr 29, 2020 at 11:34 PM Simon Glass wrote: > > Hi Rayagonda, > > +Stephen Warren > > On Wed, 29 Apr 2020 at 10:36, Rayagonda Kokatanur > wrote: > > > > Add pinctrl_ops->request api to configure pctrl > > pad register in gpio mode. > > > > Signed-off-by: Rayagonda Kokatanur > > --- > > drivers/pinctrl/pinctrl-single.c | 29 + > > 1 file changed, 29 insertions(+) > > This should use the Kconfig also (and needs a test) Please elaborate "need a test". Do you mean a testing procedure as part of the commit message ? I feel we don't need the Kconfig option, looking at Linux pinctrl-single driver. Please let me know. > > Regards, > Simon
Re: ZynqMP boot: no messages from SPL other than "Debug uart enabled"
hi, that's quite weird. Did you try any petalinux bsp and boot petalinux boot.bin on that board to make sure that board is fine? M On 30. 04. 20 13:01, Major A wrote: > Hi Michal, > > Sorry I misunderstood your message, and I didn't spot the attached > files. Now I booted with those two files, there's no output on the > UARTs whatsoever. Is there anything else I can try? > > Cheers, > > András > > > On 30/04/2020 12:33, Michal Simek wrote: >> Hi, >> >> On 30. 04. 20 12:19, Major A wrote: >>> Hi Michal, >>> can you please try these files in SD boot mode? >>> >>> Done, here are two logs, both in SD boot mode. >>> >>> First, log.sd is with SD card inserted (with the image files that >>> apparently refuse to work other than the early UART message). >>> >>> The other file, log.no-sd, is with no card inserted. >> >> we don't understand each other. I sent you boot.bin and image.itb. Just >> copy them to SD card, switch board to sd boot mode and power it up. >> >> Thanks, >> Michal >>
Re: [PATCH v2 7/7] ddr: altera: arria10: Remove call to dram_init_banksize()
On 4/30/20 1:02 PM, Ley Foon Tan wrote:
> On Mon, Apr 20, 2020 at 4:46 PM Ley Foon Tan wrote:
>>
>> dram_init_banksize() is called in board_init_f() boot sequences
>> in Uboot, remove it from SDRAM driver.
>>
>> Signed-off-by: Ley Foon Tan
>> ---
>> drivers/ddr/altera/sdram_arria10.c | 3 ---
>> 1 file changed, 3 deletions(-)
>>
>> diff --git a/drivers/ddr/altera/sdram_arria10.c
>> b/drivers/ddr/altera/sdram_arria10.c
>> index e4944ef95183..27fd393e6fe4 100644
>> --- a/drivers/ddr/altera/sdram_arria10.c
>> +++ b/drivers/ddr/altera/sdram_arria10.c
>> @@ -660,9 +660,6 @@ static int ddr_calibration_sequence(struct
>> altera_sdram_platdata *plat)
>> else
>> gd->ram_size = (u32)size;
>>
>> - /* setup the dram info within bd */
>> - dram_init_banksize();
>> -
>> if (of_sdram_firewall_setup(gd->fdt_blob))
>> puts("FW: Error Configuring Firewall\n");
>>
> Hi
>
> Need to drop this patch, Found that dcache_enable() needs gd->bd->bi_dram[].
> I will send v3.
OK, thanks.
Re: ZynqMP boot: no messages from SPL other than "Debug uart enabled"
Hi Michal, Yes, I did. The Petalinux image from here: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841937/Zynq+UltraScale+MPSoC+Ubuntu+part+2+-+Building+and+Running+the+Ubuntu+Desktop+From+Sources works fine. Cheers, András On 30/04/2020 13:03, Michal Simek wrote: hi, that's quite weird. Did you try any petalinux bsp and boot petalinux boot.bin on that board to make sure that board is fine? M On 30. 04. 20 13:01, Major A wrote: Hi Michal, Sorry I misunderstood your message, and I didn't spot the attached files. Now I booted with those two files, there's no output on the UARTs whatsoever. Is there anything else I can try? Cheers, András On 30/04/2020 12:33, Michal Simek wrote: Hi, On 30. 04. 20 12:19, Major A wrote: Hi Michal, can you please try these files in SD boot mode? Done, here are two logs, both in SD boot mode. First, log.sd is with SD card inserted (with the image files that apparently refuse to work other than the early UART message). The other file, log.no-sd, is with no card inserted. we don't understand each other. I sent you boot.bin and image.itb. Just copy them to SD card, switch board to sd boot mode and power it up. Thanks, Michal
Re: u-boot DT configuration node
On 29. 04. 20 16:55, Rob Herring wrote: > On Tue, Apr 28, 2020 at 8:51 AM Michal Simek wrote: >> >> On 28. 04. 20 15:23, Rob Herring wrote: >>> On Wed, Apr 1, 2020 at 4:23 AM Michal Simek wrote: Hi Rob and others, for couple of years already u-boot is using config node in root DT for u-boot configuration. Here is one example in u-boot source code. https://gitlab.denx.de/u-boot/u-boot/-/blob/master/arch/arm/dts/exynos5250-spring.dts#L47 And here is dt binding description https://gitlab.denx.de/u-boot/u-boot/-/blob/master/doc/device-tree-bindings/config.txt I was checking dt binding specification and there no such a thing described there. It means I expect this is more adhoc u-boot solution. We have reached the point where could be beneficial to put some u-boot specific configurations to DT. Actually I have done similar thing some time ago too by using chosen node and add xilinx specific property there to point to eeprom. https://gitlab.denx.de/u-boot/u-boot/-/blob/master/arch/arm/dts/zynqmp-zcu102-revA.dts#L39 >>> >>> In this case, I think an alias should be used as it's more of just a >>> shortcut to finding a specific node. >> >> What alias name do you suggest to use? >> We have systems where one i2c eeprom described based board and another >> i2c eeprom describe bootable module. And I need to have shotcuts to both >> of them. >> >> dt specification doesn't list any keywords for aliases but there is >> generic name recommendation. > > I do want make aliases a registered list of names. > >> Based on keywords it should look like this. >> eeprom0 = ...; >> eeprom1 = ...; > > That was my initial thought, but maybe "nvmemX" to be a bit more generic. I am fine with that. It means that multiple eeproms and order will be direct by alias number. In past I wanted to use list but aliases number is also fine. > > I think it is a time to discuss it and do it properly. First of all my question is where we could list SW prefixes to make sure that they are listed and everybody is aware about it. We have vendor-prefixes and we should have a way to record also prefixes for sw projects. U-Boot is using u-boot. Xen has file in the kernel with using xen prefix. At least these two should be listed. >>> >>> Documentation/devicetree/bindings/vendor-prefixes.yaml. >> >> thx Sent a patch for it. Please review. https://lore.kernel.org/linux-devicetree/85b8dc9e6288270bbfdf55f1c156dba160293f01.1588239081.git.michal.si...@xilinx.com/ Next my question is what is the recommended way to pass sw specific parameters via DT? I think using chosen node is more appropriate then adhoc config node. Or is there a better way how this should be done? >>> >>> /chosen >>> >>> For vendor specific things though I would be cautious. If they are >>> settings for a specific device, then they probably belong in the >>> device's node. Second, are they really vendor specific? What we don't >>> want is each vendor doing the same thing in slightly different ways. >> >> For u-boot specific setting like - offsets it should be generic for >> everybody. I was already talking to Loic that for saving u-boot >> variables to QSPI we should be using MTD partition map and put there >> maybe a flag to say that this is the location for storing them. > > I'd standardize on the partition name. ok. Documentation/devicetree/bindings/mtd/partition.txt? I have grep u-boot repo and I see these label names "NAND.u-boot"; "NAND.u-boot-env"; "NAND.u-boot-env.backup1"; "NAND.u-boot-spl-os"; "QSPI.u-boot"; "QSPI.u-boot-env"; "QSPI.u-boot-env.backup1"; "qspi-u-boot-img"; "qspi-u-boot-spl"; "QSPI.u-boot-spl-os"; "u-boot "u-boot"; "u-boot-2"; "u-boot-2.backup1"; "u-boot.backup1"; "u-boot-env"; "u-boot-env.backup1"; "u-boot-spl"; kernel is kind of similar "alt-u-boot"; "alt-u-boot-env"; "NAND.u-boot"; "NAND.u-boot-env"; "NAND.u-boot-env.backup1"; "NAND.u-boot-spl-os"; "QSPI.u-boot"; "QSPI.u-boot-env"; "QSPI.u-boot-env.backup1"; "QSPI.u-boot-spl-os"; "u-boot "u-boot"; "u-boot.backup1"; "u-boot-env"; "u-boot-env2"; "u-boot-env.backup1"; "u-boot-environment"; "u-boot-factory"; "u-boot-nand"; "u-boot-nor"; "u-boot-spi"; "u-boot-spl"; It means it is mix of names. I think SPI cases are the most complicated one because you can have multiple spi devices in the system and you can't use the same name for registration. That's why I think that make sense to use an optional prefix as people are using QSPI/NAND already. But not quite sure that using QSPI is generic enough because you can have multiple QSPIs. Using alias name is also not ideal because one simple change in aliases would require changes in partition name/label. Any better suggestion? Next thing is that u-boot. Label or if missing node name doesn't list dot a valid character for node name based on device-tree spec. It means I would consider using dot here as invalid. Some
Re: [PATCH v1 2/3] drivers: pinctrl-single: add support to parse gpio properties
Hi Simon, On Wed, Apr 29, 2020 at 11:34 PM Simon Glass wrote: > > Hi Rayagonda, > > +Stephen Warren > > On Wed, 29 Apr 2020 at 10:35, Rayagonda Kokatanur > wrote: > > > > Parse different gpio properties from dt as part of probe > > function. This detail will be used to enable pinctrl pad > > later when gpio lines are requested. > > > > Signed-off-by: Rayagonda Kokatanur > > --- > > drivers/pinctrl/pinctrl-single.c | 62 +++- > > 1 file changed, 61 insertions(+), 1 deletion(-) > > Can you please add the binding and a test? Also I think this feature > should be behind a Kconfig flag to avoid code-size increase. Sorry I didn't get it, please elaborate "binding and a test". You mean dt-binding document and test procedure. This feature is added by referring to linux pinctrl-single driver and code is in align with linux driver. This feature is going to be used in most of the gpio controllers where they have pin controllers to select different modes of gpio lines. I feel this feature should be part of the driver by default. > > Regards, > Simon
pull request of u-boot-fsl-qoriq for v2020.07
Dear Tom,
Please find my pull-request for u-boot-fsl-qoriq/master
https://travis-ci.org/github/p-priyanka-jain/u-boot/builds/680868706
Summary
Add DM_ETH support for DPAA1, DPAA2 based RDB platforms: ls1046ardb,
ls1043ardb, lx2160ardb, ls2088ardb, ls1088ardb.
Add GICv3 support for ls1028a, ls2088a, ls1088a.
Add lpuart support on ls1028aqds.
Few bug fixes and updates on ls2088a, ls1012a, ls1046a, ls1021a based platforms.
The following changes since commit d16d37bcd4087b8ea0f66cb76a73edad182d151a:
Merge tag 'video-for-v2020.07-rc1' of
https://gitlab.denx.de/u-boot/custodians/u-boot-video (2020-04-27 09:41:51
-0400)
are available in the Git repository at:
https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git HEAD
for you to fetch changes up to 206f37547e2c0f6d9bb2c37bc51d71f87e965bae:
configs: ls2088ardb: Correct DEFAULT_DEVICE_TREE value (2020-04-29 11:10:54
+0530)
Alison Wang (1):
configs: ls1021a: Append CMA configuration to bootargs
Biwen Li (3):
include/configs: ls1012afrwy: support dhcp boot
configs: ls1046aqds: support distro boot
configs: ls1012afrwy: drop env qspi_bootcmd
Hou Zhiqiang (8):
fsl-layerscape: Add RESV_RAM check in resv_ram addr
board: lx2160a: Add check in GIC RD tables init
board: lx2160a: Align RD tables address to 64KB
fsl-layerscape: Kconfig: Select RESV_RAM if GIC_V3_ITS
fsl-layerscape: Move GIC RD tables init to soc.c
configs: ls1088a: Enable GIC_V3_ITS config
configs: ls1028a: Enable GIC_V3_ITS config
configs: ls208xa: Enable GIC_V3_ITS config
Ioana Ciornei (14):
drivers: net: add Layerscape mEMAC MDIO driver
drivers: net: ldpaa: add DTS based probing support
drivers: net: fsl-mc: add support for CONFIG_DM_ETH
board: ls1088ardb: transition to DM_ETH
board: ls2088ardb: transition to DM_ETH
arm: dts: lx2160a: add external MDIO nodes
arm: dts: ls2088a: add external MDIO nodes
arm: dts: ls1088a: add external MDIO nodes
arm: dts: lx2160ardb: add DPMAC and PHY nodes
arm: dts: ls2088ardb: add DPMAC and PHY nodes
arm: dts: ls1088ardb: add DPMAC and PHY nodes
configs: ls1088ardb: enable CONFIG_DM_ETH and related
configs: ls2088ardb: enable CONFIG_DM_ETH and related
configs: lx2160ardb: enable CONFIG_DM_ETH and related
Kuldeep Singh (1):
configs: ls2088ardb: Correct DEFAULT_DEVICE_TREE value
Madalin Bucur (11):
ARM: dts: add QorIQ DPAA 1 FMan v3 device tree nodes
ARM: dts: add QorIQ DPAA 1 FMan v3 for LS1043A
ARM: dts: add QorIQ DPAA 1 FMan v3 to LS1043ARDB
ARM: dts: add QorIQ DPAA 1 FMan v3 for LS1046A
ARM: dts: add QorIQ DPAA 1 FMan v3 to LS1046ARDB
driver: net: fm: change init_phy() param
driver: net: fm: separate receive buffer free code
driver: net: fm: add DM MDIO support
driver: net: fm: add DM ETH support
configs: enable DM_ETH support for LS1043ARDB
configs: enable DM_ETH support for LS1046ARDB
Meenakshi Aggarwal (1):
lx2160a : Update eMMC boot environment variable
Yuantian Tang (5):
armv8: ls1046ardb: update the DIMM WRLVL_START value
board: freescale: ls1028a: mux changes for lpuart
arm: dts: ls1028a: add lpuart nodes
armv8: ls1028aqds: add lpuart dts support
configs: ls1028aqds: add lpuart config
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 +
arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 10 +-
arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 4 +
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 44 +++
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/fsl-ls1028a-qds-duart.dts | 15 +
arch/arm/dts/fsl-ls1028a-qds-lpuart.dts| 15 +
.../{fsl-ls1028a-qds.dts => fsl-ls1028a-qds.dtsi} | 4 +
arch/arm/dts/fsl-ls1028a.dtsi | 60 +++
arch/arm/dts/fsl-ls1043-post.dtsi | 48 +++
arch/arm/dts/fsl-ls1043a-rdb.dts | 81
arch/arm/dts/fsl-ls1043a.dtsi | 2 +-
arch/arm/dts/fsl-ls1046-post.dtsi | 49 +++
arch/arm/dts/fsl-ls1046a-rdb.dts | 67
arch/arm/dts/fsl-ls1046a.dtsi | 2 +-
arch/arm/dts/fsl-ls1088a-rdb.dts | 102 +
arch/arm/dts/fsl-ls1088a.dtsi | 102 -
arch/arm/dts/fsl-ls2080a.dtsi | 90 -
arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 88 +
arch/arm/dts/fsl-lx2160a-rdb.dts | 52 +++
arch/arm/dts/fsl-lx2160a.dtsi | 65
arch/arm/dts/qoriq-fman3-0-10g-0.dtsi | 44 +++
arch/arm/dts/qoriq-fman3-0-10g-1.dtsi | 44 +++
arch/arm/dts/qoriq-fman3-0-1g-0.dtsi | 43 ++
arch/arm/dts/qoriq-fman3-0-1g-1.dtsi
Re: [PATCH v5 1/4] omap: mmc: Avoid using libfdt with of-platdata
wt., 28 kwi 2020 o 09:01 Faiz Abbas napisał(a): > > +Bartosz > > On 28/04/20 9:47 am, Lokesh Vutla wrote: > > +Faiz, > > > > On 28/04/20 12:29 AM, Tom Rini wrote: > >> On Mon, Apr 27, 2020 at 05:33:41AM +, Peng Fan wrote: > Subject: [PATCH v5 1/4] omap: mmc: Avoid using libfdt with of-platdata > > At present this driver is enabled in SPL on omapl138_lcdk, which uses > of-platdata. The driver needs to be ported to use of-platdata properly. > For now, avoid a build error by returning an error. > > Signed-off-by: Simon Glass > > > > Does this break the boot on omap l138? > > > > I don't have a board at hand to test this out. Bartosz can you help test this > with > omapl138? > > Thanks, > Faiz Hi Faiz, I can confirm - this *does* break the mmc boot on da850-lcdk. Bart
Re: [PATCH v2 1/3] net: phy: Add helper routines to set and clear bits
Michal
On 4/30/20 3:00 AM, Michal Simek wrote:
On 28. 04. 20 21:26, Dan Murphy wrote:
Add phy_set/clear_bit helper routines so that ported drivers from the
kernel can use these functions.
Signed-off-by: Dan Murphy
---
include/phy.h | 80 +++
1 file changed, 80 insertions(+)
diff --git a/include/phy.h b/include/phy.h
index b5de14cbfc29..1a875b96edb7 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -170,6 +170,12 @@ struct fixed_link {
int asym_pause;
};
+/**
+ * phy_read - Convenience function for reading a given PHY register
+ * @phydev: the phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: register number to read
+ */
static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
{
struct mii_dev *bus = phydev->bus;
@@ -182,6 +188,13 @@ static inline int phy_read(struct phy_device *phydev, int
devad, int regnum)
return bus->read(bus, phydev->addr, devad, regnum);
}
+/**
+ * phy_write - Convenience function for writing a given PHY register
+ * @phydev: the phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: register number to write
+ * @val: value to write to @regnum
+ */
static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
u16 val)
{
@@ -209,6 +222,13 @@ static inline void phy_mmd_start_indirect(struct
phy_device *phydev, int devad,
(devad | MII_MMD_CTRL_NOINCR));
}
+/**
+ * phy_read_mmd - Convenience function for reading a register
+ * from an MMD on a given PHY.
+ * @phydev: The phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: The register on the MMD to read
+ */
static inline int phy_read_mmd(struct phy_device *phydev, int devad,
int regnum)
{
@@ -233,6 +253,14 @@ static inline int phy_read_mmd(struct phy_device *phydev,
int devad,
return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA);
}
+/**
+ * phy_write_mmd - Convenience function for writing a register
+ * on an MMD on a given PHY.
+ * @phydev: The phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: The register on the MMD to read
+ * @val: value to write to @regnum
+ */
static inline int phy_write_mmd(struct phy_device *phydev, int devad,
int regnum, u16 val)
{
@@ -257,6 +285,58 @@ static inline int phy_write_mmd(struct phy_device *phydev,
int devad,
return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val);
}
+/**
+ * phy_set_bits_mmd - Convenience function for setting bits in a register
+ * on MMD
+ * @phydev: the phy_device struct
+ * @devad: the MMD containing register to modify
+ * @regnum: register number to modify
+ * @val: bits to set
+ */
+static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad,
+ u32 regnum, u16 val)
+{
+ int value, ret;
+
+ value = phy_read_mmd(phydev, devad, regnum);
+ if (value < 0)
+ return value;
+
+ value |= val;
+
+ ret = phy_write_mmd(phydev, devad, regnum, value);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/**
+ * phy_clear_bits_mmd - Convenience function for clearing bits in a register
+ * on MMD
+ * @phydev: the phy_device struct
+ * @devad: the MMD containing register to modify
+ * @regnum: register number to modify
+ * @val: bits to clear
+ */
+static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad,
+u32 regnum, u16 val)
+{
+ int value, ret;
+
+ value = phy_read_mmd(phydev, devad, regnum);
+ if (value < 0)
+ return value;
+
+ value &= ~val;
+
+ ret = phy_write_mmd(phydev, devad, regnum, value);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;
Better would be to have one patch just with adding missing kernel-doc.
It is not described in commit message too.
Yes I was thinking that I should have done 2 patches since the kernel
doc to the other functions is completely separate work.
And second to add that functions.
And there are errors there.
[u-boot](debian)$ ./scripts/kernel-doc -v -man include/phy.h > /dev/null
I learned something new today. Now I know how to check my kernel doc :)
I will fix these.
Dan
RE: [PATCH] configs: ls2088ardb: Correct DEFAULT_DEVICE_TREE value
>-Original Message- >From: U-Boot On Behalf Of Kuldeep Singh >Sent: Thursday, March 19, 2020 3:34 PM >To: u-boot@lists.denx.de >Cc: Priyanka Jain ; Kuldeep Singh > >Subject: [PATCH] configs: ls2088ardb: Correct DEFAULT_DEVICE_TREE value > >LS2088A-RDB has CONFIG_DEFAULT_DEVICE_TREE value correctly set as "fsl- >ls2088a-rdb-qspi" for QSPI secure/non-secure boot and TFA non-secure boot >mode. > >Fix the value for TFA secure boot mode. > >Signed-off-by: Kuldeep Singh >--- Applied to fsl-qoriq. Awaiting upstream Thanks Priyanka
