Re: i.MX8MP SPL failures due to memory corruption/overflow?
Hi On Wed, Mar 15, 2023 at 3:13 PM Frieder Schrempf wrote: > > Hi, > > I'm trying to bring up a new board based on the i.MX8MP and I have an > issue I'm hoping someone can help solving. > > I'm seeing failures in the early SPL code, usually in the DDR > initialization. Often they look like: > > U-Boot SPL 2023.04-rc3 (Mar 07 2023 - 14:32:34 +) > Training FAILED > Failed to initialize DDR RAM! > ### ERROR ### Please RESET the board ### > > But sometimes ddr_init() doesn't even return an error and only the > get_ram_size() afterwards which tries to allocate the memory fails. > In my experience you don't have space inside the cpu internal memory. It means that you overlap some stack with the code. Change the printf means move a bit. So you have problem but depends what you are going to destroy Michael > The strange thing is that the issues appear or disappear > deterministically on the binary level. This means I sometimes get a > U-Boot binary which runs just fine in 100% of cases. Then I change for > example one of the following: > > * Adding a single printf() somewhere in the boards spl.c > * Using the same binary but booting from SD card instead of USB loader > * Using the same source but switching from the OS cross compiler to the > one from Yocto/OE > > And afterwards I get 100% failure rate with an error as described above. > > My suspicion is that there is some memory corruption/conflict. My SPL is > quite large and I wonder if it exceeds some limit. > > SPL is loaded to 0x92 and CONFIG_SPL_STACK is set to 0x96, which > leaves 256 KiB in between for the SPL. But all i.MX8MP boards seem to > set CONFIG_SPL_MAX_SIZE=0x26000 (152 KiB) for some reason. My > u-boot-spl-ddr.bin currently has around 193 KiB but I don't get any > warning about exceeding the SPL_MAX_SIZE. > > My questions: > > * Why is CONFIG_SPL_MAX_SIZE set to 152 KiB? > * Why is there no warning in my case? > * Any other ideas or pointers? > > Thanks for your help! > > Best regards > Frieder -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 mich...@amarulasolutions.com __ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 i...@amarulasolutions.com www.amarulasolutions.com
Re: [PATCH v1 7/7] arm: dts: rockchip: rk3288: partial sync pwm nodes
On 3/15/23 15:05, Simon Glass wrote:
> Hi Johan,
>
> On Tue, 14 Mar 2023 at 12:16, Johan Jonker wrote:
>>
>> In order to better compare the Linux rk3288.dtsi
>> version 6.3 -rc2 with the u-boot version partial
>> sync the pwm nodes.
>>
>> Signed-off-by: Johan Jonker
>> ---
>> arch/arm/dts/rk3288.dtsi | 18 +-
>> 1 file changed, 5 insertions(+), 13 deletions(-)
>>
>> diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
>> index f24e9ba5..dd1d9897 100644
>> --- a/arch/arm/dts/rk3288.dtsi
>> +++ b/arch/arm/dts/rk3288.dtsi
>> @@ -675,9 +675,7 @@
>> #pwm-cells = <3>;
>> pinctrl-names = "default";
>> pinctrl-0 = <_pin>;
>> - clocks = < PCLK_PWM>;
>> - clock-names = "pwm";
>> - rockchip,grf = <>;
>> + clocks = < PCLK_RKPWM>;
>> status = "disabled";
>> };
>>
>> @@ -687,9 +685,7 @@
>> #pwm-cells = <3>;
>> pinctrl-names = "default";
>> pinctrl-0 = <_pin>;
>> - clocks = < PCLK_PWM>;
>> - clock-names = "pwm";
>> - rockchip,grf = <>;
>> + clocks = < PCLK_RKPWM>;
>> status = "disabled";
>> };
>>
>> @@ -699,21 +695,17 @@
>> #pwm-cells = <3>;
>> pinctrl-names = "default";
>> pinctrl-0 = <_pin>;
>> - clocks = < PCLK_PWM>;
>> - clock-names = "pwm";
>> - rockchip,grf = <>;
>> + clocks = < PCLK_RKPWM>;
>> status = "disabled";
>> };
>>
>> pwm3: pwm@ff680030 {
>> compatible = "rockchip,rk3288-pwm";
>> reg = <0xff680030 0x10>;
>> - #pwm-cells = <2>;
>> + #pwm-cells = <3>;
>
> How can we do this without breaking the existing pwm usage in U-Boot?
===
>From binding pwm-rockchip.yaml:
"#pwm-cells":
enum: [2, 3]
description:
Must be 2 (rk2928) or 3 (rk3288 and later).
See pwm.yaml for a description of the cell format.
===
>From binding pwm.txt:
pwm-specifier typically encodes the chip-relative PWM number and the PWM
period in nanoseconds.
Optionally, the pwm-specifier can encode a number of flags (defined in
) in a third cell:
- PWM_POLARITY_INVERTED: invert the PWM signal polarity
===
Fixed with patch:
[PATCH] ARM: dts: rockchip: fix pwm-cells for rk3288's pwm3
https://lore.kernel.org/all/20190603143435.23352-1-j...@metanate.com/
===
U-Boot driver is ready:
static const struct rockchip_pwm_data pwm_data_v2 = {
[..]
.supports_polarity = true,
[..]
};
{ .compatible = "rockchip,rk3288-pwm", .data = (ulong)_data_v2},
===
git grep "pwms = <" | grep rk3288
rk3288-evb.dtsi:pwms = < 0 25000 0>;
rk3288-veyron.dtsi: pwms = < 0 100 0>;
rk3288-veyron.dtsi: pwms = < 0 2000 0>;
Given that there are no current users and the driver supports polarity I think
it's save to set #pwm-cells to 3.
(Unless someone calls out a specific case not to change)
Johan
>
>> pinctrl-names = "default";
>> pinctrl-0 = <_pin>;
>> - clocks = < PCLK_PWM>;
>> - clock-names = "pwm";
>> - rockchip,grf = <>;
>> + clocks = < PCLK_RKPWM>;
>> status = "disabled";
>> };
>>
>> --
>> 2.20.1
>>
>
> Regards,
> Simon
[PATCH v2 6/7] clk: rockchip: clk_rk3288: add PCLK_RKPWM
The rk3288 pwm nodes synced from Linux make use of PCLK_RKPWM instead of PCLK_PWM. They have the same pclk_cpu parent, so add PCLK_RKPWM to rk3288_clk_get_rate(). Signed-off-by: Johan Jonker Reviewed-by: Simon Glass Tested-by: Simon Glass # chromebook-jerry --- drivers/clk/rockchip/clk_rk3288.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 3b29992c..ef744c06 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -778,6 +778,7 @@ static ulong rk3288_clk_get_rate(struct clk *clk) case PCLK_I2C5: return gclk_rate; case PCLK_PWM: + case PCLK_RKPWM: return PD_BUS_PCLK_HZ; case SCLK_SARADC: new_rate = rockchip_saradc_get_clk(priv->cru); -- 2.20.1
[PATCH v2 4/7] arm: dts: rockchip: rk3288: partial sync edp node
The rk3288 edp node has a phy node in Linux with a clock
property while current U-Boot driver expects this clock
on position index 1. Move U-Boot-specific DT clock properties
to rk3288-u-boot.dtsi and partially sync the edp node.
Signed-off-by: Johan Jonker
Reviewed-by: Simon Glass
Tested-by: Simon Glass # chromebook-jerry
---
arch/arm/dts/rk3288-u-boot.dtsi | 5 +
arch/arm/dts/rk3288.dtsi| 17 +++--
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi
index e411445e..ca229150 100644
--- a/arch/arm/dts/rk3288-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-u-boot.dtsi
@@ -91,6 +91,11 @@
u-boot,dm-pre-reloc;
};
+ {
+ clocks = < SCLK_EDP>, < SCLK_EDP_24M>, < PCLK_EDP_CTRL>;
+ clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
+};
+
{
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index f06d1f5b..9f924466 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -1177,19 +1177,24 @@
};
edp: dp@ff97 {
- compatible = "rockchip,rk3288-edp";
+ compatible = "rockchip,rk3288-dp";
reg = <0xff97 0x4000>;
interrupts = ;
- clocks = < SCLK_EDP>, < SCLK_EDP_24M>, <
PCLK_EDP_CTRL>;
- clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
+ clocks = < SCLK_EDP>, < PCLK_EDP_CTRL>;
+ clock-names = "dp", "pclk";
+ phys = <_phy>;
+ phy-names = "dp";
+ power-domains = < RK3288_PD_VIO>;
resets = < SRST_EDP>;
- reset-names = "edp";
+ reset-names = "dp";
rockchip,grf = <>;
- power-domains = < RK3288_PD_VIO>;
status = "disabled";
ports {
- edp_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_in: port@0 {
+ reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
edp_in_vopb: endpoint@0 {
--
2.20.1
[PATCH v2 5/7] arm: dts: rockchip: rk3288: partial sync vop/lvds/mipi/hdmi nodes
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the vop/lvds/mipi/hdmi nodes.
Signed-off-by: Johan Jonker
Reviewed-by: Simon Glass
Tested-by: Simon Glass # chromebook-jerry
---
arch/arm/dts/rk3288.dtsi | 48
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 9f924466..f24e9ba5 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -1021,7 +1021,7 @@
vopb: vop@ff93 {
compatible = "rockchip,rk3288-vop";
- reg = <0xff93 0x19c>;
+ reg = <0xff93 0x19c>, <0xff931000 0x1000>;
interrupts = ;
clocks = < ACLK_VOP0>, < DCLK_VOP0>, < HCLK_VOP0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -1035,24 +1035,24 @@
#address-cells = <1>;
#size-cells = <0>;
- vopb_out_edp: endpoint@0 {
+ vopb_out_hdmi: endpoint@0 {
reg = <0>;
- remote-endpoint = <_in_vopb>;
+ remote-endpoint = <_in_vopb>;
};
- vopb_out_hdmi: endpoint@1 {
+ vopb_out_edp: endpoint@1 {
reg = <1>;
- remote-endpoint = <_in_vopb>;
+ remote-endpoint = <_in_vopb>;
};
- vopb_out_lvds: endpoint@2 {
+ vopb_out_mipi: endpoint@2 {
reg = <2>;
- remote-endpoint = <_in_vopb>;
+ remote-endpoint = <_in_vopb>;
};
- vopb_out_mipi: endpoint@3 {
+ vopb_out_lvds: endpoint@3 {
reg = <3>;
- remote-endpoint = <_in_vopb>;
+ remote-endpoint = <_in_vopb>;
};
};
};
@@ -1070,7 +1070,7 @@
vopl: vop@ff94 {
compatible = "rockchip,rk3288-vop";
- reg = <0xff94 0x19c>;
+ reg = <0xff94 0x19c>, <0xff941000 0x1000>;
interrupts = ;
clocks = < ACLK_VOP1>, < DCLK_VOP1>, < HCLK_VOP1>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -1084,24 +1084,24 @@
#address-cells = <1>;
#size-cells = <0>;
- vopl_out_edp: endpoint@0 {
+ vopl_out_hdmi: endpoint@0 {
reg = <0>;
- remote-endpoint = <_in_vopl>;
+ remote-endpoint = <_in_vopl>;
};
- vopl_out_hdmi: endpoint@1 {
+ vopl_out_edp: endpoint@1 {
reg = <1>;
- remote-endpoint = <_in_vopl>;
+ remote-endpoint = <_in_vopl>;
};
- vopl_out_lvds: endpoint@2 {
+ vopl_out_mipi: endpoint@2 {
reg = <2>;
- remote-endpoint = <_in_vopl>;
+ remote-endpoint = <_in_vopl>;
};
- vopl_out_mipi: endpoint@3 {
+ vopl_out_lvds: endpoint@3 {
reg = <3>;
- remote-endpoint = <_in_vopl>;
+ remote-endpoint = <_in_vopl>;
};
};
};
@@ -1118,11 +1118,11 @@
};
mipi_dsi: mipi@ff96 {
- compatible = "rockchip,rk3288_mipi_dsi";
+ compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0xff96 0x4000>;
interrupts = ;
- clocks = < PCLK_MIPI_DSI0>;
- clock-names = "pclk_mipi";
+ clocks = < SCLK_MIPIDSI_24M>, < PCLK_MIPI_DSI0>;
+ clock-names = "ref", "pclk";
power-domains = < RK3288_PD_VIO>;
rockchip,grf = <>;
status = "disabled";
@@ -1148,7 +1148,7 @@
reg = <0xff96c000 0x4000>;
clocks = < PCLK_LVDS_PHY>;
clock-names = "pclk_lvds";
- pinctrl-names = "default";
+ pinctrl-names = "lcdc";
pinctrl-0 = <_ctl>;
power-domains = < RK3288_PD_VIO>;
rockchip,grf = <>;
@@ -1216,8 +1216,8 @@
#sound-dai-cells = <0>;
rockchip,grf = <>;
[PATCH v2 7/7] arm: dts: rockchip: rk3288: partial sync pwm nodes
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the pwm nodes.
Signed-off-by: Johan Jonker
---
arch/arm/dts/rk3288.dtsi | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index f24e9ba5..dd1d9897 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -675,9 +675,7 @@
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <_pin>;
- clocks = < PCLK_PWM>;
- clock-names = "pwm";
- rockchip,grf = <>;
+ clocks = < PCLK_RKPWM>;
status = "disabled";
};
@@ -687,9 +685,7 @@
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <_pin>;
- clocks = < PCLK_PWM>;
- clock-names = "pwm";
- rockchip,grf = <>;
+ clocks = < PCLK_RKPWM>;
status = "disabled";
};
@@ -699,21 +695,17 @@
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <_pin>;
- clocks = < PCLK_PWM>;
- clock-names = "pwm";
- rockchip,grf = <>;
+ clocks = < PCLK_RKPWM>;
status = "disabled";
};
pwm3: pwm@ff680030 {
compatible = "rockchip,rk3288-pwm";
reg = <0xff680030 0x10>;
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <_pin>;
- clocks = < PCLK_PWM>;
- clock-names = "pwm";
- rockchip,grf = <>;
+ clocks = < PCLK_RKPWM>;
status = "disabled";
};
--
2.20.1
Re: [PATCH v3] binman: bintool: Add support for tool directories
Hi Neha, On Mon, 13 Mar 2023 at 21:41, Neha Malcom Francis wrote: > > Hi Simon > > On 11/03/23 07:17, Simon Glass wrote: > > Hi Neha, > > > > On Fri, 24 Feb 2023 at 03:51, Neha Malcom Francis wrote: > >> > >> Currently, bintool supports external compilable tools as single > >> executable files. Adding support for git repos that can be used to run > >> non-compilable scripting tools that cannot otherwise be present in > >> binman. > >> > >> Signed-off-by: Neha Malcom Francis > >> --- > >> Changes in v3: > >> - moved back to using DOWNLOAD_DIR as community is making > >>relevant changes > >> - extended coverage for bintool_test.py > >> - added function comment for new parameter > >> > >> Changes in v2: > >> - added parameter to obtain path to download the directory > >>optionally, enables flexibility to avoid using > >>DOWNLOAD_DESTDIR > >> - added test to bintool_test.py > >> - s/FETCH_NO_BUILD/FETCH_SOURCE > >> - code reformatting > >> > >> tools/binman/bintool.py| 47 +- > >> tools/binman/bintool_test.py | 43 +++ > >> tools/binman/btool/_testing.py | 4 +++ > >> tools/patman/tools.py | 2 +- > >> 4 files changed, 88 insertions(+), 8 deletions(-) > > > > I am OK with doing this but worried that it will be used for shell > > scripts, which we are trying to avoid. > > > > The code looks OK for now. Perhaps we can revisit this when we have a > > use case? I also think we should have each tool individually shown in > > the list, rather than having them be 'hidden' behind a btool. > > > > I get the intention, let me know your reply to our thread [1] and we can > work on it from there. OK I replied to that. - Simon > [1] > https://patchwork.ozlabs.org/project/uboot/patch/20230224120340.587786-1-n-fran...@ti.com/ > > -- > Thanking You > Neha Malcom Francis
[PATCH] Revert 9f62a472dfb2 ("video: Remove duplicate cursor-positioning function")
This reverts commit 9f62a472dfb26ec14408a27938ddd2a2579d.
The changes here aren't quite right, and on platforms such as Raspberry
Pi where we can have both serial and video output, the change above
causes output to change. This can be seen as the hush tests we have now
fail.
Signed-off-by: Tom Rini
---
Cc: Simon Glass
Some other issues in my lab meant I thought I had tested this platform
when I took the PR in originally, but hadn't. So I'd like to grab this
ASAP.
---
drivers/video/vidconsole-uclass.c | 44 ---
1 file changed, 34 insertions(+), 10 deletions(-)
diff --git a/drivers/video/vidconsole-uclass.c
b/drivers/video/vidconsole-uclass.c
index 61f4216750f2..1225de233325 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -126,14 +126,26 @@ void vidconsole_set_cursor_pos(struct udevice *dev, int
x, int y)
priv->ycur = y;
}
-void vidconsole_position_cursor(struct udevice *dev, uint col, uint row)
+/**
+ * set_cursor_position() - set cursor position
+ *
+ * @priv: private data of the video console
+ * @row: new row
+ * @col: new column
+ */
+static void set_cursor_position(struct vidconsole_priv *priv, int row, int col)
{
- struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
- short x, y;
-
- x = min_t(short, col, priv->cols - 1) * priv->x_charsize;
- y = min_t(short, row, priv->rows - 1) * priv->y_charsize;
- vidconsole_set_cursor_pos(dev, x, y);
+ /*
+* Ensure we stay in the bounds of the screen.
+*/
+ if (row >= priv->rows)
+ row = priv->rows - 1;
+ if (col >= priv->cols)
+ col = priv->cols - 1;
+
+ priv->ycur = row * priv->y_charsize;
+ priv->xcur_frac = priv->xstart_frac +
+ VID_TO_POS(col * priv->x_charsize);
}
/**
@@ -180,7 +192,7 @@ static void vidconsole_escape_char(struct udevice *dev,
char ch)
int row = priv->row_saved;
int col = priv->col_saved;
- vidconsole_position_cursor(dev, col, row);
+ set_cursor_position(priv, row, col);
priv->escape = 0;
return;
}
@@ -242,7 +254,7 @@ static void vidconsole_escape_char(struct udevice *dev,
char ch)
if (row < 0)
row = 0;
/* Right and bottom overflows are handled in the callee. */
- vidconsole_position_cursor(dev, col, row);
+ set_cursor_position(priv, row, col);
break;
}
case 'H':
@@ -266,7 +278,7 @@ static void vidconsole_escape_char(struct udevice *dev,
char ch)
if (col)
--col;
- vidconsole_position_cursor(dev, col, row);
+ set_cursor_position(priv, row, col);
break;
}
@@ -655,3 +667,15 @@ int vidconsole_clear_and_reset(struct udevice *dev)
return 0;
}
+
+void vidconsole_position_cursor(struct udevice *dev, unsigned col, unsigned
row)
+{
+ struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
+ struct udevice *vid_dev = dev->parent;
+ struct video_priv *vid_priv = dev_get_uclass_priv(vid_dev);
+ short x, y;
+
+ x = min_t(short, col * priv->x_charsize, vid_priv->xsize - 1);
+ y = min_t(short, row * priv->y_charsize, vid_priv->ysize - 1);
+ vidconsole_set_cursor_pos(dev, x, y);
+}
--
2.34.1
[PATCH v2 1/7] arm: dts: rockchip: rk3288: move io-domains nodes
In order to better compare the Linux rk3288.dtsi version
with the U-Boot version move the io-domains nodes.
Signed-off-by: Johan Jonker
Reviewed-by: John Keeping
Reviewed-by: Simon Glass
Tested-by: Simon Glass # chromebook-jerry
---
arch/arm/dts/rk3288-miqi.dtsi| 27 +++--
arch/arm/dts/rk3288-phycore-som.dtsi | 30 +---
arch/arm/dts/rk3288-popmetal.dtsi| 30 +---
arch/arm/dts/rk3288-veyron.dtsi | 28 --
arch/arm/dts/rk3288.dtsi | 5 +
5 files changed, 58 insertions(+), 62 deletions(-)
diff --git a/arch/arm/dts/rk3288-miqi.dtsi b/arch/arm/dts/rk3288-miqi.dtsi
index cb80cbf2..00c8613d 100644
--- a/arch/arm/dts/rk3288-miqi.dtsi
+++ b/arch/arm/dts/rk3288-miqi.dtsi
@@ -18,21 +18,6 @@
clock-output-names = "ext_gmac";
};
- io_domains: io-domains {
- compatible = "rockchip,rk3288-io-voltage-domain";
- rockchip,grf = <>;
-
- audio-supply = <_33>;
- flash0-supply = <_flash>;
- flash1-supply = <_lan>;
- gpio30-supply = <_io>;
- gpio1830-supply = <_io>;
- lcdc-supply = <_io>;
- sdcard-supply = <_sd>;
- wifi-supply = <_18>;
- };
-
-
leds {
compatible = "gpio-leds";
@@ -277,6 +262,18 @@
status = "okay";
};
+_domains {
+ audio-supply = <_33>;
+ flash0-supply = <_flash>;
+ flash1-supply = <_lan>;
+ gpio30-supply = <_io>;
+ gpio1830-supply = <_io>;
+ lcdc-supply = <_io>;
+ sdcard-supply = <_sd>;
+ wifi-supply = <_18>;
+ status = "okay";
+};
+
{
pcfg_output_high: pcfg-output-high {
output-high;
diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi
b/arch/arm/dts/rk3288-phycore-som.dtsi
index 821525f7..70c00308 100644
--- a/arch/arm/dts/rk3288-phycore-som.dtsi
+++ b/arch/arm/dts/rk3288-phycore-som.dtsi
@@ -71,22 +71,6 @@
clock-output-names = "ext_gmac";
};
- io_domains: io_domains {
- compatible = "rockchip,rk3288-io-voltage-domain";
-
- status = "okay";
- sdcard-supply = <_io_sd>;
- flash0-supply = <_emmc_io>;
- flash1-supply = <_misc_1v8>;
- gpio1830-supply = <_3v3_io>;
- gpio30-supply = <_3v3_io>;
- bb-supply = <_3v3_io>;
- dvp-supply = <_3v3_io>;
- lcdc-supply = <_3v3_io>;
- wifi-supply = <_3v3_io>;
- audio-supply = <_3v3_io>;
- };
-
leds: user-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -197,6 +181,20 @@
ddc-i2c-bus = <>;
};
+_domains {
+ audio-supply = <_3v3_io>;
+ bb-supply = <_3v3_io>;
+ dvp-supply = <_3v3_io>;
+ flash0-supply = <_emmc_io>;
+ flash1-supply = <_misc_1v8>;
+ gpio1830-supply = <_3v3_io>;
+ gpio30-supply = <_3v3_io>;
+ lcdc-supply = <_3v3_io>;
+ sdcard-supply = <_io_sd>;
+ wifi-supply = <_3v3_io>;
+ status = "okay";
+};
+
{
status = "okay";
clock-frequency = <40>;
diff --git a/arch/arm/dts/rk3288-popmetal.dtsi
b/arch/arm/dts/rk3288-popmetal.dtsi
index 0253933a..d732a706 100644
--- a/arch/arm/dts/rk3288-popmetal.dtsi
+++ b/arch/arm/dts/rk3288-popmetal.dtsi
@@ -71,22 +71,6 @@
};
};
- io_domains: io-domains {
- compatible = "rockchip,rk3288-io-voltage-domain";
- rockchip,grf = <>;
-
- audio-supply = <_33>;
- bb-supply = <_io>;
- dvp-supply = <_dvp>;
- flash0-supply = <_flash>;
- flash1-supply = <_lan>;
- gpio30-supply = <_io>;
- gpio1830-supply = <_io>;
- lcdc-supply = <_io>;
- sdcard-supply = <_sd>;
- wifi-supply = <_wl>;
- };
-
ir: ir-receiver {
compatible = "gpio-ir-receiver";
gpios = < 6 GPIO_ACTIVE_LOW>;
@@ -443,6 +427,20 @@
status = "okay";
};
+_domains {
+ audio-supply = <_33>;
+ bb-supply = <_io>;
+ dvp-supply = <_dvp>;
+ flash0-supply = <_flash>;
+ flash1-supply = <_lan>;
+ gpio30-supply = <_io>;
+ gpio1830-supply = <_io>;
+ lcdc-supply = <_io>;
+ sdcard-supply = <_sd>;
+ wifi-supply = <_wl>;
+ status = "okay";
+};
+
{
ak8963 {
comp_int: comp-int {
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index 35db8827..434b0d49 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -198,21 +198,6 @@
/* Faux input supply. See bt_regulator description. */
vin-supply = <_regulator>;
};
-
-
Re: Please pull u-boot-dm/next
On Tue, Mar 14, 2023 at 04:07:57PM -0600, Simon Glass wrote: > Hi Tom, > > On Mon, 13 Mar 2023 at 13:36, Tom Rini wrote: > > > > On Sun, Mar 12, 2023 at 09:10:19PM -0600, Simon Glass wrote: > > > > > Hi Tom, > > > > > > This is for the -next branch > > > > > > > > > https://source.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/15568 > > > > > > The following changes since commit > > > bcf343146ff365a88481b9a80920ed146c6dee5b: > > > > > > Merge tag 'dm-next-9mar23' of > > > https://source.denx.de/u-boot/custodians/u-boot-dm into next > > > (2023-03-09 11:22:50 -0500) > > > > > > are available in the Git repository at: > > > > > > git://git.denx.de/u-boot-dm.git tags/dm-next-12mar23 > > > > > > for you to fetch changes up to 7bb28330f7b4d20bcf844ec306dcfbb41296cfa8: > > > > > > buildman: Fix CROSS_COMPILE output for sandbox (2023-03-12 11:37:34 > > > -0600) > > > > > > > There's something, or somethings, broken here now. Take a look at: > > https://source.denx.de/u-boot/u-boot/-/jobs/593223#L904 > > where now there's a bunch of warnings but we don't fail the build (nor > > That seems to have been going for a while. See: > > https://source.denx.de/u-boot/u-boot/-/jobs/593528 I don't see it there, no. The problem, to be clear, is warnings in C NOT leading to CI failing. -- Tom signature.asc Description: PGP signature
Re: i.MX8MP SPL failures due to memory corruption/overflow?
On 15.03.23 15:42, Frieder Schrempf wrote: > On 15.03.23 15:17, Michael Nazzareno Trimarchi wrote: >> Hi >> >> On Wed, Mar 15, 2023 at 3:13 PM Frieder Schrempf >> wrote: >>> >>> Hi, >>> >>> I'm trying to bring up a new board based on the i.MX8MP and I have an >>> issue I'm hoping someone can help solving. >>> >>> I'm seeing failures in the early SPL code, usually in the DDR >>> initialization. Often they look like: >>> >>> U-Boot SPL 2023.04-rc3 (Mar 07 2023 - 14:32:34 +) >>> Training FAILED >>> Failed to initialize DDR RAM! >>> ### ERROR ### Please RESET the board ### >>> >>> But sometimes ddr_init() doesn't even return an error and only the >>> get_ram_size() afterwards which tries to allocate the memory fails. >>> >> >> In my experience you don't have space inside the cpu internal memory. It >> means >> that you overlap some stack with the code. Change the printf means >> move a bit. So you have >> problem but depends what you are going to destroy > > Thanks for your reply. That's exactly what I'm thinking, too. > >> >>> The strange thing is that the issues appear or disappear >>> deterministically on the binary level. This means I sometimes get a >>> U-Boot binary which runs just fine in 100% of cases. Then I change for >>> example one of the following: >>> >>> * Adding a single printf() somewhere in the boards spl.c >>> * Using the same binary but booting from SD card instead of USB loader >>> * Using the same source but switching from the OS cross compiler to the >>> one from Yocto/OE >>> >>> And afterwards I get 100% failure rate with an error as described above. >>> >>> My suspicion is that there is some memory corruption/conflict. My SPL is >>> quite large and I wonder if it exceeds some limit. >>> >>> SPL is loaded to 0x92 and CONFIG_SPL_STACK is set to 0x96, which >>> leaves 256 KiB in between for the SPL. But all i.MX8MP boards seem to >>> set CONFIG_SPL_MAX_SIZE=0x26000 (152 KiB) for some reason. My >>> u-boot-spl-ddr.bin currently has around 193 KiB but I don't get any >>> warning about exceeding the SPL_MAX_SIZE. >>> >>> My questions: >>> >>> * Why is CONFIG_SPL_MAX_SIZE set to 152 KiB? > > I guess the remainder between the SPL code and the SPL stack is for the > DDR firmware. Which explains why I get failures with SPL exceeding 152 > KiB size. Still, it doesn't really make sense to me at the moment as the u-boot-spl-ddr.bin already contains the DDR firmware it should be fine to exceed the 152 KiB size. My u-boot-spl.bin (without DDR firmware) is only 135 KiB. Sorry for spamming you by thinking out loud... ;) > > Now I also understand the reason why the power init code was implemented > using legacy non-DM drivers in other i.MX8MP boards. I probably also > need to do this to save some space. > >>> * Why is there no warning in my case? > > Still, I fail to see why there isn't any error or where the size check > is even implemented. > >>> * Any other ideas or pointers? >>> >>> Thanks for your help! >>> >>> Best regards >>> Frieder
Re: i.MX8MP SPL failures due to memory corruption/overflow?
On 15.03.23 15:17, Michael Nazzareno Trimarchi wrote: > Hi > > On Wed, Mar 15, 2023 at 3:13 PM Frieder Schrempf > wrote: >> >> Hi, >> >> I'm trying to bring up a new board based on the i.MX8MP and I have an >> issue I'm hoping someone can help solving. >> >> I'm seeing failures in the early SPL code, usually in the DDR >> initialization. Often they look like: >> >> U-Boot SPL 2023.04-rc3 (Mar 07 2023 - 14:32:34 +) >> Training FAILED >> Failed to initialize DDR RAM! >> ### ERROR ### Please RESET the board ### >> >> But sometimes ddr_init() doesn't even return an error and only the >> get_ram_size() afterwards which tries to allocate the memory fails. >> > > In my experience you don't have space inside the cpu internal memory. It means > that you overlap some stack with the code. Change the printf means > move a bit. So you have > problem but depends what you are going to destroy Thanks for your reply. That's exactly what I'm thinking, too. > >> The strange thing is that the issues appear or disappear >> deterministically on the binary level. This means I sometimes get a >> U-Boot binary which runs just fine in 100% of cases. Then I change for >> example one of the following: >> >> * Adding a single printf() somewhere in the boards spl.c >> * Using the same binary but booting from SD card instead of USB loader >> * Using the same source but switching from the OS cross compiler to the >> one from Yocto/OE >> >> And afterwards I get 100% failure rate with an error as described above. >> >> My suspicion is that there is some memory corruption/conflict. My SPL is >> quite large and I wonder if it exceeds some limit. >> >> SPL is loaded to 0x92 and CONFIG_SPL_STACK is set to 0x96, which >> leaves 256 KiB in between for the SPL. But all i.MX8MP boards seem to >> set CONFIG_SPL_MAX_SIZE=0x26000 (152 KiB) for some reason. My >> u-boot-spl-ddr.bin currently has around 193 KiB but I don't get any >> warning about exceeding the SPL_MAX_SIZE. >> >> My questions: >> >> * Why is CONFIG_SPL_MAX_SIZE set to 152 KiB? I guess the remainder between the SPL code and the SPL stack is for the DDR firmware. Which explains why I get failures with SPL exceeding 152 KiB size. Now I also understand the reason why the power init code was implemented using legacy non-DM drivers in other i.MX8MP boards. I probably also need to do this to save some space. >> * Why is there no warning in my case? Still, I fail to see why there isn't any error or where the size check is even implemented. >> * Any other ideas or pointers? >> >> Thanks for your help! >> >> Best regards >> Frieder > > >
[PATCH v4] pinctrl: rockchip: support rk3588 pinctrl
From: Jianqun Xu
Add support for Rockchip rk3588 variant of pinctrl.
The driver is adapted from the Linux driver.
Signed-off-by: Jianqun Xu
[eugen.hris...@collabora.com:
port to latest U-boot, bring more changes from Linux
use translated pull values table]
Signed-off-by: Eugen Hristev
---
Changes in v4:
- After checking with what happens in Linux, it appears that the gpio4
D0-D5 also work using VCCIO2, just that the value written by Uboot
appears to be wrongly computed. Linux and other drivers like rk3568
use a translated pull value. Adapt also the r3588 to use this translated
value. Now the arrays are identical with Linux
Changes in v3:
- change assert(i) to assert (i >= 0) because i==0 is a valid number it's
the first entry in the array. Otherwise it would assert wrongly when setting
gpio 0 A2 e.g.
Changes in v2:
- change the way the reg is computed to align with Linux
- For the gpio4 bank D0-8, as the downstream uboot uses VCCIO6 instead of
VCCIO2, change accordingly, otherwise D0-D5 pins won't work to set PUP/PDOWN,
DS, etc. It appears gpio4D has the registers just after gpio4A,gpio4B,gpio4C
in the same VCCIO6, and not in VCCIO2.
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rk3588.c | 353
drivers/pinctrl/rockchip/pinctrl-rockchip.h | 187 +++
3 files changed, 541 insertions(+)
create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3588.c
diff --git a/drivers/pinctrl/rockchip/Makefile
b/drivers/pinctrl/rockchip/Makefile
index 90461ae8819a..c91f650b0434 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -15,5 +15,6 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
+obj-$(CONFIG_ROCKCHIP_RK3588) += pinctrl-rk3588.o
obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3588.c
b/drivers/pinctrl/rockchip/pinctrl-rk3588.c
new file mode 100644
index ..548cf09bcca4
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3588.c
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-rockchip.h"
+#include
+
+static int rk3588_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ struct regmap *regmap;
+ int iomux_num = (pin / 8);
+ int reg, ret, mask;
+ u8 bit;
+ u32 data;
+
+ debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
+
+ regmap = priv->regmap_base;
+ reg = bank->iomux[iomux_num].offset;
+ if ((pin % 8) >= 4)
+ reg += 0x4;
+ bit = (pin % 4) * 4;
+ mask = 0xf;
+
+ if (bank->bank_num == 0) {
+ if (pin >= RK_PB4 && pin <= RK_PD7) {
+ if (mux < 8) {
+ reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+ ret = regmap_write(regmap, reg, data);
+ } else {
+ u32 reg0 = 0;
+
+ reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
+ data = (mask << (bit + 16));
+ data |= 8 << bit;
+ ret = regmap_write(regmap, reg0, data);
+
+ reg0 = reg + 0x8000; /* BUS_IOC_BASE */
+ data = (mask << (bit + 16));
+ data |= mux << bit;
+ regmap = priv->regmap_base;
+ regmap_write(regmap, reg0, data);
+ }
+ } else {
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+ ret = regmap_write(regmap, reg, data);
+ }
+ return ret;
+ } else if (bank->bank_num > 0) {
+ reg += 0x8000; /* BUS_IOC_BASE */
+ }
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+
+ return regmap_write(regmap, reg, data);
+}
+
+#define RK3588_PMU1_IOC_REG(0x)
+#define RK3588_PMU2_IOC_REG(0x4000)
+#define RK3588_BUS_IOC_REG (0x8000)
+#define RK3588_VCCIO1_4_IOC_REG(0x9000)
+#define RK3588_VCCIO3_5_IOC_REG(0xA000)
+#define RK3588_VCCIO2_IOC_REG (0xB000)
+#define RK3588_VCCIO6_IOC_REG (0xC000)
+#define RK3588_EMMC_IOC_REG(0xD000)
+
+static const u32 rk3588_ds_regs[][2] = {
+
Re: i.MX8MP SPL failures due to memory corruption/overflow?
On 15/03/2023 16.24, Frieder Schrempf wrote:
> On 15.03.23 15:42, Frieder Schrempf wrote:
>> On 15.03.23 15:17, Michael Nazzareno Trimarchi wrote:
>>> Hi
>>>
>>> On Wed, Mar 15, 2023 at 3:13 PM Frieder Schrempf
>>> wrote:
Hi,
I'm trying to bring up a new board based on the i.MX8MP and I have an
issue I'm hoping someone can help solving.
I'm seeing failures in the early SPL code, usually in the DDR
initialization. Often they look like:
U-Boot SPL 2023.04-rc3 (Mar 07 2023 - 14:32:34 +)
Training FAILED
Failed to initialize DDR RAM!
### ERROR ### Please RESET the board ###
But sometimes ddr_init() doesn't even return an error and only the
get_ram_size() afterwards which tries to allocate the memory fails.
>>>
>>> In my experience you don't have space inside the cpu internal memory. It
>>> means
>>> that you overlap some stack with the code. Change the printf means
>>> move a bit. So you have
>>> problem but depends what you are going to destroy
>>
>> Thanks for your reply. That's exactly what I'm thinking, too.
>>
>>>
The strange thing is that the issues appear or disappear
deterministically on the binary level. This means I sometimes get a
U-Boot binary which runs just fine in 100% of cases. Then I change for
example one of the following:
* Adding a single printf() somewhere in the boards spl.c
* Using the same binary but booting from SD card instead of USB loader
* Using the same source but switching from the OS cross compiler to the
one from Yocto/OE
And afterwards I get 100% failure rate with an error as described above.
My suspicion is that there is some memory corruption/conflict. My SPL is
quite large and I wonder if it exceeds some limit.
SPL is loaded to 0x92 and CONFIG_SPL_STACK is set to 0x96, which
leaves 256 KiB in between for the SPL. But all i.MX8MP boards seem to
set CONFIG_SPL_MAX_SIZE=0x26000 (152 KiB) for some reason. My
u-boot-spl-ddr.bin currently has around 193 KiB but I don't get any
warning about exceeding the SPL_MAX_SIZE.
I also ran into this problem a while back, but that was back when the
ddr firmware files were padded to 16K and 32K each to make the magic
offset computations work; now that binman symbols are used, they only
take up as much space as they actually use (give or take some 4-byte
padding perhaps), and I no longer need the debug code I put in place in
our 2022.07 branch.
Remember that from the stack, the initial (and in SPL only) malloc arena
is carved out, and if you haven't adjusted SPL_SYS_MALLOC_F_LEN, you
probably have that set to the default SYS_MALLOC_F_LEN, which in turn
(on imx8m) defaults to 0x1 aka 64KiB. So that could easily explain
why you collide with the firmware.
Maybe you can use the debug code I added to our copy of spl.c; I also
include most of my commit-message-for-future-me. But just something as
simple as
int dummy;
printf("stack is around %p\n", );
can be quite valuable.
===
add sanity check of SPL stack versus DDR firmware
The DDR firmware blobs are added via binman to the end of the SPL, and
they are found by the DDR init code via somewhat magic offset
tricks. To make those offset tricks work, binman has to pad the
firmware files to known sizes of 32KiB and 16KiB, so all four files
end up occupying 2*(32+16) = 96KiB in the image.
Since the SPL image is loaded at 0x92, and we use a stack growing
down from 0x96 (recently changed to 0x968000), from which we also
carve out space for the malloc arena and global data, there's a risk
that normal use of the stack accidentally overwrites parts of the
firmware data. That's exactly what happened when I added another 14K
table of DDR training data.
We can compute exactly where the firmware lives, and also where our
stack starts (after the mentioned reservations), so to help future me,
do a sanity check as soon as we have the console. We might already
have scribbled over the DDR firmware (the main stack use is actually
in the DM init code which runs before we do), but at least we then now
to stop and tell the developer what's wrong, instead of just silently
failing when loading corrupt firmware.
#include
#include
#include
+#include
#include
#include
@@ -102,6 +103,35 @@ int board_fit_config_name_match(const char *name)
}
#endif
+#define TOP_OF_STACK \
+ ((CONFIG_SPL_STACK - CONFIG_VAL(SYS_MALLOC_F_LEN) - sizeof(struct
global_data)) & ~15);
+
+static void check_stack_versus_ddr_firmware(void)
+{
+ unsigned long fdt_end = roundup((unsigned long)&_end +
fdt_totalsize(gd->fdt_blob), 4);
+ unsigned long ddr_firmware_end = fdt_end + 2*(16 + 32)*1024;
+ unsigned long top_of_stack = TOP_OF_STACK;
+ unsigned long available = top_of_stack - ddr_firmware_end;
+
+ if (0) {
+ printf("fdt_end = 0x%08lx\n", fdt_end);
+
Re: [PATCH] Revert 9f62a472dfb2 ("video: Remove duplicate cursor-positioning function")
On Wed, 15 Mar 2023 at 10:01, Tom Rini wrote: > > This reverts commit 9f62a472dfb26ec14408a27938ddd2a2579d. > > The changes here aren't quite right, and on platforms such as Raspberry > Pi where we can have both serial and video output, the change above > causes output to change. This can be seen as the hush tests we have now > fail. > > Signed-off-by: Tom Rini > --- > Cc: Simon Glass > > Some other issues in my lab meant I thought I had tested this platform > when I took the PR in originally, but hadn't. So I'd like to grab this > ASAP. > --- > drivers/video/vidconsole-uclass.c | 44 --- > 1 file changed, 34 insertions(+), 10 deletions(-) > Reviewed-by: Simon Glass I'll give it another go
[PATCH v2 3/7] video: rockchip: rk_vop: add rk3288-dp compare string
In the current rk3288.dtsi file the compatible string for
the DisplayPort(DP) node ends with "edp". The string in the
binding ends with "dp" which conflicts with "cdn-dp" as a
search term. Add "rk3288-dp" as compare string to select
vop_id.
Signed-off-by: Johan Jonker
Reviewed-by: Simon Glass
Tested-by: Simon Glass # chromebook-jerry
---
drivers/video/rockchip/rk_vop.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index bc98ab68..e21ac7e3 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -307,7 +307,8 @@ static int rk_display_init(struct udevice *dev, ulong
fbbase, ofnode ep_node)
__func__, dev_read_name(dev));
return -EINVAL;
}
- if (strstr(compat, "edp")) {
+ if (strstr(compat, "edp") ||
+ strstr(compat, "rk3288-dp")) {
vop_id = VOP_MODE_EDP;
} else if (strstr(compat, "mipi")) {
vop_id = VOP_MODE_MIPI;
--
2.20.1
[PATCH v2 2/7] arm: dts: rockchip: rk3288: partial sync grf and pmu nodes
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the grf and pmu nodes.
Signed-off-by: Johan Jonker
Reviewed-by: Simon Glass
Tested-by: Simon Glass # chromebook-jerry
---
arch/arm/dts/rk3288.dtsi | 269 +--
1 file changed, 173 insertions(+), 96 deletions(-)
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 9cfb86f9..f06d1f5b 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include
#include
@@ -7,13 +7,16 @@
#include
#include
#include
-#include
-#include "skeleton.dtsi"
+#include
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
compatible = "rockchip,rk3288";
interrupt-parent = <>;
+
aliases {
ethernet0 =
i2c0 =
@@ -732,8 +735,128 @@
};
pmu: power-management@ff73 {
- compatible = "rockchip,rk3288-pmu", "syscon";
+ compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
reg = <0xff73 0x100>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3288-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ assigned-clocks = < SCLK_EDP_24M>;
+ assigned-clock-parents = <>;
+
+ /*
+* Note: Although SCLK_* are the working clocks
+* of device without including on the NOC, needed for
+* synchronous reset.
+*
+* The clocks on the which NOC:
+* ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
+* ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
+* ACLK_RGA is on ACLK_RGA_NIU.
+* The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
+*
+* Which clock are device clocks:
+* clocks devices
+* *_IEP IEP:Image Enhancement Processor
+* *_ISP ISP:Image Signal Processing
+* *_VIP VIP:Video Input Processor
+* *_VOP* VOP:Visual Output Processor
+* *_RGA RGA
+* *_EDP* EDP
+* *_LVDS_*LVDS
+* *_HDMI HDMI
+* *_MIPI_*MIPI
+*/
+ power-domain@RK3288_PD_VIO {
+ reg = ;
+ clocks = < ACLK_IEP>,
+< ACLK_ISP>,
+< ACLK_RGA>,
+< ACLK_VIP>,
+< ACLK_VOP0>,
+< ACLK_VOP1>,
+< DCLK_VOP0>,
+< DCLK_VOP1>,
+< HCLK_IEP>,
+< HCLK_ISP>,
+< HCLK_RGA>,
+< HCLK_VIP>,
+< HCLK_VOP0>,
+< HCLK_VOP1>,
+< PCLK_EDP_CTRL>,
+< PCLK_HDMI_CTRL>,
+< PCLK_LVDS_PHY>,
+< PCLK_MIPI_CSI>,
+< PCLK_MIPI_DSI0>,
+< PCLK_MIPI_DSI1>,
+< SCLK_EDP_24M>,
+< SCLK_EDP>,
+< SCLK_ISP_JPE>,
+< SCLK_ISP>,
+< SCLK_RGA>;
+ pm_qos = <_vio0_iep>,
+<_vio1_vop>,
+<_vio1_isp_w0>,
+<_vio1_isp_w1>,
+<_vio0_vop>,
+<_vio0_vip>,
+<_vio2_rga_r>,
+<_vio2_rga_w>,
+<_vio1_isp_r>;
+ #power-domain-cells = <0>;
+ };
+
+ /*
Re: [PATCH] board_r: Relocate OF_EMBED if NEEDS_MANUAL_RELOC only
Hi Ajay, On Wed, 15 Mar 2023 at 13:24, Ajay Kaher wrote: > > > On Fri, Sep 09, 2022 at 09:16:18PM +0100, Pierre-Clément Tosi wrote: > > > >> When the embedded device tree is pointed to by the __dtb_dt_*begin > >> symbols, it seems to be covered by the early relocation code and doesn't > >> need to be manually patched. > >> > >> Cc: Simon Glass > >> Signed-off-by: Pierre-Clément Tosi > > > > Applied to u-boot/master, thanks! > > Getting following error on Rpi3 board and fail to boot with u-boot upstream > commit 76f921eb95d5b814f973a263187db509d6f03903: > > ERROR: invalid device tree > EFI LOAD FAILED: continuing... > > As per bdinfo: > fdt_blob= 0x000f4b00 > > Would like to understand the reasoning of this upstream commit > 76f921eb95d5b814f973a263187db509d6f03903 and looking for proper fix for Rpi3. > > -Ajay Did you bisect to that patch? The proper fix would be to get away from OF_EMBED which is not allowed in production boards. Can you post the full console log so I can see what happens before the error? The commit does not look correct to me. This is nothing to do with the horrible NEEDS_MANUAL_RELOC which is only needed on m68k I think now. It is because we have moved the executable containing the DT. The DT in the old position may be overwritten by loading something. Regards, Simon
Re: [PATCH] console: Use flush() before panic and reset
On Tue, 14 Mar 2023 at 18:24, Tony Dinh wrote: > > To make sure the panic and the reset messages will go out, console flush() > should be used. > Sleep periods do not work in early u-boot phase when timer driver is not > initialized yet. > > Reference: https://lists.denx.de/pipermail/u-boot/2023-March/512233.html > > Signed-off-by: Tony Dinh > --- > > arch/arm/lib/reset.c | 4 ++-- > lib/panic.c | 4 +++- > 2 files changed, 5 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c > index 95169bae1c..3e051e36f1 100644 > --- a/arch/arm/lib/reset.c > +++ b/arch/arm/lib/reset.c > @@ -25,6 +25,7 @@ > #include > #include > #include > +#include Reviewed-by: Simon Glass Is flush implemented widely?
Re: [PATCH v3] cmd: fdt: Use env_set_hex() for "get addr" and "get size"
On Sat, 11 Mar 2023 at 09:29, Marek Vasut wrote: > > The 'fdt get addr' and 'env get size' is always assumed to be hex > value, drop the prefix, and outright switch to env_set_hex(). Since > this might break existing users who depend on the existing behavior > with 0x prefix, this is a separate patch. > > Revert if this breaks anything. > > Signed-off-by: Marek Vasut > --- > Cc: Heinrich Schuchardt > Cc: Simon Glass > Cc: Tom Rini > --- > V2: - Use env_set_hex() instead > - Update env get size too > V3: Rebase on dm/next > --- > cmd/fdt.c | 13 ++--- > 1 file changed, 2 insertions(+), 11 deletions(-) > Reviewed-by: Simon Glass
Re: [PATCH 12/12] rockchip: Convert rk35xx to use standard boot
On Mon, 13 Mar 2023 at 18:38, Jonas Karlman wrote: > > Imply use of BOOTSTD and OF_LIBFDT_OVERLAY on RK3568 and RK3588. > Drop the use of scripts and rely on standard boot for all operation. > > Signed-off-by: Jonas Karlman > --- > arch/arm/mach-rockchip/Kconfig | 6 ++ > include/configs/rk3568_common.h | 9 +++-- > include/configs/rk3588_common.h | 9 +++-- > 3 files changed, 20 insertions(+), 4 deletions(-) Reviewed-by: Simon Glass
imx8mm/imx8mn hang on usb stop / ehci_shutdown
Greetings,
I'm seeing a hang on imx8mm-venice and imx8mn-venice boards which have
a USB host controller in host mode when ehci_shutdown() is called
(which is called for 'usb stop' as well as when booting a kernel once
'usb start' has been issued).
This appears to be caused by the ehci_shutdown() function,
specifically the write to the or_portsc register to set EHCI_PS_SUSP:
for (i = 0; i < max_ports; i++) {
reg = ehci_readl(>hcor->or_portsc[i]);
reg |= EHCI_PS_SUSP;
ehci_writel(>hcor->or_portsc[i], reg);
}
Does anyone else out there with an imx8mm/imx8mn board with usbotg1 or
usbotg2 configured with dr_mode="host" see this as well?
I'm not clear where the equivalent code would be in the Linux kernel
to compare with. I do know that commenting out the ehcI_write above
keeps ehci_shutdown from hanging but does cause the handshake to fail
on the next cmd that disables CMD_RUN and thus prints "EHCI failed to
shut down host controller.".
Any ideas?
Best Regards,
Tim
Re: [PATCH] arm: kirkwood: pogo v4: Use a more common format for stdout-path
Hi Pali,
On Wed, Mar 15, 2023 at 2:58 PM Pali Rohár wrote:
>
> On Wednesday 15 March 2023 14:56:52 Tony Dinh wrote:
> > The mainline Pogo V4 DTS uses a stdout-path format that is not
> > recognizable by u-boot. Change it to a commonly used format.
>
> Cannot we teach u-boot to understand also currently used format?
I assume it is good to document the fact that perhaps using
dm-pre-reloc tag (and later boot-phase tag) will overcome many odd
properties format in Linux DTS. We said dm-pre-reloc is a workaround,
but IMHO the tags are really good for u-boot, since u-boot is a
multi-phase boot loader. If a device like UART is needed in a certain
phase, we should say so.
Also at the moment, modifying the serial-uclass.c is something more
than I can chew. If I must do it myself, it will be a while. If
anybody wants to give it a try, please do so.
Thanks,
Tony
> > Note that this patch removes the previous workaround for this board
> > as discussed here:
> > https://lists.denx.de/pipermail/u-boot/2023-February/508936.html
> >
> > Signed-off-by: Tony Dinh
> > ---
> >
> > arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi | 9 ++---
> > 1 file changed, 6 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
> > b/arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
> > index f9e127234c..9bb97c6b6b 100644
> > --- a/arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
> > +++ b/arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
> > @@ -1,7 +1,10 @@
> > // SPDX-License-Identifier: GPL-2.0+
> > /*
> > * Copyright (C) 2023 Tony Dinh
> > - */
> > - {
> > - u-boot,dm-pre-reloc;
> > +*/
> > +
> > +/ {
> > + chosen {
> > + stdout-path =
> > + };
> > };
> > --
> > 2.30.2
> >
Re: Pull request: u-boot-sunxi/master DT update for v2023.04
On Tue, Mar 14, 2023 at 03:41:57PM +, Andre Przywara wrote: > Hi Tom, > > please pull these two patches containing just devicetree updates for > Allwinner boards. > I was still hoping for a review, since we cannot import the files > from the Linux tree verbatim, but managed to write some filter script that > convinced me that the changes are fine. > The files are from Linux v6.2-rc2, but are identical to the v6.2 release. > > Thanks, > Andre > > > The following changes since commit 33fb2d130e28982b488c2a54978031835ed2aa71: > > Merge tag 'dm-pull-29feb23' of > https://source.denx.de/u-boot/custodians/u-boot-dm (2023-03-01 16:07:24 -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-sunxi.git master > > for you to fetch changes up to 8e2c0ee3bafbc283b58b66d9007847a5a3ed07be: > > sunxi: dts: arm64: update devicetree files from Linux v6.2-rc2 (2023-03-05 > 23:33:14 +) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] Please pull u-boot-coldfire/master
On Wed, Mar 15, 2023 at 02:03:50AM +0100, Angelo Dureghello wrote: > The following changes since commit 88e08fc5f6e508eac46cd1dfb0379b11ae032c0a: > > Prepare v2023.04-rc4 (2023-03-13 20:52:48 -0400) > > are available in the Git repository at: > > git://git.denx.de/u-boot-coldfire.git master > > for you to fetch changes up to 791840fdc41d7e937158a6ac56e9316391fde7ab: > > board: m5253demo: remove floating point flash size calculation (2023-03-15 > 01:52:15 +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] console: Use flush() before panic and reset
Hi Simon, On Wed, Mar 15, 2023 at 12:43 PM Simon Glass wrote: > > On Tue, 14 Mar 2023 at 18:24, Tony Dinh wrote: > > > > To make sure the panic and the reset messages will go out, console flush() > > should be used. > > Sleep periods do not work in early u-boot phase when timer driver is not > > initialized yet. > > > > Reference: https://lists.denx.de/pipermail/u-boot/2023-March/512233.html > > > > Signed-off-by: Tony Dinh > > --- > > > > arch/arm/lib/reset.c | 4 ++-- > > lib/panic.c | 4 +++- > > 2 files changed, 5 insertions(+), 3 deletions(-) > > > > diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c > > index 95169bae1c..3e051e36f1 100644 > > --- a/arch/arm/lib/reset.c > > +++ b/arch/arm/lib/reset.c > > @@ -25,6 +25,7 @@ > > #include > > #include > > #include > > +#include > > Reviewed-by: Simon Glass > > Is flush implemented widely? Pali wrote that flush function and here was his comment on the referenced thread: "Moreover there is already new function named flush() which does "wait until stdout message was sent" and can be used instead of those sleeps. I have already did it on some places (see git history for flush function) but seems that you find some more." So I think the answer is not yet widely implemented. All the best, Tony
Re: [PATCH v2 5/5] test_vboot.py: include test of fdt_add_pubkey tool
On Fri, 2023-03-10 at 17:46 -0800, Simon Glass wrote:
> Hi Ivan,
>
> On Tue, 7 Mar 2023 at 14:13, Ivan Mikhaylov
> wrote:
> >
> > From: Roman Kopytin
> >
> > Signed-off-by: Roman Kopytin
> > Cc: Rasmus Villemoes
> > ---
> > test/py/tests/test_vboot.py | 8
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/test/py/tests/test_vboot.py
> > b/test/py/tests/test_vboot.py
> > index e3e7ca4b21..956b8fcd43 100644
> > --- a/test/py/tests/test_vboot.py
> > +++ b/test/py/tests/test_vboot.py
> > @@ -313,6 +313,13 @@ def test_vboot(u_boot_console, name, sha_algo,
> > padding, sign_options, required,
> >
> > util.run_and_log(cons, [fit_check_sign, '-f', fit, '-k',
> > dtb])
> >
> > + # Create a fresh .dtb without the public keys
> > + dtc('sandbox-u-boot.dts')
> > + # Then add the dev key via the fdt_add_pubkey tool
> > + util.run_and_log(cons, [fdt_add_pubkey, '-a', '%s,rsa2048'
> > % sha_algo,
> > + '-k', tmpdir, '-n', 'dev', '-r',
> > 'conf', dtb])
> > + util.run_and_log(cons, [fit_check_sign, '-f', fit, '-k',
> > dtb])
> > +
> > if full_test:
> > # Make sure that U-Boot checks that the config is in
> > the list of
> > # hashed nodes. If it isn't, a security bypass is
> > possible.
> > @@ -500,6 +507,7 @@ def test_vboot(u_boot_console, name, sha_algo,
> > padding, sign_options, required,
> > mkimage = cons.config.build_dir + '/tools/mkimage'
> > binman = cons.config.source_dir + '/tools/binman/binman'
> > fit_check_sign = cons.config.build_dir +
> > '/tools/fit_check_sign'
> > + fdt_add_pubkey = cons.config.build_dir +
> > '/tools/fdt_add_pubkey'
> > dtc_args = '-I dts -O dtb -i %s' % tmpdir
> > dtb = '%ssandbox-u-boot.dtb' % tmpdir
> > sig_node = '/configurations/conf-1/signature'
> > --
> > 2.39.1
> >
>
> Unfortunately this test fails on sandbox:
>
> https://source.denx.de/u-boot/custodians/u-boot-dm/-/jobs/591975
>
> I think it would be better to put it in its own test (perhaps in the
> same file) so we are not doing it on every test run. Also you could
> check (in a very basic way) that it adds the key correctly since we
> don't really need another test of the logic of doing that. We are
> just
> checking that your tool calls that logic correctly.
>
> I'll drop this one when applying, for now. Please take a look.
>
> Regards,
> Simon
Simon, does it look ok? Test for test_vboot is passed fine.
Thanks.
>From 5484d525d4950b064adf1204f5bf055229c942ac Mon Sep 17 00:00:00 2001
From: Roman Kopytin
Date: Thu, 11 Nov 2021 11:15:12 +0300
Subject: [PATCH v3] test_vboot.py: include test of fdt_add_pubkey tool
Signed-off-by: Roman Kopytin
Signed-off-by: Ivan Mikhaylov
Cc: Rasmus Villemoes
---
test/py/tests/test_vboot.py | 33 +
1 file changed, 33 insertions(+)
diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py
index e3e7ca4b21..5ae622fe21 100644
--- a/test/py/tests/test_vboot.py
+++ b/test/py/tests/test_vboot.py
@@ -491,6 +491,37 @@ def test_vboot(u_boot_console, name, sha_algo,
padding, sign_options, required,
# Check that the boot fails if the global signature is not
provided
run_bootm(sha_algo, 'global image signature', 'signature is
mandatory', False)
+def test_fdt_add_pubkey(sha_algo, padding, sign_options):
+"""Test fdt_add_pubkey utility with given hash algorithm and
padding.
+
+This function tests if fdt_add_pubkey utility may add public
keys into dtb.
+
+Args:
+sha_algo: Either 'sha1' or 'sha256', to select the
algorithm to use
+padding: Either '' or '-pss', to select the padding to use
for the
+rsa signature algorithm.
+sign_options: Options to mkimage when signing a fit image.
+"""
+
+# Create a fresh .dtb without the public keys
+dtc('sandbox-u-boot.dts')
+make_fit('sign-configs-%s%s.its' % (sha_algo, padding))
+
+# Sign images with our dev keys
+sign_fit(sha_algo, sign_options)
+
+# Create a fresh .dtb without the public keys
+dtc('sandbox-u-boot.dts')
+
+cons.log.action('%s: Test fdt_add_pubkey with signed
configuration' % sha_algo)
+# Then add the dev key via the fdt_add_pubkey tool
+util.run_and_log(cons, [fdt_add_pubkey, '-a', '%s,%s' %
('sha256' if algo_arg else sha_algo, \
+'rsa3072' if sha_algo == 'sha384' else
'rsa2048'),
+'-k', tmpdir, '-n', 'dev', '-r',
'conf', dtb])
+
+# Check with fit_check_sign that FIT is signed with key
+util.run_and_log(cons, [fit_check_sign, '-f', fit, '-k', dtb])
+
cons = u_boot_console
tmpdir = os.path.join(cons.config.result_dir, name) + '/'
if not os.path.exists(tmpdir):
@@ -500,6 +531,7 @@ def test_vboot(u_boot_console, name, sha_algo,
padding, sign_options,
Re: [PATCH] arm: kirkwood: pogo v4: Use a more common format for stdout-path
On Wednesday 15 March 2023 14:56:52 Tony Dinh wrote:
> The mainline Pogo V4 DTS uses a stdout-path format that is not
> recognizable by u-boot. Change it to a commonly used format.
Cannot we teach u-boot to understand also currently used format?
> Note that this patch removes the previous workaround for this board
> as discussed here:
> https://lists.denx.de/pipermail/u-boot/2023-February/508936.html
>
> Signed-off-by: Tony Dinh
> ---
>
> arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
> b/arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
> index f9e127234c..9bb97c6b6b 100644
> --- a/arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
> +++ b/arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
> @@ -1,7 +1,10 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> * Copyright (C) 2023 Tony Dinh
> - */
> - {
> - u-boot,dm-pre-reloc;
> +*/
> +
> +/ {
> + chosen {
> + stdout-path =
> + };
> };
> --
> 2.30.2
>
mkimage for Windows?
Hi, Does anyone know how to build mkimage (or other tools) on a Windows host, or at least with a Windows target? Regards, SImon
[PATCH] arm: kirkwood: pogo v4: Use a more common format for stdout-path
The mainline Pogo V4 DTS uses a stdout-path format that is not
recognizable by u-boot. Change it to a commonly used format.
Note that this patch removes the previous workaround for this board
as discussed here:
https://lists.denx.de/pipermail/u-boot/2023-February/508936.html
Signed-off-by: Tony Dinh
---
arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
b/arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
index f9e127234c..9bb97c6b6b 100644
--- a/arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
+++ b/arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
@@ -1,7 +1,10 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2023 Tony Dinh
- */
- {
- u-boot,dm-pre-reloc;
+*/
+
+/ {
+ chosen {
+ stdout-path =
+ };
};
--
2.30.2
[PATCH v4 12/17] board: starfive: Add Kconfig for StarFive VisionFive v2 Board
Add Kconfig to select the basic functions for StarFive VisionFive v2 Board. Signed-off-by: Yanhong Wang Tested-by: Conor Dooley --- board/starfive/visionfive2/Kconfig | 53 ++ 1 file changed, 53 insertions(+) create mode 100644 board/starfive/visionfive2/Kconfig diff --git a/board/starfive/visionfive2/Kconfig b/board/starfive/visionfive2/Kconfig new file mode 100644 index 00..2186a93964 --- /dev/null +++ b/board/starfive/visionfive2/Kconfig @@ -0,0 +1,53 @@ +if TARGET_STARFIVE_VISIONFIVE2 + +config SYS_CPU + default "jh7110" + +config SYS_BOARD + default "visionfive2" + +config SYS_VENDOR + default "starfive" + +config SYS_CONFIG_NAME + default "starfive-visionfive2" + +config TEXT_BASE + default 0x4020 if SPL + default 0x4000 if !RISCV_SMODE + default 0x4020 if RISCV_SMODE + +config SPL_TEXT_BASE + default 0x0800 + +config SPL_OPENSBI_LOAD_ADDR + default 0x8000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select STARFIVE_JH7110 + select SUPPORT_SPL + select BINMAN + imply CMD_CPU + imply CMD_DHCP + imply CMD_EXT2 + imply CMD_EXT4 + imply CMD_FAT + imply CMD_FS_GENERIC + imply CMD_GPIO + imply CMD_GPT + imply CMD_MMC + imply CMD_NET + imply CMD_PING + imply CMD_SF + imply DM_GPIO + imply DOS_PARTITION + imply EFI_PARTITION + imply MII + imply IP_DYN + imply ISO_PARTITION + imply PARTITION_TYPE_GUID + imply PHY_LIB + imply PHY_MSCC + +endif -- 2.17.1
[PATCH v4 04/17] reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC
Add a DM reset driver for StarFive JH7110 SoC.
Note that the register base address of reset controller is the
same with the clock controller. Therefore, there is no device
tree node alone for reset driver.It binds device node in
the clock driver
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
drivers/reset/Kconfig| 16
drivers/reset/Makefile | 1 +
drivers/reset/reset-jh7110.c | 158 +++
3 files changed, 175 insertions(+)
create mode 100644 drivers/reset/reset-jh7110.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index e4039d7474..73bbd30692 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -172,6 +172,22 @@ config RESET_SIFIVE
different hw blocks like DDR, gemgxl. With this driver we leverage
U-Boot's reset framework to reset these hardware blocks.
+config RESET_JH7110
+ bool "Reset driver for StarFive JH7110 SoC"
+ depends on DM_RESET && STARFIVE_JH7110
+ default y
+ help
+ Support for reset controller on StarFive
+ JH7110 SoCs.
+
+config SPL_RESET_JH7110
+ bool "SPL Reset driver for StarFive JH7110 SoC"
+ depends on SPL && STARFIVE_JH7110
+ default y
+ help
+ Support for reset controller on StarFive
+ JH7110 SoCs in SPL.
+
config RESET_SYSCON
bool "Enable generic syscon reset driver support"
depends on DM_RESET
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 6c8b45ecba..6801268180 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -32,3 +32,4 @@ obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o
obj-$(CONFIG_RESET_DRA7) += reset-dra7.o
obj-$(CONFIG_RESET_AT91) += reset-at91.o
+obj-$(CONFIG_$(SPL_TPL_)RESET_JH7110) += reset-jh7110.o
diff --git a/drivers/reset/reset-jh7110.c b/drivers/reset/reset-jh7110.c
new file mode 100644
index 00..d6bdf6bb00
--- /dev/null
+++ b/drivers/reset/reset-jh7110.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct jh7110_reset_priv {
+ void __iomem *reg;
+ u32 assert;
+ u32 status;
+ u32 resets;
+};
+
+struct reset_info {
+ const char *compat;
+ const u32 nr_resets;
+ const u32 assert_offset;
+ const u32 status_offset;
+};
+
+static const struct reset_info jh7110_rst_info[] = {
+ {
+ .compat = "starfive,jh7110-syscrg",
+ .nr_resets = JH7110_SYSRST_END,
+ .assert_offset = 0x2F8,
+ .status_offset = 0x308,
+ },
+ {
+ .compat = "starfive,jh7110-aoncrg",
+ .nr_resets = JH7110_AONRST_END,
+ .assert_offset = 0x38,
+ .status_offset = 0x3C,
+ },
+ {
+ .compat = "starfive,jh7110-stgcrg",
+ .nr_resets = JH7110_STGRST_END,
+ .assert_offset = 0x74,
+ .status_offset = 0x78,
+ }
+};
+
+static const struct reset_info *jh7110_reset_get_cfg(const char *compat)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(jh7110_rst_info); i++)
+ if (!strcmp(compat, jh7110_rst_info[i].compat))
+ return _rst_info[i];
+
+ return NULL;
+}
+
+static int jh7110_reset_trigger(struct jh7110_reset_priv *priv,
+ unsigned long id, bool assert)
+{
+ ulong group;
+ u32 mask, value, done = 0;
+ ulong addr;
+
+ group = id / 32;
+ mask = BIT(id % 32);
+
+ if (!assert)
+ done ^= mask;
+
+ addr = (ulong)priv->reg + priv->assert + group * sizeof(u32);
+ value = readl((ulong *)addr);
+
+ if (assert)
+ value |= mask;
+ else
+ value &= ~mask;
+
+ writel(value, (ulong *)addr);
+ addr = (ulong)priv->reg + priv->status + group * sizeof(u32);
+
+ return readl_poll_timeout((ulong *)addr, value,
+ (value & mask) == done, 1000);
+}
+
+static int jh7110_reset_assert(struct reset_ctl *rst)
+{
+ struct jh7110_reset_priv *priv = dev_get_priv(rst->dev);
+
+ jh7110_reset_trigger(priv, rst->id, true);
+
+ return 0;
+}
+
+static int jh7110_reset_deassert(struct reset_ctl *rst)
+{
+ struct jh7110_reset_priv *priv = dev_get_priv(rst->dev);
+
+ jh7110_reset_trigger(priv, rst->id, false);
+
+ return 0;
+}
+
+static int jh7110_reset_free(struct reset_ctl *rst)
+{
+ return 0;
+}
+
+static int jh7110_reset_request(struct reset_ctl *rst)
+{
+ struct jh7110_reset_priv *priv = dev_get_priv(rst->dev);
+
+ if (rst->id >= priv->resets)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int
[PATCH v4 01/17] riscv: cpu: jh7110: Add support for jh7110 SoC
Add StarFive JH7110 SoC to support RISC-V arch.
Signed-off-by: Yanhong Wang
Reviewed-by: Rick Chen
Tested-by: Conor Dooley
---
arch/riscv/cpu/jh7110/Makefile| 10
arch/riscv/cpu/jh7110/cpu.c | 23
arch/riscv/cpu/jh7110/dram.c | 38 ++
arch/riscv/cpu/jh7110/spl.c | 64 +++
arch/riscv/include/asm/arch-jh7110/regs.h | 19 +++
arch/riscv/include/asm/arch-jh7110/spl.h | 12 +
6 files changed, 166 insertions(+)
create mode 100644 arch/riscv/cpu/jh7110/Makefile
create mode 100644 arch/riscv/cpu/jh7110/cpu.c
create mode 100644 arch/riscv/cpu/jh7110/dram.c
create mode 100644 arch/riscv/cpu/jh7110/spl.c
create mode 100644 arch/riscv/include/asm/arch-jh7110/regs.h
create mode 100644 arch/riscv/include/asm/arch-jh7110/spl.h
diff --git a/arch/riscv/cpu/jh7110/Makefile b/arch/riscv/cpu/jh7110/Makefile
new file mode 100644
index 00..951c95631e
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y += spl.o
+else
+obj-y += cpu.o
+obj-y += dram.o
+endif
diff --git a/arch/riscv/cpu/jh7110/cpu.c b/arch/riscv/cpu/jh7110/cpu.c
new file mode 100644
index 00..1d7c026584
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/cpu.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+ cache_flush();
+
+ return 0;
+}
diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c
new file mode 100644
index 00..2ad3f2044a
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/dram.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+{
+ /*
+* Ensure that we run from first 4GB so that all
+* addresses used by U-Boot are 32bit addresses.
+*
+* This in-turn ensures that 32bit DMA capable
+* devices work fine because DMA mapping APIs will
+* provide 32bit DMA addresses only.
+*/
+ if (IS_ENABLED(CONFIG_64BIT) && gd->ram_top > SZ_4G)
+ return SZ_4G;
+
+ return gd->ram_top;
+}
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
new file mode 100644
index 00..104f0fe949
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+
+#define CSR_U74_FEATURE_DISABLE0x7c1
+#define L2_LIM_MEM_END 0x81FUL
+
+int spl_soc_init(void)
+{
+ int ret;
+ struct udevice *dev;
+
+ /* DDR init */
+ ret = uclass_get_device(UCLASS_RAM, 0, );
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+void harts_early_init(void)
+{
+ ulong *ptr;
+ u8 *tmp;
+ ulong len, remain;
+ /*
+* Feature Disable CSR
+*
+* Clear feature disable CSR to '0' to turn on all features for
+* each core. This operation must be in M-mode.
+*/
+ if (CONFIG_IS_ENABLED(RISCV_MMODE))
+ csr_write(CSR_U74_FEATURE_DISABLE, 0);
+
+ /* clear L2 LIM memory
+* set __bss_end to 0x81F region to zero
+* The L2 Cache Controller supports ECC. ECC is applied to SRAM.
+* If it is not cleared, the ECC part is invalid, and an ECC error
+* will be reported when reading data.
+*/
+ ptr = (ulong *)&__bss_end;
+ len = L2_LIM_MEM_END - (ulong)&__bss_end;
+ remain = len % sizeof(ulong);
+ len /= sizeof(ulong);
+
+ while (len--)
+ *ptr++ = 0;
+
+ /* clear the remain bytes */
+ if (remain) {
+ tmp = (u8 *)ptr;
+ while (remain--)
+ *tmp++ = 0;
+ }
+}
diff --git a/arch/riscv/include/asm/arch-jh7110/regs.h
b/arch/riscv/include/asm/arch-jh7110/regs.h
new file mode 100644
index 00..05026870a0
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7110/regs.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ *
[PATCH v4 00/17] Basic StarFive JH7110 RISC-V SoC support
This series of patches base on the latest branch/master, and add support for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for this to be achieved, the respective DT nodes have been added, and the required defconfigs have been added to the boards' defconfig. What is more, the basic required DM drivers have been added, such as reset, clock, pinctrl, uart, ram etc. Note that the register base address of reset controller is same with the clock controller. Therefore, there is no device tree node alone for reset driver. It binds device node in the clock driver. The u-boot-spl and u-boot has been tested on the StarFive VisionFive 2 1.2A and 1.3B boards which equip with JH7110 SoC and works normally. For more information and support, you can visit RVspace wiki[1]. [1] https://wiki.rvspace.org/ v4: - Replace compatible string "starfive,jh7110-ccache" with "sifive,ccache0". - Added 'gmac0_tx_inv','gmac1_tx_inv','gmac1_rx' clock registration. - Added enable_caches() call to enable L2 cache in board_init() function. - Moved 'S7_0' device node from board dts to SoC -u-boot.dtsi. - Added 'i2cx' device node to board dts to consistent with linux. - Renamed device node 'sdcard1_pins' to 'mmc1_pins'. v3: - Added doc/board/starfive/visionfive2.rst file. - Added support booting from SD. - Added support pinctrl in SPL. - Reworded dts to consistent with linux. - Added CFG_EXTRA_ENV_SETTINGS configuration. - Reworded starfive_visionfive2_defconfig. - Reworded the clock driver. - Renamed 'starfive-jh7110.h' to 'starfive,jh7110-crg.h'. - Separated 'starfive_visionfive2.dts' to 'jh7110-starfive-visionfive-2-v1.3b.dts' and 'jh7110-starfive-visionfive-2-v1.2a.dts' to consistent with linux. - Added pinmux_property_set callback function implementation in 'pinctrl-starfive.c'. v2: - Renamed file 'jh7110-regs.h' to 'regs.h'. - Reworded the clear L2 LIM memory code in C. - Removed flash init call in 'spl_soc_init' function. - Reworded the clock driver. - Rename the macro 'SET_DIV' to 'ASSIGNED_CLOCK_PARENTS' in 'spl.c'. - Moved the device tree node 'dmc@1570' from 'jh7110-u-boot.dtsi' to 'starfive_visionfive2-u-boot.dtsi' Previous versions: v1 - https://patchwork.ozlabs.org/project/uboot/cover/20221212025020.23778-1-yanhong.w...@starfivetech.com/ v2 - https://patchwork.ozlabs.org/project/uboot/cover/20230118081132.31403-1-yanhong.w...@starfivetech.com/ v3 - https://patchwork.ozlabs.org/project/uboot/patch/20230303032432.7837-2-yanhong.w...@starfivetech.com/ Jianlong Huang (1): dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions Kuan Lim Lee (1): pinctrl: starfive: Add StarFive JH7110 driver Yanhong Wang (15): riscv: cpu: jh7110: Add support for jh7110 SoC cache: starfive: Add StarFive JH7110 support dt-bindings: reset: Add StarFive JH7110 reset definitions reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC dt-bindings: clock: Add StarFive JH7110 clock definitions clk: starfive: Add StarFive JH7110 clock driver ram: starfive: add ddr driver board: starfive: add StarFive VisionFive v2 board support riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC board: starfive: Add Kconfig for StarFive VisionFive v2 Board board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig riscv: dts: jh7110: Add initial StarFive JH7110 device tree riscv: dts: jh7110: Add initial u-boot device tree riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree configs: starfive: add starfive_visionfive2_defconfig arch/riscv/Kconfig|5 + arch/riscv/cpu/jh7110/Kconfig | 28 + arch/riscv/cpu/jh7110/Makefile| 10 + arch/riscv/cpu/jh7110/cpu.c | 23 + arch/riscv/cpu/jh7110/dram.c | 38 + arch/riscv/cpu/jh7110/spl.c | 64 + arch/riscv/dts/Makefile |3 +- ...10-starfive-visionfive-2-v1.2a-u-boot.dtsi | 69 + .../jh7110-starfive-visionfive-2-v1.2a.dts| 12 + ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69 + .../jh7110-starfive-visionfive-2-v1.3b.dts| 12 + .../dts/jh7110-starfive-visionfive-2.dtsi | 319 +++ arch/riscv/dts/jh7110-u-boot.dtsi | 99 + arch/riscv/dts/jh7110.dtsi| 582 + arch/riscv/include/asm/arch-jh7110/regs.h | 19 + arch/riscv/include/asm/arch-jh7110/spl.h | 12 + board/starfive/visionfive2/Kconfig| 53 + board/starfive/visionfive2/MAINTAINERS|7 + board/starfive/visionfive2/Makefile |7 + board/starfive/visionfive2/spl.c | 87 + .../visionfive2/starfive_visionfive2.c| 40 + configs/starfive_visionfive2_defconfig| 79 + doc/board/starfive/index.rst |9 + doc/board/starfive/visionfive2.rst| 492 + drivers/cache/cache-sifive-ccache.c |1 + drivers/clk/Kconfig
[PATCH v4 02/17] cache: starfive: Add StarFive JH7110 support
This adds support for the StarFive JH7110 SoC which also
feature this SiFive cache controller.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
drivers/cache/cache-sifive-ccache.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cache/cache-sifive-ccache.c
b/drivers/cache/cache-sifive-ccache.c
index c8766f6242..521df40466 100644
--- a/drivers/cache/cache-sifive-ccache.c
+++ b/drivers/cache/cache-sifive-ccache.c
@@ -62,6 +62,7 @@ static int sifive_ccache_probe(struct udevice *dev)
static const struct udevice_id sifive_ccache_ids[] = {
{ .compatible = "sifive,fu540-c000-ccache" },
{ .compatible = "sifive,fu740-c000-ccache" },
+ { .compatible = "sifive,ccache0" },
{}
};
--
2.17.1
[PATCH v4 14/17] riscv: dts: jh7110: Add initial StarFive JH7110 device tree
Add initial device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
arch/riscv/dts/jh7110.dtsi | 582 +
1 file changed, 582 insertions(+)
create mode 100644 arch/riscv/dts/jh7110.dtsi
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
new file mode 100644
index 00..d3e9f92987
--- /dev/null
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -0,0 +1,582 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+#include
+#include
+
+/ {
+ compatible = "starfive,jh7110";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ S7_0: cpu@0 {
+ compatible = "sifive,s7", "riscv";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <8192>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <16384>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <>;
+ riscv,isa = "rv64imac_zba_zbb";
+ tlb-split;
+ status = "disabled";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_1: cpu@1 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <1>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <>;
+ riscv,isa = "rv64imafdc_zba_zbb";
+ tlb-split;
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_2: cpu@2 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <2>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <>;
+ riscv,isa = "rv64imafdc_zba_zbb";
+ tlb-split;
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_3: cpu@3 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <3>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <>;
+ riscv,isa = "rv64imafdc_zba_zbb";
+ tlb-split;
+
+ cpu3_intc:
[PATCH v4 17/17] configs: starfive: add starfive_visionfive2_defconfig
This is the initial basic config for StarFive VisionFive v2 board. It
includes consol, Norflash, sdio, ddr etc.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
configs/starfive_visionfive2_defconfig | 79 ++
1 file changed, 79 insertions(+)
create mode 100644 configs/starfive_visionfive2_defconfig
diff --git a/configs/starfive_visionfive2_defconfig
b/configs/starfive_visionfive2_defconfig
new file mode 100644
index 00..550d0ff3ab
--- /dev/null
+++ b/configs/starfive_visionfive2_defconfig
@@ -0,0 +1,79 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x80
+CONFIG_SYS_MALLOC_F_LEN=0x1
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8000
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.3b"
+CONFIG_SPL_TEXT_BASE=0x800
+CONFIG_SYS_PROMPT="StarFive #"
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_STACK=0x818
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x8200
+CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
+CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
+CONFIG_ARCH_RV64I=y
+CONFIG_CMODEL_MEDANY=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_QSPI_BOOT=y
+CONFIG_SD_BOOT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
+CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_BSS_START_ADDR=0x804
+CONFIG_SPL_BSS_MAX_SIZE=0x1
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x8000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x40
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
+CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_JH7110=y
+# CONFIG_I2C is not set
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_SF_DEFAULT_SPEED=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_SPL_PINCONF=y
+CONFIG_SPL_PINCTRL_STARFIVE=y
+CONFIG_SPL_PINCTRL_STARFIVE_JH7110=y
+CONFIG_PINCTRL_STARFIVE=y
+# CONFIG_RAM_SIFIVE is not set
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_TIMER_EARLY=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--
2.17.1
[PATCH v4 06/17] clk: starfive: Add StarFive JH7110 clock driver
Add a DM clock driver for StarFive JH7110 SoC.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/starfive/Kconfig | 17 +
drivers/clk/starfive/Makefile | 4 +
drivers/clk/starfive/clk-jh7110-pll.c | 321 ++
drivers/clk/starfive/clk-jh7110.c | 603 ++
drivers/clk/starfive/clk.h| 57 +++
7 files changed, 1004 insertions(+)
create mode 100644 drivers/clk/starfive/Kconfig
create mode 100644 drivers/clk/starfive/Makefile
create mode 100644 drivers/clk/starfive/clk-jh7110-pll.c
create mode 100644 drivers/clk/starfive/clk-jh7110.c
create mode 100644 drivers/clk/starfive/clk.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 09aa97ee8c..4d60c84aad 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -235,6 +235,7 @@ source "drivers/clk/owl/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/sunxi/Kconfig"
source "drivers/clk/sifive/Kconfig"
+source "drivers/clk/starfive/Kconfig"
source "drivers/clk/stm32/Kconfig"
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/ti/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index c274cda77c..66f5860356 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o
obj-y += analogbits/
obj-y += imx/
+obj-$(CONFIG_CLK_JH7110) += starfive/
obj-y += tegra/
obj-y += ti/
obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
new file mode 100644
index 00..9399ef6d51
--- /dev/null
+++ b/drivers/clk/starfive/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+config SPL_CLK_JH7110
+ bool "SPL clock support for JH7110"
+ depends on STARFIVE_JH7110 && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM support for clock driver in JH7110.
+
+config CLK_JH7110
+ bool "StarFive JH7110 clock support"
+ depends on STARFIVE_JH7110
+ select CLK
+ select CLK_CCF
+ help
+ This enables support clock driver for StarFive JH7110 SoC platform.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
new file mode 100644
index 00..ec0d157094
--- /dev/null
+++ b/drivers/clk/starfive/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += clk-jh7110.o
+obj-y += clk-jh7110-pll.o
diff --git a/drivers/clk/starfive/clk-jh7110-pll.c
b/drivers/clk/starfive/clk-jh7110-pll.c
new file mode 100644
index 00..02e6d9000e
--- /dev/null
+++ b/drivers/clk/starfive/clk-jh7110-pll.c
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022-23 StarFive Technology Co., Ltd.
+ *
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define UBOOT_DM_CLK_JH7110_PLLX "jh7110_clk_pllx"
+
+#define PLL_PD_OFF 1
+#define PLL_PD_ON 0
+
+#define CLK_DDR_BUS_MASK GENMASK(29, 24)
+#define CLK_DDR_BUS_OFFSET 0xAC
+#define CLK_DDR_BUS_OSC_DIV2 0
+#define CLK_DDR_BUS_PLL1_DIV2 1
+#define CLK_DDR_BUS_PLL1_DIV4 2
+#define CLK_DDR_BUS_PLL1_DIV8 3
+
+struct clk_jh7110_pllx {
+ struct clk clk;
+ void __iomem*base;
+ void __iomem*sysreg;
+ enum starfive_pll_type type;
+ const struct starfive_pllx_offset *offset;
+ const struct starfive_pllx_rate *rate_table;
+ int rate_count;
+};
+
+#define getbits_le32(addr, mask) ((in_le32(addr) & (mask)) >> __ffs((mask)))
+
+#define PLLX_SET(offset, mask, val) do {\
+ reg = readl((ulong *)((ulong)pll->base + (offset))); \
+ reg &= ~(mask); \
+ reg |= (mask) & ((val) << __ffs(mask)); \
+ writel(reg, (ulong *)((ulong)pll->base + (offset))); \
+ } while (0)
+
+#define PLLX_RATE(_rate, _pd, _fd) \
+ { \
+ .rate = (_rate), \
+ .prediv = (_pd),\
+ .fbdiv = (_fd),\
+ }
+
+#define to_clk_pllx(_clk) container_of(_clk, struct clk_jh7110_pllx, clk)
+
+static const struct starfive_pllx_rate jh7110_pll0_tbl[] = {
+ PLLX_RATE(37500UL, 8, 125),
+ PLLX_RATE(5UL, 6, 125),
+ PLLX_RATE(62500UL, 24, 625),
+ PLLX_RATE(75000UL, 4, 125),
+ PLLX_RATE(87500UL, 24, 875),
+ PLLX_RATE(10UL, 3, 125),
+ PLLX_RATE(125000UL, 12, 625),
+ PLLX_RATE(137500UL, 24, 1375),
+ PLLX_RATE(15UL, 2, 125),
+ PLLX_RATE(162500UL, 24, 1625),
+ PLLX_RATE(175000UL, 12, 875),
+ PLLX_RATE(18UL, 3, 225),
+};
[PATCH v4 08/17] pinctrl: starfive: Add StarFive JH7110 driver
From: Kuan Lim Lee Add pinctrl driver for StarFive JH7110 SoC. Signed-off-by: Kuan Lim Lee Signed-off-by: Emil Renner Berthing Signed-off-by: Jianlong Huang Signed-off-by: Yanhong Wang Tested-by: Conor Dooley --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/starfive/Kconfig | 28 ++ drivers/pinctrl/starfive/Makefile | 6 + drivers/pinctrl/starfive/pinctrl-jh7110-aon.c | 113 + drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 399 ++ drivers/pinctrl/starfive/pinctrl-starfive.c | 382 + drivers/pinctrl/starfive/pinctrl-starfive.h | 55 +++ 8 files changed, 985 insertions(+) create mode 100644 drivers/pinctrl/starfive/Kconfig create mode 100644 drivers/pinctrl/starfive/Makefile create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-aon.c create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.c create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.h diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index b6ef2acced..75b3ff47a2 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -359,5 +359,6 @@ source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/rockchip/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" source "drivers/pinctrl/uniphier/Kconfig" +source "drivers/pinctrl/starfive/Kconfig" endmenu diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 3b167d099f..852adee4b4 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -32,3 +32,4 @@ obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o obj-$(CONFIG_$(SPL_)PINCTRL_STMFX) += pinctrl-stmfx.o obj-y += broadcom/ obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o +obj-$(CONFIG_PINCTRL_STARFIVE) += starfive/ diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig new file mode 100644 index 00..1b859c863e --- /dev/null +++ b/drivers/pinctrl/starfive/Kconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SPL_PINCTRL_STARFIVE + bool "Support Pinctrl driver for StarFive SoC in SPL" + depends on SPL_PINCTRL_FULL && STARFIVE_JH7110 + help + Enable support pin control driver for StarFive SoC. + +config SPL_PINCTRL_STARFIVE_JH7110 + bool "Support Pinctrl and GPIO driver for StarFive JH7110 SoC in SPL" + depends on SPL_PINCTRL_STARFIVE + help + Enable support pinctrl and gpio driver for StarFive JH7110 in SPL. + +config PINCTRL_STARFIVE + bool "Pinctrl driver for StarFive SoC" + depends on PINCTRL_FULL && STARFIVE_JH7110 + help + Say yes here to support pin control on the StarFive RISC-V SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. + +config PINCTRL_STARFIVE_JH7110 + bool "Pinctrl and GPIO driver for StarFive JH7110 SoC" + depends on PINCTRL_STARFIVE + help + This selects the pinctrl driver for JH7110 starfive. diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile new file mode 100644 index 00..a4a12069b3 --- /dev/null +++ b/drivers/pinctrl/starfive/Makefile @@ -0,0 +1,6 @@ + +# SPDX-License-Identifier: GPL-2.0 +# Core +obj-$(CONFIG_$(SPL_TPL_)PINCTRL_STARFIVE) += pinctrl-starfive.o +# SoC Drivers +obj-$(CONFIG_$(SPL_TPL_)PINCTRL_STARFIVE_JH7110) += pinctrl-jh7110-sys.o pinctrl-jh7110-aon.o diff --git a/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c b/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c new file mode 100644 index 00..2d739906e2 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Pinctrl / GPIO driver for StarFive JH7110 SoC + * + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Author: Lee Kuan Lim + * Author: Jianlong Huang + */ + +#include +#include +#include + +#include +#include "pinctrl-starfive.h" + +#define JH7110_AON_NGPIO 4 +#define JH7110_AON_GC_BASE 64 + +/* registers */ +#define JH7110_AON_DOEN0x0 +#define JH7110_AON_DOUT0x4 +#define JH7110_AON_GPI 0x8 +#define JH7110_AON_GPIOIN 0x2c + +#define JH7110_AON_GPIOEN 0xc +#define JH7110_AON_GPIOIS 0x10 +#define JH7110_AON_GPIOIC 0x14 +#define JH7110_AON_GPIOIBE 0x18 +#define JH7110_AON_GPIOIEV 0x1c +#define JH7110_AON_GPIOIE 0x20 +#define JH7110_AON_GPIORIS 0x28 +#define JH7110_AON_GPIOMIS 0x28 + +#define AON_GPO_PDA_0_5_CFG0x30 + +static int jh7110_aon_set_one_pin_mux(struct udevice *dev, unsigned
[PATCH v4 07/17] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions
From: Jianlong Huang Add pinctrl definitions for StarFive JH7110 SoC. Signed-off-by: Kuan Lim Lee Signed-off-by: Emil Renner Berthing Signed-off-by: Jianlong Huang Signed-off-by: Yanhong Wang Tested-by: Conor Dooley --- .../pinctrl/pinctrl-starfive-jh7110.h | 427 ++ 1 file changed, 427 insertions(+) create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h diff --git a/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h new file mode 100644 index 00..f273547e7b --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h @@ -0,0 +1,427 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2022 Emil Renner Berthing + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__ +#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__ + +/* + * mux bits: + * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 | + * | din| dout | doen | function | gpio nr | + * + * dout: output signal + * doen: output enable signal + * din: optional input signal, 0xff = none + * function: + * gpio nr: gpio number, 0 - 63 + */ +#define GPIOMUX(n, dout, doen, din) ( \ + (((din) & 0xff) << 24) | \ + (((dout) & 0xff) << 16) | \ + (((doen) & 0x3f) << 10) | \ + ((n) & 0x3f)) + +#define PINMUX(n, func) ((1 << 10) | (((func) & 0x3) << 8) | ((n) & 0xff)) + +/* sys_iomux pin */ +#definePAD_GPIO00 +#definePAD_GPIO11 +#definePAD_GPIO22 +#definePAD_GPIO33 +#definePAD_GPIO44 +#definePAD_GPIO55 +#definePAD_GPIO66 +#definePAD_GPIO77 +#definePAD_GPIO88 +#definePAD_GPIO99 +#definePAD_GPIO10 10 +#definePAD_GPIO11 11 +#definePAD_GPIO12 12 +#definePAD_GPIO13 13 +#definePAD_GPIO14 14 +#definePAD_GPIO15 15 +#definePAD_GPIO16 16 +#definePAD_GPIO17 17 +#definePAD_GPIO18 18 +#definePAD_GPIO19 19 +#definePAD_GPIO20 20 +#definePAD_GPIO21 21 +#definePAD_GPIO22 22 +#definePAD_GPIO23 23 +#definePAD_GPIO24 24 +#definePAD_GPIO25 25 +#definePAD_GPIO26 26 +#definePAD_GPIO27 27 +#definePAD_GPIO28 28 +#definePAD_GPIO29 29 +#definePAD_GPIO30 30 +#definePAD_GPIO31 31 +#definePAD_GPIO32 32 +#definePAD_GPIO33 33 +#definePAD_GPIO34 34 +#definePAD_GPIO35 35 +#definePAD_GPIO36 36 +#definePAD_GPIO37 37 +#definePAD_GPIO38 38 +#definePAD_GPIO39 39 +#definePAD_GPIO40 40 +#definePAD_GPIO41 41 +#definePAD_GPIO42 42 +#definePAD_GPIO43 43 +#definePAD_GPIO44 44 +#definePAD_GPIO45 45 +#definePAD_GPIO46 46 +#definePAD_GPIO47 47 +#definePAD_GPIO48 48 +#definePAD_GPIO49 49 +#definePAD_GPIO50 50 +#definePAD_GPIO51 51 +#definePAD_GPIO52 52 +#definePAD_GPIO53 53 +#definePAD_GPIO54 54 +#definePAD_GPIO55 55 +#definePAD_GPIO56 56 +#definePAD_GPIO57 57 +#definePAD_GPIO58 58 +#definePAD_GPIO59 59 +#definePAD_GPIO60 60 +#definePAD_GPIO61 61 +#definePAD_GPIO62 62 +#definePAD_GPIO63 63 +#definePAD_SD0_CLK 64 +#definePAD_SD0_CMD 65 +#definePAD_SD0_DATA0 66 +#definePAD_SD0_DATA1 67 +#definePAD_SD0_DATA2 68 +#definePAD_SD0_DATA3 69 +#definePAD_SD0_DATA4 70 +#definePAD_SD0_DATA5 71 +#definePAD_SD0_DATA6 72 +#definePAD_SD0_DATA7 73 +#definePAD_SD0_STRB74 +#definePAD_GMAC1_MDC 75 +#definePAD_GMAC1_MDIO 76 +#definePAD_GMAC1_RXD0 77 +#definePAD_GMAC1_RXD1 78 +#definePAD_GMAC1_RXD2 79 +#definePAD_GMAC1_RXD3 80 +#definePAD_GMAC1_RXDV 81 +#definePAD_GMAC1_RXC 82 +#definePAD_GMAC1_TXD0 83 +#definePAD_GMAC1_TXD1 84 +#definePAD_GMAC1_TXD2 85 +#definePAD_GMAC1_TXD3 86 +#definePAD_GMAC1_TXEN 87 +#definePAD_GMAC1_TXC 88 +#definePAD_QSPI_SCLK 89 +#definePAD_QSPI_CS090 +#definePAD_QSPI_DATA0 91 +#definePAD_QSPI_DATA1 92 +#definePAD_QSPI_DATA2 93 +#definePAD_QSPI_DATA3 94 + +/* aon_iomux pin */ +#definePAD_TESTEN 0 +#definePAD_RGPIO0 1 +#definePAD_RGPIO1 2
[PATCH v4 05/17] dt-bindings: clock: Add StarFive JH7110 clock definitions
Add all clock outputs for the StarFive JH7110 clock generator. Signed-off-by: Yanhong Wang Acked-by: Sean Anderson Tested-by: Conor Dooley --- .../dt-bindings/clock/starfive,jh7110-crg.h | 257 ++ 1 file changed, 257 insertions(+) create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h new file mode 100644 index 00..77b70e7a83 --- /dev/null +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h @@ -0,0 +1,257 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * + * Author: Yanhong Wang + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ + +#define JH7110_SYSCLK_CPU_ROOT 0 +#define JH7110_SYSCLK_CPU_CORE 1 +#define JH7110_SYSCLK_CPU_BUS 2 +#define JH7110_SYSCLK_GPU_ROOT 3 +#define JH7110_SYSCLK_PERH_ROOT4 +#define JH7110_SYSCLK_BUS_ROOT 5 +#define JH7110_SYSCLK_NOCSTG_BUS 6 +#define JH7110_SYSCLK_AXI_CFG0 7 +#define JH7110_SYSCLK_STG_AXIAHB 8 +#define JH7110_SYSCLK_AHB0 9 +#define JH7110_SYSCLK_AHB1 10 +#define JH7110_SYSCLK_APB_BUS 11 +#define JH7110_SYSCLK_APB0 12 +#define JH7110_SYSCLK_PLL0_DIV213 +#define JH7110_SYSCLK_PLL1_DIV214 +#define JH7110_SYSCLK_PLL2_DIV215 +#define JH7110_SYSCLK_AUDIO_ROOT 16 +#define JH7110_SYSCLK_MCLK_INNER 17 +#define JH7110_SYSCLK_MCLK 18 +#define JH7110_SYSCLK_MCLK_OUT 19 +#define JH7110_SYSCLK_ISP_2X 20 +#define JH7110_SYSCLK_ISP_AXI 21 +#define JH7110_SYSCLK_GCLK022 +#define JH7110_SYSCLK_GCLK123 +#define JH7110_SYSCLK_GCLK224 +#define JH7110_SYSCLK_CORE 25 +#define JH7110_SYSCLK_CORE126 +#define JH7110_SYSCLK_CORE227 +#define JH7110_SYSCLK_CORE328 +#define JH7110_SYSCLK_CORE429 +#define JH7110_SYSCLK_DEBUG30 +#define JH7110_SYSCLK_RTC_TOGGLE 31 +#define JH7110_SYSCLK_TRACE0 32 +#define JH7110_SYSCLK_TRACE1 33 +#define JH7110_SYSCLK_TRACE2 34 +#define JH7110_SYSCLK_TRACE3 35 +#define JH7110_SYSCLK_TRACE4 36 +#define JH7110_SYSCLK_TRACE_COM37 +#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 +#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 +#define JH7110_SYSCLK_OSC_DIV2 40 +#define JH7110_SYSCLK_PLL1_DIV441 +#define JH7110_SYSCLK_PLL1_DIV842 +#define JH7110_SYSCLK_DDR_BUS 43 +#define JH7110_SYSCLK_DDR_AXI 44 +#define JH7110_SYSCLK_GPU_CORE 45 +#define JH7110_SYSCLK_GPU_CORE_CLK 46 +#define JH7110_SYSCLK_GPU_SYS_CLK 47 +#define JH7110_SYSCLK_GPU_APB 48 +#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 +#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 +#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X 51 +#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI 52 +#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 +#define JH7110_SYSCLK_HIFI4_CORE 54 +#define JH7110_SYSCLK_HIFI4_AXI55 +#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN56 +#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57 +#define JH7110_SYSCLK_VOUT_SRC 58 +#define JH7110_SYSCLK_VOUT_AXI 59 +#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 +#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB61 +#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI62 +#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK63 +#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF 64 +#define JH7110_SYSCLK_JPEGC_AXI65 +#define JH7110_SYSCLK_CODAJ12_AXI 66 +#define JH7110_SYSCLK_CODAJ12_CORE 67 +#define JH7110_SYSCLK_CODAJ12_APB 68 +#define JH7110_SYSCLK_VDEC_AXI 69 +#define JH7110_SYSCLK_WAVE511_AXI 70 +#define JH7110_SYSCLK_WAVE511_BPU 71 +#define JH7110_SYSCLK_WAVE511_VCE 72 +#define JH7110_SYSCLK_WAVE511_APB 73 +#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74 +#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN75 +#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 +#define JH7110_SYSCLK_VENC_AXI 77 +#define JH7110_SYSCLK_WAVE420L_AXI 78 +#define JH7110_SYSCLK_WAVE420L_BPU 79 +#define JH7110_SYSCLK_WAVE420L_VCE 80 +#define JH7110_SYSCLK_WAVE420L_APB
[PATCH v4 03/17] dt-bindings: reset: Add StarFive JH7110 reset definitions
Add resets for the StarFive JH7110 system(SYS),system-top-group(STG) and always-on(AON) reset controller. Signed-off-by: Yanhong Wang Tested-by: Conor Dooley --- .../dt-bindings/reset/starfive,jh7110-crg.h | 183 ++ 1 file changed, 183 insertions(+) create mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h new file mode 100644 index 00..1d596581da --- /dev/null +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * + * Author: Yanhong Wang + */ + +#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ +#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ + +/* SYSCRG resets */ +#define JH7110_SYSRST_JTAG2APB 0 +#define JH7110_SYSRST_SYSCON 1 +#define JH7110_SYSRST_IOMUX_APB2 +#define JH7110_SYSRST_BUS 3 +#define JH7110_SYSRST_DEBUG4 +#define JH7110_SYSRST_CORE05 +#define JH7110_SYSRST_CORE16 +#define JH7110_SYSRST_CORE27 +#define JH7110_SYSRST_CORE38 +#define JH7110_SYSRST_CORE49 +#define JH7110_SYSRST_CORE0_ST 10 +#define JH7110_SYSRST_CORE1_ST 11 +#define JH7110_SYSRST_CORE2_ST 12 +#define JH7110_SYSRST_CORE3_ST 13 +#define JH7110_SYSRST_CORE4_ST 14 +#define JH7110_SYSRST_TRACE0 15 +#define JH7110_SYSRST_TRACE1 16 +#define JH7110_SYSRST_TRACE2 17 +#define JH7110_SYSRST_TRACE3 18 +#define JH7110_SYSRST_TRACE4 19 +#define JH7110_SYSRST_TRACE_COM20 +#define JH7110_SYSRST_GPU_APB 21 +#define JH7110_SYSRST_GPU_DOMA 22 +#define JH7110_SYSRST_NOC_BUS_APB_BUS 23 +#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24 +#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25 +#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26 +#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27 +#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28 +#define JH7110_SYSRST_NOC_BUS_DDRC 29 +#define JH7110_SYSRST_NOC_BUS_STG_AXI 30 +#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31 + +#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32 +#define JH7110_SYSRST_AXI_CFG1_DEC_AHB 33 +#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN34 +#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN35 +#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV36 +#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4 37 +#define JH7110_SYSRST_DDR_AXI 38 +#define JH7110_SYSRST_DDR_OSC 39 +#define JH7110_SYSRST_DDR_APB 40 +#define JH7110_SYSRST_DOM_ISP_TOP_N41 +#define JH7110_SYSRST_DOM_ISP_TOP_AXI 42 +#define JH7110_SYSRST_DOM_VOUT_TOP_SRC 43 +#define JH7110_SYSRST_CODAJ12_AXI 44 +#define JH7110_SYSRST_CODAJ12_CORE 45 +#define JH7110_SYSRST_CODAJ12_APB 46 +#define JH7110_SYSRST_WAVE511_AXI 47 +#define JH7110_SYSRST_WAVE511_BPU 48 +#define JH7110_SYSRST_WAVE511_VCE 49 +#define JH7110_SYSRST_WAVE511_APB 50 +#define JH7110_SYSRST_VDEC_JPG_ARB_JPG 51 +#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN52 +#define JH7110_SYSRST_AXIMEM0_AXI 53 +#define JH7110_SYSRST_WAVE420L_AXI 54 +#define JH7110_SYSRST_WAVE420L_BPU 55 +#define JH7110_SYSRST_WAVE420L_VCE 56 +#define JH7110_SYSRST_WAVE420L_APB 57 +#define JH7110_SYSRST_AXIMEM1_AXI 58 +#define JH7110_SYSRST_AXIMEM2_AXI 59 +#define JH7110_SYSRST_INTMEM 60 +#define JH7110_SYSRST_QSPI_AHB 61 +#define JH7110_SYSRST_QSPI_APB 62 +#define JH7110_SYSRST_QSPI_REF 63 + +#define JH7110_SYSRST_SDIO0_AHB64 +#define JH7110_SYSRST_SDIO1_AHB65 +#define JH7110_SYSRST_GMAC1_AXI66 +#define JH7110_SYSRST_GMAC1_AHB67 +#define JH7110_SYSRST_MAILBOX 68 +#define JH7110_SYSRST_SPI0_APB 69 +#define JH7110_SYSRST_SPI1_APB 70 +#define JH7110_SYSRST_SPI2_APB 71 +#define JH7110_SYSRST_SPI3_APB 72 +#define JH7110_SYSRST_SPI4_APB 73 +#define JH7110_SYSRST_SPI5_APB 74 +#define JH7110_SYSRST_SPI6_APB 75 +#define JH7110_SYSRST_I2C0_APB 76 +#define JH7110_SYSRST_I2C1_APB 77 +#define JH7110_SYSRST_I2C2_APB 78 +#define JH7110_SYSRST_I2C3_APB 79 +#define JH7110_SYSRST_I2C4_APB 80 +#define
[PATCH v4 09/17] ram: starfive: add ddr driver
Add driver for StarFive JH7110 to support ddr initialization in SPL.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
drivers/ram/Kconfig |1 +
drivers/ram/Makefile|4 +-
drivers/ram/starfive/Kconfig|5 +
drivers/ram/starfive/Makefile | 11 +
drivers/ram/starfive/ddrcsr_boot.c | 339 +
drivers/ram/starfive/ddrphy_start.c | 279
drivers/ram/starfive/ddrphy_train.c | 383 ++
drivers/ram/starfive/ddrphy_utils.c | 1955 +++
drivers/ram/starfive/starfive_ddr.c | 161 +++
drivers/ram/starfive/starfive_ddr.h | 65 +
10 files changed, 3202 insertions(+), 1 deletion(-)
create mode 100644 drivers/ram/starfive/Kconfig
create mode 100644 drivers/ram/starfive/Makefile
create mode 100644 drivers/ram/starfive/ddrcsr_boot.c
create mode 100644 drivers/ram/starfive/ddrphy_start.c
create mode 100644 drivers/ram/starfive/ddrphy_train.c
create mode 100644 drivers/ram/starfive/ddrphy_utils.c
create mode 100644 drivers/ram/starfive/starfive_ddr.c
create mode 100644 drivers/ram/starfive/starfive_ddr.h
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index e085119963..1acf212f87 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -112,3 +112,4 @@ source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/sifive/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
source "drivers/ram/octeon/Kconfig"
+source "drivers/ram/starfive/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 83948e2c43..2b9429cfee 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -20,5 +20,7 @@ obj-$(CONFIG_K3_DDRSS) += k3-ddrss/
obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
obj-$(CONFIG_RAM_SIFIVE) += sifive/
-
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/
+endif
obj-$(CONFIG_ARCH_OCTEON) += octeon/
diff --git a/drivers/ram/starfive/Kconfig b/drivers/ram/starfive/Kconfig
new file mode 100644
index 00..80c790066f
--- /dev/null
+++ b/drivers/ram/starfive/Kconfig
@@ -0,0 +1,5 @@
+config SPL_STARFIVE_DDR
+ bool "StarFive DDR driver in SPL"
+ depends on SPL_RAM && STARFIVE_JH7110
+ help
+ This enables DDR support for the platforms based on StarFive JH7110
SoC.
diff --git a/drivers/ram/starfive/Makefile b/drivers/ram/starfive/Makefile
new file mode 100644
index 00..1df42c377b
--- /dev/null
+++ b/drivers/ram/starfive/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2022 StarFive, Inc
+#
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_start.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_train.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive_ddr.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_utils.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrcsr_boot.o
+endif
\ No newline at end of file
diff --git a/drivers/ram/starfive/ddrcsr_boot.c
b/drivers/ram/starfive/ddrcsr_boot.c
new file mode 100644
index 00..f2dd55f74a
--- /dev/null
+++ b/drivers/ram/starfive/ddrcsr_boot.c
@@ -0,0 +1,339 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "starfive_ddr.h"
+
+#define REGOFFSET(offset) ((offset) / 4)
+
+static const struct ddr_reg_cfg ddr_csr_cfg[] = {
+ {0x0, 0x0,0x0001, REGSETALL},
+ {0xf00, 0x0,0x40001030, (OFFSET_SEL | F_SET | REG4G |
REG8G)},
+ {0xf00, 0x0,0x40001030, (OFFSET_SEL | F_SET | REG2G)},
+ {0xf04, 0x0,0x0001, (OFFSET_SEL | F_SET | REG4G |
REG8G)},
+ {0xf04, 0x0,0x0081, (OFFSET_SEL | F_SET | REG2G)},
+ {0xf10, 0x0,0x0040, (OFFSET_SEL | REGSETALL)},
+ {0xf14, 0x0,0x043f, (OFFSET_SEL | REGSETALL)},
+ {0xf18, 0x0,0x, (OFFSET_SEL | REGSETALL)},
+ {0xf30, 0x0,0x1f41, (OFFSET_SEL | REGSETALL)},
+ {0xf34, 0x0,0x1f41, (OFFSET_SEL | F_SET | REG4G |
REG8G)},
+ {0x110, 0x0,0xc001, (OFFSET_SEL | REGSETALL)},
+ {0x114, 0x0,0x, (OFFSET_SEL | REGSETALL)},
+ {0x10c, 0x0,0x0505, REGSETALL},
+ {0x11c, 0x0,0x, REGSETALL},
+ {0x500, 0x0,0x0201, REGSETALL},
+ {0x514, 0x0,0x0100, REGSETALL},
+ {0x6a8, 0x0,0x0004, REGSETALL},
+ {0xea8, 0x0,0x0004, REGSETALL},
+ {0x504, 0x0,0x4000, REGSETALL}
+};
+
+static const struct ddr_reg_cfg ddr_csr_cfg1[] = {
+ {0x310, 0x0,0x0002, REGSETALL},
+ {0x310, 0x0,0x00020001, REGSETALL},
+ {0x600, 0x0,0x002e0176, REGSETALL},
+ {0x604, 0x0,
[PATCH v4 10/17] board: starfive: add StarFive VisionFive v2 board support
Add board support for StarFive VisionFive v2.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
board/starfive/visionfive2/MAINTAINERS| 7 +
board/starfive/visionfive2/Makefile | 7 +
board/starfive/visionfive2/spl.c | 87
.../visionfive2/starfive_visionfive2.c| 40 ++
doc/board/starfive/index.rst | 9 +
doc/board/starfive/visionfive2.rst| 492 ++
include/configs/starfive-visionfive2.h| 49 ++
7 files changed, 691 insertions(+)
create mode 100644 board/starfive/visionfive2/MAINTAINERS
create mode 100644 board/starfive/visionfive2/Makefile
create mode 100644 board/starfive/visionfive2/spl.c
create mode 100644 board/starfive/visionfive2/starfive_visionfive2.c
create mode 100644 doc/board/starfive/index.rst
create mode 100644 doc/board/starfive/visionfive2.rst
create mode 100644 include/configs/starfive-visionfive2.h
diff --git a/board/starfive/visionfive2/MAINTAINERS
b/board/starfive/visionfive2/MAINTAINERS
new file mode 100644
index 00..c5369086d8
--- /dev/null
+++ b/board/starfive/visionfive2/MAINTAINERS
@@ -0,0 +1,7 @@
+STARFIVE JH7110 VISIONFIVE2 BOARD
+M: startfive
+S: Maintained
+F: arch/riscv/include/asm/arch-jh7110/
+F: board/starfive/visionfive2/
+F: include/configs/starfive-visionfive2.h
+F: configs/starfive_visionfive2_defconfig
diff --git a/board/starfive/visionfive2/Makefile
b/board/starfive/visionfive2/Makefile
new file mode 100644
index 00..66c854df39
--- /dev/null
+++ b/board/starfive/visionfive2/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+#
+
+obj-y := starfive_visionfive2.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
new file mode 100644
index 00..db0b4cb433
--- /dev/null
+++ b/board/starfive/visionfive2/spl.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define JH7110_CLK_CPU_ROOT_OFFSET 0x0U
+#define JH7110_CLK_CPU_ROOT_SHIFT 24
+#define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24)
+
+int spl_board_init_f(void)
+{
+ int ret;
+
+ ret = spl_soc_init();
+ if (ret) {
+ debug("JH7110 SPL init failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+u32 spl_boot_device(void)
+{
+ u32 mode;
+
+ mode = in_le32(JH7110_BOOT_MODE_SELECT_REG)
+ & JH7110_BOOT_MODE_SELECT_MASK;
+ switch (mode) {
+ case 0:
+ return BOOT_DEVICE_SPI;
+
+ case 1:
+ return BOOT_DEVICE_MMC2;
+
+ case 2:
+ return BOOT_DEVICE_MMC1;
+
+ case 3:
+ return BOOT_DEVICE_UART;
+
+ default:
+ debug("Unsupported boot device 0x%x.\n", mode);
+ return BOOT_DEVICE_NONE;
+ }
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ ret = spl_early_init();
+ if (ret)
+ panic("spl_early_init() failed: %d\n", ret);
+
+ riscv_cpu_setup(NULL, NULL);
+ preloader_console_init();
+
+ /* Set the parent clock of cpu_root clock to pll0,
+* it must be initialized here
+*/
+ clrsetbits_le32(JH7110_SYS_CRG + JH7110_CLK_CPU_ROOT_OFFSET,
+ JH7110_CLK_CPU_ROOT_MASK,
+ BIT(JH7110_CLK_CPU_ROOT_SHIFT));
+
+ ret = spl_board_init_f();
+ if (ret) {
+ debug("spl_board_init_f init failed: %d\n", ret);
+ return;
+ }
+}
+
+#if CONFIG_IS_ENABLED(SPL_LOAD_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ /* boot using first FIT config */
+ return 0;
+}
+#endif
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c
b/board/starfive/visionfive2/starfive_visionfive2.c
new file mode 100644
index 00..613fe793c4
--- /dev/null
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+
+#define JH7110_L2_PREFETCHER_BASE_ADDR 0x203
+#define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000
+
+/* enable U74-mc hart1~hart4 prefetcher */
+static void enable_prefetcher(void)
+{
+ u8 hart;
+ u32 *reg;
+
+ /* JH7110 use U74MC CORE IP, it include five cores(one S7 and four U7),
+* but only U7 cores support prefetcher configuration
+*/
+ for (hart = 1; hart < 5; hart++) {
+ reg = (void *)(u64)(JH7110_L2_PREFETCHER_BASE_ADDR
+ + hart *
JH7110_L2_PREFETCHER_HART_OFFSET);
+
+
[PATCH v4 15/17] riscv: dts: jh7110: Add initial u-boot device tree
Add initial u-boot device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
arch/riscv/dts/jh7110-u-boot.dtsi | 99 +++
1 file changed, 99 insertions(+)
create mode 100644 arch/riscv/dts/jh7110-u-boot.dtsi
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi
b/arch/riscv/dts/jh7110-u-boot.dtsi
new file mode 100644
index 00..31ca054f54
--- /dev/null
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include
+
+/ {
+ cpus: cpus {
+ u-boot,dm-spl;
+
+ S7_0: cpu@0 {
+ u-boot,dm-spl;
+ status = "okay";
+ cpu0_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+
+ U74_1: cpu@1 {
+ u-boot,dm-spl;
+ cpu1_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+
+ U74_2: cpu@2 {
+ u-boot,dm-spl;
+ cpu2_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+
+ U74_3: cpu@3 {
+ u-boot,dm-spl;
+ cpu3_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+
+ U74_4: cpu@4 {
+ u-boot,dm-spl;
+ cpu4_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ };
+
+ soc {
+ u-boot,dm-spl;
+
+ clint: timer@200 {
+ u-boot,dm-spl;
+ };
+
+ dmc: dmc@1570 {
+ u-boot,dm-spl;
+ compatible = "starfive,jh7110-dmc";
+ reg = <0x0 0x1570 0x0 0x1>,
+ <0x0 0x1300 0x0 0x1>;
+ resets = < JH7110_SYSRST_DDR_AXI>,
+ < JH7110_SYSRST_DDR_OSC>,
+ < JH7110_SYSRST_DDR_APB>;
+ reset-names = "axi", "osc", "apb";
+ clocks = < JH7110_SYSCLK_PLL1_OUT>;
+ clock-names = "pll1_out";
+ clock-frequency = <2133>;
+ };
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_rmii_refin {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+ starfive,sys-syscon = <_syscon>;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_syscon {
+ u-boot,dm-spl;
+};
+
+_0 {
+ status = "okay";
+};
--
2.17.1
[PATCH v4 16/17] riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree
Add initial device tree for StarFive VisionFive v2 board.
Signed-off-by: Yanhong Wang
Tested-by: Conor Dooley
---
arch/riscv/dts/Makefile | 3 +-
...10-starfive-visionfive-2-v1.2a-u-boot.dtsi | 69
.../jh7110-starfive-visionfive-2-v1.2a.dts| 12 +
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69
.../jh7110-starfive-visionfive-2-v1.3b.dts| 12 +
.../dts/jh7110-starfive-visionfive-2.dtsi | 319 ++
6 files changed, 483 insertions(+), 1 deletion(-)
create mode 100644
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
create mode 100644
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index c576c55767..79a58694f5 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -7,7 +7,8 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
jh7110-starfive-visionfive-2-v1.3b.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
jh7110-starfive-visionfive-2-v1.2a.dtb
include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
new file mode 100644
index 00..0b20be0f10
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include "binman.dtsi"
+#include "jh7110-u-boot.dtsi"
+/ {
+ chosen {
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ spi0 =
+ u-boot,dm-spl;
+ };
+
+ config {
+ u-boot,dm-spl;
+ u-boot,spl-payload-offset = <0x10>;
+ };
+
+ memory@4000 {
+ u-boot,dm-spl;
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+
+ nor-flash@0 {
+ u-boot,dm-spl;
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_pins {
+ u-boot,dm-spl;
+ mmc0-pins-rest {
+ u-boot,dm-spl;
+ };
+};
+
+_pins {
+ u-boot,dm-spl;
+ mmc1-pins0 {
+ u-boot,dm-spl;
+ };
+
+ mmc1-pins1 {
+ u-boot,dm-spl;
+ };
+};
+
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
new file mode 100644
index 00..b9d26d7af7
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+#include "jh7110-starfive-visionfive-2.dtsi"
+
+/ {
+ model = "StarFive VisionFive 2 v1.2A";
+ compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
new file mode 100644
index 00..0b20be0f10
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include "binman.dtsi"
+#include "jh7110-u-boot.dtsi"
+/ {
+ chosen {
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ spi0 =
+ u-boot,dm-spl;
+ };
+
+ config {
+ u-boot,dm-spl;
+ u-boot,spl-payload-offset = <0x10>;
+ };
+
+ memory@4000 {
+ u-boot,dm-spl;
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+
+ nor-flash@0 {
+ u-boot,dm-spl;
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_pins {
+ u-boot,dm-spl;
+ mmc0-pins-rest {
+ u-boot,dm-spl;
+ };
+};
+
+_pins {
+ u-boot,dm-spl;
+ mmc1-pins0 {
+ u-boot,dm-spl;
+ };
+
+ mmc1-pins1 {
+ u-boot,dm-spl;
+ };
+};
+
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
new file mode 100644
index 00..3b3b3453a1
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
@@ -0,0 +1,12 @@
+//
[PATCH v4 13/17] board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig
Add board support for StarFive VisionFive v2. Signed-off-by: Yanhong Wang Tested-by: Conor Dooley --- arch/riscv/Kconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 48ca4ff4c4..f6ed05906a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -24,6 +24,9 @@ config TARGET_SIFIVE_UNMATCHED bool "Support SiFive Unmatched Board" select SYS_CACHE_SHIFT_6 +config TARGET_STARFIVE_VISIONFIVE2 + bool "Support StarFive VisionFive2 Board" + config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" select SYS_CACHE_SHIFT_6 @@ -65,12 +68,14 @@ source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" +source "board/starfive/visionfive2/Kconfig" # platform-specific options below source "arch/riscv/cpu/andesv5/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" +source "arch/riscv/cpu/jh7110/Kconfig" # architecture-specific options below -- 2.17.1
[PATCH v4 11/17] riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC
Add Kconfig to select the basic functions for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang Tested-by: Conor Dooley --- arch/riscv/cpu/jh7110/Kconfig | 28 1 file changed, 28 insertions(+) create mode 100644 arch/riscv/cpu/jh7110/Kconfig diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig new file mode 100644 index 00..3f145415eb --- /dev/null +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022 StarFive Technology Co., Ltd. + +config STARFIVE_JH7110 + bool + select ARCH_EARLY_INIT_R + select CLK_JH7110 + select CPU + select CPU_RISCV + select RAM + select RESET_JH7110 + select SUPPORT_SPL + select SPL_RAM if SPL + select SPL_STARFIVE_DDR + select PINCTRL_STARFIVE_JH7110 + imply MMC + imply MMC_BROKEN_CD + imply MMC_SPI + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply SIFIVE_CACHE + imply SIFIVE_CCACHE + imply SMP + imply SPI + imply SPL_CPU + imply SPL_LOAD_FIT + imply SPL_OPENSBI + imply SPL_SIFIVE_CLINT -- 2.17.1
Re: [PATCH 0/9] Enable splash screen
Hi Simon, On 15/03/23 19:38, Simon Glass wrote: Hi Nikhil, On Wed, 15 Mar 2023 at 00:07, Nikhil M Jain wrote: Hi Simon, On 15/03/23 03:38, Simon Glass wrote: Hi Nikhil, On Mon, 13 Mar 2023 at 04:15, Nikhil M Jain wrote: To enable splash screen at SPL stage move video driver and splash screen framework at SPL, which will bring up image on display very quickly and thus have early display support in SPL. Nikhil M Jain (9): drivers: video: Kconfig: Necessary configs for video at SPL drivers: video: tidss: Kconfig: Configs to enable TIDSS at SPL cmd: Kconfig: Add necessary configs for splash screen at SPL drivers: video: Makefile: Compile video driver files at SPL drivers: video: tidss: Makefile: Add condition to compile TIDSS at SPL cmd: Makefile: Add rules to build bmp.c and read.c at SPL common: splash: Enable splash_display at SPL stage drivers: video: video-uclass: Disable u-boot logo at SPL board: ti: am62x: evm: OSPI support for splash screen board/ti/am62x/evm.c | 6 ++ cmd/Kconfig | 17 + cmd/Makefile | 2 ++ common/splash.c | 2 +- drivers/video/Kconfig| 32 drivers/video/Makefile | 6 ++ drivers/video/tidss/Kconfig | 6 ++ drivers/video/tidss/Makefile | 1 + drivers/video/video-uclass.c | 2 +- include/splash.h | 2 +- 10 files changed, 69 insertions(+), 7 deletions(-) I'm not necessarily arguing against this, but what is the need for this? How many milliseconds earlier does the image appear with this patch? What is the bottleneck? We should be able to get to U-Boot proper very quickly. There is a significant difference in time, by adding support in SPL splash screen comes up by approx 650ms and at u-boot proper it comes at 2.6s, measured from first print in console as seen on AM62x. Also we plan to skip u-boot proper and load kernel directly. Yes that really is terrible. It should be under a second for U-Boot proper! Have you tried using bootstage to report the numbers? No I haven't used the bootstage, I will use it to get the numbers. Have you tried using tracing to figure out what is wrong? Is it just slow storage? U-boot proper comes up in one sec but the splash display is called through stdio_add_devices which is late in the board_init_r sequence defined in board_r.c. Regards, Simon Thanks
Re: i.MX8MP SPL failures due to memory corruption/overflow?
On 15/03/2023 16:24, Frieder Schrempf wrote:
On 15.03.23 15:42, Frieder Schrempf wrote:
On 15.03.23 15:17, Michael Nazzareno Trimarchi wrote:
Hi
On Wed, Mar 15, 2023 at 3:13 PM Frieder Schrempf
wrote:
Hi,
I'm trying to bring up a new board based on the i.MX8MP and I have an
issue I'm hoping someone can help solving.
I'm seeing failures in the early SPL code, usually in the DDR
initialization. Often they look like:
U-Boot SPL 2023.04-rc3 (Mar 07 2023 - 14:32:34 +)
Training FAILED
Failed to initialize DDR RAM!
### ERROR ### Please RESET the board ###
But sometimes ddr_init() doesn't even return an error and only the
get_ram_size() afterwards which tries to allocate the memory fails.
In my experience you don't have space inside the cpu internal memory. It means
that you overlap some stack with the code. Change the printf means
move a bit. So you have
problem but depends what you are going to destroy
Thanks for your reply. That's exactly what I'm thinking, too.
The strange thing is that the issues appear or disappear
deterministically on the binary level. This means I sometimes get a
U-Boot binary which runs just fine in 100% of cases. Then I change for
example one of the following:
* Adding a single printf() somewhere in the boards spl.c
* Using the same binary but booting from SD card instead of USB loader
* Using the same source but switching from the OS cross compiler to the
one from Yocto/OE
And afterwards I get 100% failure rate with an error as described above.
My suspicion is that there is some memory corruption/conflict. My SPL is
quite large and I wonder if it exceeds some limit.
SPL is loaded to 0x92 and CONFIG_SPL_STACK is set to 0x96, which
leaves 256 KiB in between for the SPL. But all i.MX8MP boards seem to
set CONFIG_SPL_MAX_SIZE=0x26000 (152 KiB) for some reason. My
u-boot-spl-ddr.bin currently has around 193 KiB but I don't get any
warning about exceeding the SPL_MAX_SIZE.
My questions:
* Why is CONFIG_SPL_MAX_SIZE set to 152 KiB?
I guess the remainder between the SPL code and the SPL stack is for the
DDR firmware. Which explains why I get failures with SPL exceeding 152
KiB size.
Still, it doesn't really make sense to me at the moment as the
u-boot-spl-ddr.bin already contains the DDR firmware it should be fine
to exceed the 152 KiB size. My u-boot-spl.bin (without DDR firmware) is
only 135 KiB.
Sorry for spamming you by thinking out loud... ;)
Now I also understand the reason why the power init code was implemented
using legacy non-DM drivers in other i.MX8MP boards. I probably also
need to do this to save some space.
* Why is there no warning in my case?
Still, I fail to see why there isn't any error or where the size check
is even implemented.
* Any other ideas or pointers?
Thanks for your help!
Best regards
Frieder
Hello,
I fall in a similar problem.
Some hints:
- commit 5004901efb3b ("board_init: Do not reserve MALLOC_F area on stack
if non-zero MALLOC_F_ADDR") - but you should already have it
- Reduce (set to something different from default value) SPL_SYS_MALLOC_F_LEN.
Normally that area is not used a lot. Stack start before heap area and,
if I remember well, start address of heap area depend upon this config.
And... its default value is equal to SYS_MALLOC_F_LEN, that normally is high.
Suggestions from Rasmus are precious. I adopt a rather similar approch to find
that stack / gd (global data) was overlapping DDR firmware / cfg.
Best regards,
Emanuele Ghidoli
Default value for bootcmd not defined
Hello, I followed the official documentation [1] to build U-Boot for my Rock Pi 4, instead of evb-rk3399_defconfig I used the config file for my board (rock-pi-4-rk3399_defconfig). After I flashed the single boot image to an SD card and put it in I got stuck with the error message: "distro_bootcmd" not defined. Since I have no idea of U-Boot it took me some time to find out that all I needed was to set a different default value for bootcmd. Now I use CONFIG_BOOTCOMMAND="bootflow scan" and it boots my OS as expected. The official documentation looks straightforward for simple users like me, so I thought it might not be intended that the default value for the bootcmd entry is (still) distro_bootcmd. Regards, Stefan. [1] https://u-boot.readthedocs.io/en/latest/board/rockchip/rockchip.html -- E-Mails signieren & verschlüsseln · https://emailselfdefense.fsf.org/de/ signature.asc Description: This is a digitally signed message part
Re: [PATCH] board_r: Relocate OF_EMBED if NEEDS_MANUAL_RELOC only
> On Fri, Sep 09, 2022 at 09:16:18PM +0100, Pierre-Clément Tosi wrote: > >> When the embedded device tree is pointed to by the __dtb_dt_*begin >> symbols, it seems to be covered by the early relocation code and doesn't >> need to be manually patched. >> >> Cc: Simon Glass >> Signed-off-by: Pierre-Clément Tosi > > Applied to u-boot/master, thanks! Getting following error on Rpi3 board and fail to boot with u-boot upstream commit 76f921eb95d5b814f973a263187db509d6f03903: ERROR: invalid device tree EFI LOAD FAILED: continuing... As per bdinfo: fdt_blob= 0x000f4b00 Would like to understand the reasoning of this upstream commit 76f921eb95d5b814f973a263187db509d6f03903 and looking for proper fix for Rpi3. -Ajay
[PATCH v5 0/4] J721E HS Fixes
This series fixes the support for J721E board along with some maintainance for it. v5: - change the memory map to list-table v4: - Fix docs - applied reviewed-by v3: - drop fixes related to other boards ( make series j721e specific ) - memory map added in docs - applied reviewed-by v2: - Merge two series - Include some more commits that fix the gp builds when merging defconfigs - Update MAINTAINERS to remove hs related defconfigs - applied Acks Andrew Davis (1): arm: k3: config.mk: Add missing dependencies on tispl.bin HS Dave Gerlach (1): arm: mach-k3: Increase SYSFW max image size Manorit Chawdhry (2): configs: j721e: Merge the HS and non-HS defconfigs Kconfig: j721e: Change K3_MCU_SCRATCHPAD_BASE to non firewalled region MAINTAINERS| 2 - arch/arm/mach-k3/Kconfig | 6 +- arch/arm/mach-k3/config.mk | 2 + configs/j721e_evm_a72_defconfig| 3 +- configs/j721e_evm_r5_defconfig | 11 +- configs/j721e_hs_evm_a72_defconfig | 208 - configs/j721e_hs_evm_r5_defconfig | 176 doc/board/ti/j721e_evm.rst | 43 ++ 8 files changed, 59 insertions(+), 392 deletions(-) delete mode 100644 configs/j721e_hs_evm_a72_defconfig delete mode 100644 configs/j721e_hs_evm_r5_defconfig -- 2.34.1
[PATCH v5 1/4] arm: k3: config.mk: Add missing dependencies on tispl.bin HS
From: Andrew Davis When building for secure devices using non-buildman based image generation the signed tispl.bin file is called tispl.bin_HS. Also build the unsigned tispl.bin file as expected. Signed-off-by: Andrew Davis Signed-off-by: Manorit Chawdhry --- arch/arm/mach-k3/config.mk | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk index 9306f2627d9a..cbf9c10210a6 100644 --- a/arch/arm/mach-k3/config.mk +++ b/arch/arm/mach-k3/config.mk @@ -68,6 +68,8 @@ ifeq ($(CONFIG_TI_SECURE_DEVICE),y) SPL_ITS := u-boot-spl-k3_HS.its $(SPL_ITS): export IS_HS=1 INPUTS-y += tispl.bin_HS +INPUTS-y += tispl.bin +tispl.bin: $(obj)/u-boot-spl-nodtb.bin_HS $(patsubst %,$(obj)/dts/%.dtb_HS,$(subst ",,$(CONFIG_SPL_OF_LIST))) else SPL_ITS := u-boot-spl-k3.its INPUTS-y += tispl.bin -- 2.34.1
Re: [PATCH 0/9] Enable splash screen
Hi Simon, On 15/03/23 03:38, Simon Glass wrote: Hi Nikhil, On Mon, 13 Mar 2023 at 04:15, Nikhil M Jain wrote: To enable splash screen at SPL stage move video driver and splash screen framework at SPL, which will bring up image on display very quickly and thus have early display support in SPL. Nikhil M Jain (9): drivers: video: Kconfig: Necessary configs for video at SPL drivers: video: tidss: Kconfig: Configs to enable TIDSS at SPL cmd: Kconfig: Add necessary configs for splash screen at SPL drivers: video: Makefile: Compile video driver files at SPL drivers: video: tidss: Makefile: Add condition to compile TIDSS at SPL cmd: Makefile: Add rules to build bmp.c and read.c at SPL common: splash: Enable splash_display at SPL stage drivers: video: video-uclass: Disable u-boot logo at SPL board: ti: am62x: evm: OSPI support for splash screen board/ti/am62x/evm.c | 6 ++ cmd/Kconfig | 17 + cmd/Makefile | 2 ++ common/splash.c | 2 +- drivers/video/Kconfig| 32 drivers/video/Makefile | 6 ++ drivers/video/tidss/Kconfig | 6 ++ drivers/video/tidss/Makefile | 1 + drivers/video/video-uclass.c | 2 +- include/splash.h | 2 +- 10 files changed, 69 insertions(+), 7 deletions(-) I'm not necessarily arguing against this, but what is the need for this? How many milliseconds earlier does the image appear with this patch? What is the bottleneck? We should be able to get to U-Boot proper very quickly. There is a significant difference in time, by adding support in SPL splash screen comes up by approx 650ms and at u-boot proper it comes at 2.6s, measured from first print in console as seen on AM62x. Also we plan to skip u-boot proper and load kernel directly. Regards, Simon Regards, Nikhil
[PATCH v5 2/4] configs: j721e: Merge the HS and non-HS defconfigs
K3 devices have runtime type board detection. Make the default defconfig
include the secure configuration. Then remove the HS specific config.
Non-HS devices will continue to boot due to runtime device type detection.
If TI_SECURE_DEV_PKG is not set the build will emit warnings, for non-HS
devices these can be ignored.
Signed-off-by: Manorit Chawdhry
Acked-by: Andrew Davis
---
MAINTAINERS| 2 -
configs/j721e_evm_a72_defconfig| 3 +-
configs/j721e_evm_r5_defconfig | 1 +
configs/j721e_hs_evm_a72_defconfig | 208 -
configs/j721e_hs_evm_r5_defconfig | 176
5 files changed, 3 insertions(+), 387 deletions(-)
delete mode 100644 configs/j721e_hs_evm_a72_defconfig
delete mode 100644 configs/j721e_hs_evm_r5_defconfig
diff --git a/MAINTAINERS b/MAINTAINERS
index 41c9f265f815..9e5e51b2eeeb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1462,8 +1462,6 @@ F:configs/am65x_hs_evm_r5_defconfig
F: configs/am65x_hs_evm_a53_defconfig
F: configs/j7200_hs_evm_a72_defconfig
F: configs/j7200_hs_evm_r5_defconfig
-F: configs/j721e_hs_evm_a72_defconfig
-F: configs/j721e_hs_evm_r5_defconfig
F: configs/j721s2_hs_evm_a72_defconfig
F: configs/j721s2_hs_evm_r5_defconfig
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 2190df1f3a51..48b48f43e7ec 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x200
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
@@ -30,7 +31,7 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run
main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_kern_${boot}; run
get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
main_cpsw0_qsgmii_phyinit; run boot_rprocs; if test ${boot_fit} -eq 1; then run
get_fit_${boot}; run get_overlaystring; run run_fit; else; run
get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern;
fi;"
CONFIG_LOGLEVEL=7
CONFIG_SPL_MAX_SIZE=0xc
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 16fa386792d4..476072659571 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x200
CONFIG_SYS_MALLOC_F_LEN=0x7
CONFIG_SPL_GPIO=y
diff --git a/configs/j721e_hs_evm_a72_defconfig
b/configs/j721e_hs_evm_a72_defconfig
deleted file mode 100644
index 7aba55c2d488..
--- a/configs/j721e_hs_evm_a72_defconfig
+++ /dev/null
@@ -1,208 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_K3=y
-CONFIG_TI_SECURE_DEVICE=y
-CONFIG_SYS_MALLOC_LEN=0x200
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SOC_K3_J721E=y
-CONFIG_TARGET_J721E_A72_EVM=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8048
-CONFIG_ENV_SIZE=0x2
-CONFIG_DM_GPIO=y
-CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
-CONFIG_SPL_TEXT_BASE=0x8008
-CONFIG_DM_RESET=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x8200
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-# CONFIG_PSCI_RESET is not set
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_fit_${boot}; run
get_overlay_${boot}; run run_fit"
-CONFIG_LOGLEVEL=7
-CONFIG_SPL_MAX_SIZE=0xc
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x80a0
-CONFIG_SPL_BSS_MAX_SIZE=0x8
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x80
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
-CONFIG_SPL_DMA=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_I2C=y
-CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-# CONFIG_SPL_SPI_FLASH_TINY is not set
-CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x28
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_DFU=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_SYS_MAXARGS=64
[PATCH v5 3/4] Kconfig: j721e: Change K3_MCU_SCRATCHPAD_BASE to non firewalled region
In non-combined boot flow for K3, all the firewalls are locked by default
until sysfw comes up. Rom configures some of the firewall for its usage
along with the SRAM for R5 but the PSRAM region is still locked.
The K3 MCU Scratchpad for j721e was set to a PSRAM region triggering the
firewall exception before sysfw came up. The exception started happening
after adding multi dtb support that accesses the scratchpad for reading
EEPROM contents.
The commit changes R5 MCU scratchpad for j721e to an SRAM region.
Old Map:
┌─┐ 0x41c0
│ SPL │
├─┤ 0x41c4 (approx)
│STACK│
├─┤ 0x41c85b20
│ Global data │
│ sizeof(struct global_data) = 0xd8 │
├─┤ gd->malloc_base = 0x41c85bfc
│HEAP │
│ CONFIG_SYS_MALLOC_F_LEN = 0x7 │
├─┤ CONFIG_SPL_BSS_START_ADDR
│ SPL BSS │ (0x41cf5bfc)
│ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │
└─┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
(0x41cffbfc)
New Map:
┌─┐ 0x41c0
│ SPL │
├─┤ 0x41c4 (approx)
│EMPTY│
├─┤ 0x41c81920
│STACK│
│ SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 │
├─┤ 0x41c85920
│ Global data │
│ sizeof(struct global_data) = 0xd8 │
├─┤ gd->malloc_base = 0x41c859f0
│HEAP │
│ CONFIG_SYS_MALLOC_F_LEN = 0x7 │
├─┤ CONFIG_SPL_BSS_START_ADDR
│ SPL BSS │ (0x41cf59f0)
│ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │
├─┤ 0x41cff9fc
│ NEW MCU SCRATCHPAD │
│ SYS_K3_MCU_SCRATCHPAD_SIZE = 0x200 │
└─┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
(0x41cffbfc)
Fixes: ab977c8b91b4 ("configs: j721s2_evm_r5: Enable support for building
multiple dtbs into FIT")
Signed-off-by: Manorit Chawdhry
[n-fran...@ti.com: SRAM allocation addressing diagram]
Signed-off-by: Neha Francis
Reviewed-by: Tom Rini
Reviewed-by: Kamlesh Gurudasani
---
arch/arm/mach-k3/Kconfig | 3 ++-
configs/j721e_evm_r5_defconfig | 10 ++--
doc/board/ti/j721e_evm.rst | 43 ++
3 files changed, 53 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index a8c3a593d570..0991b42423a0 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -52,7 +52,8 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
config SYS_K3_MCU_SCRATCHPAD_BASE
hex
default 0x4028 if SOC_K3_AM654
- default 0x4028 if SOC_K3_J721E || SOC_K3_J721S2
+ default 0x4028 if SOC_K3_J721S2
+ default 0x41cff9fc if SOC_K3_J721E
help
Describes the base address of MCU Scratchpad RAM.
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 476072659571..afe1f3a31306 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -21,10 +21,16 @@ CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x8200
+CONFIG_SPL_SIZE_LIMIT=0xf59f0
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf59f0
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8008
@@ -32,9 +38,9 @@ CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_MAX_SIZE=0xc
+CONFIG_SPL_MAX_SIZE=0xf59f0
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x41cf5bfc
+CONFIG_SPL_BSS_START_ADDR=0x41cf59f0
CONFIG_SPL_BSS_MAX_SIZE=0xa000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst
index e898601c41ea..feaa2da5e9ac 100644
--- a/doc/board/ti/j721e_evm.rst
+++ b/doc/board/ti/j721e_evm.rst
@@ -268,6 +268,49 @@ Image formats:
| +---+ |
+---+
+R5 Memory Map:
+--
+
+.. list-table::
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Region
+ - Start Address
+ - End Address
+
+ * - SPL
+ - 0x41c0
+ - 0x41c4
+
+
Re: [PATCH v4 3/4] Kconfig: j721e: Change K3_MCU_SCRATCHPAD_BASE to non firewalled region
On 14:01-20230306, Tom Rini wrote:
> On Mon, Mar 06, 2023 at 11:12:53AM +0530, Manorit Chawdhry wrote:
> > In non-combined boot flow for K3, all the firewalls are locked by default
> > until sysfw comes up. Rom configures some of the firewall for its usage
> > along with the SRAM for R5 but the PSRAM region is still locked.
> >
> > The K3 MCU Scratchpad for j721e was set to a PSRAM region triggering the
> > firewall exception before sysfw came up. The exception started happening
> > after adding multi dtb support that accesses the scratchpad for reading
> > EEPROM contents.
> >
> > The commit changes R5 MCU scratchpad for j721e to an SRAM region.
> >
> > Old Map:
> > ┌─┐ 0x41c0
> > │ SPL │
> > ├─┤ 0x41c4 (approx)
> > │STACK│
> > ├─┤ 0x41c85b20
> > │ Global data │
> > │ sizeof(struct global_data) = 0xd8 │
> > ├─┤ gd->malloc_base = 0x41c85bfc
> > │HEAP │
> > │ CONFIG_SYS_MALLOC_F_LEN = 0x7 │
> > ├─┤ CONFIG_SPL_BSS_START_ADDR
> > │ SPL BSS │ (0x41cf5bfc)
> > │ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │
> > └─┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
> > (0x41cffbfc)
> >
> > New Map:
> > ┌─┐ 0x41c0
> > │ SPL │
> > ├─┤ 0x41c4 (approx)
> > │EMPTY│
> > ├─┤ 0x41c81920
> > │STACK│
> > │ SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 │
> > ├─┤ 0x41c85920
> > │ Global data │
> > │ sizeof(struct global_data) = 0xd8 │
> > ├─┤ gd->malloc_base = 0x41c859f0
> > │HEAP │
> > │ CONFIG_SYS_MALLOC_F_LEN = 0x7 │
> > ├─┤ CONFIG_SPL_BSS_START_ADDR
> > │ SPL BSS │ (0x41cf59f0)
> > │ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │
> > ├─┤ 0x41cff9fc
> > │ NEW MCU SCRATCHPAD │
> > │ SYS_K3_MCU_SCRATCHPAD_SIZE = 0x200 │
> > └─┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
> > (0x41cffbfc)
> >
> > Fixes: ab977c8b91b4 ("configs: j721s2_evm_r5: Enable support for building
> > multiple dtbs into FIT")
> >
> > Signed-off-by: Manorit Chawdhry
> > [n-fran...@ti.com: SRAM allocation addressing diagram]
> > Signed-off-by: Neha Francis
> > Reviewed-by: Tom Rini
> > Reviewed-by: Kamlesh Gurudasani
> > ---
> > arch/arm/mach-k3/Kconfig | 3 ++-
> > configs/j721e_evm_r5_defconfig | 10 --
> > doc/board/ti/j721e_evm.rst | 27 +++
>
> OK, but now this just renders differently poorly. Please see the
> list-table directive as used for example in doc/board/apple/m1.rst and
> it would be good to get other ascii tables updated to produce nice
> output as well.
>
Hi Tom,
I've updated this table in v5, we can look at updating other tables
later.
Thanks and regards,
Manorit
> --
> Tom
[PATCH v5 4/4] arm: mach-k3: Increase SYSFW max image size
From: Dave Gerlach When booting with HS silicon, the system firmware image is 278270, which is slightly larger than currently allocated amount. This can cause unexpected behavior if this overlap interferes with other things in memory, so increase this with a slightly margin added as well to avoid any boot issues that can appear after system firmware gets loaded. Signed-off-by: Dave Gerlach Signed-off-by: Tero Kristo Signed-off-by: Manorit Chawdhry --- arch/arm/mach-k3/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 0991b42423a0..bae0a827c29f 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -141,8 +141,7 @@ config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART config K3_SYSFW_IMAGE_SIZE_MAX int "Amount of memory dynamically allocated for loading SYSFW blob" depends on K3_LOAD_SYSFW - default 163840 if SOC_K3_AM625 || SOC_K3_AM62A7 - default 278000 + default 28 help Amount of memory (in bytes) reserved through dynamic allocation at runtime for loading the combined System Firmware and configuration image -- 2.34.1
Re: [PATCH v6 7/7] test: dm: fwu: fix for the updated api
On Mon, Mar 06, 2023 at 05:18:58PM -0600, jassisinghb...@gmail.com wrote:
> From: Jassi Brar
>
> fwu_get_mdata() no more requires 'dev' argument and
> fwu_check_mdata_validity() has been rendered useless and dropped.
> Fix the test cases to work with aforementioned changes.
>
> Signed-off-by: Jassi Brar
> ---
> test/dm/fwu_mdata.c | 22 +++---
> 1 file changed, 3 insertions(+), 19 deletions(-)
>
> diff --git a/test/dm/fwu_mdata.c b/test/dm/fwu_mdata.c
> index b179a65c15..8b5c83ef4e 100644
> --- a/test/dm/fwu_mdata.c
> +++ b/test/dm/fwu_mdata.c
> @@ -98,7 +98,7 @@ static int dm_test_fwu_mdata_read(struct unit_test_state
> *uts)
> ut_assertok(populate_mmc_disk_image(uts));
> ut_assertok(write_mmc_blk_device(uts));
>
> - ut_assertok(fwu_get_mdata(dev, ));
> + ut_assertok(fwu_get_mdata());
>
> ut_asserteq(mdata.version, 0x1);
>
> @@ -118,30 +118,14 @@ static int dm_test_fwu_mdata_write(struct
> unit_test_state *uts)
>
> ut_assertok(uclass_first_device_err(UCLASS_FWU_MDATA, ));
>
> - ut_assertok(fwu_get_mdata(dev, ));
> + ut_assertok(fwu_get_mdata());
>
> active_idx = (mdata.active_index + 1) % CONFIG_FWU_NUM_BANKS;
> ut_assertok(fwu_set_active_index(active_idx));
>
> - ut_assertok(fwu_get_mdata(dev, ));
> + ut_assertok(fwu_get_mdata());
> ut_asserteq(mdata.active_index, active_idx);
>
> return 0;
> }
> DM_TEST(dm_test_fwu_mdata_write, UT_TESTF_SCAN_FDT);
> -
> -static int dm_test_fwu_mdata_check(struct unit_test_state *uts)
> -{
> - struct udevice *dev;
> -
> - ut_assertok(setup_blk_device(uts));
> - ut_assertok(populate_mmc_disk_image(uts));
> - ut_assertok(write_mmc_blk_device(uts));
> -
> - ut_assertok(uclass_first_device_err(UCLASS_FWU_MDATA, ));
> -
> - ut_assertok(fwu_check_mdata_validity());
> -
> - return 0;
> -}
> -DM_TEST(dm_test_fwu_mdata_check, UT_TESTF_SCAN_FDT);
> --
> 2.34.1
>
Acked-by: Ilias Apalodimas
Re: [PATCH v1 1/7] arm: dts: rockchip: rk3288: move io-domains nodes
On Tue, Mar 14, 2023 at 07:13:30PM +0100, Johan Jonker wrote:
> In order to better compare the Linux rk3288.dtsi version
> with the u-boot version move the io-domains nodes.
>
> Signed-off-by: Johan Jonker
A few minor nits below, but with or without those fixed this is a step
in the right direction.
Reviewed-by: John Keeping
> ---
> arch/arm/dts/rk3288-miqi.dtsi| 27 +++--
> arch/arm/dts/rk3288-phycore-som.dtsi | 30 +---
> arch/arm/dts/rk3288-popmetal.dtsi| 30 +---
> arch/arm/dts/rk3288-veyron.dtsi | 28 --
> arch/arm/dts/rk3288.dtsi | 5 +
> 5 files changed, 58 insertions(+), 62 deletions(-)
>
> diff --git a/arch/arm/dts/rk3288-miqi.dtsi b/arch/arm/dts/rk3288-miqi.dtsi
> index cb80cbf2..00c8613d 100644
> --- a/arch/arm/dts/rk3288-miqi.dtsi
> +++ b/arch/arm/dts/rk3288-miqi.dtsi
> @@ -18,21 +18,6 @@
> clock-output-names = "ext_gmac";
> };
>
> - io_domains: io-domains {
> - compatible = "rockchip,rk3288-io-voltage-domain";
> - rockchip,grf = <>;
> -
> - audio-supply = <_33>;
> - flash0-supply = <_flash>;
> - flash1-supply = <_lan>;
> - gpio30-supply = <_io>;
> - gpio1830-supply = <_io>;
> - lcdc-supply = <_io>;
> - sdcard-supply = <_sd>;
> - wifi-supply = <_18>;
> - };
> -
> -
> leds {
> compatible = "gpio-leds";
>
> @@ -277,6 +262,18 @@
> status = "okay";
> };
>
> +_domains {
> + audio-supply = <_33>;
> + flash0-supply = <_flash>;
> + flash1-supply = <_lan>;
> + gpio30-supply = <_io>;
> + gpio1830-supply = <_io>;
> + lcdc-supply = <_io>;
> + sdcard-supply = <_sd>;
> + wifi-supply = <_18>;
> + status = "okay";
To match Linux, the status property should be at the top.
> +};
> +
> {
> pcfg_output_high: pcfg-output-high {
> output-high;
> diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi
> b/arch/arm/dts/rk3288-phycore-som.dtsi
> index 821525f7..70c00308 100644
> --- a/arch/arm/dts/rk3288-phycore-som.dtsi
> +++ b/arch/arm/dts/rk3288-phycore-som.dtsi
> @@ -71,22 +71,6 @@
> clock-output-names = "ext_gmac";
> };
>
> - io_domains: io_domains {
> - compatible = "rockchip,rk3288-io-voltage-domain";
> -
> - status = "okay";
> - sdcard-supply = <_io_sd>;
> - flash0-supply = <_emmc_io>;
> - flash1-supply = <_misc_1v8>;
> - gpio1830-supply = <_3v3_io>;
> - gpio30-supply = <_3v3_io>;
> - bb-supply = <_3v3_io>;
> - dvp-supply = <_3v3_io>;
> - lcdc-supply = <_3v3_io>;
> - wifi-supply = <_3v3_io>;
> - audio-supply = <_3v3_io>;
> - };
> -
> leds: user-leds {
> compatible = "gpio-leds";
> pinctrl-names = "default";
> @@ -197,6 +181,20 @@
> ddc-i2c-bus = <>;
> };
>
> +_domains {
> + audio-supply = <_3v3_io>;
> + bb-supply = <_3v3_io>;
> + dvp-supply = <_3v3_io>;
> + flash0-supply = <_emmc_io>;
> + flash1-supply = <_misc_1v8>;
> + gpio1830-supply = <_3v3_io>;
> + gpio30-supply = <_3v3_io>;
> + lcdc-supply = <_3v3_io>;
> + sdcard-supply = <_io_sd>;
> + wifi-supply = <_3v3_io>;
> + status = "okay";
Likewise, the Linux version of this file has status at the top (although
the supplies are sorted very strangely in the Linux version).
> +};
> +
> {
> status = "okay";
> clock-frequency = <40>;
> diff --git a/arch/arm/dts/rk3288-popmetal.dtsi
> b/arch/arm/dts/rk3288-popmetal.dtsi
> index 0253933a..d732a706 100644
> --- a/arch/arm/dts/rk3288-popmetal.dtsi
> +++ b/arch/arm/dts/rk3288-popmetal.dtsi
> @@ -71,22 +71,6 @@
> };
> };
>
> - io_domains: io-domains {
> - compatible = "rockchip,rk3288-io-voltage-domain";
> - rockchip,grf = <>;
> -
> - audio-supply = <_33>;
> - bb-supply = <_io>;
> - dvp-supply = <_dvp>;
> - flash0-supply = <_flash>;
> - flash1-supply = <_lan>;
> - gpio30-supply = <_io>;
> - gpio1830-supply = <_io>;
> - lcdc-supply = <_io>;
> - sdcard-supply = <_sd>;
> - wifi-supply = <_wl>;
> - };
> -
> ir: ir-receiver {
> compatible = "gpio-ir-receiver";
> gpios = < 6 GPIO_ACTIVE_LOW>;
> @@ -443,6 +427,20 @@
> status = "okay";
> };
>
> +_domains {
> + audio-supply = <_33>;
> + bb-supply = <_io>;
> + dvp-supply = <_dvp>;
> + flash0-supply = <_flash>;
> + flash1-supply = <_lan>;
> + gpio30-supply = <_io>;
> + gpio1830-supply = <_io>;
> + lcdc-supply = <_io>;
> + sdcard-supply = <_sd>;
> + wifi-supply = <_wl>;
> + status = "okay";
Re: [PATCH v2 2/5] tools: relocate-rela: introduce elf16_to_cpu() and elf32_to_cpu()
On 3/11/23 18:38, Ovidiu Panait wrote: Add elf16_to_cpu() and elf32_to_cpu() functions that allow to read data in both big-endian and little-endian formats. Reviewed-by: Michal Simek I didn't give you this line in v1. But patch looks fine now. Applied the whole series. Thanks, Michal
[GIT PULL] xilinx patches for v2023.07-rc1
Hi Tom, please pull these patches to your next branch. CI loop doesn't report any issue. Thanks, Michal The following changes since commit 70ed05ce6c051e55e126e67e72ab20409134c953: Merge tag 'next-20230307' of https://source.denx.de/u-boot/custodians/u-boot-video into next (2023-03-07 12:54:01 -0500) are available in the Git repository at: g...@source.denx.de:u-boot/custodians/u-boot-microblaze.git tags/xilinx-for-v2023.07-rc1 for you to fetch changes up to 7ac50f88f8a9374e5cb4bc2a88c002d02ef3c570: microblaze: drop remnants of manual reloc (2023-03-13 11:46:17 +0100) Xilinx changes for v2023.07-rc1 cmd: - Print results in hex instead of dec in smc command firmware: - Cover missing ZYNQMP_FIRMWARE dependencies fpga: - fix loads for unencrypted use case relocation - Add support for BE systems spi: - Fix xilinx_spi init reset sequence arasan nand: - Remove hardcoded bbt option - Set ofnode value xilinx: - Enable SMC command - Fix some sparse issues zynqmp: - Remove cdns,zynq-gem compatible string - Add optee node - Some DT cleanups zynq: - Some DT cleanups microblaze - Remove MANUAL_RELOC option Algapally Santosh Sagar (3): arm64: zynqmp: Add missing ZYNQMP_FIRMWARE dependencies xilinx: zynqmp: Add missing prototype for zynqmp_mmio_write spl: Add missing prototype for board_boot_order Ashok Reddy Soma (4): mtd: nand: arasan: Remove hardcoded bbt option mtd: nand: arasan: Set ofnode value arm64: dts: zynqmp: Fix nand dt node arm64: dts: zynqmp: Enable nand-on-flash-bbt in DT by default Ilias Apalodimas (1): arm64: zynqmp: Add an OP-TEE node to the device tree Jiajie Chen (1): spi: xilinx_spi: Fix spi reset Krzysztof Kozlowski (3): arm64: dts: xilinx: align LED node names with dtschema ARM: dts: xilinx: align gpio-key node names with dtschema ARM: dts: zynq-7000: drop useless 'dma-channels/requests' properties Michael Grzeschik (1): arm64: zynqmp: Enable hs termination flag for USB dwc3 controller Michal Simek (6): xilinx: dts: Remove cdns,zynq-gem ARM: zynq: Use recommended dma-controller name instead of dmac ARM: zynq: Comment interrupt names IRQs for pl330 cmd: smccc: Print results in hex instead of dec xilinx: Enable SMC command for arm64 targets arm64: zynqmp: Remove comment about gem spec in kv260 Neal Frager (1): fpga: zynqmppl: fix fpga loads command for unencrypted use case Ovidiu Panait (5): tools: relocate-rela: adjust le64_to_cpu -> le32_to_cpu in decode_elf32() tools: relocate-rela: introduce elf16_to_cpu() and elf32_to_cpu() tools: relocate-rela: add support for handling 32-bit big endian files microblaze: drop CONFIG_NEEDS_MANUAL_RELOC microblaze: drop remnants of manual reloc arch/arm/dts/zynq-7000.dtsi | 14 +-- arch/arm/dts/zynq-zc702.dts | 4 +- arch/arm/dts/zynq-zturn-common.dtsi | 2 +- arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 2 +- arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 4 +- arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 4 +- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 + arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 119 arch/arm/dts/zynqmp-zcu100-revC.dts | 2 +- arch/arm/dts/zynqmp.dtsi | 15 ++- arch/arm/mach-versal-net/include/mach/sys_proto.h | 7 +- arch/arm/mach-versal/include/mach/sys_proto.h | 6 +- arch/microblaze/Kconfig | 13 +-- arch/microblaze/config.mk | 4 - arch/microblaze/cpu/Makefile | 3 +- arch/microblaze/cpu/start.S | 28 - board/xilinx/zynqmp/Kconfig | 1 + cmd/smccc.c | 2 +- configs/xilinx_versal_net_virt_defconfig | 1 + configs/xilinx_versal_virt_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 + drivers/clk/Kconfig | 4 +- drivers/fpga/Kconfig | 2 +- drivers/fpga/zynqmppl.c | 12 +- drivers/mmc/zynq_sdhci.c | 5 +- drivers/mtd/nand/raw/arasan_nfc.c | 5 +- drivers/net/zynq_gem.c| 2 +- drivers/spi/xilinx_spi.c | 5 +- drivers/spi/zynqmp_gqspi.c| 5 + include/spl.h | 1 + tools/relocate-rela.c | 52 ++--- 32 files changed, 175 insertions(+), 155 deletions(-) -- Michal Simek, Ing. (M.Eng), OpenPGP ->
Re: [PATCH 0/2] drivers: net: fsl-mc: fix MAC address fixup procedure
On Thu, Feb 09, 2023 at 06:07:02PM +0200, Ioana Ciornei wrote: > This patch set fixes the MAC address fixup procedure which was impacted > by several changes in the phy_interface_t used to describe some > interfaces. The transitions from "xgmii" to "xfi" and then finally > to "10gbase-r" were involved. > > The first patch just exports a function to identify the DPMAC id of an > UCLASS_ETH device and the DPAA2 driver name as a macro. > > Ioana Ciornei (2): > drivers: net: ldpaa: export driver name and API to get DPMAC id > drivers: net: fsl-mc: fix MAC address fixup procedure > Is there any chance for this two patches to be picked up for the v2023.04 release?
[PATCH] configs: convert NXP LS1028A RDB and QDS to DM_SERIAL
Since the device trees are more or less synchronized with Linux, the only necessary changes are to enable CONFIG_DM_SERIAL and the DM_SERIAL driver for ns16550 (ns16550.c rather than serial_ns16550.c). ls1028aqds_tfa_lpuart_defconfig already uses DM_SERIAL for the LPUART driver, so I didn't touch that. Signed-off-by: Vladimir Oltean --- configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 3 ++- configs/ls1028aqds_tfa_defconfig | 3 ++- configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 3 ++- configs/ls1028ardb_tfa_defconfig | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 525c7df6d0f4..76607920e2b8 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -86,7 +86,8 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index dde204eaa0df..e054e1781899 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -92,7 +92,8 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index b8df245025f3..5fa1c936eef0 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -80,7 +80,8 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 5b1cf988cf07..a73a8092a3e8 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -86,7 +86,8 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y -- 2.34.1
[PATCH 03/10] arch: arm: dts: fsl-ls1088a.dtsi: sync serial nodes with Linux
Sync the serial nodes of the LS1088A based boards with their
representation in Linux. We also imported the clockgen and sysclk nodes
which are dependencies.
Signed-off-by: Ioana Ciornei
---
arch/arm/dts/fsl-ls1088a-qds.dtsi | 8 +++
arch/arm/dts/fsl-ls1088a-rdb.dts | 8 +++
arch/arm/dts/fsl-ls1088a-ten64.dts | 6 +++--
arch/arm/dts/fsl-ls1088a.dtsi | 35 ++
4 files changed, 46 insertions(+), 11 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a-qds.dtsi
b/arch/arm/dts/fsl-ls1088a-qds.dtsi
index 85dc7457bfb3..4d21d4fbd5e0 100644
--- a/arch/arm/dts/fsl-ls1088a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1088a-qds.dtsi
@@ -132,6 +132,14 @@
};
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
{
bus-num = <0>;
status = "okay";
diff --git a/arch/arm/dts/fsl-ls1088a-rdb.dts b/arch/arm/dts/fsl-ls1088a-rdb.dts
index 01f8fcb61aef..c63d4158e49f 100644
--- a/arch/arm/dts/fsl-ls1088a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1088a-rdb.dts
@@ -142,6 +142,14 @@
};
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
{
status = "okay";
diff --git a/arch/arm/dts/fsl-ls1088a-ten64.dts
b/arch/arm/dts/fsl-ls1088a-ten64.dts
index 43b669c642ce..55a7d41fb01b 100644
--- a/arch/arm/dts/fsl-ls1088a-ten64.dts
+++ b/arch/arm/dts/fsl-ls1088a-ten64.dts
@@ -20,6 +20,8 @@
compatible = "traverse,ten64", "fsl,ls1088a";
aliases {
+ serial0 =
+ serial1 =
spi0 =
};
@@ -164,11 +166,11 @@
status = "okay";
};
- {
+ {
status = "okay";
};
- {
+ {
status = "okay";
};
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index 0eb0f6c41aef..b094bcf67c4f 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -2,9 +2,10 @@
/*
* NXP ls1088a SOC common device tree source
*
- * Copyright 2017, 2020-2021 NXP
+ * Copyright 2017, 2020-2021, 2023 NXP
*/
+#include
#include
/ {
compatible = "fsl,ls1088a";
@@ -35,6 +36,13 @@
<1 10 0x8>; /* Hypervisor PPI, active-low */
};
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1>;
+ clock-output-names = "sysclk";
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -42,20 +50,29 @@
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x>;
- serial0: serial@21c0500 {
- device_type = "serial";
+ clockgen: clocking@130 {
+ compatible = "fsl,ls1088a-clockgen";
+ reg = <0 0x130 0 0xa>;
+ #clock-cells = <2>;
+ clocks = <>;
+ };
+
+ duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0500 0x0 0x100>;
- clock-frequency = <0>; /* Updated by bootloader */
- interrupts = <0 32 0x1>; /* edge triggered */
+ clocks = < QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
- serial1: serial@21c0600 {
- device_type = "serial";
+ duart1: serial@21c0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0600 0x0 0x100>;
- clock-frequency = <0>; /* Updated by bootloader */
- interrupts = <0 32 0x1>; /* edge triggered */
+ clocks = < QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
};
--
2.25.1
[PATCH 01/10] arch: arm: dts: fsl-ls1088a.dtsi: add an 'soc' node
The u-boot dts for these boards do not have an soc node, unlike its
Linux counterpart. This patch just adds the soc node as seen in Linux,
the next patches will move some nodes under it.
Signed-off-by: Ioana Ciornei
---
arch/arm/dts/fsl-ls1088a.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index 9b7c54b260e2..36ec0ff51f2a 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -35,6 +35,15 @@
<1 10 0x8>; /* Hypervisor PPI, active-low */
};
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x>;
+
+ };
+
i2c0: i2c@200 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
--
2.25.1
[PATCH 02/10] arch: arm: dts: fsl-ls1088a.dtsi: move the serial nodes under soc
Move the serial nodes under the soc node. No changes are made to the
nodes, just their location is changed.
Signed-off-by: Ioana Ciornei
---
arch/arm/dts/fsl-ls1088a.dtsi | 31 +++
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index 36ec0ff51f2a..0eb0f6c41aef 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -42,6 +42,21 @@
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x>;
+ serial0: serial@21c0500 {
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0500 0x0 0x100>;
+ clock-frequency = <0>; /* Updated by bootloader */
+ interrupts = <0 32 0x1>; /* edge triggered */
+ };
+
+ serial1: serial@21c0600 {
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0600 0x0 0x100>;
+ clock-frequency = <0>; /* Updated by bootloader */
+ interrupts = <0 32 0x1>; /* edge triggered */
+ };
};
i2c0: i2c@200 {
@@ -76,22 +91,6 @@
interrupts = <0 35 4>;
};
- serial0: serial@21c0500 {
- device_type = "serial";
- compatible = "fsl,ns16550", "ns16550a";
- reg = <0x0 0x21c0500 0x0 0x100>;
- clock-frequency = <0>; /* Updated by bootloader */
- interrupts = <0 32 0x1>; /* edge triggered */
- };
-
- serial1: serial@21c0600 {
- device_type = "serial";
- compatible = "fsl,ns16550", "ns16550a";
- reg = <0x0 0x21c0600 0x0 0x100>;
- clock-frequency = <0>; /* Updated by bootloader */
- interrupts = <0 32 0x1>; /* edge triggered */
- };
-
dspi: dspi@210 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
--
2.25.1
[PATCH 00/10] Convert LS1088A and LX2160 to DM_SERIAL
This patch set converts the LS1088A and LX216X based boards to DM_SERIAL. Since we don't want to introduce even more differences between the U-Boot's and Linux's device trees, the DT patches make the necessary updates so that the serial nodes are synced with their counterpart. We also update the LS1088A's defconfigs so that DM_SERIAL is enabled. On LX2160A's defconfigs these updates are not needed since DM_SERIAL was already enabled. On the other hand, we did remove the hardcoded PL01X device instantiation from the board files in the last patch. Ioana Ciornei (10): arch: arm: dts: fsl-ls1088a.dtsi: add an 'soc' node arch: arm: dts: fsl-ls1088a.dtsi: move the serial nodes under soc arch: arm: dts: fsl-ls1088a.dtsi: sync serial nodes with Linux arch: arm: dts: fsl-ls1088a.dtsi: tag serial nodes with bootph-all configs: ls1088a: enable DM_SERIAL arch: arm: dts: fsl-lx2160a.dtsi: add an 'soc' node arch: arm: dts: fsl-lx2160a.dtsi: move the serial nodes under soc arch: arm: dts: fsl-lx2160a.dtsi: sync serial nodes with Linux arch: arm: dts: fsl-lx2160a.dtsi: tag serial nodes with bootph-all board: freescale: lx2160a: remove the PL01X device instantiation arch/arm/dts/fsl-ls1088a-qds.dtsi| 8 +++ arch/arm/dts/fsl-ls1088a-rdb.dts | 8 +++ arch/arm/dts/fsl-ls1088a-ten64.dts | 6 +- arch/arm/dts/fsl-ls1088a.dtsi| 61 +++- arch/arm/dts/fsl-lx2160a-qds.dtsi| 11 ++- arch/arm/dts/fsl-lx2160a-rdb.dts | 11 ++- arch/arm/dts/fsl-lx2160a.dtsi| 74 board/freescale/lx2160a/lx2160a.c| 34 - configs/ls1088aqds_tfa_defconfig | 4 +- configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 4 +- configs/ls1088ardb_tfa_defconfig | 4 +- 11 files changed, 138 insertions(+), 87 deletions(-) -- 2.25.1
[PATCH 07/10] arch: arm: dts: fsl-lx2160a.dtsi: move the serial nodes under soc
Move the serial nodes under the soc node. No changes are made to the
nodes, just their location is changed.
Signed-off-by: Ioana Ciornei
---
arch/arm/dts/fsl-lx2160a.dtsi | 56 +--
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 08f160f6989f..58a408d2dc34 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -33,6 +33,34 @@
#size-cells = <2>;
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x>;
+
+ uart0: serial@21c {
+ compatible = "arm,pl011";
+ reg = <0x0 0x21c 0x0 0x1000>;
+ clocks = < 4 0>;
+ status = "disabled";
+ };
+
+ uart1: serial@21d {
+ compatible = "arm,pl011";
+ reg = <0x0 0x21d 0x0 0x1000>;
+ clocks = < 4 0>;
+ status = "disabled";
+ };
+
+ uart2: serial@21e {
+ compatible = "arm,pl011";
+ reg = <0x0 0x21e 0x0 0x1000>;
+ clocks = < 4 0>;
+ status = "disabled";
+ };
+
+ uart3: serial@21f {
+ compatible = "arm,pl011";
+ reg = <0x0 0x21f 0x0 0x1000>;
+ clocks = < 4 0>;
+ status = "disabled";
+ };
};
crypto: crypto@800 {
@@ -185,34 +213,6 @@
status = "disabled";
};
- uart0: serial@21c {
- compatible = "arm,pl011";
- reg = <0x0 0x21c 0x0 0x1000>;
- clocks = < 4 0>;
- status = "disabled";
- };
-
- uart1: serial@21d {
- compatible = "arm,pl011";
- reg = <0x0 0x21d 0x0 0x1000>;
- clocks = < 4 0>;
- status = "disabled";
- };
-
- uart2: serial@21e {
- compatible = "arm,pl011";
- reg = <0x0 0x21e 0x0 0x1000>;
- clocks = < 4 0>;
- status = "disabled";
- };
-
- uart3: serial@21f {
- compatible = "arm,pl011";
- reg = <0x0 0x21f 0x0 0x1000>;
- clocks = < 4 0>;
- status = "disabled";
- };
-
dspi0: dspi@210 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
--
2.25.1
[PATCH 05/10] configs: ls1088a: enable DM_SERIAL
Now that the DT nodes for the serial devices are in place for these boards, enable DM_SERIAL in the associated configs. Signed-off-by: Ioana Ciornei --- configs/ls1088aqds_tfa_defconfig | 4 +++- configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 4 +++- configs/ls1088ardb_tfa_defconfig | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index c8ab5723539a..3e103b93c8c8 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -118,7 +118,9 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 0ec80be2ea6a..d57ef3e8adf1 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -90,7 +90,9 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index 27323be40890..32d43aa653d1 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -96,7 +96,9 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y -- 2.25.1
[PATCH 06/10] arch: arm: dts: fsl-lx2160a.dtsi: add an 'soc' node
The u-boot dts for these boards do not have an soc node, unlike its
Linux counterpart. This patch just adds the soc node as seen in Linux,
the next patches will move some nodes under it.
Signed-off-by: Ioana Ciornei
---
arch/arm/dts/fsl-lx2160a.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 57c7d3ef7111..08f160f6989f 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -27,6 +27,14 @@
clock-output-names = "sysclk";
};
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x>;
+ };
+
crypto: crypto@800 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <10>;
--
2.25.1
[PATCH 09/10] arch: arm: dts: fsl-lx2160a.dtsi: tag serial nodes with bootph-all
Tag the serial nodes with bootph-all in order to have these nodes and
the drivers available before relocation.
Signed-off-by: Ioana Ciornei
---
arch/arm/dts/fsl-lx2160a.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 0b0f317f3056..680c69c7b738 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -40,6 +40,7 @@
interrupts = ;
current-speed = <115200>;
status = "disabled";
+ bootph-all;
};
uart1: serial@21d {
@@ -48,6 +49,7 @@
interrupts = ;
current-speed = <115200>;
status = "disabled";
+ bootph-all;
};
uart2: serial@21e {
@@ -56,6 +58,7 @@
interrupts = ;
current-speed = <115200>;
status = "disabled";
+ bootph-all;
};
uart3: serial@21f {
@@ -64,6 +67,7 @@
interrupts = ;
current-speed = <115200>;
status = "disabled";
+ bootph-all;
};
};
--
2.25.1
[PATCH 04/10] arch: arm: dts: fsl-ls1088a.dtsi: tag serial nodes with bootph-all
Tag the serial nodes with bootph-all in order to have these nodes and
the drivers available before relocation.
Signed-off-by: Ioana Ciornei
---
arch/arm/dts/fsl-ls1088a.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index b094bcf67c4f..4782b83515af 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -64,6 +64,7 @@
QORIQ_CLK_PLL_DIV(4)>;
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
+ bootph-all;
};
duart1: serial@21c0600 {
@@ -73,6 +74,7 @@
QORIQ_CLK_PLL_DIV(4)>;
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
+ bootph-all;
};
};
--
2.25.1
[PATCH 10/10] board: freescale: lx2160a: remove the PL01X device instantiation
There is no need for the board file to instantiate a PL01X platform
device anymore. This is all taken care of by the DM code which now will
probe the device based on the DT node.
Signed-off-by: Ioana Ciornei
---
board/freescale/lx2160a/lx2160a.c | 34 ---
1 file changed, 34 deletions(-)
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index 33842d02178a..2a752054cd99 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -55,45 +55,11 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct pl01x_serial_plat serial0 = {
-#if CONFIG_CONS_INDEX == 0
- .base = CFG_SYS_SERIAL0,
-#elif CONFIG_CONS_INDEX == 1
- .base = CFG_SYS_SERIAL1,
-#else
-#error "Unsupported console index value."
-#endif
- .type = TYPE_PL011,
-};
-
-U_BOOT_DRVINFO(nxp_serial0) = {
- .name = "serial_pl01x",
- .plat = ,
-};
-
-static struct pl01x_serial_plat serial1 = {
- .base = CFG_SYS_SERIAL1,
- .type = TYPE_PL011,
-};
-
-U_BOOT_DRVINFO(nxp_serial1) = {
- .name = "serial_pl01x",
- .plat = ,
-};
-
-static void uart_get_clock(void)
-{
- serial0.clock = get_serial_clock();
- serial1.clock = get_serial_clock();
-}
-
int board_early_init_f(void)
{
#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD)
i2c_early_init_f();
#endif
- /* get required clock for UART IP */
- uart_get_clock();
#ifdef CONFIG_EMC2305
select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305, 0);
--
2.25.1
[PATCH 08/10] arch: arm: dts: fsl-lx2160a.dtsi: sync serial nodes with Linux
Sync the serial nodes of the LX2160A based boards with their
representation in Linux. We also imported the clockgen and sysclk nodes
which are dependencies.
Signed-off-by: Ioana Ciornei
---
arch/arm/dts/fsl-lx2160a-qds.dtsi | 11 ++-
arch/arm/dts/fsl-lx2160a-rdb.dts | 11 ++-
arch/arm/dts/fsl-lx2160a.dtsi | 22 +-
3 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi
b/arch/arm/dts/fsl-lx2160a-qds.dtsi
index 6635c5258590..e96605b1b4fb 100644
--- a/arch/arm/dts/fsl-lx2160a-qds.dtsi
+++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi
@@ -2,7 +2,7 @@
/*
* NXP LX2160AQDS common device tree source
*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2020, 2023 NXP
*
*/
@@ -11,6 +11,7 @@
/ {
aliases {
spi0 =
+ serial0 =
};
};
@@ -286,3 +287,11 @@
{
status = "okay";
};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts
index 399409776e74..aaa59598bd4c 100644
--- a/arch/arm/dts/fsl-lx2160a-rdb.dts
+++ b/arch/arm/dts/fsl-lx2160a-rdb.dts
@@ -5,7 +5,7 @@
* Author: Priyanka Jain
* Sriram Dash
*
- * Copyright 2018 NXP
+ * Copyright 2018, 2023 NXP
*
*/
@@ -18,6 +18,7 @@
compatible = "fsl,lx2160ardb", "fsl,lx2160a";
aliases {
spi0 =
+ serial0 =
};
};
@@ -137,3 +138,11 @@
{
status = "okay";
};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 58a408d2dc34..0b0f317f3056 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -2,7 +2,7 @@
/*
* NXP lx2160a SOC common device tree source
*
- * Copyright 2018-2021 NXP
+ * Copyright 2018-2021, 2023 NXP
*
*/
@@ -35,30 +35,34 @@
dma-ranges = <0x0 0x0 0x0 0x0 0x1 0x>;
uart0: serial@21c {
- compatible = "arm,pl011";
+ compatible = "arm,sbsa-uart","arm,pl011";
reg = <0x0 0x21c 0x0 0x1000>;
- clocks = < 4 0>;
+ interrupts = ;
+ current-speed = <115200>;
status = "disabled";
};
uart1: serial@21d {
- compatible = "arm,pl011";
+ compatible = "arm,sbsa-uart","arm,pl011";
reg = <0x0 0x21d 0x0 0x1000>;
- clocks = < 4 0>;
+ interrupts = ;
+ current-speed = <115200>;
status = "disabled";
};
uart2: serial@21e {
- compatible = "arm,pl011";
+ compatible = "arm,sbsa-uart","arm,pl011";
reg = <0x0 0x21e 0x0 0x1000>;
- clocks = < 4 0>;
+ interrupts = ;
+ current-speed = <115200>;
status = "disabled";
};
uart3: serial@21f {
- compatible = "arm,pl011";
+ compatible = "arm,sbsa-uart","arm,pl011";
reg = <0x0 0x21f 0x0 0x1000>;
- clocks = < 4 0>;
+ interrupts = ;
+ current-speed = <115200>;
status = "disabled";
};
};
--
2.25.1
Re: [PATCH] configs: convert NXP LS1028A RDB and QDS to DM_SERIAL
On Wed, Mar 15, 2023 at 01:01:16PM +0200, Vladimir Oltean wrote: > Since the device trees are more or less synchronized with Linux, the > only necessary changes are to enable CONFIG_DM_SERIAL and the DM_SERIAL > driver for ns16550 (ns16550.c rather than serial_ns16550.c). > > ls1028aqds_tfa_lpuart_defconfig already uses DM_SERIAL for the LPUART > driver, so I didn't touch that. > > Signed-off-by: Vladimir Oltean Reviewed-by: Ioana Ciornei
RE: [PATCH 1/2] Revert "mmc: s5p_sdhci: unset the SDHCI_QUIRK_BROKEN_R1B"
Hi Jaehoon
> commit 4a3ea75de4c5b3053eac326bf1c753ed65df8cb9
> Author: yuezhang...@sony.com
> Date: Wed Mar 17 06:44:37 2021 +
>
> Revert "mmc: sdhci: set to INT_DATA_END when there are data"
>
> This reverts commit 17ea3c862865c0d704646f67dbf8412f9ff54f59.
>
> Revert the above commit.
>
> To Andy,
>
> Was there any problem without above commit?
Without above revert commit, we found "sdhci_transfer_data: Transfer data
timeout" on db410c board with v2018.01.
Best Regards
Andy Wu
> -Original Message-
> From: Jaehoon Chung
> Sent: Monday, March 13, 2023 9:03 PM
> To: Henrik Grimler ; Jaehoon Chung
>
> Cc: jo...@diskos.nl; peng@nxp.com; Wu, Andy ;
> s...@chromium.org; u-boot@lists.denx.de;
> ~postmarketos/upstream...@lists.sr.ht
> Subject: Re: [PATCH 1/2] Revert "mmc: s5p_sdhci: unset the
> SDHCI_QUIRK_BROKEN_R1B"
>
> Hi,
>
> On 3/11/23 19:31, Henrik Grimler wrote:
> > Hi Jaehoon,
> >
> > On Fri, Feb 10, 2023 at 09:00:33AM +0900, Jaehoon Chung wrote:
> >> Hi,
> >>
> >>> -Original Message-
> >>> From: U-Boot On Behalf Of Henrik
> >>> Grimler
> >>> Sent: Thursday, February 9, 2023 4:04 AM
> >>> To: jo...@diskos.nl; jh80.ch...@gmail.com; andy...@sony.com;
> >>> s...@chromium.org; m.szyprow...@samsung.com; u-boot@lists.denx.de;
> >>> ~postmarketos/upstream...@lists.sr.ht
> >>> Cc: Henrik Grimler
> >>> Subject: [PATCH 1/2] Revert "mmc: s5p_sdhci: unset the
> SDHCI_QUIRK_BROKEN_R1B"
> >>>
> >>> This reverts commit a034ec06ff1d558bbe11d5ee05edbb4de3ee2215.
> >>>
> >>> Commit 4a3ea75de4c5 ("Revert "mmc: sdhci: set to INT_DATA_END when
> >>> there are data"") reverted the alternative fix that was added for
> >>> Exynos 4 devices, causing an error when trying to boot from an sdcard:
> >>>
> >>> <...>
> >>> Loading Environment from MMC... sdhci_send_command: Timeout
> for status update!
> >>> mmc fail to send stop cmd
> >>> <...>
> >>
> >> Thanks for sharing issue.
> >>
> >> I will check this on Exynos Board. Frankly, I hope not to re-add QUIRK.
> >> Because it was verified that it was working fine without
> SDHCI_QUIKR_BROKEN_RIB.
> >
> > Just wondering if you have had an opportunity to test this on any of
> > your devices? You can find v2 here, though this patch had no changes:
> > INVALID URI REMOVED
> >
> 3-February/508928.html__;!!JmoZiZGBv3RvKRSx!5wpP-x5Y69S7MynP1sOmQI
> HaVG
> > N9_ZLl5dxDDenNWPHdwFnNPdAEvBrUt69tSpQ9o0Nv-LQ9Gie_aGgP$
>
> In my opinion,
>
> commit 4a3ea75de4c5b3053eac326bf1c753ed65df8cb9
> Author: yuezhang...@sony.com
> Date: Wed Mar 17 06:44:37 2021 +
>
> Revert "mmc: sdhci: set to INT_DATA_END when there are data"
>
> This reverts commit 17ea3c862865c0d704646f67dbf8412f9ff54f59.
>
> Revert the above commit.
>
> To Andy,
>
> Was there any problem without above commit?
>
>
> Best Regards,
> Jaehoon Chung
>
>
> >
> >> Best Regards,
> >> Jaehoon Chung
> >
> > Best regards,
> > Henrik Grimler
> >
> >>>
> >>> Re-add the quirk to allow booting from sdcards again.
> >>>
> >>> Signed-off-by: Henrik Grimler
> >>> ---
> >>> drivers/mmc/s5p_sdhci.c | 2 +-
> >>> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index
> >>> dee84263c3fd..3b74feae68c7 100644
> >>> --- a/drivers/mmc/s5p_sdhci.c
> >>> +++ b/drivers/mmc/s5p_sdhci.c
> >>> @@ -90,7 +90,7 @@ static int s5p_sdhci_core_init(struct sdhci_host
> *host)
> >>> host->name = S5P_NAME;
> >>>
> >>> host->quirks = SDHCI_QUIRK_NO_HISPD_BIT |
> SDHCI_QUIRK_BROKEN_VOLTAGE |
> >>> - SDHCI_QUIRK_32BIT_DMA_ADDR |
> >>> + SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR
> |
> >>> SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8;
> >>> host->max_clk = 5200;
> >>> host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 |
> MMC_VDD_165_195;
> >>> --
> >>> 2.30.2
> >>
> >>
Re: [EXTERNAL] [PATCH 0/2] phy: ti: j721e-wiz: Add support to manage type-C swap on Lane2 and lane3
On 13/03/23 6:12 pm, Sinthu Raja wrote: > From: Sinthu Raja > > Hi All, > This series of patch add support to enable lane2 and lane3 swap by > configuring the LN23 bit. Also, it's possible that the Type-C plug orientation > on the DIR line will be implemented through hardware design. In that > situation, there won't be an external GPIO line available, but the > driver still needs to address this since the DT won't use the > typec-gpio-dir property. Update code to handle if typec-dir-gpios property > is not specified in DT. > > Sinthu Raja (2): > phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not > specified > phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap > > drivers/phy/ti/phy-j721e-wiz.c | 58 -- > 1 file changed, 49 insertions(+), 9 deletions(-) > Reviewed-by: Ravi Gunasekaran -- Regards, Ravi
[PATCH 1/3] dm: adc: add iMX93 ADC support
This commit adds driver for iMX93 ADC.
The driver is implemented using driver model and provides
ADC uclass's methods for ADC single channel operations:
- adc_start_channel()
- adc_channel_data()
- adc_stop()
ADC features:
- channels: 4
- resolution: 12-bit
Signed-off-by: Luca Ellero
---
drivers/adc/Kconfig | 8 ++
drivers/adc/Makefile| 1 +
drivers/adc/imx93-adc.c | 286
3 files changed, 295 insertions(+)
create mode 100644 drivers/adc/imx93-adc.c
diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig
index e719c38bb3..4336732dee 100644
--- a/drivers/adc/Kconfig
+++ b/drivers/adc/Kconfig
@@ -63,3 +63,11 @@ config STM32_ADC
- core driver to deal with common resources
- child driver to deal with individual ADC resources (declare ADC
device and associated channels, start/stop conversions)
+
+config ADC_IMX93
+ bool "Enable NXP IMX93 ADC driver"
+ help
+ This enables basic driver for NXP IMX93 ADC.
+ It provides:
+ - 4 analog input channels
+ - 12-bit resolution
diff --git a/drivers/adc/Makefile b/drivers/adc/Makefile
index c1387f3a34..5336c82097 100644
--- a/drivers/adc/Makefile
+++ b/drivers/adc/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_ADC_SANDBOX) += sandbox.o
obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o
obj-$(CONFIG_SARADC_MESON) += meson-saradc.o
obj-$(CONFIG_STM32_ADC) += stm32-adc.o stm32-adc-core.o
+obj-$(CONFIG_ADC_IMX93) += imx93-adc.o
diff --git a/drivers/adc/imx93-adc.c b/drivers/adc/imx93-adc.c
new file mode 100644
index 00..b3bbea6c4e
--- /dev/null
+++ b/drivers/adc/imx93-adc.c
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 ASEM Srl
+ * Author: Luca Ellero
+ *
+ * Originally based on NXP linux-imx kernel v5.15 drivers/iio/adc/imx93_adc.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define IMX93_ADC_MCR 0x00
+#define IMX93_ADC_MSR 0x04
+#define IMX93_ADC_ISR 0x10
+#define IMX93_ADC_IMR 0x20
+#define IMX93_ADC_CIMR00x24
+#define IMX93_ADC_CTR0 0x94
+#define IMX93_ADC_NCMR00xA4
+#define IMX93_ADC_PCDR00x100
+#define IMX93_ADC_PCDR10x104
+#define IMX93_ADC_PCDR20x108
+#define IMX93_ADC_PCDR30x10c
+#define IMX93_ADC_PCDR40x110
+#define IMX93_ADC_PCDR50x114
+#define IMX93_ADC_PCDR60x118
+#define IMX93_ADC_PCDR70x11c
+#define IMX93_ADC_CALSTAT 0x39C
+
+#define IMX93_ADC_MCR_MODE_MASKBIT(29)
+#define IMX93_ADC_MCR_NSTART_MASK BIT(24)
+#define IMX93_ADC_MCR_CALSTART_MASKBIT(14)
+#define IMX93_ADC_MCR_ADCLKSE_MASK BIT(8)
+#define IMX93_ADC_MCR_PWDN_MASKBIT(0)
+
+#define IMX93_ADC_MSR_CALFAIL_MASK BIT(30)
+#define IMX93_ADC_MSR_CALBUSY_MASK BIT(29)
+#define IMX93_ADC_MSR_ADCSTATUS_MASK GENMASK(2, 0)
+
+#define IMX93_ADC_ISR_EOC_MASK BIT(1)
+
+#define IMX93_ADC_IMR_EOC_MASK BIT(1)
+#define IMX93_ADC_IMR_ECH_MASK BIT(0)
+
+#define IMX93_ADC_PCDR_CDATA_MASK GENMASK(11, 0)
+
+#define IDLE 0
+#define POWER_DOWN 1
+#define WAIT_STATE 2
+#define BUSY_IN_CALIBRATION3
+#define SAMPLE 4
+#define CONVERSION 6
+
+#define IMX93_ADC_MAX_CHANNEL 3
+#define IMX93_ADC_DAT_MASK 0xfff
+#define IMX93_ADC_TIMEOUT 10
+
+struct imx93_adc_priv {
+ int active_channel;
+ void __iomem *regs;
+};
+
+static int imx93_adc_power_down(struct imx93_adc_priv *adc)
+{
+ u32 mcr, msr;
+ int ret;
+
+ mcr = readl(adc->regs + IMX93_ADC_MCR);
+ mcr |= FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1);
+ writel(mcr, adc->regs + IMX93_ADC_MCR);
+
+ ret = readl_poll_timeout(adc->regs + IMX93_ADC_MSR, msr,
+ ((msr & IMX93_ADC_MSR_ADCSTATUS_MASK) == POWER_DOWN), 50);
+ if (ret == -ETIMEDOUT)
+ pr_warn("ADC not in power down mode, current MSR: %x\n", msr);
+
+ return ret;
+}
+
+static int imx93_adc_config_ad_clk(struct imx93_adc_priv *adc)
+{
+ u32 mcr;
+ int ret;
+
+ /* put adc in power down mode */
+ ret = imx93_adc_power_down(adc);
+ if (ret < 0)
+ return ret;
+
+ /* config the AD_CLK equal to bus clock */
+ mcr = readl(adc->regs + IMX93_ADC_MCR);
+ mcr |= FIELD_PREP(IMX93_ADC_MCR_ADCLKSE_MASK, 1);
+ writel(mcr, adc->regs + IMX93_ADC_MCR);
+
+ /* bring ADC out of power down state, in idle state */
+ mcr = readl(adc->regs + IMX93_ADC_MCR);
+ mcr &= ~FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK,
[PATCH v4 0/3] imx93: add ADC support
Add ADC support for NXP iMX93 Changes for v2: - add "static" to functions - enable ADC in iMX93 EVK Changes for v3: - split in 3 commits - keep dts file in sync with Linux devicetree - add comments to commits Changes for v4: - add imx93_adc_power_down() in imx93_adc_stop() Luca Ellero (3): dm: adc: add iMX93 ADC support imx93_evk: add adc node to dts file imx93_evk: defconfig: add adc support arch/arm/dts/imx93-11x11-evk.dts | 4 + configs/imx93_11x11_evk_defconfig | 1 + drivers/adc/Kconfig | 8 + drivers/adc/Makefile | 1 + drivers/adc/imx93-adc.c | 286 ++ 5 files changed, 300 insertions(+) create mode 100644 drivers/adc/imx93-adc.c -- 2.25.1
[PATCH 2/3] imx93_evk: add adc node to dts file
This node uses imx93_adc driver under drivers/adc.
The node is added keeping dts file in sync with iMX9 evk Linux
devicetree.
Signed-off-by: Luca Ellero
---
arch/arm/dts/imx93-11x11-evk.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imx93-11x11-evk.dts b/arch/arm/dts/imx93-11x11-evk.dts
index b3a5a3d71e..91f99cebae 100644
--- a/arch/arm/dts/imx93-11x11-evk.dts
+++ b/arch/arm/dts/imx93-11x11-evk.dts
@@ -58,6 +58,10 @@
};
+ {
+ status = "okay";
+};
+
{
#address-cells = <1>;
#size-cells = <0>;
--
2.25.1
[PATCH 3/3] imx93_evk: defconfig: add adc support
iMX93 ADC features: - 4 channels - 12 bit resolution Signed-off-by: Luca Ellero --- configs/imx93_11x11_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 477fb25807..fa929dd4ec 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -82,6 +82,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_ADC_IMX93=y CONFIG_IMX_RGPIO2P=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y -- 2.25.1
Re: [PATCH v9 06/10] arm_ffa: introduce the FF-A Sandbox driver
Hi Abdellatif,
On Tue, 14 Mar 2023 at 11:59, Abdellatif El Khlifi
wrote:
>
> Hi Simon,
>
> > Hi Abdellatif,
> >
> > On Fri, 10 Mar 2023 at 06:10, Abdellatif El Khlifi
> > wrote:
> > >
> > > Provide a Sandbox driver to emulate the FF-A ABIs
> > >
> > > The emulated ABIs are those supported by the FF-A core driver
> > > and according to FF-A specification v1.0.
> > >
> > > The Sandbox driver provides operations allowing the test
> > > application to read the status of all the inspected ABIs
> > > and perform functional tests based on that.
> > >
> > > sandbox driver supports only 64-bit direct messaging.
> > >
> > > Signed-off-by: Abdellatif El Khlifi
> > > Cc: Tom Rini
> > > Cc: Simon Glass
> > > Cc: Ilias Apalodimas
> > > Cc: Jens Wiklander
> > >
> > > ---
> > > Changelog:
> > > ===
> > >
> > > v9: align FF-A sandbox driver with FF-A discovery through DM
> > >
> > > v8: update ffa_bus_prvdata_get() to return a pointer rather than
> > > a pointer address
> > >
> > > v7: state that sandbox driver supports only 64-bit direct messaging
> > >
> > > v4: align sandbox driver with the new FF-A driver interfaces
> > > and new way of error handling
> > >
> > > v1: introduce the sandbox driver
> > >
> > > MAINTAINERS | 1 +
> > > arch/sandbox/dts/sandbox.dtsi | 4 +
> > > arch/sandbox/dts/test.dts | 4 +
> > > configs/sandbox64_defconfig | 2 +
> > > configs/sandbox_defconfig | 2 +
> > > doc/arch/arm64.ffa.rst| 4 +
> > > doc/arch/sandbox/sandbox.rst | 1 +
> > > drivers/firmware/arm-ffa/Kconfig | 11 +-
> > > drivers/firmware/arm-ffa/Makefile | 1 +
> > > drivers/firmware/arm-ffa/core.c | 36 +-
> > > drivers/firmware/arm-ffa/sandbox.c| 610 ++
> > > .../firmware/arm-ffa/sandbox_arm_ffa_priv.h | 129
> > > include/arm_ffa.h | 5 +-
> > > include/sandbox_arm_ffa.h | 124
> > > 14 files changed, 928 insertions(+), 6 deletions(-)
> > > create mode 100644 drivers/firmware/arm-ffa/sandbox.c
> > > create mode 100644 drivers/firmware/arm-ffa/sandbox_arm_ffa_priv.h
> > > create mode 100644 include/sandbox_arm_ffa.h
> > >
> >
> > Could you use 80 columns where possible? There seem to be a lot of
> > things that extend beyond that without much of a reason.
> >
> > Also you can use 'ulong' instead of 'unsigned long'. It is less
> > verbose and a U-Boot standard.
> >
> > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > index 18e9c2ce99..2b9d33e964 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -274,6 +274,7 @@ F: doc/arch/arm64.ffa.rst
> > > F: doc/usage/cmd/armffa.rst
> > > F: drivers/firmware/arm-ffa/
> > > F: include/arm_ffa.h
> > > +F: include/sandbox_arm_ffa.h
> > >
> > > ARM FREESCALE IMX
> > > M: Stefano Babic
> > > diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi
> > > index 30a305c4d2..059c273277 100644
> > > --- a/arch/sandbox/dts/sandbox.dtsi
> > > +++ b/arch/sandbox/dts/sandbox.dtsi
> > > @@ -445,6 +445,10 @@
> > > thermal {
> > > compatible = "sandbox,thermal";
> > > };
> > > +
> > > + sandbox_arm_ffa {
> > > + compatible = "sandbox,arm_ffa";
> > > + };
> > > };
> > >
> > > _ec {
> > > diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
> > > index d72d7a567a..11dc6ed0d9 100644
> > > --- a/arch/sandbox/dts/test.dts
> > > +++ b/arch/sandbox/dts/test.dts
> > > @@ -1802,6 +1802,10 @@
> > > compatible = "u-boot,fwu-mdata-gpt";
> > > fwu-mdata-store = <>;
> > > };
> > > +
> > > + sandbox_arm_ffa {
> > > + compatible = "sandbox,arm_ffa";
> > > + };
> >
> > I see that you have this, so the driver should bind automatically.
> >
> > Is the problem that you are trying to bind the sandbox emulator?
> > Again, you can actually add that to the DT. See how this works for
> > i2c, SPI, PCI, for example.
> >
> > > };
> > >
> > > #include "sandbox_pmic.dtsi"
> > > diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
> > > index ccbc18aad0..35d4676cf7 100644
> > > --- a/configs/sandbox64_defconfig
> > > +++ b/configs/sandbox64_defconfig
> > > @@ -259,3 +259,5 @@ CONFIG_FWU_MULTI_BANK_UPDATE=y
> > > CONFIG_UNIT_TEST=y
> > > CONFIG_UT_TIME=y
> > > CONFIG_UT_DM=y
> > > +CONFIG_ARM_FFA_TRANSPORT=y
> > > +CONFIG_SANDBOX_FFA=y
> > > diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
> > > index a0fbdad20a..8aab8dda31 100644
> > > --- a/configs/sandbox_defconfig
> > > +++ b/configs/sandbox_defconfig
> > > @@ -336,3 +336,5 @@ CONFIG_TEST_FDTDEC=y
> > > CONFIG_UNIT_TEST=y
> > > CONFIG_UT_TIME=y
> > > CONFIG_UT_DM=y
> > > +CONFIG_ARM_FFA_TRANSPORT=y
> > >
Re: [PATCH v5 21/44] x86: Use string functions for all 32-bit builds
Hi Tom. On Thu, 2 Mar 2023 at 13:37, Tom Rini wrote: > > On Wed, Feb 22, 2023 at 09:34:02AM -0700, Simon Glass wrote: > > > At present these are not included in SPL. They do add to code size but > > are a bit faster, so adjust the setting to add them. > > > > Signed-off-by: Simon Glass > > --- > > > > (no changes since v1) > > > > arch/x86/include/asm/string.h | 2 +- > > arch/x86/lib/Makefile | 2 +- > > 2 files changed, 2 insertions(+), 2 deletions(-) I've moved this to another series, x86-specific. Regards, Simon
Re: [PATCH v1 4/7] arm: dts: rockchip: rk3288: partial sync edp node
On Tue, 14 Mar 2023 at 12:16, Johan Jonker wrote: > > The rk3288 edp node has a phy node in Linux with a clock > property while current U-boot driver expects this clock U-Boot > on position index 1. Move U-boot specific DT clock properties U-Boot-specific > to rk3288-u-boot.dtsi and partially the sync edp node. > > Signed-off-by: Johan Jonker > --- > arch/arm/dts/rk3288-u-boot.dtsi | 5 + > arch/arm/dts/rk3288.dtsi| 17 +++-- > 2 files changed, 16 insertions(+), 6 deletions(-) Reviewed-by: Simon Glass Tested-by: Simon Glass # chromebook-jerry
Re: [PATCH v1 3/7] video: rockchip: rk_vop: add rk3288-dp compare string
On Tue, 14 Mar 2023 at 12:16, Johan Jonker wrote: > > In the current rk3288.dtsi file the compatible string for > the DisplayPort(DP) node ends with "edp". The string in the > binding ends with "dp" which conflicts with "cdn-dp" as a > search term. Add "rk3288-dp" as compare string to select > vop_id. > > Signed-off-by: Johan Jonker > --- > drivers/video/rockchip/rk_vop.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Simon Glass Tested-by: Simon Glass # chromebook-jerry
Re: [PATCH v1 6/7] clk: rockchip: clk_rk3288: add PCLK_RKPWM
On Tue, 14 Mar 2023 at 12:16, Johan Jonker wrote: > > The rk3288 pwm node synced from Linux make use of PCLK_RKPWM > instead of PCLK_PWM. They have the same pclk_cpu parent, > so add PCLK_RKPWM to rk3288_clk_get_rate(). > > Signed-off-by: Johan Jonker > --- > drivers/clk/rockchip/clk_rk3288.c | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Simon Glass Tested-by: Simon Glass # chromebook-jerry
Re: [PATCH v1 1/7] arm: dts: rockchip: rk3288: move io-domains nodes
On Tue, 14 Mar 2023 at 12:13, Johan Jonker wrote: > > In order to better compare the Linux rk3288.dtsi version > with the u-boot version move the io-domains nodes. > > Signed-off-by: Johan Jonker > --- > arch/arm/dts/rk3288-miqi.dtsi| 27 +++-- > arch/arm/dts/rk3288-phycore-som.dtsi | 30 +--- > arch/arm/dts/rk3288-popmetal.dtsi| 30 +--- > arch/arm/dts/rk3288-veyron.dtsi | 28 -- > arch/arm/dts/rk3288.dtsi | 5 + > 5 files changed, 58 insertions(+), 62 deletions(-) > Reviewed-by: Simon Glass Tested-by: Simon Glass # chromebook-jerry
Re: [PATCH v1 2/7] arm: dts: rockchip: rk3288: partial sync grf and pmu nodes
On Tue, 14 Mar 2023 at 12:15, Johan Jonker wrote: > > In order to better compare the Linux rk3288.dtsi > version 6.3 -rc2 with the u-boot version partial > sync the grf and pmu nodes. > > Signed-off-by: Johan Jonker > --- > arch/arm/dts/rk3288.dtsi | 269 +-- > 1 file changed, 173 insertions(+), 96 deletions(-) > Reviewed-by: Simon Glass Tested-by: Simon Glass # chromebook-jerry
Re: [PATCH v1 5/7] arm: dts: rockchip: rk3288: partial sync vop/lvds/mipi/hdmi nodes
On Tue, 14 Mar 2023 at 12:16, Johan Jonker wrote: > > In order to better compare the Linux rk3288.dtsi > version 6.3 -rc2 with the u-boot version partial > sync the vop/lvds/mipi/hdmi nodes. > > Signed-off-by: Johan Jonker > --- > arch/arm/dts/rk3288.dtsi | 48 > 1 file changed, 24 insertions(+), 24 deletions(-) Reviewed-by: Simon Glass Tested-by: Simon Glass # chromebook-jerry
Re: [PATCH 0/9] Enable splash screen
Hi Nikhil, On Wed, 15 Mar 2023 at 00:07, Nikhil M Jain wrote: > > Hi Simon, > > On 15/03/23 03:38, Simon Glass wrote: > > Hi Nikhil, > > > > On Mon, 13 Mar 2023 at 04:15, Nikhil M Jain wrote: > >> > >> To enable splash screen at SPL stage move video driver and splash screen > >> framework at SPL, which will bring up image on display very quickly and > >> thus have early display support in SPL. > >> > >> Nikhil M Jain (9): > >>drivers: video: Kconfig: Necessary configs for video at SPL > >>drivers: video: tidss: Kconfig: Configs to enable TIDSS at SPL > >>cmd: Kconfig: Add necessary configs for splash screen at SPL > >>drivers: video: Makefile: Compile video driver files at SPL > >>drivers: video: tidss: Makefile: Add condition to compile TIDSS at SPL > >>cmd: Makefile: Add rules to build bmp.c and read.c at SPL > >>common: splash: Enable splash_display at SPL stage > >>drivers: video: video-uclass: Disable u-boot logo at SPL > >>board: ti: am62x: evm: OSPI support for splash screen > >> > >> board/ti/am62x/evm.c | 6 ++ > >> cmd/Kconfig | 17 + > >> cmd/Makefile | 2 ++ > >> common/splash.c | 2 +- > >> drivers/video/Kconfig| 32 > >> drivers/video/Makefile | 6 ++ > >> drivers/video/tidss/Kconfig | 6 ++ > >> drivers/video/tidss/Makefile | 1 + > >> drivers/video/video-uclass.c | 2 +- > >> include/splash.h | 2 +- > >> 10 files changed, 69 insertions(+), 7 deletions(-) > > > > I'm not necessarily arguing against this, but what is the need for > > this? How many milliseconds earlier does the image appear with this > > patch? What is the bottleneck? We should be able to get to U-Boot > > proper very quickly. > > > There is a significant difference in time, by adding support in SPL > splash screen comes up by approx 650ms and at u-boot proper it comes at > 2.6s, measured from first print in console as seen on AM62x. Also we > plan to skip u-boot proper and load kernel directly. Yes that really is terrible. It should be under a second for U-Boot proper! Have you tried using bootstage to report the numbers? Have you tried using tracing to figure out what is wrong? Is it just slow storage? Regards, Simon
i.MX8MP SPL failures due to memory corruption/overflow?
Hi, I'm trying to bring up a new board based on the i.MX8MP and I have an issue I'm hoping someone can help solving. I'm seeing failures in the early SPL code, usually in the DDR initialization. Often they look like: U-Boot SPL 2023.04-rc3 (Mar 07 2023 - 14:32:34 +) Training FAILED Failed to initialize DDR RAM! ### ERROR ### Please RESET the board ### But sometimes ddr_init() doesn't even return an error and only the get_ram_size() afterwards which tries to allocate the memory fails. The strange thing is that the issues appear or disappear deterministically on the binary level. This means I sometimes get a U-Boot binary which runs just fine in 100% of cases. Then I change for example one of the following: * Adding a single printf() somewhere in the boards spl.c * Using the same binary but booting from SD card instead of USB loader * Using the same source but switching from the OS cross compiler to the one from Yocto/OE And afterwards I get 100% failure rate with an error as described above. My suspicion is that there is some memory corruption/conflict. My SPL is quite large and I wonder if it exceeds some limit. SPL is loaded to 0x92 and CONFIG_SPL_STACK is set to 0x96, which leaves 256 KiB in between for the SPL. But all i.MX8MP boards seem to set CONFIG_SPL_MAX_SIZE=0x26000 (152 KiB) for some reason. My u-boot-spl-ddr.bin currently has around 193 KiB but I don't get any warning about exceeding the SPL_MAX_SIZE. My questions: * Why is CONFIG_SPL_MAX_SIZE set to 152 KiB? * Why is there no warning in my case? * Any other ideas or pointers? Thanks for your help! Best regards Frieder
Re: [PATCH v1 7/7] arm: dts: rockchip: rk3288: partial sync pwm nodes
Hi Johan,
On Tue, 14 Mar 2023 at 12:16, Johan Jonker wrote:
>
> In order to better compare the Linux rk3288.dtsi
> version 6.3 -rc2 with the u-boot version partial
> sync the pwm nodes.
>
> Signed-off-by: Johan Jonker
> ---
> arch/arm/dts/rk3288.dtsi | 18 +-
> 1 file changed, 5 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
> index f24e9ba5..dd1d9897 100644
> --- a/arch/arm/dts/rk3288.dtsi
> +++ b/arch/arm/dts/rk3288.dtsi
> @@ -675,9 +675,7 @@
> #pwm-cells = <3>;
> pinctrl-names = "default";
> pinctrl-0 = <_pin>;
> - clocks = < PCLK_PWM>;
> - clock-names = "pwm";
> - rockchip,grf = <>;
> + clocks = < PCLK_RKPWM>;
> status = "disabled";
> };
>
> @@ -687,9 +685,7 @@
> #pwm-cells = <3>;
> pinctrl-names = "default";
> pinctrl-0 = <_pin>;
> - clocks = < PCLK_PWM>;
> - clock-names = "pwm";
> - rockchip,grf = <>;
> + clocks = < PCLK_RKPWM>;
> status = "disabled";
> };
>
> @@ -699,21 +695,17 @@
> #pwm-cells = <3>;
> pinctrl-names = "default";
> pinctrl-0 = <_pin>;
> - clocks = < PCLK_PWM>;
> - clock-names = "pwm";
> - rockchip,grf = <>;
> + clocks = < PCLK_RKPWM>;
> status = "disabled";
> };
>
> pwm3: pwm@ff680030 {
> compatible = "rockchip,rk3288-pwm";
> reg = <0xff680030 0x10>;
> - #pwm-cells = <2>;
> + #pwm-cells = <3>;
How can we do this without breaking the existing pwm usage in U-Boot?
> pinctrl-names = "default";
> pinctrl-0 = <_pin>;
> - clocks = < PCLK_PWM>;
> - clock-names = "pwm";
> - rockchip,grf = <>;
> + clocks = < PCLK_RKPWM>;
> status = "disabled";
> };
>
> --
> 2.20.1
>
Regards,
Simon
