[PATCH v3 08/19] video: mxsfb: add support for i.MXRT
Add support for i.MXRT by adding CONFIG_IMXRT in register structure and
adding .compatible = "fsl,imxrt-lcdif".
Signed-off-by: Giulio Benetti
---
arch/arm/include/asm/arch-imxrt/imx-regs.h | 6 ++
arch/arm/include/asm/mach-imx/regs-lcdif.h | 6 +++---
drivers/video/mxsfb.c | 1 +
3 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-imxrt/imx-regs.h
b/arch/arm/include/asm/arch-imxrt/imx-regs.h
index 4f1d439f6f..44c95dcd11 100644
--- a/arch/arm/include/asm/arch-imxrt/imx-regs.h
+++ b/arch/arm/include/asm/arch-imxrt/imx-regs.h
@@ -17,4 +17,10 @@
#define ANATOP_BASE_ADDR 0x400d8000
+#define MXS_LCDIF_BASE 0x402b8000
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include
+#endif
+
#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h
b/arch/arm/include/asm/mach-imx/regs-lcdif.h
index b4c430a35c..5874638796 100644
--- a/arch/arm/include/asm/mach-imx/regs-lcdif.h
+++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h
@@ -22,7 +22,7 @@ struct mxs_lcdif_regs {
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
- defined(CONFIG_IMX8M)
+ defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT)
mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
#endif
mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
@@ -49,7 +49,7 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */
mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */
mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
- mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
+ mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */
#if defined(CONFIG_MX23)
@@ -61,7 +61,7 @@ struct mxs_lcdif_regs {
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
- defined(CONFIG_IMX8M)
+ defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT)
mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
#endif
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index f21f8247d9..6826ba3d1b 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -440,6 +440,7 @@ static const struct udevice_id mxs_video_ids[] = {
{ .compatible = "fsl,imx23-lcdif" },
{ .compatible = "fsl,imx28-lcdif" },
{ .compatible = "fsl,imx7ulp-lcdif" },
+ { .compatible = "fsl,imxrt-lcdif" },
{ /* sentinel */ }
};
--
2.20.1
[PATCH v3 09/19] video: mxsfb: refactor for using display_timings
struct display_timings provides more informations such clock and DE
polarity, so let's refactor the code to use struct display_timings
instead of struct ctfb_res_modes, so we'll become able to get clock and
DE polarity settings and set register according to them in the next patch.
Signed-off-by: Giulio Benetti
---
drivers/video/mxsfb.c | 54 ++-
1 file changed, 23 insertions(+), 31 deletions(-)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 6826ba3d1b..cdd6dfaced 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -54,7 +54,7 @@ __weak void mxsfb_system_setup(void)
*/
static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
-struct ctfb_res_modes *mode, int bpp)
+struct display_timing *timings, int bpp)
{
struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
uint32_t word_len = 0, bus_width = 0;
@@ -70,14 +70,14 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
return;
}
- ret = clk_set_rate(_clk, PS2KHZ(mode->pixclock) * 1000);
+ ret = clk_set_rate(_clk, timings->pixelclock.typ);
if (ret < 0) {
dev_err(dev, "Failed to set mxs clk: %d\n", ret);
return;
}
#else
/* Kick in the LCDIF clock */
- mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock));
+ mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
#endif
/* Restart the LCDIF block */
@@ -115,25 +115,25 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
mxsfb_system_setup();
- writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
- >hw_lcdif_transfer_count);
+ writel((timings->vactive.typ << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
+ timings->hactive.typ, >hw_lcdif_transfer_count);
writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
- mode->vsync_len, >hw_lcdif_vdctrl0);
- writel(mode->upper_margin + mode->lower_margin +
- mode->vsync_len + mode->yres,
+ timings->vsync_len.typ, >hw_lcdif_vdctrl0);
+ writel(timings->vback_porch.typ + timings->vfront_porch.typ +
+ timings->vsync_len.typ + timings->vactive.typ,
>hw_lcdif_vdctrl1);
- writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
- (mode->left_margin + mode->right_margin +
- mode->hsync_len + mode->xres),
+ writel((timings->hsync_len.typ <<
LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
+ (timings->hback_porch.typ + timings->hfront_porch.typ +
+ timings->hsync_len.typ + timings->hactive.typ),
>hw_lcdif_vdctrl2);
- writel(((mode->left_margin + mode->hsync_len) <<
+ writel(((timings->hback_porch.typ + timings->hsync_len.typ) <<
LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
- (mode->upper_margin + mode->vsync_len),
+ (timings->vback_porch.typ + timings->vsync_len.typ),
>hw_lcdif_vdctrl3);
- writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
+ writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) |
timings->hactive.typ,
>hw_lcdif_vdctrl4);
writel(fb_addr, >hw_lcdif_cur_buf);
@@ -154,11 +154,11 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
writel(LCDIF_CTRL_RUN, >hw_lcdif_ctrl_set);
}
-static int mxs_probe_common(struct udevice *dev, struct ctfb_res_modes *mode,
+static int mxs_probe_common(struct udevice *dev, struct display_timing
*timings,
int bpp, u32 fb)
{
/* Start framebuffer */
- mxs_lcd_init(dev, fb, mode, bpp);
+ mxs_lcd_init(dev, fb, timings, bpp);
#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
/*
@@ -224,6 +224,7 @@ void *video_hw_init(void)
char *penv;
void *fb = NULL;
struct ctfb_res_modes mode;
+ struct display_timing timings;
puts("Video: ");
@@ -280,7 +281,9 @@ void *video_hw_init(void)
printf("%s\n", panel.modeIdent);
- ret = mxs_probe_common(NULL, , bpp, (u32)fb);
+ video_ctfb_mode_to_display_timing(, );
+
+ ret = mxs_probe_common(NULL, , bpp, (u32)fb);
if (ret)
goto dealloc_fb;
@@ -334,7 +337,6 @@ static int mxs_video_probe(struct udevice *dev)
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
- struc
[PATCH v3 03/19] clk: imx: clk-imxrt1050: setup PLL5 for video in non-SPL
mxsfb needs PLL5 as source, so let's setup it at its default frequency
specified in RM(650Mhz).
Signed-off-by: Giulio Benetti
Reviewed-by: Lukasz Majewski
---
V1->V2:
* removed LCDIF set_parent() since it's setup in dts file(suggested by Fabio)
---
drivers/clk/imx/clk-imxrt1050.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index e33d426363..bb12644605 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -238,9 +238,9 @@ static int imxrt1050_clk_probe(struct udevice *dev)
clk_dm(IMXRT1050_CLK_LCDIF,
imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
-#ifdef CONFIG_SPL_BUILD
struct clk *clk, *clk1;
+#ifdef CONFIG_SPL_BUILD
/* bypass pll1 before setting its rate */
clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, );
clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, );
@@ -271,7 +271,14 @@ static int imxrt1050_clk_probe(struct udevice *dev)
clk_get_by_id(IMXRT1050_CLK_PLL3_BYPASS, );
clk_set_parent(clk1, clk);
+#else
+ /* Set PLL5 for LCDIF to its default 650Mhz */
+ clk_get_by_id(IMXRT1050_CLK_PLL5_VIDEO, );
+ clk_enable(clk);
+ clk_set_rate(clk, 65000UL);
+ clk_get_by_id(IMXRT1050_CLK_PLL5_BYPASS, );
+ clk_set_parent(clk1, clk);
#endif
return 0;
--
2.20.1
[PATCH v3 00/19] i.MXRT1050 add LCDIF support
This patchset add support for LCDIF on i.MXRT1050 evk. This requires PLL5 to be setup, mxsfb needs to use display_timing to retrieve if Lcd has inverted PIXCLOCK from dts. With this patchset applied we temporary loose DCache support until it will get implemented, since a function in mxsfb.c is needed for setting cache behaviour. Anyway this way Lcd will show the console same way as serial does. Also I've moved private sunxi_ctfb_mode_to_display_timing() to videomodes since I need it for mxfsb.c too, then having a unified function to convert from ctfb_mode to display_timing. Changes: V1->V2: * moved hard-coded LCDIF's parent clock from clk-imxrt1050.c to imxrt1050-evk.dts * reworded some commit log V2->V3: * added comment to describe what is a ctfb in videomodes Giulio Benetti (19): clk: imx: pllv3: add enable_bit clk: imx: clk-imxrt1050: fix typo in clock name "video:" clk: imx: clk-imxrt1050: setup PLL5 for video in non-SPL clk: imx: clk-imxrt1050: add set_parent() callback videomodes: add helper function to convert from ctfb to display_timing sunxi: display: use common video_ctfb_mode_to_display_timing() video: mxsfb: add support for DM CLK video: mxsfb: add support for i.MXRT video: mxsfb: refactor for using display_timings video: mxsfb: enable setting HSYNC negative polarity video: mxsfb: enable setting VSYNC negative polarity video: mxsfb: enable setting PIXDATA on negative edge video: mxsfb: enable setting ENABLE negative polarity imxrt1050_evk: add 16bpp video support if video layer enabled ARM: dts: i.mxrt1050: add lcdif node ARM: dts: imxrt1050: allow this dtsi file to be compiled in Linux arch: arm: dts: imxrt1050-evk: add lcdif node configs: imxrt1050-evk: enable video support/console configs: imxrt1050-evk: temporary disable DCACHE arch/arm/dts/imxrt1050-evk.dts | 60 ++ arch/arm/dts/imxrt1050.dtsi| 14 +++- arch/arm/include/asm/arch-imxrt/imx-regs.h | 6 ++ arch/arm/include/asm/mach-imx/regs-lcdif.h | 6 +- configs/imxrt1050-evk_defconfig| 6 ++ drivers/clk/imx/clk-imxrt1050.c| 30 ++- drivers/clk/imx/clk-pllv3.c| 9 +++ drivers/video/mxsfb.c | 94 ++ drivers/video/sunxi/sunxi_display.c| 33 +--- drivers/video/videomodes.c | 29 +++ drivers/video/videomodes.h | 11 +++ include/configs/imxrt1050-evk.h| 15 12 files changed, 242 insertions(+), 71 deletions(-) -- 2.20.1
[PATCH v3 05/19] videomodes: add helper function to convert from ctfb to display_timing
This function converts from "struct ctf_res_modes" to
"struct display_timing".
Signed-off-by: Giulio Benetti
---
V2->V3:
* comment function prototype and make it clear what ctfb is
---
drivers/video/videomodes.c | 29 +
drivers/video/videomodes.h | 11 +++
2 files changed, 40 insertions(+)
diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c
index ac25b45f81..89003eea72 100644
--- a/drivers/video/videomodes.c
+++ b/drivers/video/videomodes.c
@@ -444,3 +444,32 @@ int video_edid_dtd_to_ctfb_res_modes(struct
edid_detailed_timing *t,
return 0;
}
+
+void video_ctfb_mode_to_display_timing(const struct ctfb_res_modes *mode,
+ struct display_timing *timing)
+{
+ timing->pixelclock.typ = mode->pixclock_khz * 1000;
+
+ timing->hactive.typ = mode->xres;
+ timing->hfront_porch.typ = mode->right_margin;
+ timing->hback_porch.typ = mode->left_margin;
+ timing->hsync_len.typ = mode->hsync_len;
+
+ timing->vactive.typ = mode->yres;
+ timing->vfront_porch.typ = mode->lower_margin;
+ timing->vback_porch.typ = mode->upper_margin;
+ timing->vsync_len.typ = mode->vsync_len;
+
+ timing->flags = 0;
+
+ if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
+ timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
+ else
+ timing->flags |= DISPLAY_FLAGS_HSYNC_LOW;
+ if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
+ timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
+ else
+ timing->flags |= DISPLAY_FLAGS_VSYNC_LOW;
+ if (mode->vmode == FB_VMODE_INTERLACED)
+ timing->flags |= DISPLAY_FLAGS_INTERLACED;
+}
diff --git a/drivers/video/videomodes.h b/drivers/video/videomodes.h
index 29a3db4ae3..aefe4ef94a 100644
--- a/drivers/video/videomodes.h
+++ b/drivers/video/videomodes.h
@@ -92,3 +92,14 @@ int video_get_option_int(const char *options, const char
*name, int def);
int video_edid_dtd_to_ctfb_res_modes(struct edid_detailed_timing *t,
struct ctfb_res_modes *mode);
+/**
+ * video_ctfb_mode_to_display_timing() - Convert a ctfb(Cathode Tube Frame
+ * Buffer)_res_modes struct to a
+ * display_timing struct.
+ *
+ * @mode: Input ctfb_res_modes structure pointer to be converted
+ * from
+ * @timing:Output display_timing structure pointer to be converted to
+ */
+void video_ctfb_mode_to_display_timing(const struct ctfb_res_modes *mode,
+ struct display_timing *timing);
--
2.20.1
[PATCH v3 01/19] clk: imx: pllv3: add enable_bit
pllv3 PLLs have powerdown/up bits but enable bits too. Specifically
"enable bit" enable the pll output, so when dis/enabling pll by
setting/clearing power_bit we must also set/clear enable_bit.
Signed-off-by: Giulio Benetti
Reviewed-by: Lukasz Majewski
---
drivers/clk/imx/clk-pllv3.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 525442debf..b4a9d587e1 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -25,6 +25,7 @@
#define PLL_DENOM_OFFSET 0x20
#define BM_PLL_POWER (0x1 << 12)
+#define BM_PLL_ENABLE (0x1 << 13)
#define BM_PLL_LOCK(0x1 << 31)
struct clk_pllv3 {
@@ -32,6 +33,7 @@ struct clk_pllv3 {
void __iomem*base;
u32 power_bit;
boolpowerup_set;
+ u32 enable_bit;
u32 div_mask;
u32 div_shift;
};
@@ -83,6 +85,9 @@ static int clk_pllv3_generic_enable(struct clk *clk)
val |= pll->power_bit;
else
val &= ~pll->power_bit;
+
+ val |= pll->enable_bit;
+
writel(val, pll->base);
return 0;
@@ -98,6 +103,9 @@ static int clk_pllv3_generic_disable(struct clk *clk)
val &= ~pll->power_bit;
else
val |= pll->power_bit;
+
+ val &= ~pll->enable_bit;
+
writel(val, pll->base);
return 0;
@@ -238,6 +246,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const
char *name,
return ERR_PTR(-ENOMEM);
pll->power_bit = BM_PLL_POWER;
+ pll->enable_bit = BM_PLL_ENABLE;
switch (type) {
case IMX_PLLV3_GENERIC:
--
2.20.1
[PATCH v3 17/19] arch: arm: dts: imxrt1050-evk: add lcdif node
Add lcdif node and its pinctrl.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050-evk.dts | 60 ++
1 file changed, 60 insertions(+)
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index 56b75986e2..b5e781275e 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -185,6 +185,33 @@
0x17061
>;
};
+
+ pinctrl_lcdif: lcdifgrp {
+ u-boot,dm-spl;
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31
0x0b069
+ MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02
0x0b069
+ >;
+ };
};
};
@@ -198,3 +225,36 @@
cd-gpios = < 28 GPIO_ACTIVE_LOW>;
};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_lcdif>;
+ display = <>;
+ status = "okay";
+
+ assigned-clocks = < IMXRT1050_CLK_LCDIF_SEL>;
+ assigned-clock-parents = < IMXRT1050_CLK_PLL5_VIDEO>;
+
+ display0: display0 {
+ bits-per-pixel = <16>;
+ bus-width = <16>;
+
+ display-timings {
+ timing0: timing0 {
+ clock-frequency = <930>;
+ hactive = <480>;
+ vactive = <272>;
+ hback-porch = <4>;
+ hfront-porch = <8>;
+ vback-porch = <4>;
+ vfront-porch = <8>;
+ hsync-len = <41>;
+ vsync-len = <10>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ };
+ };
+ };
+};
--
2.20.1
[PATCH v3 18/19] configs: imxrt1050-evk: enable video support/console
Enable DM_VIDEO subsystem and its BACKLIGHT_GPIO. Then enable SYS_WHITE_ON_BLACK to have classic black background on display. Need also to enable CONFIG_SYS_CONSOLE_ENV_OVERWRITE to retrieve stdin/stdout/stderr from CONFIG_EXTRA_ENV_SETTINGS. Signed-off-by: Giulio Benetti --- configs/imxrt1050-evk_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index 71970552c0..810f391fdc 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_TEXT_BASE=0x20209000 CONFIG_DISTRO_DEFAULTS=y CONFIG_SD_BOOT=y # CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set @@ -62,6 +63,9 @@ CONFIG_IMXRT_SDRAM=y CONFIG_FSL_LPUART=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y +CONFIG_DM_VIDEO=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SHA1=y CONFIG_SHA256=y CONFIG_HEXDUMP=y -- 2.20.1
Re: [PATCH v2 00/19] i.MXRT1050 add LCDIF support
I've pinged the wrong patchset, sorry for the noise, the right one is v3. -- Giulio Benetti Benetti Engineering sas On 4/15/20 9:51 PM, Giulio Benetti wrote: Kindly ping
Re: [PATCH v2 00/19] i.MXRT1050 add LCDIF support
Kindly ping -- Giulio Benetti Benetti Engineering sas On 3/22/20 11:48 PM, Giulio Benetti wrote: This patchset passed travis: https://travis-ci.org/github/giuliobenetti/u-boot-imxrt/builds/665577905?utm_medium=notification_source=email And also: ./tools/buildman/buildman.py --branch=dev/imxrt-lcdif odroid edison trats trats2 imxrt --show_errors --force-build --count=19 --output-dir=../BUILD/ Best regards
Re: [PATCH v3 00/19] i.MXRT1050 add LCDIF support
Kindly ping -- Giulio Benetti Benetti Engineering sas On 4/8/20 5:10 PM, Giulio Benetti wrote: This patchset add support for LCDIF on i.MXRT1050 evk. This requires PLL5 to be setup, mxsfb needs to use display_timing to retrieve if Lcd has inverted PIXCLOCK from dts. With this patchset applied we temporary loose DCache support until it will get implemented, since a function in mxsfb.c is needed for setting cache behaviour. Anyway this way Lcd will show the console same way as serial does. Also I've moved private sunxi_ctfb_mode_to_display_timing() to videomodes since I need it for mxfsb.c too, then having a unified function to convert from ctfb_mode to display_timing. Changes: V1->V2: * moved hard-coded LCDIF's parent clock from clk-imxrt1050.c to imxrt1050-evk.dts * reworded some commit log V2->V3: * added comment to describe what is a ctfb in videomodes Giulio Benetti (19): clk: imx: pllv3: add enable_bit clk: imx: clk-imxrt1050: fix typo in clock name "video:" clk: imx: clk-imxrt1050: setup PLL5 for video in non-SPL clk: imx: clk-imxrt1050: add set_parent() callback videomodes: add helper function to convert from ctfb to display_timing sunxi: display: use common video_ctfb_mode_to_display_timing() video: mxsfb: add support for DM CLK video: mxsfb: add support for i.MXRT video: mxsfb: refactor for using display_timings video: mxsfb: enable setting HSYNC negative polarity video: mxsfb: enable setting VSYNC negative polarity video: mxsfb: enable setting PIXDATA on negative edge video: mxsfb: enable setting ENABLE negative polarity imxrt1050_evk: add 16bpp video support if video layer enabled ARM: dts: i.mxrt1050: add lcdif node ARM: dts: imxrt1050: allow this dtsi file to be compiled in Linux arch: arm: dts: imxrt1050-evk: add lcdif node configs: imxrt1050-evk: enable video support/console configs: imxrt1050-evk: temporary disable DCACHE arch/arm/dts/imxrt1050-evk.dts | 60 ++ arch/arm/dts/imxrt1050.dtsi| 14 +++- arch/arm/include/asm/arch-imxrt/imx-regs.h | 6 ++ arch/arm/include/asm/mach-imx/regs-lcdif.h | 6 +- configs/imxrt1050-evk_defconfig| 6 ++ drivers/clk/imx/clk-imxrt1050.c| 30 ++- drivers/clk/imx/clk-pllv3.c| 9 +++ drivers/video/mxsfb.c | 94 ++ drivers/video/sunxi/sunxi_display.c| 33 +--- drivers/video/videomodes.c | 29 +++ drivers/video/videomodes.h | 11 +++ include/configs/imxrt1050-evk.h| 15 12 files changed, 242 insertions(+), 71 deletions(-)
Re: [PATCH v3 19/19] configs: imxrt1050-evk: temporary disable DCACHE
Thank you Anatolij -- Giulio Benetti Benetti Engineering sas On 4/17/20 8:33 PM, Anatolij Gustschin wrote: On Wed, 8 Apr 2020 17:11:08 +0200 Giulio Benetti giulio.bene...@benettiengineering.com wrote: mxsfb needs a dcache function not implemented in cortex-M7, so for the moment let's keep dcache not enabled. Signed-off-by: Giulio Benetti Reviewed-by: Anatolij Gustschin -- Anatolij
Re: [PATCH v2 04/19] clk: imx: clk-imxrt1050: add set_parent() callback
Hi Lukasz,
On 3/22/20 11:44 PM, Giulio Benetti wrote:
Need to add set_parent() callback to allow dts assigned-clock-parents to
work so let's add it accordingly.
Signed-off-by: Giulio Benetti
---
V1->V2:
* introduce patch to allow clock's parent setting in dts to work
---
drivers/clk/imx/clk-imxrt1050.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index bb12644605..329f4580c5 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -71,11 +71,30 @@ static int imxrt1050_clk_enable(struct clk *clk)
return __imxrt1050_clk_enable(clk, 1);
}
+static int imxrt1050_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *cp;
+ int ret;
+
+ debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(parent->id, );
+ if (ret)
+ return ret;
+
+ return clk_set_parent(c, cp);
+}
+
static struct clk_ops imxrt1050_clk_ops = {
.set_rate = imxrt1050_clk_set_rate,
.get_rate = imxrt1050_clk_get_rate,
.enable = imxrt1050_clk_enable,
.disable = imxrt1050_clk_disable,
+ .set_parent = imxrt1050_clk_set_parent,
};
static const char * const pll_ref_sels[] = {"osc", "dummy", };
Can you please review this patch? There was not in previous patchset.
Thanks in advance
Kind regards
--
Giulio Benetti
Benetti Engineering sas
Re: [PATCH v2 00/19] i.MXRT1050 add LCDIF support
Hi Fabio, Simon and Anatolij, On 4/16/20 5:23 PM, Fabio Estevam wrote: Hi Giulio, On Thu, Apr 16, 2020 at 12:20 PM Giulio Benetti wrote: Ah I didn't know I had to point someone. So in this case would be either Stefano or Fabio and indeed Fabio answered before here: https://lists.denx.de/pipermail/u-boot/2020-April/406857.html Since this series touches video, clock and i.MX, we still need to get some feedback from Anatolij and Lukasz. Lukasz already reviewed his patches, only Anatolij is missing. Anatolij, can you please take a look at video patches on this patchset? Thanks in advance Best regards -- Giulio Benetti Benetti Engineering sas
Re: [PATCH v3 00/19] i.MXRT1050 add LCDIF support
Hi Fabio, On 4/16/20 3:26 AM, Fabio Estevam wrote: Hi Giulio, On Wed, Apr 8, 2020 at 12:10 PM Giulio Benetti wrote: This patchset add support for LCDIF on i.MXRT1050 evk. This requires PLL5 to be setup, mxsfb needs to use display_timing to retrieve if Lcd has inverted PIXCLOCK from dts. With this patchset applied we temporary loose DCache support until it will get implemented, since a function in mxsfb.c is needed for setting cache behaviour. Anyway this way Lcd will show the console same way as serial does. Also I've moved private sunxi_ctfb_mode_to_display_timing() to videomodes since I need it for mxfsb.c too, then having a unified function to convert from ctfb_mode to display_timing. Nice work! This series looks good to me: Reviewed-by: Fabio Estevam Thank you for reviewing Best regards -- Giulio Benetti Benetti Engineering sas
Re: [PATCH v2 00/19] i.MXRT1050 add LCDIF support
On 4/16/20 5:08 AM, Simon Glass wrote: Hi Giulio, On Wed, 15 Apr 2020 at 14:05, Giulio Benetti wrote: I've pinged the wrong patchset, sorry for the noise, the right one is v3. -- Giulio Benetti Benetti Engineering sas On 4/15/20 9:51 PM, Giulio Benetti wrote: Kindly ping Who are you pinging? Who is the maintainer? Ah I didn't know I had to point someone. So in this case would be either Stefano or Fabio and indeed Fabio answered before here: https://lists.denx.de/pipermail/u-boot/2020-April/406857.html -- Giulio Benetti Benetti Engineering sas
Re: [PATCH 0/5] i.MXRT1020 add basic support
Hi Stefano, I ping you for reviewing this patchset, Lukasz already reviewed his patches, so it should be ready to be committed. Thank you -- Giulio Benetti Benetti Engineering sas On 2/18/20 8:02 PM, Giulio Benetti wrote: Add Soc i.MXRT1020 to i.MXRT family and its evk support. This Soc has many in common with i.MXRT1050 except clock init and pins listing. Giulio Benetti (5): clk: imx: add i.IMXRT1020 clk driver Add i.MXRT1020 support ARM: dts: imxrt1020: add dtsi file dt-bindings: pinctrl: add i.MXRT1020 pins definition Add support for i.MXRT1020-EVK board arch/arm/dts/Makefile | 3 +- arch/arm/dts/imxrt1020-evk-u-boot.dtsi| 44 + arch/arm/dts/imxrt1020-evk.dts| 198 + arch/arm/dts/imxrt1020.dtsi | 133 +++ arch/arm/mach-imx/imxrt/Kconfig | 9 + board/freescale/imxrt1020-evk/Kconfig | 22 + board/freescale/imxrt1020-evk/MAINTAINERS | 6 + board/freescale/imxrt1020-evk/Makefile| 6 + board/freescale/imxrt1020-evk/README | 31 + board/freescale/imxrt1020-evk/imximage.cfg| 36 + board/freescale/imxrt1020-evk/imxrt1020-evk.c | 81 ++ configs/imxrt1020-evk_defconfig | 67 ++ drivers/clk/imx/Kconfig | 16 + drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-imxrt1020.c | 227 ++ include/configs/imxrt1020-evk.h | 46 ++ include/dt-bindings/clock/imxrt1020-clock.h | 52 ++ include/dt-bindings/pinctrl/pins-imxrt1020.h | 763 ++ 18 files changed, 1740 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imxrt1020-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imxrt1020-evk.dts create mode 100644 arch/arm/dts/imxrt1020.dtsi create mode 100644 board/freescale/imxrt1020-evk/Kconfig create mode 100644 board/freescale/imxrt1020-evk/MAINTAINERS create mode 100644 board/freescale/imxrt1020-evk/Makefile create mode 100644 board/freescale/imxrt1020-evk/README create mode 100644 board/freescale/imxrt1020-evk/imximage.cfg create mode 100644 board/freescale/imxrt1020-evk/imxrt1020-evk.c create mode 100644 configs/imxrt1020-evk_defconfig create mode 100644 drivers/clk/imx/clk-imxrt1020.c create mode 100644 include/configs/imxrt1020-evk.h create mode 100644 include/dt-bindings/clock/imxrt1020-clock.h create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1020.h
Re: [PATCH 0/5] i.MXRT1020 add basic support
On 4/18/20 2:57 PM, Stefano Babic wrote: Hi Giulio, On 18/04/20 14:32, Giulio Benetti wrote: Hi Stefano, I ping you for reviewing this patchset, Lukasz already reviewed his patches, so it should be ready to be committed. Yes, I have already merge the big series after Anatolji's ACK, this series was not yet in. I merged into -next and I restart my Travis' job. Ok, thank you very much Best regards -- Giulio Benetti Benetti Engineering sas
[PATCH] dt-bindings: pinctrl: imxrt1020: remove useless comment
A comment note has been left after completing pinctrl listing, so let's remove it since it's useless. Signed-off-by: Giulio Benetti --- include/dt-bindings/pinctrl/pins-imxrt1020.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/dt-bindings/pinctrl/pins-imxrt1020.h b/include/dt-bindings/pinctrl/pins-imxrt1020.h index c6bacb7378..b3a833bde2 100644 --- a/include/dt-bindings/pinctrl/pins-imxrt1020.h +++ b/include/dt-bindings/pinctrl/pins-imxrt1020.h @@ -7,8 +7,6 @@ #ifndef _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H #define _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H -/* TODO: continue from LPI2C4_SDA_SELECT_INPUT */ - #define IMX_PAD_SION 0x4000 /* -- 2.20.1
Re: [PATCH v5 06/14] sifive: fu540: add ddr driver
24
+#define DFI_PHY_RDLVL_MODE_OFFSET 24
+#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0
+#define VREF_EN_OFFSET 24
+#define PORT_ADDR_PROTECTION_EN_OFFSET 0
+#define AXI0_ADDRESS_RANGE_ENABLE 8
+#define AXI0_RANGE_PROT_BITS_0_OFFSET 24
+#define RDLVL_EN_OFFSET 16
+#define RDLVL_GATE_EN_OFFSET24
+#define WRLVL_EN_OFFSET 0
+
+#define PHY_RX_CAL_DQ0_0_OFFSET 0
+#define PHY_RX_CAL_DQ1_0_OFFSET 16
+
+struct fu540_ddrctl {
+ volatile u32 denali_ctl[265];
+};
+
+struct fu540_ddrphy {
+ volatile u32 denali_phy[1215];
+};
+
+struct fu540_sdram_params {
+ struct fu540_ddrctl pctl_regs;
+ struct fu540_ddrphy phy_regs;
+};
+
+struct sifive_dmc_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_sifive_fu540_dmc dtplat;
+#else
+ struct fu540_sdram_params sdram_params;
+#endif
+};
+
+/**
+ * struct ddr_info
+ *
+ * @dev: pointer for the device
+ * @info : UCLASS RAM information
+ * @ctl: DDR controleur base address
+ * @phy: DDR PHY base address
+ * @ctrl : DDR control base address
+ * @physical_filter_ctrl : DDR physical filter control base address
+ */
+struct ddr_info {
+ struct udevice *dev;
+ struct ram_info info;
+ struct fu540_ddrctl *ctl;
+ struct fu540_ddrphy *phy;
+ u32 *physical_filter_ctrl;
+};
IMHO I would keep all these structs and define in driver's .c file, I
mean you should keep them private if not used outside. And then add to
dt-bindings the define needed by dts files.
Best regards
--
Giulio Benetti
Benetti Engineering sas
[PATCH v2 0/4] Various i.MXRT bug/typo fixes
Hi Anatolij, Lukasz, Stefano, Fabio, All, this patchset fix 2 bugs preventing from LCDIF to work when booting from sd-card. There are also 2 little typo fixes for boards READMEs. V1->V2: * modify mxfsb.c patch as suggested by Fabio Giulio Benetti (4): imxrt1050-evk: README: fix dd command destination imxrt1020-evk: README: fix dd command destination video: mxsfb: add clk_enable() clk: imx: clk-imxrt1050: fix lcdif clock gate board/freescale/imxrt1020-evk/README | 2 +- board/freescale/imxrt1050-evk/README | 2 +- drivers/clk/imx/clk-imxrt1050.c | 2 +- drivers/video/mxsfb.c| 6 ++ 4 files changed, 9 insertions(+), 3 deletions(-) -- 2.20.1
[PATCH v2 3/4] video: mxsfb: add clk_enable()
BROM doesn't enable lcdif by default so add clk_enable() after
clk_set_rate().
Signed-off-by: Giulio Benetti
---
V1->V2:
* call clk_enable() after clk_set_rate() as suggested by Fabio
---
drivers/video/mxsfb.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 8a5a61c9fb..12d00b4689 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -77,6 +77,12 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
dev_err(dev, "Failed to set mxs clk: %d\n", ret);
return;
}
+
+ ret = clk_enable(_clk);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable mxs clk: %d\n", ret);
+ return;
+ }
#else
/* Kick in the LCDIF clock */
mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
--
2.20.1
[PATCH v2 2/4] imxrt1020-evk: README: fix dd command destination
Make "of=" the same for the 2 commands since we're writing to the same sd-card. Signed-off-by: Giulio Benetti --- board/freescale/imxrt1020-evk/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/imxrt1020-evk/README b/board/freescale/imxrt1020-evk/README index 3da72fdad2..bcb3683163 100644 --- a/board/freescale/imxrt1020-evk/README +++ b/board/freescale/imxrt1020-evk/README @@ -11,7 +11,7 @@ This will generate the SPL image called SPL and the u-boot.img. - Flash the SPL image into the micro SD card: -sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync +sudo dd if=SPL of=/dev/sdb bs=1k seek=1; sync - Flash the u-boot.img image into the micro SD card: -- 2.20.1
[PATCH v2 4/4] clk: imx: clk-imxrt1050: fix lcdif clock gate
LCDIF clock gate was wrong so set it according to RM.
Signed-off-by: Giulio Benetti
---
drivers/clk/imx/clk-imxrt1050.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index 329f4580c5..8279e784fe 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -255,7 +255,7 @@ static int imxrt1050_clk_probe(struct udevice *dev)
clk_dm(IMXRT1050_CLK_SEMC,
imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
clk_dm(IMXRT1050_CLK_LCDIF,
- imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
+ imx_clk_gate2("lcdif", "lcdif_podf", base + 0x74, 10));
struct clk *clk, *clk1;
--
2.20.1
[PATCH v2 1/4] imxrt1050-evk: README: fix dd command destination
Make "of=" the same for the 2 commands since we're writing to the same sd-card. Signed-off-by: Giulio Benetti --- board/freescale/imxrt1050-evk/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/imxrt1050-evk/README b/board/freescale/imxrt1050-evk/README index f7e2894025..55b6a0877a 100644 --- a/board/freescale/imxrt1050-evk/README +++ b/board/freescale/imxrt1050-evk/README @@ -11,7 +11,7 @@ This will generate the SPL image called SPL and the u-boot.img. - Flash the SPL image into the micro SD card: -sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync +sudo dd if=SPL of=/dev/sdb bs=1k seek=1; sync - Flash the u-boot.img image into the micro SD card: -- 2.20.1
Re: [PATCH 3/4] video: mxsfb: add clk_enable()
Hi Fabio,
On 4/27/20 1:48 AM, Fabio Estevam wrote:
Hi Giulio,
On Sun, Apr 26, 2020 at 8:43 PM Giulio Benetti
wrote:
+ ret = clk_enable(_clk);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable mxs clk: %d\n", ret);
+ return;
+ }
+
ret = clk_set_rate(_clk, timings->pixelclock.typ);
if (ret < 0) {
dev_err(dev, "Failed to set mxs clk: %d\n", ret);
Usually it is safer to configure the clock rate first and then enable
the clock to avoid glitches.
Could you try to call clk_enable() after clk_set_rate() here?
Sure, I'm going to send it for V2.
Thanks for reviewing
--
Giulio Benetti
Benetti Engineering sas
[PATCH] ARM: dts: imxrt1050: indent lcdif node correctly
Accidentally submitted a patch with indentation not correct, let's fix it
by indenting wrong lines.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050.dtsi | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index 7cfe5f5c95..a9281001e5 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -147,12 +147,12 @@
};
lcdif: lcdif@402b8000 {
- compatible = "fsl,imxrt-lcdif";
- reg = <0x402b8000 0x1>;
- interrupts = ;
- clocks = < IMXRT1050_CLK_LCDIF>;
- clock-names = "per";
- status = "disabled";
+ compatible = "fsl,imxrt-lcdif";
+ reg = <0x402b8000 0x4000>;
+ interrupts = ;
+ clocks = < IMXRT1050_CLK_LCDIF>;
+ clock-names = "per";
+ status = "disabled";
};
};
};
--
2.20.1
Re: [PATCH v2 1/4] imxrt1050-evk: README: fix dd command destination
On 4/27/20 5:34 PM, Fabio Estevam wrote: Hi Giulio, On Mon, Apr 27, 2020 at 12:11 PM Giulio Benetti wrote: Make "of=" the same for the 2 commands since we're writing to the same sd-card. Signed-off-by: Giulio Benetti --- board/freescale/imxrt1050-evk/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/imxrt1050-evk/README b/board/freescale/imxrt1050-evk/README index f7e2894025..55b6a0877a 100644 --- a/board/freescale/imxrt1050-evk/README +++ b/board/freescale/imxrt1050-evk/README @@ -11,7 +11,7 @@ This will generate the SPL image called SPL and the u-boot.img. - Flash the SPL image into the micro SD card: -sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync +sudo dd if=SPL of=/dev/sdb bs=1k seek=1; sync I usually prefer to write /dev/sdX instead because someone may follow the instructions as is and inadvertently kill their hard disk or another device that may appear at /dev/sdb. Oh, that's right. I send V3 with that corrected. Thank you -- Giulio Benetti Benetti Engineering sas
[PATCH v3 4/4] clk: imx: clk-imxrt1050: fix lcdif clock gate
LCDIF clock gate was wrong so set it according to RM.
Signed-off-by: Giulio Benetti
---
drivers/clk/imx/clk-imxrt1050.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index 329f4580c5..8279e784fe 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -255,7 +255,7 @@ static int imxrt1050_clk_probe(struct udevice *dev)
clk_dm(IMXRT1050_CLK_SEMC,
imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
clk_dm(IMXRT1050_CLK_LCDIF,
- imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
+ imx_clk_gate2("lcdif", "lcdif_podf", base + 0x74, 10));
struct clk *clk, *clk1;
--
2.20.1
[PATCH v3 1/4] imxrt1050-evk: README: change dd command destination
Set dd "of=" to "of=/dev/sdX" to be generic and prevent host hard drive damage. Signed-off-by: Giulio Benetti --- V2->V3: * change /dev/sdb to /dev/sdX as suggested by Fabio --- board/freescale/imxrt1050-evk/README | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/imxrt1050-evk/README b/board/freescale/imxrt1050-evk/README index f7e2894025..a7e68fa9b3 100644 --- a/board/freescale/imxrt1050-evk/README +++ b/board/freescale/imxrt1050-evk/README @@ -11,11 +11,11 @@ This will generate the SPL image called SPL and the u-boot.img. - Flash the SPL image into the micro SD card: -sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync +sudo dd if=SPL of=/dev/sdX bs=1k seek=1; sync - Flash the u-boot.img image into the micro SD card: -sudo dd if=u-boot.img of=/dev/sdb bs=1k seek=128; sync +sudo dd if=u-boot.img of=/dev/sdX bs=1k seek=128; sync - Jumper settings: -- 2.20.1
[PATCH v3 2/4] imxrt1020-evk: README: change dd command destination
Set dd "of=" to "of=/dev/sdX" to be generic and prevent host hard drive damage. Signed-off-by: Giulio Benetti --- V2->V3: * change /dev/sdb to /dev/sdX as suggested by Fabio --- board/freescale/imxrt1020-evk/README | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/imxrt1020-evk/README b/board/freescale/imxrt1020-evk/README index 3da72fdad2..abee7ca5f3 100644 --- a/board/freescale/imxrt1020-evk/README +++ b/board/freescale/imxrt1020-evk/README @@ -11,11 +11,11 @@ This will generate the SPL image called SPL and the u-boot.img. - Flash the SPL image into the micro SD card: -sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync +sudo dd if=SPL of=/dev/sdX bs=1k seek=1; sync - Flash the u-boot.img image into the micro SD card: -sudo dd if=u-boot.img of=/dev/sdb bs=1k seek=128; sync +sudo dd if=u-boot.img of=/dev/sdX bs=1k seek=128; sync - Jumper settings: -- 2.20.1
[PATCH v3 3/4] video: mxsfb: add clk_enable()
BROM doesn't enable lcdif by default so add clk_enable() after
clk_set_rate().
Signed-off-by: Giulio Benetti
---
V1->V2:
* call clk_enable() after clk_set_rate() as suggested by Fabio
---
drivers/video/mxsfb.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 8a5a61c9fb..12d00b4689 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -77,6 +77,12 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
dev_err(dev, "Failed to set mxs clk: %d\n", ret);
return;
}
+
+ ret = clk_enable(_clk);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable mxs clk: %d\n", ret);
+ return;
+ }
#else
/* Kick in the LCDIF clock */
mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
--
2.20.1
[PATCH v3 0/4] Various i.MXRT bug/typo fixes
Hi Anatolij, Lukasz, Stefano, Fabio, All, this patchset fix 2 bugs preventing from LCDIF to work when booting from sd-card. There are also 2 little typo fixes for boards READMEs. V1->V2: * modify mxfsb.c patch as suggested by Fabio V2->V3: * change /dev/sdb into /dev/sdX as suggested by Fabio Giulio Benetti (4): imxrt1050-evk: README: change dd command destination imxrt1020-evk: README: change dd command destination video: mxsfb: add clk_enable() clk: imx: clk-imxrt1050: fix lcdif clock gate board/freescale/imxrt1020-evk/README | 4 ++-- board/freescale/imxrt1050-evk/README | 4 ++-- drivers/clk/imx/clk-imxrt1050.c | 2 +- drivers/video/mxsfb.c| 6 ++ 4 files changed, 11 insertions(+), 5 deletions(-) -- 2.20.1
Re: [PATCH v3 4/4] clk: imx: clk-imxrt1050: fix lcdif clock gate
Forgotten to add
On 4/27/20 5:53 PM, Giulio Benetti wrote:
LCDIF clock gate was wrong so set it according to RM.
Signed-off-by: Giulio Benetti
Reviewed-by: Anatolij Gustschin
Reviewed-by: Fabio Estevam
---
drivers/clk/imx/clk-imxrt1050.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index 329f4580c5..8279e784fe 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -255,7 +255,7 @@ static int imxrt1050_clk_probe(struct udevice *dev)
clk_dm(IMXRT1050_CLK_SEMC,
imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
clk_dm(IMXRT1050_CLK_LCDIF,
- imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
+ imx_clk_gate2("lcdif", "lcdif_podf", base + 0x74, 10));
struct clk *clk, *clk1;
--
Giulio Benetti
Benetti Engineering sas
Re: [PATCH v3 3/4] video: mxsfb: add clk_enable()
Forgotten to add
On 4/27/20 5:53 PM, Giulio Benetti wrote:
BROM doesn't enable lcdif by default so add clk_enable() after
clk_set_rate().
Signed-off-by: Giulio Benetti
Reviewed-by: Anatolij Gustschin
Reviewed-by: Fabio Estevam
---
V1->V2:
* call clk_enable() after clk_set_rate() as suggested by Fabio
---
drivers/video/mxsfb.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 8a5a61c9fb..12d00b4689 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -77,6 +77,12 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
dev_err(dev, "Failed to set mxs clk: %d\n", ret);
return;
}
+
+ ret = clk_enable(_clk);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable mxs clk: %d\n", ret);
+ return;
+ }
#else
/* Kick in the LCDIF clock */
mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
--
Giulio Benetti
Benetti Engineering sas
Re: [PATCH v3 0/4] Various i.MXRT bug/typo fixes
On 4/27/20 5:57 PM, Fabio Estevam wrote: Hi Giulio, On Mon, Apr 27, 2020 at 12:53 PM Giulio Benetti wrote: Hi Anatolij, Lukasz, Stefano, Fabio, All, this patchset fix 2 bugs preventing from LCDIF to work when booting from sd-card. There are also 2 little typo fixes for boards READMEs. V1->V2: * modify mxfsb.c patch as suggested by Fabio V2->V3: * change /dev/sdb into /dev/sdX as suggested by Fabio For the whole series: Reviewed-by: Fabio Estevam Just a hint for future submissions: when you re-submit a series, please keep the Reviewed-by tags that you received. Yes, I've missed it sorry and re-sent 2 answers to integrate. Thank you very much Best regards -- Giulio Benetti Benetti Engineering sas
[PATCH 0/4] Various i.MXRT bug/typo fixes
Hi Anatolij, Stefano, Fabio, All, this patchset fix 2 bugs preventing from LCDIF to work when booting from sd-card. There are also 2 little typo fixes for boards READMEs. Giulio Benetti (4): imxrt1050-evk: README: fix dd command destination imxrt1020-evk: README: fix dd command destination video: mxsfb: add clk_enable() clk: imx: clk-imxrt1050: fix lcdif clock gate board/freescale/imxrt1020-evk/README | 2 +- board/freescale/imxrt1050-evk/README | 2 +- drivers/clk/imx/clk-imxrt1050.c | 2 +- drivers/video/mxsfb.c| 6 ++ 4 files changed, 9 insertions(+), 3 deletions(-) -- 2.20.1
[PATCH 4/4] clk: imx: clk-imxrt1050: fix lcdif clock gate
LCDIF clock gate was wrong so set it according to RM.
Signed-off-by: Giulio Benetti
---
drivers/clk/imx/clk-imxrt1050.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index 329f4580c5..8279e784fe 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -255,7 +255,7 @@ static int imxrt1050_clk_probe(struct udevice *dev)
clk_dm(IMXRT1050_CLK_SEMC,
imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
clk_dm(IMXRT1050_CLK_LCDIF,
- imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
+ imx_clk_gate2("lcdif", "lcdif_podf", base + 0x74, 10));
struct clk *clk, *clk1;
--
2.20.1
[PATCH 3/4] video: mxsfb: add clk_enable()
BROM doesn't enable lcdif by default so add clk_enable() before
clk_set_rate().
Signed-off-by: Giulio Benetti
---
drivers/video/mxsfb.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 8a5a61c9fb..7eab8835b0 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -72,6 +72,12 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
return;
}
+ ret = clk_enable(_clk);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable mxs clk: %d\n", ret);
+ return;
+ }
+
ret = clk_set_rate(_clk, timings->pixelclock.typ);
if (ret < 0) {
dev_err(dev, "Failed to set mxs clk: %d\n", ret);
--
2.20.1
[PATCH 1/4] imxrt1050-evk: README: fix dd command destination
Make "of=" the same for the 2 commands since we're writing to the same sd-card. Signed-off-by: Giulio Benetti --- board/freescale/imxrt1050-evk/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/imxrt1050-evk/README b/board/freescale/imxrt1050-evk/README index f7e2894025..55b6a0877a 100644 --- a/board/freescale/imxrt1050-evk/README +++ b/board/freescale/imxrt1050-evk/README @@ -11,7 +11,7 @@ This will generate the SPL image called SPL and the u-boot.img. - Flash the SPL image into the micro SD card: -sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync +sudo dd if=SPL of=/dev/sdb bs=1k seek=1; sync - Flash the u-boot.img image into the micro SD card: -- 2.20.1
Re: [PATCH 0/4] Various i.MXRT bug/typo fixes
On 4/27/20 1:42 AM, Giulio Benetti wrote: Hi Anatolij, Stefano, Fabio, All, forgotten Lukasz, sorry. -- Giulio Benetti Benetti Engineering sas this patchset fix 2 bugs preventing from LCDIF to work when booting from sd-card. There are also 2 little typo fixes for boards READMEs. Giulio Benetti (4): imxrt1050-evk: README: fix dd command destination imxrt1020-evk: README: fix dd command destination video: mxsfb: add clk_enable() clk: imx: clk-imxrt1050: fix lcdif clock gate board/freescale/imxrt1020-evk/README | 2 +- board/freescale/imxrt1050-evk/README | 2 +- drivers/clk/imx/clk-imxrt1050.c | 2 +- drivers/video/mxsfb.c| 6 ++ 4 files changed, 9 insertions(+), 3 deletions(-)
[PATCH 2/4] imxrt1020-evk: README: fix dd command destination
Make "of=" the same for the 2 commands since we're writing to the same sd-card. Signed-off-by: Giulio Benetti --- board/freescale/imxrt1020-evk/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/imxrt1020-evk/README b/board/freescale/imxrt1020-evk/README index 3da72fdad2..bcb3683163 100644 --- a/board/freescale/imxrt1020-evk/README +++ b/board/freescale/imxrt1020-evk/README @@ -11,7 +11,7 @@ This will generate the SPL image called SPL and the u-boot.img. - Flash the SPL image into the micro SD card: -sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync +sudo dd if=SPL of=/dev/sdb bs=1k seek=1; sync - Flash the u-boot.img image into the micro SD card: -- 2.20.1
Re: [PATCH v8 06/21] sifive: fu540: add ddr driver
>physical_filter_ctrl, ddr_end);
+
+ ddr_phy_fixup(denali_phy);
+
+ /* check size */
+ priv->info.size = get_ram_size((long *)priv->info.base,
+ DDR_MEM_SIZE);
+
+ debug("%s : %lx\n", __func__, priv->info.size);
+
+ /* check memory access for all memory */
+ if (priv->info.size != DDR_MEM_SIZE) {
+ printf("DDR invalid size : 0x%lx, expected 0x%lx\n",
+ priv->info.size, DDR_MEM_SIZE);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+#endif
+
+static int fu540_ddr_probe(struct udevice *dev)
+{
+ struct ddr_info *priv = dev_get_priv(dev);
+
+#if defined(CONFIG_TPL_BUILD) || \
+ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
+ struct regmap *map;
+ int ret;
+ u32 clock = 0;
+
+ debug("FU540 DDR probe\n");
+ priv->dev = dev;
+
+ ret = regmap_init_mem(dev_ofnode(dev), );
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_index(dev, 0, >ddr_clk);
+ if (ret) {
+ debug("clk get failed %d\n", ret);
+ return ret;
+ }
+
+ ret = dev_read_u32(dev, "clock-frequency", );
+ if (ret) {
+ debug("clock-frequency not found in dt %d\n", ret);
+ return ret;
+ } else {
+ ret = clk_set_rate(>ddr_clk, clock);
+ if (ret < 0) {
+ debug("Could not set DDR clock\n");
+ return ret;
+ }
+ }
+
+ ret = clk_enable(>ddr_clk);
+ priv->ctl = regmap_get_range(map, 0);
+ priv->phy = regmap_get_range(map, 1);
+ priv->physical_filter_ctrl = regmap_get_range(map, 2);
+
+ priv->info.base = CONFIG_SYS_SDRAM_BASE;
+
+ priv->info.size = 0;
+ return fu540_ddr_setup(dev);
+#else
+ priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.size = DDR_MEM_SIZE;
+#endif
+ return 0;
+}
+
+static int fu540_ddr_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct ddr_info *priv = dev_get_priv(dev);
+
+ *info = priv->info;
+
+ return 0;
+}
+
+static struct ram_ops fu540_ddr_ops = {
+ .get_info = fu540_ddr_get_info,
+};
+
+static const struct udevice_id fu540_ddr_ids[] = {
+ { .compatible = "sifive,fu540-c000-ddr" },
+ { }
+};
+
+U_BOOT_DRIVER(fu540_ddr) = {
+ .name = "fu540_ddr",
+ .id = UCLASS_RAM,
+ .of_match = fu540_ddr_ids,
+ .ops = _ddr_ops,
+ .probe = fu540_ddr_probe,
+ .priv_auto_alloc_size = sizeof(struct ddr_info),
+#if defined(CONFIG_TPL_BUILD) || \
+ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
+ .platdata_auto_alloc_size = sizeof(struct sifive_dmc_plat),
+#endif
+};
Best regards
--
Giulio Benetti
Benetti Engineering sas
Re: [PATCH 03/18] clk: imx: clk-imxrt1050: setup PLL5 for video in non-SPL
Hi Lukasz, Fabio,
On 3/9/20 10:11 AM, Lukasz Majewski wrote:
On Sun, 8 Mar 2020 22:05:42 +0100
Giulio Benetti wrote:
Hi Lukasz,
On 3/8/20 9:27 PM, Lukasz Majewski wrote:
On Wed, 26 Feb 2020 18:15:46 +0100
Giulio Benetti wrote:
mxsfb needs PLL5 as source, so let's setup it and set it as source
for mxsfb(lcdif).
Signed-off-by: Giulio Benetti
---
drivers/clk/imx/clk-imxrt1050.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imxrt1050.c
b/drivers/clk/imx/clk-imxrt1050.c index e33d426363..2819ffb9ac
100644 --- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -238,9 +238,9 @@ static int imxrt1050_clk_probe(struct udevice
*dev) clk_dm(IMXRT1050_CLK_LCDIF,
imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70,
28));
-#ifdef CONFIG_SPL_BUILD
struct clk *clk, *clk1;
+#ifdef CONFIG_SPL_BUILD
/* bypass pll1 before setting its rate */
clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, );
clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, );
@@ -271,7 +271,18 @@ static int imxrt1050_clk_probe(struct udevice
*dev)
clk_get_by_id(IMXRT1050_CLK_PLL3_BYPASS, );
clk_set_parent(clk1, clk);
+#else
+ /* Set PLL5 for LCDIF to its default 650Mhz */
+ clk_get_by_id(IMXRT1050_CLK_PLL5_VIDEO, );
+ clk_enable(clk);
+ clk_set_rate(clk, 65000UL);
+
+ clk_get_by_id(IMXRT1050_CLK_PLL5_BYPASS, );
+ clk_set_parent(clk1, clk);
+ /* Configure PLL5 as LCDIF source */
+ clk_get_by_id(IMXRT1050_CLK_LCDIF_SEL, );
+ clk_set_parent(clk1, clk);
As pointed by Fabio, this ^^^ should be substituted with a using
assigned-parent-clocks in dts instead of being hardcoded here.
Upss.. Apparently I've missed the conversation. Thanks for pointing
this out.
What do you think about it?
If it is relatively easy to do then I'm for it.
Yes, I've done it.
I'm going to send v2 series soon.
Best regards
--
Giulio Benetti
Benetti Engineering sas
Thanks for reviewing and
best regards
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
Re: [PATCH 00/18] i.MXRT1050 add LCDIF support
Hi All, On 2/26/20 6:15 PM, Giulio Benetti wrote: This patchset add support for LCDIF on i.MXRT1050 evk. This requires PLL5 to be setup, mxsfb needs to use display_timing to retrieve if Lcd has inverted PIXCLOCK from dts. With this patchset applied we temporary loose DCache support until it will get implemented, since a function in mxsfb.c is needed for setting cache behaviour. Anyway this way Lcd will show the console same way as serial does. Also I've moved private sunxi_ctfb_mode_to_display_timing() to videomodes since I need it for mxfsb.c too, then having a unified function to convert from ctfb_mode to display_timing. Giulio Benetti (18): clk: imx: pllv3: add enable_bit clk: imx: imxrt1050-clk: fix typo in clock name "video:" clk: imx: clk-imxrt1050: setup PLL5 for video in non-SPL videomodes: add helper function to convert from ctfb to display_timing sunxi: display: use common video_ctfb_mode_to_display_timing() video: mxsfb: add support for DM CLK video: mxsfb: add support for i.MXRT video: mxsfb: refactor for using display_timings video: mxsfb: enable setting HSYNC negative polarity video: mxsfb: enable setting VSYNC negative polarity video: mxsfb: enable setting PIXDATA on negative edge video: mxsfb: enable setting ENABLE negative polarity kindly ping for all "video: " and "sunxi: " patches. I've already fixed what Fabio and Lukasz pointed about clock-parents, sowhen can I send v2-series? Does it look ok the rest? Thanks in advance Best regards -- Giulio Benetti Benetti Engineering sas imxrt1050_evk: add 16bpp video support if video layer enabled ARM: dts: i.mxrt1050: add lcdif node ARM: dts: imxrt1050: allow this dtsi file to be compiled in Linux arch: arm: dts: imxrt1050-evk: add lcdif node configs: imxrt1050-evk: enable video support/console configs: imxrt1050-evk: temporary disable DCACHE arch/arm/dts/imxrt1050-evk.dts | 57 + arch/arm/dts/imxrt1050.dtsi| 14 +++- arch/arm/include/asm/arch-imxrt/imx-regs.h | 6 ++ arch/arm/include/asm/mach-imx/regs-lcdif.h | 6 +- configs/imxrt1050-evk_defconfig| 6 ++ drivers/clk/imx/clk-imxrt1050.c| 15 +++- drivers/clk/imx/clk-pllv3.c| 9 +++ drivers/video/mxsfb.c | 94 ++ drivers/video/sunxi/sunxi_display.c| 33 +--- drivers/video/videomodes.c | 29 +++ drivers/video/videomodes.h | 3 + include/configs/imxrt1050-evk.h| 15 12 files changed, 216 insertions(+), 71 deletions(-)
[PATCH v2 07/19] video: mxsfb: add support for DM CLK
Allow using DM CLK instead of mxs_set_lcdclk() so we can avoid to
implement a special function to set lcd clock on i.MXRT.
Signed-off-by: Giulio Benetti
---
drivers/video/mxsfb.c | 30 +-
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 585af3d571..f21f8247d9 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -5,6 +5,7 @@
* Copyright (C) 2011-2013 Marek Vasut
*/
#include
+#include
#include
#include
#include
@@ -52,14 +53,32 @@ __weak void mxsfb_system_setup(void)
* le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
*/
-static void mxs_lcd_init(u32 fb_addr, struct ctfb_res_modes *mode, int bpp)
+static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
+struct ctfb_res_modes *mode, int bpp)
{
struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
uint32_t word_len = 0, bus_width = 0;
uint8_t valid_data = 0;
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk per_clk;
+ int ret;
+
+ ret = clk_get_by_name(dev, "per", _clk);
+ if (ret) {
+ dev_err(dev, "Failed to get mxs clk: %d\n", ret);
+ return;
+ }
+
+ ret = clk_set_rate(_clk, PS2KHZ(mode->pixclock) * 1000);
+ if (ret < 0) {
+ dev_err(dev, "Failed to set mxs clk: %d\n", ret);
+ return;
+ }
+#else
/* Kick in the LCDIF clock */
mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock));
+#endif
/* Restart the LCDIF block */
mxs_reset_block(>hw_lcdif_ctrl_reg);
@@ -135,10 +154,11 @@ static void mxs_lcd_init(u32 fb_addr, struct
ctfb_res_modes *mode, int bpp)
writel(LCDIF_CTRL_RUN, >hw_lcdif_ctrl_set);
}
-static int mxs_probe_common(struct ctfb_res_modes *mode, int bpp, u32 fb)
+static int mxs_probe_common(struct udevice *dev, struct ctfb_res_modes *mode,
+ int bpp, u32 fb)
{
/* Start framebuffer */
- mxs_lcd_init(fb, mode, bpp);
+ mxs_lcd_init(dev, fb, mode, bpp);
#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
/*
@@ -260,7 +280,7 @@ void *video_hw_init(void)
printf("%s\n", panel.modeIdent);
- ret = mxs_probe_common(, bpp, (u32)fb);
+ ret = mxs_probe_common(NULL, , bpp, (u32)fb);
if (ret)
goto dealloc_fb;
@@ -337,7 +357,7 @@ static int mxs_video_probe(struct udevice *dev)
mode.vsync_len = timings.vsync_len.typ;
mode.pixclock = HZ2PS(timings.pixelclock.typ);
- ret = mxs_probe_common(, bpp, plat->base);
+ ret = mxs_probe_common(dev, , bpp, plat->base);
if (ret)
return ret;
--
2.20.1
[PATCH v2 05/19] videomodes: add helper function to convert from ctfb to display_timing
This function converts from "struct ctf_res_modes" to
"struct display_timing".
Signed-off-by: Giulio Benetti
---
drivers/video/videomodes.c | 29 +
drivers/video/videomodes.h | 3 +++
2 files changed, 32 insertions(+)
diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c
index ac25b45f81..89003eea72 100644
--- a/drivers/video/videomodes.c
+++ b/drivers/video/videomodes.c
@@ -444,3 +444,32 @@ int video_edid_dtd_to_ctfb_res_modes(struct
edid_detailed_timing *t,
return 0;
}
+
+void video_ctfb_mode_to_display_timing(const struct ctfb_res_modes *mode,
+ struct display_timing *timing)
+{
+ timing->pixelclock.typ = mode->pixclock_khz * 1000;
+
+ timing->hactive.typ = mode->xres;
+ timing->hfront_porch.typ = mode->right_margin;
+ timing->hback_porch.typ = mode->left_margin;
+ timing->hsync_len.typ = mode->hsync_len;
+
+ timing->vactive.typ = mode->yres;
+ timing->vfront_porch.typ = mode->lower_margin;
+ timing->vback_porch.typ = mode->upper_margin;
+ timing->vsync_len.typ = mode->vsync_len;
+
+ timing->flags = 0;
+
+ if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
+ timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
+ else
+ timing->flags |= DISPLAY_FLAGS_HSYNC_LOW;
+ if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
+ timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
+ else
+ timing->flags |= DISPLAY_FLAGS_VSYNC_LOW;
+ if (mode->vmode == FB_VMODE_INTERLACED)
+ timing->flags |= DISPLAY_FLAGS_INTERLACED;
+}
diff --git a/drivers/video/videomodes.h b/drivers/video/videomodes.h
index 29a3db4ae3..6713f96d19 100644
--- a/drivers/video/videomodes.h
+++ b/drivers/video/videomodes.h
@@ -92,3 +92,6 @@ int video_get_option_int(const char *options, const char
*name, int def);
int video_edid_dtd_to_ctfb_res_modes(struct edid_detailed_timing *t,
struct ctfb_res_modes *mode);
+
+void video_ctfb_mode_to_display_timing(const struct ctfb_res_modes *mode,
+ struct display_timing *timing);
--
2.20.1
[PATCH v2 08/19] video: mxsfb: add support for i.MXRT
Add support for i.MXRT by adding CONFIG_IMXRT in register structure and
adding .compatible = "fsl,imxrt-lcdif".
Signed-off-by: Giulio Benetti
---
arch/arm/include/asm/arch-imxrt/imx-regs.h | 6 ++
arch/arm/include/asm/mach-imx/regs-lcdif.h | 6 +++---
drivers/video/mxsfb.c | 1 +
3 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-imxrt/imx-regs.h
b/arch/arm/include/asm/arch-imxrt/imx-regs.h
index 4f1d439f6f..44c95dcd11 100644
--- a/arch/arm/include/asm/arch-imxrt/imx-regs.h
+++ b/arch/arm/include/asm/arch-imxrt/imx-regs.h
@@ -17,4 +17,10 @@
#define ANATOP_BASE_ADDR 0x400d8000
+#define MXS_LCDIF_BASE 0x402b8000
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include
+#endif
+
#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h
b/arch/arm/include/asm/mach-imx/regs-lcdif.h
index b4c430a35c..5874638796 100644
--- a/arch/arm/include/asm/mach-imx/regs-lcdif.h
+++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h
@@ -22,7 +22,7 @@ struct mxs_lcdif_regs {
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
- defined(CONFIG_IMX8M)
+ defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT)
mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
#endif
mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
@@ -49,7 +49,7 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */
mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */
mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
- mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
+ mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */
#if defined(CONFIG_MX23)
@@ -61,7 +61,7 @@ struct mxs_lcdif_regs {
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
- defined(CONFIG_IMX8M)
+ defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT)
mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
#endif
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index f21f8247d9..6826ba3d1b 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -440,6 +440,7 @@ static const struct udevice_id mxs_video_ids[] = {
{ .compatible = "fsl,imx23-lcdif" },
{ .compatible = "fsl,imx28-lcdif" },
{ .compatible = "fsl,imx7ulp-lcdif" },
+ { .compatible = "fsl,imxrt-lcdif" },
{ /* sentinel */ }
};
--
2.20.1
[PATCH v2 10/19] video: mxsfb: enable setting HSYNC negative polarity
HSYNC signal can now be flipped according to display_flags bitmaks by
writing its bitmask on vdctrl0 register.
Signed-off-by: Giulio Benetti
---
drivers/video/mxsfb.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index cdd6dfaced..9912cf3d82 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -57,8 +57,10 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
struct display_timing *timings, int bpp)
{
struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+ const enum display_flags flags = timings->flags;
uint32_t word_len = 0, bus_width = 0;
uint8_t valid_data = 0;
+ uint32_t vdctrl0;
#if CONFIG_IS_ENABLED(CLK)
struct clk per_clk;
@@ -118,10 +120,14 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
writel((timings->vactive.typ << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
timings->hactive.typ, >hw_lcdif_transfer_count);
- writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
- LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
- LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
- timings->vsync_len.typ, >hw_lcdif_vdctrl0);
+ vdctrl0 = LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
+ LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
+ LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
+ timings->vsync_len.typ;
+
+ if(flags & DISPLAY_FLAGS_HSYNC_HIGH)
+ vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
+ writel(vdctrl0, >hw_lcdif_vdctrl0);
writel(timings->vback_porch.typ + timings->vfront_porch.typ +
timings->vsync_len.typ + timings->vactive.typ,
>hw_lcdif_vdctrl1);
--
2.20.1
[PATCH v2 12/19] video: mxsfb: enable setting PIXDATA on negative edge
DOTCLK signal can now be flipped by writing its bitmask on vdctrl0 register. Signed-off-by: Giulio Benetti --- drivers/video/mxsfb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 4d33e24e1a..648e1c22fe 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -129,6 +129,8 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr, vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL; if(flags & DISPLAY_FLAGS_VSYNC_HIGH) vdctrl0 |= LCDIF_VDCTRL0_VSYNC_POL; + if(flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) + vdctrl0 |= LCDIF_VDCTRL0_DOTCLK_POL; writel(vdctrl0, >hw_lcdif_vdctrl0); writel(timings->vback_porch.typ + timings->vfront_porch.typ + timings->vsync_len.typ + timings->vactive.typ, -- 2.20.1
[PATCH v2 09/19] video: mxsfb: refactor for using display_timings
struct display_timings provides more informations such clock and DE
polarity, so let's refactor the code to use struct display_timings
instead of struct ctfb_res_modes, so we'll become able to get clock and
DE polarity settings and set register according to them in the next patch.
Signed-off-by: Giulio Benetti
---
drivers/video/mxsfb.c | 54 ++-
1 file changed, 23 insertions(+), 31 deletions(-)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 6826ba3d1b..cdd6dfaced 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -54,7 +54,7 @@ __weak void mxsfb_system_setup(void)
*/
static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
-struct ctfb_res_modes *mode, int bpp)
+struct display_timing *timings, int bpp)
{
struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
uint32_t word_len = 0, bus_width = 0;
@@ -70,14 +70,14 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
return;
}
- ret = clk_set_rate(_clk, PS2KHZ(mode->pixclock) * 1000);
+ ret = clk_set_rate(_clk, timings->pixelclock.typ);
if (ret < 0) {
dev_err(dev, "Failed to set mxs clk: %d\n", ret);
return;
}
#else
/* Kick in the LCDIF clock */
- mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock));
+ mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
#endif
/* Restart the LCDIF block */
@@ -115,25 +115,25 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
mxsfb_system_setup();
- writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
- >hw_lcdif_transfer_count);
+ writel((timings->vactive.typ << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
+ timings->hactive.typ, >hw_lcdif_transfer_count);
writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
- mode->vsync_len, >hw_lcdif_vdctrl0);
- writel(mode->upper_margin + mode->lower_margin +
- mode->vsync_len + mode->yres,
+ timings->vsync_len.typ, >hw_lcdif_vdctrl0);
+ writel(timings->vback_porch.typ + timings->vfront_porch.typ +
+ timings->vsync_len.typ + timings->vactive.typ,
>hw_lcdif_vdctrl1);
- writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
- (mode->left_margin + mode->right_margin +
- mode->hsync_len + mode->xres),
+ writel((timings->hsync_len.typ <<
LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
+ (timings->hback_porch.typ + timings->hfront_porch.typ +
+ timings->hsync_len.typ + timings->hactive.typ),
>hw_lcdif_vdctrl2);
- writel(((mode->left_margin + mode->hsync_len) <<
+ writel(((timings->hback_porch.typ + timings->hsync_len.typ) <<
LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
- (mode->upper_margin + mode->vsync_len),
+ (timings->vback_porch.typ + timings->vsync_len.typ),
>hw_lcdif_vdctrl3);
- writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
+ writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) |
timings->hactive.typ,
>hw_lcdif_vdctrl4);
writel(fb_addr, >hw_lcdif_cur_buf);
@@ -154,11 +154,11 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
writel(LCDIF_CTRL_RUN, >hw_lcdif_ctrl_set);
}
-static int mxs_probe_common(struct udevice *dev, struct ctfb_res_modes *mode,
+static int mxs_probe_common(struct udevice *dev, struct display_timing
*timings,
int bpp, u32 fb)
{
/* Start framebuffer */
- mxs_lcd_init(dev, fb, mode, bpp);
+ mxs_lcd_init(dev, fb, timings, bpp);
#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
/*
@@ -224,6 +224,7 @@ void *video_hw_init(void)
char *penv;
void *fb = NULL;
struct ctfb_res_modes mode;
+ struct display_timing timings;
puts("Video: ");
@@ -280,7 +281,9 @@ void *video_hw_init(void)
printf("%s\n", panel.modeIdent);
- ret = mxs_probe_common(NULL, , bpp, (u32)fb);
+ video_ctfb_mode_to_display_timing(, );
+
+ ret = mxs_probe_common(NULL, , bpp, (u32)fb);
if (ret)
goto dealloc_fb;
@@ -334,7 +337,6 @@ static int mxs_video_probe(struct udevice *dev)
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
- struc
[PATCH v2 04/19] clk: imx: clk-imxrt1050: add set_parent() callback
Need to add set_parent() callback to allow dts assigned-clock-parents to
work so let's add it accordingly.
Signed-off-by: Giulio Benetti
---
V1->V2:
* introduce patch to allow clock's parent setting in dts to work
---
drivers/clk/imx/clk-imxrt1050.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index bb12644605..329f4580c5 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -71,11 +71,30 @@ static int imxrt1050_clk_enable(struct clk *clk)
return __imxrt1050_clk_enable(clk, 1);
}
+static int imxrt1050_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *cp;
+ int ret;
+
+ debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(parent->id, );
+ if (ret)
+ return ret;
+
+ return clk_set_parent(c, cp);
+}
+
static struct clk_ops imxrt1050_clk_ops = {
.set_rate = imxrt1050_clk_set_rate,
.get_rate = imxrt1050_clk_get_rate,
.enable = imxrt1050_clk_enable,
.disable = imxrt1050_clk_disable,
+ .set_parent = imxrt1050_clk_set_parent,
};
static const char * const pll_ref_sels[] = {"osc", "dummy", };
--
2.20.1
[PATCH v2 02/19] clk: imx: clk-imxrt1050: fix typo in clock name "video:"
"video:" must be "video", ":" is a typo.
Signed-off-by: Giulio Benetti
Reviewed-by: Lukasz Majewski
---
drivers/clk/imx/clk-imxrt1050.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index 44ca52c013..e33d426363 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -90,7 +90,7 @@ static const char *const usdhc_sels[] = { "pll2_pfd2_396m",
"pll2_pfd0_352m", };
static const char *const lpuart_sels[] = { "pll3_80m", "osc", };
static const char *const semc_alt_sels[] = { "pll2_pfd2_396m",
"pll3_pfd1_664_62m", };
static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
-static const char *const lcdif_sels[] = { "pll2_sys", "pll3_pfd3_454_74m",
"pll5_video:", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_664_62m"};
+static const char *const lcdif_sels[] = { "pll2_sys", "pll3_pfd3_454_74m",
"pll5_video", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_664_62m"};
static int imxrt1050_clk_probe(struct udevice *dev)
{
--
2.20.1
[PATCH v2 01/19] clk: imx: pllv3: add enable_bit
pllv3 PLLs have powerdown/up bits but enable bits too. Specifically
"enable bit" enable the pll output, so when dis/enabling pll by
setting/clearing power_bit we must also set/clear enable_bit.
Signed-off-by: Giulio Benetti
Reviewed-by: Lukasz Majewski
---
drivers/clk/imx/clk-pllv3.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 525442debf..b4a9d587e1 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -25,6 +25,7 @@
#define PLL_DENOM_OFFSET 0x20
#define BM_PLL_POWER (0x1 << 12)
+#define BM_PLL_ENABLE (0x1 << 13)
#define BM_PLL_LOCK(0x1 << 31)
struct clk_pllv3 {
@@ -32,6 +33,7 @@ struct clk_pllv3 {
void __iomem*base;
u32 power_bit;
boolpowerup_set;
+ u32 enable_bit;
u32 div_mask;
u32 div_shift;
};
@@ -83,6 +85,9 @@ static int clk_pllv3_generic_enable(struct clk *clk)
val |= pll->power_bit;
else
val &= ~pll->power_bit;
+
+ val |= pll->enable_bit;
+
writel(val, pll->base);
return 0;
@@ -98,6 +103,9 @@ static int clk_pllv3_generic_disable(struct clk *clk)
val &= ~pll->power_bit;
else
val |= pll->power_bit;
+
+ val &= ~pll->enable_bit;
+
writel(val, pll->base);
return 0;
@@ -238,6 +246,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const
char *name,
return ERR_PTR(-ENOMEM);
pll->power_bit = BM_PLL_POWER;
+ pll->enable_bit = BM_PLL_ENABLE;
switch (type) {
case IMX_PLLV3_GENERIC:
--
2.20.1
[PATCH v2 06/19] sunxi: display: use common video_ctfb_mode_to_display_timing()
Since video_ctfb_mode_to_display_timing() has been implemented by moving
sunxi_ctfb_mode_to_display_timing() to video_modes.c and it's meant to be
used by other video subsystem, let's use it instead of local
sunxi_ctfb_mode_to_display_timing().
Signed-off-by: Giulio Benetti
---
drivers/video/sunxi/sunxi_display.c | 33 ++---
1 file changed, 2 insertions(+), 31 deletions(-)
diff --git a/drivers/video/sunxi/sunxi_display.c
b/drivers/video/sunxi/sunxi_display.c
index 31f0aa7ddc..a6a62c83ef 100644
--- a/drivers/video/sunxi/sunxi_display.c
+++ b/drivers/video/sunxi/sunxi_display.c
@@ -615,35 +615,6 @@ static void sunxi_lcdc_backlight_enable(void)
gpio_direction_output(pin, PWM_ON);
}
-static void sunxi_ctfb_mode_to_display_timing(const struct ctfb_res_modes
*mode,
- struct display_timing *timing)
-{
- timing->pixelclock.typ = mode->pixclock_khz * 1000;
-
- timing->hactive.typ = mode->xres;
- timing->hfront_porch.typ = mode->right_margin;
- timing->hback_porch.typ = mode->left_margin;
- timing->hsync_len.typ = mode->hsync_len;
-
- timing->vactive.typ = mode->yres;
- timing->vfront_porch.typ = mode->lower_margin;
- timing->vback_porch.typ = mode->upper_margin;
- timing->vsync_len.typ = mode->vsync_len;
-
- timing->flags = 0;
-
- if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
- timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
- else
- timing->flags |= DISPLAY_FLAGS_HSYNC_LOW;
- if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
- timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
- else
- timing->flags |= DISPLAY_FLAGS_VSYNC_LOW;
- if (mode->vmode == FB_VMODE_INTERLACED)
- timing->flags |= DISPLAY_FLAGS_INTERLACED;
-}
-
static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
bool for_ext_vga_dac)
{
@@ -673,7 +644,7 @@ static void sunxi_lcdc_tcon0_mode_set(const struct
ctfb_res_modes *mode,
lcdc_pll_set(ccm, 0, mode->pixclock_khz, _div, _double,
sunxi_is_composite());
- sunxi_ctfb_mode_to_display_timing(mode, );
+ video_ctfb_mode_to_display_timing(mode, );
lcdc_tcon0_mode_set(lcdc, , clk_div, for_ext_vga_dac,
sunxi_display.depth, CONFIG_VIDEO_LCD_DCLK_PHASE);
}
@@ -689,7 +660,7 @@ static void sunxi_lcdc_tcon1_mode_set(const struct
ctfb_res_modes *mode,
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct display_timing timing;
- sunxi_ctfb_mode_to_display_timing(mode, );
+ video_ctfb_mode_to_display_timing(mode, );
lcdc_tcon1_mode_set(lcdc, , use_portd_hvsync,
sunxi_is_composite());
--
2.20.1
[PATCH v2 11/19] video: mxsfb: enable setting VSYNC negative polarity
VSYNC signal can now be flipped by writing its bitmask on vdctrl0 register. Signed-off-by: Giulio Benetti --- drivers/video/mxsfb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 9912cf3d82..4d33e24e1a 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -127,6 +127,8 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr, if(flags & DISPLAY_FLAGS_HSYNC_HIGH) vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL; + if(flags & DISPLAY_FLAGS_VSYNC_HIGH) + vdctrl0 |= LCDIF_VDCTRL0_VSYNC_POL; writel(vdctrl0, >hw_lcdif_vdctrl0); writel(timings->vback_porch.typ + timings->vfront_porch.typ + timings->vsync_len.typ + timings->vactive.typ, -- 2.20.1
[PATCH v2 14/19] imxrt1050_evk: add 16bpp video support if video layer enabled
i.MXRT1050 provides mxsfb compatible lcd controller, so let's enable video mxsfb driver with 16bpp depth if CONFIG_DM_VIDEO is selected since board has 16bpp only connection. Signed-off-by: Giulio Benetti --- include/configs/imxrt1050-evk.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index cdec657fb0..3a6b972d9a 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -30,6 +30,21 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#ifdef CONFIG_DM_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" +#endif + /* * Configuration of the external SDRAM memory */ -- 2.20.1
Re: [PATCH v2 00/19] i.MXRT1050 add LCDIF support
This patchset passed travis: https://travis-ci.org/github/giuliobenetti/u-boot-imxrt/builds/665577905?utm_medium=notification_source=email And also: ./tools/buildman/buildman.py --branch=dev/imxrt-lcdif odroid edison trats trats2 imxrt --show_errors --force-build --count=19 --output-dir=../BUILD/ Best regards -- Giulio Benetti Benetti Engineering sas On 3/22/20 11:44 PM, Giulio Benetti wrote: This patchset add support for LCDIF on i.MXRT1050 evk. This requires PLL5 to be setup, mxsfb needs to use display_timing to retrieve if Lcd has inverted PIXCLOCK from dts. With this patchset applied we temporary loose DCache support until it will get implemented, since a function in mxsfb.c is needed for setting cache behaviour. Anyway this way Lcd will show the console same way as serial does. Also I've moved private sunxi_ctfb_mode_to_display_timing() to videomodes since I need it for mxfsb.c too, then having a unified function to convert from ctfb_mode to display_timing. Changes: V1->V2: * moved hard-coded LCDIF's parent clock from clk-imxrt1050.c to imxrt1050-evk.dts * reworded some commit log Giulio Benetti (19): clk: imx: pllv3: add enable_bit clk: imx: clk-imxrt1050: fix typo in clock name "video:" clk: imx: clk-imxrt1050: setup PLL5 for video in non-SPL clk: imx: clk-imxrt1050: add set_parent() callback videomodes: add helper function to convert from ctfb to display_timing sunxi: display: use common video_ctfb_mode_to_display_timing() video: mxsfb: add support for DM CLK video: mxsfb: add support for i.MXRT video: mxsfb: refactor for using display_timings video: mxsfb: enable setting HSYNC negative polarity video: mxsfb: enable setting VSYNC negative polarity video: mxsfb: enable setting PIXDATA on negative edge video: mxsfb: enable setting ENABLE negative polarity imxrt1050_evk: add 16bpp video support if video layer enabled ARM: dts: i.mxrt1050: add lcdif node ARM: dts: imxrt1050: allow this dtsi file to be compiled in Linux arch: arm: dts: imxrt1050-evk: add lcdif node configs: imxrt1050-evk: enable video support/console configs: imxrt1050-evk: temporary disable DCACHE arch/arm/dts/imxrt1050-evk.dts | 60 ++ arch/arm/dts/imxrt1050.dtsi| 14 +++- arch/arm/include/asm/arch-imxrt/imx-regs.h | 6 ++ arch/arm/include/asm/mach-imx/regs-lcdif.h | 6 +- configs/imxrt1050-evk_defconfig| 6 ++ drivers/clk/imx/clk-imxrt1050.c| 30 ++- drivers/clk/imx/clk-pllv3.c| 9 +++ drivers/video/mxsfb.c | 94 ++ drivers/video/sunxi/sunxi_display.c| 33 +--- drivers/video/videomodes.c | 29 +++ drivers/video/videomodes.h | 3 + include/configs/imxrt1050-evk.h| 15 12 files changed, 234 insertions(+), 71 deletions(-)
Re: [PATCH v2 15/19] ARM: dts: i.mxrt1050: add lcdif node
Sorry I've sent this patch twice.
--
Giulio Benetti
Benetti Engineering sas
On 3/22/20 11:44 PM, Giulio Benetti wrote:
Add lcdif node to SoC.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index b1d98e6feb..0123f4788c 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -13,6 +13,7 @@
/ {
aliases {
+ display0 =
gpio0 =
gpio1 =
gpio2 =
@@ -142,5 +143,14 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ lcdif: lcdif@402b8000 {
+ compatible = "fsl,imxrt-lcdif";
+ reg = <0x402b8000 0x1>;
+ interrupts = ;
+ clocks = < IMXRT1050_CLK_LCDIF>;
+ clock-names = "per";
+ status = "disabled";
+ };
};
};
[PATCH v2 17/19] arch: arm: dts: imxrt1050-evk: add lcdif node
Add lcdif node and its pinctrl.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050-evk.dts | 60 ++
1 file changed, 60 insertions(+)
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index 56b75986e2..b5e781275e 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -185,6 +185,33 @@
0x17061
>;
};
+
+ pinctrl_lcdif: lcdifgrp {
+ u-boot,dm-spl;
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15
0x1b0b1
+ MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31
0x0b069
+ MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02
0x0b069
+ >;
+ };
};
};
@@ -198,3 +225,36 @@
cd-gpios = < 28 GPIO_ACTIVE_LOW>;
};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_lcdif>;
+ display = <>;
+ status = "okay";
+
+ assigned-clocks = < IMXRT1050_CLK_LCDIF_SEL>;
+ assigned-clock-parents = < IMXRT1050_CLK_PLL5_VIDEO>;
+
+ display0: display0 {
+ bits-per-pixel = <16>;
+ bus-width = <16>;
+
+ display-timings {
+ timing0: timing0 {
+ clock-frequency = <930>;
+ hactive = <480>;
+ vactive = <272>;
+ hback-porch = <4>;
+ hfront-porch = <8>;
+ vback-porch = <4>;
+ vfront-porch = <8>;
+ hsync-len = <41>;
+ vsync-len = <10>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ };
+ };
+ };
+};
--
2.20.1
[PATCH v2 15/19] ARM: dts: i.mxrt1050: add lcdif node
Add lcdif node to SoC.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index b1d98e6feb..0123f4788c 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -13,6 +13,7 @@
/ {
aliases {
+ display0 =
gpio0 =
gpio1 =
gpio2 =
@@ -142,5 +143,14 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ lcdif: lcdif@402b8000 {
+ compatible = "fsl,imxrt-lcdif";
+ reg = <0x402b8000 0x1>;
+ interrupts = ;
+ clocks = < IMXRT1050_CLK_LCDIF>;
+ clock-names = "per";
+ status = "disabled";
+ };
};
};
--
2.20.1
[PATCH v2 16/19] ARM: dts: imxrt1050: allow this dtsi file to be compiled in Linux
Linux doesn't provide skeleton.dtsi file so let's remove its include and
provide #address-cells/size-cells = <1> that were defined in
skeleton.dtsi before.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index 0123f4788c..7cfe5f5c95 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -4,7 +4,6 @@
* Author(s): Giulio Benetti
*/
-#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include
#include
@@ -12,6 +11,9 @@
#include
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
display0 =
gpio0 =
--
2.20.1
[PATCH v2 13/19] video: mxsfb: enable setting ENABLE negative polarity
ENABLE signal can now be flipped by writing its bitmask on vdctrl0 register. Signed-off-by: Giulio Benetti --- drivers/video/mxsfb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 648e1c22fe..8a5a61c9fb 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -131,6 +131,9 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr, vdctrl0 |= LCDIF_VDCTRL0_VSYNC_POL; if(flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) vdctrl0 |= LCDIF_VDCTRL0_DOTCLK_POL; + if(flags & DISPLAY_FLAGS_DE_HIGH) + vdctrl0 |= LCDIF_VDCTRL0_ENABLE_POL; + writel(vdctrl0, >hw_lcdif_vdctrl0); writel(timings->vback_porch.typ + timings->vfront_porch.typ + timings->vsync_len.typ + timings->vactive.typ, -- 2.20.1
[PATCH v2 19/19] configs: imxrt1050-evk: temporary disable DCACHE
mxsfb needs a dcache function not implemented in cortex-M7, so for the moment let's keep dcache not enabled. Signed-off-by: Giulio Benetti --- configs/imxrt1050-evk_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index 810f391fdc..25d0ba191c 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -1,4 +1,6 @@ CONFIG_ARM=y +CONFIG_SYS_DCACHE_OFF=y +# CONFIG_SPL_SYS_DCACHE_OFF is not set CONFIG_ARCH_IMXRT=y CONFIG_SYS_TEXT_BASE=0x80002000 CONFIG_SPL_GPIO_SUPPORT=y -- 2.20.1
[PATCH v2 18/19] configs: imxrt1050-evk: enable video support/console
Enable DM_VIDEO subsystem and its BACKLIGHT_GPIO. Then enable SYS_WHITE_ON_BLACK to have classic black background on display. Need also to enable CONFIG_SYS_CONSOLE_ENV_OVERWRITE to retrieve stdin/stdout/stderr from CONFIG_EXTRA_ENV_SETTINGS. Signed-off-by: Giulio Benetti --- configs/imxrt1050-evk_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index 71970552c0..810f391fdc 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_TEXT_BASE=0x20209000 CONFIG_DISTRO_DEFAULTS=y CONFIG_SD_BOOT=y # CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set @@ -62,6 +63,9 @@ CONFIG_IMXRT_SDRAM=y CONFIG_FSL_LPUART=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y +CONFIG_DM_VIDEO=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SHA1=y CONFIG_SHA256=y CONFIG_HEXDUMP=y -- 2.20.1
[PATCH v2 15/19] ARM: dts: i.mxrt1050: add lcdif node
Add lcdif node to SoC.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index b1d98e6feb..0123f4788c 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -13,6 +13,7 @@
/ {
aliases {
+ display0 =
gpio0 =
gpio1 =
gpio2 =
@@ -142,5 +143,14 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ lcdif: lcdif@402b8000 {
+ compatible = "fsl,imxrt-lcdif";
+ reg = <0x402b8000 0x1>;
+ interrupts = ;
+ clocks = < IMXRT1050_CLK_LCDIF>;
+ clock-names = "per";
+ status = "disabled";
+ };
};
};
--
2.20.1
[PATCH v2 00/19] i.MXRT1050 add LCDIF support
This patchset add support for LCDIF on i.MXRT1050 evk. This requires PLL5 to be setup, mxsfb needs to use display_timing to retrieve if Lcd has inverted PIXCLOCK from dts. With this patchset applied we temporary loose DCache support until it will get implemented, since a function in mxsfb.c is needed for setting cache behaviour. Anyway this way Lcd will show the console same way as serial does. Also I've moved private sunxi_ctfb_mode_to_display_timing() to videomodes since I need it for mxfsb.c too, then having a unified function to convert from ctfb_mode to display_timing. Changes: V1->V2: * moved hard-coded LCDIF's parent clock from clk-imxrt1050.c to imxrt1050-evk.dts * reworded some commit log Giulio Benetti (19): clk: imx: pllv3: add enable_bit clk: imx: clk-imxrt1050: fix typo in clock name "video:" clk: imx: clk-imxrt1050: setup PLL5 for video in non-SPL clk: imx: clk-imxrt1050: add set_parent() callback videomodes: add helper function to convert from ctfb to display_timing sunxi: display: use common video_ctfb_mode_to_display_timing() video: mxsfb: add support for DM CLK video: mxsfb: add support for i.MXRT video: mxsfb: refactor for using display_timings video: mxsfb: enable setting HSYNC negative polarity video: mxsfb: enable setting VSYNC negative polarity video: mxsfb: enable setting PIXDATA on negative edge video: mxsfb: enable setting ENABLE negative polarity imxrt1050_evk: add 16bpp video support if video layer enabled ARM: dts: i.mxrt1050: add lcdif node ARM: dts: imxrt1050: allow this dtsi file to be compiled in Linux arch: arm: dts: imxrt1050-evk: add lcdif node configs: imxrt1050-evk: enable video support/console configs: imxrt1050-evk: temporary disable DCACHE arch/arm/dts/imxrt1050-evk.dts | 60 ++ arch/arm/dts/imxrt1050.dtsi| 14 +++- arch/arm/include/asm/arch-imxrt/imx-regs.h | 6 ++ arch/arm/include/asm/mach-imx/regs-lcdif.h | 6 +- configs/imxrt1050-evk_defconfig| 6 ++ drivers/clk/imx/clk-imxrt1050.c| 30 ++- drivers/clk/imx/clk-pllv3.c| 9 +++ drivers/video/mxsfb.c | 94 ++ drivers/video/sunxi/sunxi_display.c| 33 +--- drivers/video/videomodes.c | 29 +++ drivers/video/videomodes.h | 3 + include/configs/imxrt1050-evk.h| 15 12 files changed, 234 insertions(+), 71 deletions(-) -- 2.20.1
[PATCH v2 03/19] clk: imx: clk-imxrt1050: setup PLL5 for video in non-SPL
mxsfb needs PLL5 as source, so let's setup it at its default frequency
specified in RM(650Mhz).
Signed-off-by: Giulio Benetti
Reviewed-by: Lukasz Majewski
---
V1->V2:
* removed LCDIF set_parent() since it's setup in dts file(suggested by Fabio)
---
drivers/clk/imx/clk-imxrt1050.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index e33d426363..bb12644605 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -238,9 +238,9 @@ static int imxrt1050_clk_probe(struct udevice *dev)
clk_dm(IMXRT1050_CLK_LCDIF,
imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
-#ifdef CONFIG_SPL_BUILD
struct clk *clk, *clk1;
+#ifdef CONFIG_SPL_BUILD
/* bypass pll1 before setting its rate */
clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, );
clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, );
@@ -271,7 +271,14 @@ static int imxrt1050_clk_probe(struct udevice *dev)
clk_get_by_id(IMXRT1050_CLK_PLL3_BYPASS, );
clk_set_parent(clk1, clk);
+#else
+ /* Set PLL5 for LCDIF to its default 650Mhz */
+ clk_get_by_id(IMXRT1050_CLK_PLL5_VIDEO, );
+ clk_enable(clk);
+ clk_set_rate(clk, 65000UL);
+ clk_get_by_id(IMXRT1050_CLK_PLL5_BYPASS, );
+ clk_set_parent(clk1, clk);
#endif
return 0;
--
2.20.1
Re: [PATCH v2 05/19] videomodes: add helper function to convert from ctfb to display_timing
On 3/23/20 4:36 PM, Simon Glass wrote:
Hi Giulio,
On Sun, 22 Mar 2020 at 16:44, Giulio Benetti
wrote:
This function converts from "struct ctf_res_modes" to
"struct display_timing".
Signed-off-by: Giulio Benetti
---
drivers/video/videomodes.c | 29 +
drivers/video/videomodes.h | 3 +++
2 files changed, 32 insertions(+)
diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c
index ac25b45f81..89003eea72 100644
--- a/drivers/video/videomodes.c
+++ b/drivers/video/videomodes.c
@@ -444,3 +444,32 @@ int video_edid_dtd_to_ctfb_res_modes(struct
edid_detailed_timing *t,
return 0;
}
+
+void video_ctfb_mode_to_display_timing(const struct ctfb_res_modes *mode,
+ struct display_timing *timing)
+{
+ timing->pixelclock.typ = mode->pixclock_khz * 1000;
+
+ timing->hactive.typ = mode->xres;
+ timing->hfront_porch.typ = mode->right_margin;
+ timing->hback_porch.typ = mode->left_margin;
+ timing->hsync_len.typ = mode->hsync_len;
+
+ timing->vactive.typ = mode->yres;
+ timing->vfront_porch.typ = mode->lower_margin;
+ timing->vback_porch.typ = mode->upper_margin;
+ timing->vsync_len.typ = mode->vsync_len;
+
+ timing->flags = 0;
+
+ if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
+ timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
+ else
+ timing->flags |= DISPLAY_FLAGS_HSYNC_LOW;
+ if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
+ timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
+ else
+ timing->flags |= DISPLAY_FLAGS_VSYNC_LOW;
+ if (mode->vmode == FB_VMODE_INTERLACED)
+ timing->flags |= DISPLAY_FLAGS_INTERLACED;
+}
diff --git a/drivers/video/videomodes.h b/drivers/video/videomodes.h
index 29a3db4ae3..6713f96d19 100644
--- a/drivers/video/videomodes.h
+++ b/drivers/video/videomodes.h
@@ -92,3 +92,6 @@ int video_get_option_int(const char *options, const char
*name, int def);
int video_edid_dtd_to_ctfb_res_modes(struct edid_detailed_timing *t,
struct ctfb_res_modes *mode);
+
+void video_ctfb_mode_to_display_timing(const struct ctfb_res_modes *mode,
+ struct display_timing *timing);
Please add a comment for this.
Ok
What is ctfb?
If I'm not wrong it should stand for "Cathode Tube Frame Buffer" and it
describes a Display(old Cathode Tube) Frame Buffer. This is at least
what I've deducted :-)
Thanks for reviewing and
Best regards
--
Giulio Benetti
Benetti Engineering sas
Regards,
Simon
Re: [PATCH v2 05/19] videomodes: add helper function to convert from ctfb to display_timing
On 3/23/20 7:42 PM, Simon Glass wrote:
Hi Giulio,
On Mon, 23 Mar 2020 at 10:00, Giulio Benetti
wrote:
On 3/23/20 4:36 PM, Simon Glass wrote:
Hi Giulio,
On Sun, 22 Mar 2020 at 16:44, Giulio Benetti
wrote:
This function converts from "struct ctf_res_modes" to
"struct display_timing".
Signed-off-by: Giulio Benetti
---
drivers/video/videomodes.c | 29 +
drivers/video/videomodes.h | 3 +++
2 files changed, 32 insertions(+)
diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c
index ac25b45f81..89003eea72 100644
--- a/drivers/video/videomodes.c
+++ b/drivers/video/videomodes.c
@@ -444,3 +444,32 @@ int video_edid_dtd_to_ctfb_res_modes(struct
edid_detailed_timing *t,
return 0;
}
+
+void video_ctfb_mode_to_display_timing(const struct ctfb_res_modes *mode,
+ struct display_timing *timing)
+{
+ timing->pixelclock.typ = mode->pixclock_khz * 1000;
+
+ timing->hactive.typ = mode->xres;
+ timing->hfront_porch.typ = mode->right_margin;
+ timing->hback_porch.typ = mode->left_margin;
+ timing->hsync_len.typ = mode->hsync_len;
+
+ timing->vactive.typ = mode->yres;
+ timing->vfront_porch.typ = mode->lower_margin;
+ timing->vback_porch.typ = mode->upper_margin;
+ timing->vsync_len.typ = mode->vsync_len;
+
+ timing->flags = 0;
+
+ if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
+ timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
+ else
+ timing->flags |= DISPLAY_FLAGS_HSYNC_LOW;
+ if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
+ timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
+ else
+ timing->flags |= DISPLAY_FLAGS_VSYNC_LOW;
+ if (mode->vmode == FB_VMODE_INTERLACED)
+ timing->flags |= DISPLAY_FLAGS_INTERLACED;
+}
diff --git a/drivers/video/videomodes.h b/drivers/video/videomodes.h
index 29a3db4ae3..6713f96d19 100644
--- a/drivers/video/videomodes.h
+++ b/drivers/video/videomodes.h
@@ -92,3 +92,6 @@ int video_get_option_int(const char *options, const char
*name, int def);
int video_edid_dtd_to_ctfb_res_modes(struct edid_detailed_timing *t,
struct ctfb_res_modes *mode);
+
+void video_ctfb_mode_to_display_timing(const struct ctfb_res_modes *mode,
+ struct display_timing *timing);
Please add a comment for this.
Ok
What is ctfb?
If I'm not wrong it should stand for "Cathode Tube Frame Buffer" and it
describes a Display(old Cathode Tube) Frame Buffer. This is at least
what I've deducted :-)
OK certainly plausible! Then you should add it to your comment somewhere.
Perfect, done while describing what functions does in Doxygen style!
Best regards
--
Giulio Benetti
Benetti Engineering sas
Regards,
Simon
Re: i.MX RT1050 toolchain
Hi Andy, On 10/16/20 9:05 AM, Andy Pont wrote: Hi Giulio, Is there a preferred / recommended toolchain for building U-Boot for the i.MX RT10xx platforms or should any recent ARM cross compiler work? It should compile fine with any recent ARM cross-compiler. Please let me know if it builds correctly Best regards -- Giulio Benetti Benetti Engineering sas
Re: i.MX RT1050 toolchain
On 10/17/20 2:53 PM, Andy Pont wrote: Giulio wrote... Is there a preferred / recommended toolchain for building U-Boot for the i.MX RT10xx platforms or should any recent ARM cross compiler work? It should compile fine with any recent ARM cross-compiler. Please let me know if it builds correctly I used the arm-linux-gnueabi-gcc v10.1.0 compiler available from www.kernel.org and it has built fine. Now I have a working toolchain I can start adding the new board. Perfect, I suggest you to test it on a EVK before than going with your custom board if you can, and after port your board, that should make it easier. Kind regards -- Giulio Benetti Benetti Engineering sas
Re: i.MX RT1050 toolchain
> Il giorno 18 ott 2020, alle ore 14:53, Andy Pont > ha scritto: > > Giulio wrote… > >> Perfect, I suggest you to test it on a EVK before than going with your >> custom board if you can, and after port your board, that should make it >> easier. > I certainly will do! One supplementary question… what did you use U-Boot to > boot? I’m looking to get uClinux running on it. As a starting point I have > only been able to find the BSP from EmCraft[1] but at kernel version 4.5 it > is quite old. I’ve started to port i.MXRT to Linux too but for the moment I’ve paused it. You can find it here https://github.com/giuliobenetti/linux-imxrt All patches are WIP. Honestly I’ve stopped it since I’ve seen no much interest on it. My idea was to create a complete BSP in Buildroot with UBoot, Linux and a basic File System. If you interested and want also to contribute to I can restart so develop in spare time. Let me know Best regards Giulio
[RFC] VIDEO_MXS in Kconfig and SUNXI video DM
Hello Anatolij, All, I was wondering if there is any drawback in adding VIDEO_MXS in drivers/video/Kconfig This is to allow removing CONFIG_VIDEO_MXS from every include/configs/xxx.h and adding to specific _defconfig and to make it more clear when you enable or disable it through 'make menuconfig'. I can do that with a patchset if it makes sense for you. Same would go for: CONFIG_VIDEO_LOGO CONFIG_VIDEO_BMP_LOGO with other 2 patchsets more. This idea came into my mind when looking at imxrt1050-evk board I maintain. What do you think? Also I want to add DM support for sunxi video as I've done for mxsfb.c, if I follow the same #ifndef CONFIG_VIDEO_DM '''legacy driver init #else '''new u-boot DM driver #endif it should be ok, right? This would allow me to specify lcd timings in DTS instead of CONFIG_VIDEO_LCD_MODE, so I could avoid having many uboot binaries as many lcds my board supports. What about that? Best regards -- Giulio Benetti Benetti Engineering sas
Re: [PATCH] sunxi: display: introduce "sunxi-video" environment variable
On 1/11/21 10:48 AM, Maxime Ripard wrote: Hi, On Mon, Jan 11, 2021 at 10:13:32AM +0100, Giulio Benetti wrote: From: Giulio Benetti At the moment you can specify lcd_mode only through hardcoded CONFIG_VIDEO_LCD_MODE but this way, if you have a board with multiple lcds compatible, you have to rebuild u-boot for every single lcd, so let's add sunxi-video environment variable to give the possibility to specify lcd settings at runtime. It's mandatory to "saveenv" after setting sunxi-video variable and then "reset" since sunxi_display driver apply those settings only on startup. Signed-off-by: Giulio Benetti What's different from the video= parameter that already exists (and should work like you suggest)? My bad, don't even know why I haven't noticed it. So please drop this patch. Thank you Best regards -- Giulio Benetti Benetti Engineering sas
[PATCH] sunxi: display: introduce "sunxi-video" environment variable
From: Giulio Benetti
At the moment you can specify lcd_mode only through hardcoded
CONFIG_VIDEO_LCD_MODE but this way, if you have a board with multiple lcds
compatible, you have to rebuild u-boot for every single lcd, so let's add
sunxi-video environment variable to give the possibility to specify lcd
settings at runtime. It's mandatory to "saveenv" after setting sunxi-video
variable and then "reset" since sunxi_display driver apply those settings
only on startup.
Signed-off-by: Giulio Benetti
---
drivers/video/sunxi/sunxi_display.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/video/sunxi/sunxi_display.c
b/drivers/video/sunxi/sunxi_display.c
index f52aba4d21..99bafc544a 100644
--- a/drivers/video/sunxi/sunxi_display.c
+++ b/drivers/video/sunxi/sunxi_display.c
@@ -1017,6 +1017,10 @@ static bool sunxi_has_lcd(void)
{
char *lcd_mode = CONFIG_VIDEO_LCD_MODE;
+ lcd_mode = env_get("sunxi-video");
+ if(lcd_mode == NULL)
+ lcd_mode = CONFIG_VIDEO_LCD_MODE;
+
return lcd_mode[0] != 0;
}
@@ -1065,7 +1069,11 @@ void *video_hw_init(void)
int i, overscan_offset, overscan_x, overscan_y;
unsigned int fb_dma_addr;
char mon[16];
- char *lcd_mode = CONFIG_VIDEO_LCD_MODE;
+ char *lcd_mode;
+
+ lcd_mode = env_get("sunxi-video");
+ if(lcd_mode == NULL)
+ lcd_mode = CONFIG_VIDEO_LCD_MODE;
memset(_display, 0, sizeof(struct sunxi_display));
--
2.25.1
Re: [PATCH 0/5] Fix i.MXRT1050 hang on lcdif init and improve DT for mxsfb
Hi Stefano, On 5/2/21 1:44 AM, Giulio Benetti wrote: On 4/13/21 1:05 AM, Giulio Benetti wrote: On 4/13/21 1:03 AM, Giulio Benetti wrote: This patchset fixes u-boot hang on i.MXRT1050 while setting lcdif in mxsfb driver. There are 2 gates to be enabled to initialize mxsfb so let's introduce the missing gate as a clock and rename "per" clock to "pix" clock since in the other .dts files using *-lcdif "pix" is used. This patchset add also "disp_axi" clock enabling in mxsfb that should make able to every i.MX SoC with lcdif using DT. I didn't test it other than i.MXRT1050 since I don't have the boards. If someone can test it it would be great. Note that i.MX23/28 should fail using DT instead because they don't specify any clock-names in their dts. I've forgotten to specify that this patchset depends on this patchset: https://patchwork.ozlabs.org/project/uboot/list/?series=237909 This ^^^ series is superseeded by v2: https://patchwork.ozlabs.org/project/uboot/list/?series=241701 Current patchset is not superseeded, only the one which depends to is superseeded by v2. Do you prefer me to send a unique patchset with all patches of both patchsets? Kind regards -- Giulio Benetti Benetti Engineering sas
[PATCH v3 00/22] Fix i.MXRT1020/50
This patchset adds imx-gpt-timer driver that is supported by i.MXRT and also a lot of other i.MX* SoCs. This driver is needed for i.MXRT SoC family that is lacking at the moment the timer at all and that makes u-boot to fail running on i.MXRT. There are also some fixes in imxrt10*0-evk.dts and other minor fixed and improvements and specifically on imxrt1050 has been fixed lcdif init hang. --- V1->V2: * fixed 32 to 64 bit conversion on timer as suggested by Sean Anderson V2->V3: * merge with patchset with https://patchwork.ozlabs.org/project/uboot/list/?series=238842=* that fixes lcdif init hang * improve some commit log --- Giulio Benetti (22): arm: imxrt: soc: make mpu regions generic timer: imx-gpt: Add timer support for i.MX SoCs family ARM: dts: imxrt1020: add node label to osc ARM: dts: imxrt1020: add gpt1 node ARM: dts: imxrt1020-evk: enable gpt1 timer ARM: dts: imxrt1020-evk: set gpt1 as tick-timer for u-boot ARM: dts: imxrt1020-evk-u-boot: make gpt1 present for SPL ARM: dts: imxrt1020-evk: add device_type = "memory" to memory node configs: imxrt1020-evk: enable imx gpt timer as tick-timer ARM: dts: imxrt1050: add node label to osc ARM: dts: imxrt1050: add gpt1 node ARM: dts: imxrt1050-evk: enable gpt1 timer ARM: dts: imxrt1050-evk: set gpt1 as tick-timer for u-boot ARM: dts: imxrt1050-evk-u-boot: make gpt1 present for SPL ARM: dts: imxrt1050-evk: add device_type = "memory" to memory node configs: imxrt1050-evk: enable imx gpt timer as tick-timer video: mxsfb: add enabling of "axi" clock other than "per" clock video: mxsfb: add enabling of "disp_axi" clock clk: imx: clk-imxrt1050: introduce LCDIF_PIX and rename LCDIF to LCDIF_APB ARM: dts: imxrt1050: move lcdif assigned clock to dtsi ARM: dts: imxrt1050: set lcdif clocks according to mxsfb driver ARM: dts: imxrt1050-evk: remove u-boot,dm-spl arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 4 + arch/arm/dts/imxrt1020-evk.dts | 6 + arch/arm/dts/imxrt1020.dtsi | 10 +- arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 4 + arch/arm/dts/imxrt1050-evk.dts | 10 +- arch/arm/dts/imxrt1050.dtsi | 17 +- arch/arm/mach-imx/imxrt/soc.c | 6 +- configs/imxrt1020-evk_defconfig | 1 + configs/imxrt1050-evk_defconfig | 1 + drivers/clk/imx/clk-imxrt1050.c | 6 +- drivers/timer/Kconfig | 7 + drivers/timer/Makefile | 1 + drivers/timer/imx-gpt-timer.c | 162 drivers/video/mxsfb.c | 36 - include/dt-bindings/clock/imxrt1050-clock.h | 5 +- 15 files changed, 254 insertions(+), 22 deletions(-) create mode 100644 drivers/timer/imx-gpt-timer.c -- 2.25.1
[PATCH v3 02/22] timer: imx-gpt: Add timer support for i.MX SoCs family
This timer driver uses GPT Timer (General Purpose Timer) available on
a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator
as well as peripheral clock.
Signed-off-by: Giulio Benetti
[Giulio: added the driver's stub and handled peripheral clock prescaler
setting making driver to work correctly]
Signed-off-by: Jesse Taube
[Jesse: added init, setting prescaler for 24Mhz support and enabling
timer]
---
drivers/timer/Kconfig | 7 ++
drivers/timer/Makefile| 1 +
drivers/timer/imx-gpt-timer.c | 162 ++
3 files changed, 170 insertions(+)
create mode 100644 drivers/timer/imx-gpt-timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 80743a2551..ee81dfa776 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -227,4 +227,11 @@ config MCHP_PIT64B_TIMER
Select this to enable support for Microchip 64-bit periodic
interval timer.
+config IMX_GPT_TIMER
+ bool "NXP i.MX GPT timer support"
+ depends on TIMER
+ help
+ Select this to enable support for the timer found on
+ NXP i.MX devices.
+
endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index eb5c48cc6c..e214ba7268 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
obj-$(CONFIG_X86_TSC_TIMER)+= tsc_timer.o
obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
obj-$(CONFIG_MCHP_PIT64B_TIMER)+= mchp-pit64b-timer.o
+obj-$(CONFIG_IMX_GPT_TIMER)+= imx-gpt-timer.o
diff --git a/drivers/timer/imx-gpt-timer.c b/drivers/timer/imx-gpt-timer.c
new file mode 100644
index 00..72be297754
--- /dev/null
+++ b/drivers/timer/imx-gpt-timer.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021
+ * Author(s): Giulio Benetti
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define GPT_CR_EN BIT(0)
+#define GPT_CR_FRR BIT(9)
+#define GPT_CR_EN_24M BIT(10)
+#define GPT_CR_SWR BIT(15)
+
+#define GPT_PR_PRESCALER24M_MASK 0xF000
+#define GPT_PR_PRESCALER24M_SHIFT 12
+#define GPT_PR_PRESCALER24M_MAX(GPT_PR_PRESCALER24M_MASK >>
GPT_PR_PRESCALER24M_SHIFT)
+#define GPT_PR_PRESCALER_MASK 0x0FFF
+#define GPT_PR_PRESCALER_SHIFT 0
+#define GPT_PR_PRESCALER_MAX (GPT_PR_PRESCALER_MASK >>
GPT_PR_PRESCALER_SHIFT)
+
+#define GPT_CLKSRC_IPG_CLK (1 << 6)
+#define GPT_CLKSRC_IPG_CLK_24M (5 << 6)
+
+/* If CONFIG_SYS_HZ_CLOCK not specified et's default to 3Mhz */
+#ifndef CONFIG_SYS_HZ_CLOCK
+#define CONFIG_SYS_HZ_CLOCK300
+#endif
+
+struct imx_gpt_timer_regs {
+ u32 cr;
+ u32 pr;
+ u32 sr;
+ u32 ir;
+ u32 ocr1;
+ u32 ocr2;
+ u32 ocr3;
+ u32 icr1;
+ u32 icr2;
+ u32 cnt;
+};
+
+struct imx_gpt_timer_priv {
+ struct imx_gpt_timer_regs *base;
+};
+
+static u64 imx_gpt_timer_get_count(struct udevice *dev)
+{
+ struct imx_gpt_timer_priv *priv = dev_get_priv(dev);
+ struct imx_gpt_timer_regs *regs = priv->base;
+
+ return timer_conv_64(readl(>cnt));
+}
+
+static int imx_gpt_setup(struct imx_gpt_timer_regs *regs, u32 rate)
+{
+ u32 prescaler = (rate / CONFIG_SYS_HZ_CLOCK) - 1;
+
+ /* Reset the timer */
+ setbits_le32(>cr, GPT_CR_SWR);
+
+ /* Wait for timer to finish reset */
+ while (readl(>cr) & GPT_CR_SWR)
+ ;
+
+ if (rate == 2400UL) {
+ /* Set timer frequency if using 24M clock source */
+ if (prescaler > GPT_PR_PRESCALER24M_MAX)
+ return -EINVAL;
+
+ /* Set 24M prescaler */
+ writel((prescaler << GPT_PR_PRESCALER24M_SHIFT), >pr);
+ /* Set Oscillator as clock source, enable 24M input and set gpt
+* in free-running mode
+*/
+ writel(GPT_CLKSRC_IPG_CLK_24M | GPT_CR_EN_24M | GPT_CR_FRR,
>cr);
+ } else {
+ if (prescaler > GPT_PR_PRESCALER_MAX)
+ return -EINVAL;
+
+ /* Set prescaler */
+ writel((prescaler << GPT_PR_PRESCALER_SHIFT), >pr);
+ /* Set Peripheral as clock source and set gpt in free-running
+* mode
+*/
+ writel(GPT_CLKSRC_IPG_CLK | GPT_CR_FRR, >cr);
+ }
+
+ /* Start timer */
+ setbits_le32(>cr, GPT_CR_EN);
+
+ return 0;
+}
+
+static int imx_gpt_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct imx_gpt_timer_priv *priv = dev_get_priv(dev);
+ struct imx_gpt_timer_regs *regs;
+ struct clk clk;
+ fdt_add
[PATCH v3 06/22] ARM: dts: imxrt1020-evk: set gpt1 as tick-timer for u-boot
Let's set gpt1 as u-boot timer.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1020-evk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
index a471ff3838..b527206fcf 100644
--- a/arch/arm/dts/imxrt1020-evk.dts
+++ b/arch/arm/dts/imxrt1020-evk.dts
@@ -16,6 +16,7 @@
chosen {
bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
+ tick-timer =
};
memory {
--
2.25.1
[PATCH v3 04/22] ARM: dts: imxrt1020: add gpt1 node
Add gpt1 node for using it as timer.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1020.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi
index 0a3a3b451a..cab608c644 100644
--- a/arch/arm/dts/imxrt1020.dtsi
+++ b/arch/arm/dts/imxrt1020.dtsi
@@ -129,5 +129,13 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ gpt1: gpt1@401ec000 {
+ compatible = "fsl,imxrt-gpt";
+ reg = <0x401ec000 0x4000>;
+ interrupts = <100>;
+ clocks = <>;
+ status = "disabled";
+ };
};
};
--
2.25.1
[PATCH v3 05/22] ARM: dts: imxrt1020-evk: enable gpt1 timer
Enable gpt1 timer.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1020-evk.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
index ece13601bd..a471ff3838 100644
--- a/arch/arm/dts/imxrt1020-evk.dts
+++ b/arch/arm/dts/imxrt1020-evk.dts
@@ -186,6 +186,10 @@
};
};
+ {
+ status = "okay";
+};
+
{
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <_usdhc0>;
--
2.25.1
[PATCH v3 08/22] ARM: dts: imxrt1020-evk: add device_type = "memory" to memory node
Now device_type = "memory" is mandatory to allow u-boot to read memory
node, so let's add it to memory node.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1020-evk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
index b527206fcf..2da79e5c20 100644
--- a/arch/arm/dts/imxrt1020-evk.dts
+++ b/arch/arm/dts/imxrt1020-evk.dts
@@ -20,6 +20,7 @@
};
memory {
+ device_type = "memory";
reg = <0x8000 0x200>;
};
};
--
2.25.1
[PATCH v3 12/22] ARM: dts: imxrt1050-evk: enable gpt1 timer
Enable gpt1 timer.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050-evk.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index b5e781275e..e592330332 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -215,6 +215,10 @@
};
};
+ {
+ status = "okay";
+};
+
{
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <_usdhc0>;
--
2.25.1
[PATCH v3 09/22] configs: imxrt1020-evk: enable imx gpt timer as tick-timer
Let's enable imx-gpt-timer in imx1020-evk defconfig. Signed-off-by: Giulio Benetti --- configs/imxrt1020-evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig index ad408ebef8..f0b05b7165 100644 --- a/configs/imxrt1020-evk_defconfig +++ b/configs/imxrt1020-evk_defconfig @@ -61,6 +61,7 @@ CONFIG_IMXRT_SDRAM=y CONFIG_FSL_LPUART=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y +CONFIG_IMX_GPT_TIMER=y CONFIG_SHA1=y CONFIG_SHA256=y CONFIG_HEXDUMP=y -- 2.25.1
[PATCH v3 03/22] ARM: dts: imxrt1020: add node label to osc
Let's add node label to osc to be used as clock source for other nodes.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1020.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi
index 97f3cec9f3..0a3a3b451a 100644
--- a/arch/arm/dts/imxrt1020.dtsi
+++ b/arch/arm/dts/imxrt1020.dtsi
@@ -36,7 +36,7 @@
clock-frequency = <0>;
};
- osc {
+ osc: osc {
u-boot,dm-spl;
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
--
2.25.1
[PATCH v3 10/22] ARM: dts: imxrt1050: add node label to osc
Let's add node label to osc to be used as clock source for other nodes.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index a9281001e5..b7cc3fbc2a 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -28,7 +28,7 @@
clocks {
u-boot,dm-spl;
- osc {
+ osc: osc {
u-boot,dm-spl;
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
--
2.25.1
[PATCH v3 17/22] video: mxsfb: add enabling of "axi" clock other than "per" clock
On some SoC mxsfb needs more than one clock gate(actual "per" clock). So
let's introduce "axi" clock that can be provided but it's not mandatory.
This is inspired from linux mxsfb driver. Also let's rename "per" clock to
"pix" clock for compatibility with already existing .dts lcdif nodes
implementation.
Signed-off-by: Giulio Benetti
---
drivers/video/mxsfb.c | 25 ++---
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index e1fd36a62d..147bd668fe 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -67,26 +67,37 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
uint32_t vdctrl0;
#if CONFIG_IS_ENABLED(CLK)
- struct clk per_clk;
+ struct clk clk;
int ret;
- ret = clk_get_by_name(dev, "per", _clk);
+ ret = clk_get_by_name(dev, "pix", );
if (ret) {
- dev_err(dev, "Failed to get mxs clk: %d\n", ret);
+ dev_err(dev, "Failed to get mxs pix clk: %d\n", ret);
return;
}
- ret = clk_set_rate(_clk, timings->pixelclock.typ);
+ ret = clk_set_rate(, timings->pixelclock.typ);
if (ret < 0) {
- dev_err(dev, "Failed to set mxs clk: %d\n", ret);
+ dev_err(dev, "Failed to set mxs pix clk: %d\n", ret);
return;
}
- ret = clk_enable(_clk);
+ ret = clk_enable();
if (ret < 0) {
- dev_err(dev, "Failed to enable mxs clk: %d\n", ret);
+ dev_err(dev, "Failed to enable mxs pix clk: %d\n", ret);
return;
}
+
+ ret = clk_get_by_name(dev, "axi", );
+ if (!ret) {
+ debug("%s: Failed to get mxs axi clk: %d\n", __func__, ret);
+ } else {
+ ret = clk_enable();
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable mxs axi clk: %d\n", ret);
+ return;
+ }
+ }
#else
/* Kick in the LCDIF clock */
mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
--
2.25.1
[PATCH v3 16/22] configs: imxrt1050-evk: enable imx gpt timer as tick-timer
Let's enable imx-gpt-timer in imx1050-evk defconfig. Signed-off-by: Giulio Benetti --- configs/imxrt1050-evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index d03572e7db..9c8bdb07dc 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -64,6 +64,7 @@ CONFIG_IMXRT_SDRAM=y CONFIG_FSL_LPUART=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y +CONFIG_IMX_GPT_TIMER=y CONFIG_DM_VIDEO=y CONFIG_BACKLIGHT_GPIO=y CONFIG_SYS_WHITE_ON_BLACK=y -- 2.25.1
[PATCH v3 01/22] arm: imxrt: soc: make mpu regions generic
This mpu handling works for every i.MXRT SoC that we have, so let's
generalize imxrt1050_region_config to imxrt_region_config.
Signed-off-by: Giulio Benetti
---
arch/arm/mach-imx/imxrt/soc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c
index 8e7d15160d..c533f3554a 100644
--- a/arch/arm/mach-imx/imxrt/soc.c
+++ b/arch/arm/mach-imx/imxrt/soc.c
@@ -14,7 +14,7 @@ int arch_cpu_init(void)
{
int i;
- struct mpu_region_config imxrt1050_region_config[] = {
+ struct mpu_region_config imxrt_region_config[] = {
{ 0x, REGION_0, XN_DIS, PRIV_RW_USR_RW,
STRONG_ORDER, REGION_4GB },
{ PHYS_SDRAM, REGION_1, XN_DIS, PRIV_RW_USR_RW,
@@ -29,8 +29,8 @@ int arch_cpu_init(void)
* the whole 4GB address space.
*/
disable_mpu();
- for (i = 0; i < ARRAY_SIZE(imxrt1050_region_config); i++)
- mpu_config(_region_config[i]);
+ for (i = 0; i < ARRAY_SIZE(imxrt_region_config); i++)
+ mpu_config(_region_config[i]);
enable_mpu();
return 0;
--
2.25.1
Re: [PATCH v3 18/22] video: mxsfb: add enabling of "disp_axi" clock
Sorry for this patch sent twice. My e-mail provider doesn't let me send
more than 18 e-mail at a time, so I need to send it in 2 times and I've
left this.
Best regards
--
Giulio Benetti
Benetti Engineering sas
On 5/13/21 12:19 PM, Giulio Benetti wrote:
Some SoC needs "disp_axi" clock to be enabled, so let's try to retrieve it
and enabling. If it fails it gives only a debug(), but this clock as well
as "axi" clock is not mandatory.
Signed-off-by: Giulio Benetti
---
drivers/video/mxsfb.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 147bd668fe..523d8a8d98 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -98,6 +98,17 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
return;
}
}
+
+ ret = clk_get_by_name(dev, "disp_axi", );
+ if (!ret) {
+ debug("%s: Failed to get mxs disp_axi clk: %d\n", __func__,
ret);
+ } else {
+ ret = clk_enable();
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable mxs disp_axi clk: %d\n",
ret);
+ return;
+ }
+ }
#else
/* Kick in the LCDIF clock */
mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
[PATCH v3 22/22] ARM: dts: imxrt1050-evk: remove u-boot,dm-spl
We don't need lcdif to be enable in SPL, so let's remove u-boot,dm-spl.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050-evk.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index dc66fc9c37..81db1a446d 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -189,7 +189,6 @@
};
pinctrl_lcdif: lcdifgrp {
- u-boot,dm-spl;
fsl,pins = <
MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK
0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE
0x1b0b1
--
2.25.1
[PATCH v3 20/22] ARM: dts: imxrt1050: move lcdif assigned clock to dtsi
Since we assume pll5 is the default lcdif clock source let's move
assigned-clocks(-parents) properties to .dtsi file.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050-evk.dts | 3 ---
arch/arm/dts/imxrt1050.dtsi| 2 ++
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index 2052d4eb4e..dc66fc9c37 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -238,9 +238,6 @@
display = <>;
status = "okay";
- assigned-clocks = < IMXRT1050_CLK_LCDIF_SEL>;
- assigned-clock-parents = < IMXRT1050_CLK_PLL5_VIDEO>;
-
display0: display0 {
bits-per-pixel = <16>;
bus-width = <16>;
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index 6f9da3fe8a..eb5e09e971 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -152,6 +152,8 @@
interrupts = ;
clocks = < IMXRT1050_CLK_LCDIF>;
clock-names = "per";
+ assigned-clocks = < IMXRT1050_CLK_LCDIF_SEL>;
+ assigned-clock-parents = <
IMXRT1050_CLK_PLL5_VIDEO>;
status = "disabled";
};
--
2.25.1
[PATCH v3 11/22] ARM: dts: imxrt1050: add gpt1 node
Add gpt1 node for using it as timer.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index b7cc3fbc2a..6f9da3fe8a 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -154,5 +154,13 @@
clock-names = "per";
status = "disabled";
};
+
+ gpt1: gpt1@401ec000 {
+ compatible = "fsl,imxrt-gpt";
+ reg = <0x401ec000 0x4000>;
+ interrupts = <100>;
+ clocks = <>;
+ status = "disabled";
+ };
};
};
--
2.25.1
[PATCH v3 19/22] clk: imx: clk-imxrt1050: introduce LCDIF_PIX and rename LCDIF to LCDIF_APB
Lcd peripheral needs 2 different gates to be enable to work, so let's
introduce the missing one(LCDIF_PIX) and rename the existing one
(LCDIF_APB).
Signed-off-by: Giulio Benetti
---
drivers/clk/imx/clk-imxrt1050.c | 6 --
include/dt-bindings/clock/imxrt1050-clock.h | 5 +++--
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index 594093ee5f..eb6847f865 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -255,8 +255,10 @@ static int imxrt1050_clk_probe(struct udevice *dev)
imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
clk_dm(IMXRT1050_CLK_SEMC,
imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
- clk_dm(IMXRT1050_CLK_LCDIF,
- imx_clk_gate2("lcdif", "lcdif_podf", base + 0x74, 10));
+ clk_dm(IMXRT1050_CLK_LCDIF_APB,
+ imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
+ clk_dm(IMXRT1050_CLK_LCDIF_PIX,
+ imx_clk_gate2("lcdif_pix", "lcdif", base + 0x74, 10));
struct clk *clk, *clk1;
diff --git a/include/dt-bindings/clock/imxrt1050-clock.h
b/include/dt-bindings/clock/imxrt1050-clock.h
index c174f90c1a..09b65e5df2 100644
--- a/include/dt-bindings/clock/imxrt1050-clock.h
+++ b/include/dt-bindings/clock/imxrt1050-clock.h
@@ -52,7 +52,7 @@
#define IMXRT1050_CLK_USDHC2 43
#define IMXRT1050_CLK_LPUART1 44
#define IMXRT1050_CLK_SEMC 45
-#define IMXRT1050_CLK_LCDIF46
+#define IMXRT1050_CLK_LCDIF_APB46
#define IMXRT1050_CLK_PLL1_ARM 47
#define IMXRT1050_CLK_PLL2_SYS 48
#define IMXRT1050_CLK_PLL3_USB_OTG 49
@@ -60,6 +60,7 @@
#define IMXRT1050_CLK_PLL5_VIDEO 51
#define IMXRT1050_CLK_PLL6_ENET52
#define IMXRT1050_CLK_PLL7_USB_HOST53
-#define IMXRT1050_CLK_END 54
+#define IMXRT1050_CLK_LCDIF_PIX54
+#define IMXRT1050_CLK_END 55
#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */
--
2.25.1
[PATCH v3 21/22] ARM: dts: imxrt1050: set lcdif clocks according to mxsfb driver
Lcdif needs both "pix" and "axi" clocks to be enabled so let's add them to lcdif node. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1050.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi index eb5e09e971..ec1eb88e45 100644 --- a/arch/arm/dts/imxrt1050.dtsi +++ b/arch/arm/dts/imxrt1050.dtsi @@ -150,8 +150,9 @@ compatible = "fsl,imxrt-lcdif"; reg = <0x402b8000 0x4000>; interrupts = ; - clocks = < IMXRT1050_CLK_LCDIF>; - clock-names = "per"; + clocks = < IMXRT1050_CLK_LCDIF_PIX>, +< IMXRT1050_CLK_LCDIF_APB>; + clock-names = "pix", "axi"; assigned-clocks = < IMXRT1050_CLK_LCDIF_SEL>; assigned-clock-parents = < IMXRT1050_CLK_PLL5_VIDEO>; status = "disabled"; -- 2.25.1
[PATCH v3 18/22] video: mxsfb: add enabling of "disp_axi" clock
Some SoC needs "disp_axi" clock to be enabled, so let's try to retrieve it
and enabling. If it fails it gives only a debug(), but this clock as well
as "axi" clock is not mandatory.
Signed-off-by: Giulio Benetti
---
drivers/video/mxsfb.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 147bd668fe..523d8a8d98 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -98,6 +98,17 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
return;
}
}
+
+ ret = clk_get_by_name(dev, "disp_axi", );
+ if (!ret) {
+ debug("%s: Failed to get mxs disp_axi clk: %d\n", __func__,
ret);
+ } else {
+ ret = clk_enable();
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable mxs disp_axi clk: %d\n",
ret);
+ return;
+ }
+ }
#else
/* Kick in the LCDIF clock */
mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
--
2.25.1
[PATCH v3 07/22] ARM: dts: imxrt1020-evk-u-boot: make gpt1 present for SPL
Timer needs to be already enabled in spl, so let's add its node to spl dtb.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
index d32c98de9c..34d19e06c5 100644
--- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
@@ -10,6 +10,10 @@
};
};
+ {
+ u-boot,dm-spl;
+};
+
{ /* console */
u-boot,dm-spl;
};
--
2.25.1
[PATCH v3 14/22] ARM: dts: imxrt1050-evk-u-boot: make gpt1 present for SPL
Timer needs to be already enabled in spl, so let's add its node to spl dtb.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index fb4f7f6f9d..a4b50f0bb2 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -10,6 +10,10 @@
};
};
+ {
+ u-boot,dm-spl;
+};
+
{ /* console */
u-boot,dm-spl;
};
--
2.25.1
[PATCH v3 18/22] video: mxsfb: add enabling of "disp_axi" clock
Some SoC needs "disp_axi" clock to be enabled, so let's try to retrieve it
and enabling. If it fails it gives only a debug(), but this clock as well
as "axi" clock is not mandatory.
Signed-off-by: Giulio Benetti
---
drivers/video/mxsfb.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 147bd668fe..523d8a8d98 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -98,6 +98,17 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
return;
}
}
+
+ ret = clk_get_by_name(dev, "disp_axi", );
+ if (!ret) {
+ debug("%s: Failed to get mxs disp_axi clk: %d\n", __func__,
ret);
+ } else {
+ ret = clk_enable();
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable mxs disp_axi clk: %d\n",
ret);
+ return;
+ }
+ }
#else
/* Kick in the LCDIF clock */
mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
--
2.25.1
