[U-Boot-Users] [PATCH] [UPDATED] POWERPC: Change 86xx platforms to use CONFIG_NR_CPUS
Currently, they use CONFIG_NUM_CPUS, which is different than 85xx for no good reason. Signed-off-by: Becky Bruce [EMAIL PROTECTED] --- Note: This is a resend; the first version accidentally changed the NR_CPUs on 8610 to 2. cpu/mpc86xx/start.S |4 ++-- include/configs/MPC8610HPCD.h |2 +- include/configs/MPC8641HPCN.h |2 +- include/configs/sbc8641d.h|2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 03f2128..83072bb 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -183,7 +183,7 @@ boot_warm: /* if this is a multi-core system we need to check which cpu * this is, if it is not cpu 0 send the cpu to the linux reset * vector */ -#if (CONFIG_NUM_CPUS 1) +#if (CONFIG_NR_CPUS 1) mfspr r0, MSSCR0 andi. r0, r0, 0x0020 rlwinm r0,r0,27,31,31 @@ -979,7 +979,7 @@ unlock_ram_in_cache: * Sri: Much of this initialization is not required. Linux * rewrites the bats, and the sprs and also enables the L1 cache. */ -#if (CONFIG_NUM_CPUS 1) +#if (CONFIG_NR_CPUS 1) .globl secondary_cpu_setup secondary_cpu_setup: /* Do only core setup on all cores except cpu0 */ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 1cba270..50a05f2 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -17,7 +17,7 @@ #define CONFIG_MPC86xx 1 /* MPC86xx */ #define CONFIG_MPC8610 1 /* MPC8610 specific */ #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ -#define CONFIG_NUM_CPUS1 /* Number of CPUs in the system */ +#define CONFIG_NR_CPUS 1 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index ccba409..78a9d11 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -36,7 +36,7 @@ #define CONFIG_MPC86xx 1 /* MPC86xx */ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ -#define CONFIG_NUM_CPUS2 /* Number of CPUs in the system */ +#define CONFIG_NR_CPUS 2 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ #ifdef RUN_DIAG diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 3cd9ff8..76712fd 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -40,7 +40,7 @@ #define CONFIG_MPC86xx 1 /* MPC86xx */ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_SBC8641D1 /* SBC8641D board specific */ -#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ +#define CONFIG_NR_CPUS 2 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ #ifdef RUN_DIAG -- 1.5.5.1 - This SF.Net email is sponsored by the Moblin Your Move Developer's challenge Build the coolest Linux based applications with Moblin SDK win great prizes Grand prize is a trip for two to an Open Source event anywhere in the world http://moblin-contest.org/redirect.php?banner_id=100url=/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH] POWERPC: Change 86xx platforms to use CONFIG_NR_CPUS
On Aug 5, 2008, at 7:03 AM, Andy Fleming wrote: On Mon, Aug 4, 2008 at 9:02 PM, Becky Bruce [EMAIL PROTECTED] wrote: Currently, they use CONFIG_NUM_CPUS, which is different than 85xx for no good reason. --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -17,7 +17,7 @@ #define CONFIG_MPC86xx 1 /* MPC86xx */ #define CONFIG_MPC8610 1 /* MPC8610 specific */ #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ -#define CONFIG_NUM_CPUS1 /* Number of CPUs in the system */ +#define CONFIG_NR_CPUS 2 /* Number of CPUs in the system */ Are you sure you wanted to change the number, too? I think this is used to support Cooperative Multi-processing? If we want to do this, we should probably document it in the commit message. Nope, that's a stupid cut and paste error :) Will respin, thank! -becky - This SF.Net email is sponsored by the Moblin Your Move Developer's challenge Build the coolest Linux based applications with Moblin SDK win great prizes Grand prize is a trip for two to an Open Source event anywhere in the world http://moblin-contest.org/redirect.php?banner_id=100url=/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH] POWERPC: Add synchronization to write_bat in lib_ppc/bat_rw.c
Perform sync/isync as required by the architecture.
Signed-off-by: Becky Bruce [EMAIL PROTECTED]
---
lib_ppc/bat_rw.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/lib_ppc/bat_rw.c b/lib_ppc/bat_rw.c
index 8546333..a40b377 100644
--- a/lib_ppc/bat_rw.c
+++ b/lib_ppc/bat_rw.c
@@ -25,9 +25,12 @@
#include common.h
#include asm/processor.h
#include asm/mmu.h
+#include asm/io.h
int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
{
+ sync();
+
switch (bat) {
case DBAT0:
mtspr (DBAT0L, lower);
@@ -99,6 +102,9 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned
long lower)
return (-1);
}
+ sync();
+ isync();
+
return (0);
}
--
1.5.5.1
-
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[U-Boot-Users] [PATCH] POWERPC 86xx: Move BAT setup code to C
This is needed because we will be possibly be locating
devices at physical addresses above 32bits, and the asm
preprocessing does not appear to deal with ULL constants
properly. We now call write_bat in lib_ppc/bat_rw.c.
Signed-off-by: Becky Bruce [EMAIL PROTECTED]
---
cpu/mpc86xx/cpu_init.c | 25 ++
cpu/mpc86xx/start.S| 119
2 files changed, 25 insertions(+), 119 deletions(-)
diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index 78ba1ea..1fda3fe 100644
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -26,8 +26,10 @@
* cpu_init.c - low level cpu init
*/
+#include config.h
#include common.h
#include mpc86xx.h
+#include asm/mmu.h
#include asm/fsl_law.h
DECLARE_GLOBAL_DATA_PTR;
@@ -121,3 +123,26 @@ int cpu_init_r(void)
{
return 0;
}
+
+/* Set up BAT registers */
+void setup_bats(void)
+{
+ write_bat(DBAT0, CFG_DBAT0U, CFG_DBAT0L);
+ write_bat(IBAT0, CFG_IBAT0U, CFG_IBAT0L);
+ write_bat(DBAT1, CFG_DBAT1U, CFG_DBAT1L);
+ write_bat(IBAT1, CFG_IBAT1U, CFG_IBAT1L);
+ write_bat(DBAT2, CFG_DBAT2U, CFG_DBAT2L);
+ write_bat(IBAT2, CFG_IBAT2U, CFG_IBAT2L);
+ write_bat(DBAT3, CFG_DBAT3U, CFG_DBAT3L);
+ write_bat(IBAT3, CFG_IBAT3U, CFG_IBAT3L);
+ write_bat(DBAT4, CFG_DBAT4U, CFG_DBAT4L);
+ write_bat(IBAT4, CFG_IBAT4U, CFG_IBAT4L);
+ write_bat(DBAT5, CFG_DBAT5U, CFG_DBAT5L);
+ write_bat(IBAT5, CFG_IBAT5U, CFG_IBAT5L);
+ write_bat(DBAT6, CFG_DBAT6U, CFG_DBAT6L);
+ write_bat(IBAT6, CFG_IBAT6U, CFG_IBAT6L);
+ write_bat(DBAT7, CFG_DBAT7U, CFG_DBAT7L);
+ write_bat(IBAT7, CFG_IBAT7U, CFG_IBAT7L);
+
+ return;
+}
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index c39dc46..03f2128 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -358,125 +358,6 @@ invalidate_bats:
sync
blr
-
- /* setup_bats - set them up to some initial state */
- /* Skip any BATS setup in early_bats */
- .globl setup_bats
-setup_bats:
-
- addis r0, r0, 0x
-
- /* IBAT 0 */
- addis r4, r0, [EMAIL PROTECTED]
- ori r4, r4, [EMAIL PROTECTED]
- addis r3, r0, [EMAIL PROTECTED]
- ori r3, r3, [EMAIL PROTECTED]
- mtspr IBAT0L, r4
- mtspr IBAT0U, r3
- isync
-
- /* DBAT 0 */
- addis r4, r0, [EMAIL PROTECTED]
- ori r4, r4, [EMAIL PROTECTED]
- addis r3, r0, [EMAIL PROTECTED]
- ori r3, r3, [EMAIL PROTECTED]
- mtspr DBAT0L, r4
- mtspr DBAT0U, r3
- isync
-
- /* IBAT 1 */
- addis r4, r0, [EMAIL PROTECTED]
- ori r4, r4, [EMAIL PROTECTED]
- addis r3, r0, [EMAIL PROTECTED]
- ori r3, r3, [EMAIL PROTECTED]
- mtspr IBAT1L, r4
- mtspr IBAT1U, r3
- isync
-
- /* DBAT 1 */
- addis r4, r0, [EMAIL PROTECTED]
- ori r4, r4, [EMAIL PROTECTED]
- addis r3, r0, [EMAIL PROTECTED]
- ori r3, r3, [EMAIL PROTECTED]
- mtspr DBAT1L, r4
- mtspr DBAT1U, r3
- isync
-
- /* IBAT 2 */
- addis r4, r0, [EMAIL PROTECTED]
- ori r4, r4, [EMAIL PROTECTED]
- addis r3, r0, [EMAIL PROTECTED]
- ori r3, r3, [EMAIL PROTECTED]
- mtspr IBAT2L, r4
- mtspr IBAT2U, r3
- isync
-
- /* DBAT 2 */
- addis r4, r0, [EMAIL PROTECTED]
- ori r4, r4, [EMAIL PROTECTED]
- addis r3, r0, [EMAIL PROTECTED]
- ori r3, r3, [EMAIL PROTECTED]
- mtspr DBAT2L, r4
- mtspr DBAT2U, r3
- isync
-
- /* IBAT 3 */
- addis r4, r0, [EMAIL PROTECTED]
- ori r4, r4, [EMAIL PROTECTED]
- addis r3, r0, [EMAIL PROTECTED]
- ori r3, r3, [EMAIL PROTECTED]
- mtspr IBAT3L, r4
- mtspr IBAT3U, r3
- isync
-
- /* DBAT 3 */
- addis r4, r0, [EMAIL PROTECTED]
- ori r4, r4, [EMAIL PROTECTED]
- addis r3, r0, [EMAIL PROTECTED]
- ori r3, r3, [EMAIL PROTECTED]
- mtspr DBAT3L, r4
- mtspr DBAT3U, r3
- isync
-
- /* IBAT 4 */
- addis r4, r0, [EMAIL PROTECTED]
- ori r4, r4, [EMAIL PROTECTED]
- addis r3, r0, [EMAIL PROTECTED]
- ori r3, r3, [EMAIL PROTECTED]
- mtspr IBAT4L, r4
- mtspr IBAT4U, r3
- isync
-
- /* DBAT 4 */
- addis r4, r0, [EMAIL PROTECTED]
- ori r4, r4, [EMAIL PROTECTED]
- addis r3, r0, [EMAIL PROTECTED]
- ori r3, r3, [EMAIL PROTECTED]
- mtspr DBAT4L, r4
- mtspr DBAT4U, r3
- isync
-
- /* IBAT 7 */
- addis r4, r0, [EMAIL PROTECTED]
- ori r4, r4, [EMAIL PROTECTED]
- addis r3, r0, [EMAIL PROTECTED]
- ori r3, r3, [EMAIL PROTECTED]
- mtspr IBAT7L, r4
- mtspr IBAT7U, r3
- isync
-
- /* DBAT 7
[U-Boot-Users] [PATCH] POWERPC: Change 86xx platforms to use CONFIG_NR_CPUS
Currently, they use CONFIG_NUM_CPUS, which is different than 85xx for no good reason. Signed-off-by: Becky Bruce [EMAIL PROTECTED] --- cpu/mpc86xx/start.S |4 ++-- include/configs/MPC8610HPCD.h |2 +- include/configs/MPC8641HPCN.h |2 +- include/configs/sbc8641d.h|2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 03f2128..83072bb 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -183,7 +183,7 @@ boot_warm: /* if this is a multi-core system we need to check which cpu * this is, if it is not cpu 0 send the cpu to the linux reset * vector */ -#if (CONFIG_NUM_CPUS 1) +#if (CONFIG_NR_CPUS 1) mfspr r0, MSSCR0 andi. r0, r0, 0x0020 rlwinm r0,r0,27,31,31 @@ -979,7 +979,7 @@ unlock_ram_in_cache: * Sri: Much of this initialization is not required. Linux * rewrites the bats, and the sprs and also enables the L1 cache. */ -#if (CONFIG_NUM_CPUS 1) +#if (CONFIG_NR_CPUS 1) .globl secondary_cpu_setup secondary_cpu_setup: /* Do only core setup on all cores except cpu0 */ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 1cba270..b97e56d 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -17,7 +17,7 @@ #define CONFIG_MPC86xx 1 /* MPC86xx */ #define CONFIG_MPC8610 1 /* MPC8610 specific */ #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ -#define CONFIG_NUM_CPUS1 /* Number of CPUs in the system */ +#define CONFIG_NR_CPUS 2 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index ccba409..78a9d11 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -36,7 +36,7 @@ #define CONFIG_MPC86xx 1 /* MPC86xx */ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ -#define CONFIG_NUM_CPUS2 /* Number of CPUs in the system */ +#define CONFIG_NR_CPUS 2 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ #ifdef RUN_DIAG diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 3cd9ff8..76712fd 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -40,7 +40,7 @@ #define CONFIG_MPC86xx 1 /* MPC86xx */ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_SBC8641D1 /* SBC8641D board specific */ -#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ +#define CONFIG_NR_CPUS 2 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ #ifdef RUN_DIAG -- 1.5.5.1 - This SF.Net email is sponsored by the Moblin Your Move Developer's challenge Build the coolest Linux based applications with Moblin SDK win great prizes Grand prize is a trip for two to an Open Source event anywhere in the world http://moblin-contest.org/redirect.php?banner_id=100url=/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] variable type issues in LMB code
On Jul 5, 2008, at 5:32 PM, Wolfgang Denk wrote: Hello Andy Becky Kumar, there is a general problem of variable types with the LMB code; at the moment, it uses some u64 (and in lib_ppc/bootm.c actually a mix of u64 and uint64_t) declarations where I think we should use phys_addr_t resp. phys_size_t types instead. At the moment, this results in lots of compiler messages: warning: cast from pointer to integer of different size Could you please have a look and try and clean up? Thanks in advance. I see the following when I build for 8641HPCN on the latest tree: bootm.c: In function ‘do_bootm_linux’: bootm.c:208: warning: cast from pointer to integer of different size bootm.c:215: warning: cast from pointer to integer of different size It looks like these errors were introduced in the following 2 commits: commit 41c5eaa7253ed82bbae1eda5667755872c615164 Author: Andy Fleming [EMAIL PROTECTED] Date: Mon Jun 16 13:58:56 2008 -0500 Resize device tree to allow space for board changes and the chosen node commit 63796c4e61b207d2e635729d41b7a7f7d188b03c Author: Andy Fleming [EMAIL PROTECTED] Date: Mon Jun 16 13:58:54 2008 -0500 Add lmb_free Andy, please fix the build warnings, and change lmb_free to use phys_size_t/phys_addr_t as appropriate - let me know if you have questions about this. Wolfgang, please let me know if there are other errors you're seeing on some other build config that I haven't addressed here, and I'll look into those. FYI, one possible source of confusion here for folks who are used to the linux version of the lmb: when the lmb became generic instead of ppc-only, the linux folks decided to always use u64 for types in the lmb code. This made some sense since ppc was the only platform using the lmb that used a smaller data type, and the other platforms lacked the concept of phys_addr_t. We've done the right thing in u-boot and used phys_size/addr_t since most of the platforms are 32-bit, and using u64 unconditionally is a waste. Cheers, B - Sponsored by: SourceForge.net Community Choice Awards: VOTE NOW! Studies have shown that voting for your favorite open source project, along with a healthy diet, reduces your potential for chronic lameness and boredom. Vote Now at http://www.sourceforge.net/community/cca08 ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 1/4] Change initdram() return type to phys_size_t
Bah - I thought I had updated my tree right before I sent that out. Not sure what happened here. Sorry about that, and thanks, Kumar! -Becky On Jun 11, 2008, at 11:47 PM, Kumar Gala wrote: Since Becky's been under the weather today and I'm feeling generous how about this version: http://gate.crashing.org/~galak/0001-v2-Change-initdram-return-type- to-phys_size_t.patch It should apply clean to: commit cdeb62e20d94005f2e80604fda03b498c3a6f704 Merge: 1859e42... ae9e97f... Author: Wolfgang Denk [EMAIL PROTECTED] Date: Wed Jun 11 22:30:47 2008 +0200 Merge branch 'master' of git://www.denx.de/git/u-boot-fdt - k - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH v2] 85xx/86xx: Move to dynamic mgmt of LAWs
On Jun 10, 2008, at 12:03 AM, Kumar Gala wrote: With the new LAW interface (set_next_law) we can move to letting the system allocate which LAWs are used for what purpose. This makes life a bit easier going forward with the new DDR code. Signed-off-by: Kumar Gala [EMAIL PROTECTED] --- Acked-by: Becky Bruce [EMAIL PROTECTED] - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH 4/4] Change lmb to use phys_size_t/phys_addr_t
This updates the lmb code to use phys_size_t
and phys_addr_t instead of unsigned long. Other code
which interacts with this code, like getenv_bootm_size()
is also updated.
Booted on MPC8641HPCN, build-tested ppc, arm, mips.
Signed-off-by: Becky Bruce [EMAIL PROTECTED]
---
common/cmd_bootm.c |5 ++-
common/image.c | 17
include/image.h|2 +-
include/lmb.h | 22 +---
lib_generic/lmb.c | 69 ++-
lib_ppc/bootm.c| 16 +++-
6 files changed, 71 insertions(+), 60 deletions(-)
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 0d67132..959689e 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -127,7 +127,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char
*argv[])
ulong os_data, os_len;
ulong image_start, image_end;
ulong load_start, load_end;
- ulong mem_start, mem_size;
+ ulong mem_start;
+ phys_size_t mem_size;
struct lmb lmb;
@@ -141,7 +142,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char
*argv[])
mem_start = getenv_bootm_low();
mem_size = getenv_bootm_size();
- lmb_add(lmb, mem_start, mem_size);
+ lmb_add(lmb, (phys_addr_t)mem_start, mem_size);
board_lmb_reserve(lmb);
diff --git a/common/image.c b/common/image.c
index 9188024..ddd9e8b 100644
--- a/common/image.c
+++ b/common/image.c
@@ -435,11 +435,16 @@ ulong getenv_bootm_low(void)
#endif
}
-ulong getenv_bootm_size(void)
+phys_size_t getenv_bootm_size(void)
{
char *s = getenv (bootm_size);
if (s) {
- ulong tmp = simple_strtoul (s, NULL, 16);
+ phys_size_t tmp;
+#ifdef CFG_64BIT_STRTOUL
+ tmp = (phys_size_t)simple_strtoull (s, NULL, 16);
+#else
+ tmp = (phys_size_t)simple_strtoul (s, NULL, 16);
+#endif
return tmp;
}
@@ -1034,9 +1039,9 @@ int boot_ramdisk_high (struct lmb *lmb, ulong rd_data,
ulong rd_len,
lmb_reserve(lmb, rd_data, rd_len);
} else {
if (initrd_high)
- *initrd_start = lmb_alloc_base (lmb, rd_len,
0x1000, initrd_high);
+ *initrd_start = (ulong)lmb_alloc_base (lmb,
rd_len, 0x1000, initrd_high);
else
- *initrd_start = lmb_alloc (lmb, rd_len, 0x1000);
+ *initrd_start = (ulong)lmb_alloc (lmb, rd_len,
0x1000);
if (*initrd_start == 0) {
puts (ramdisk - allocation error\n);
@@ -1089,7 +1094,7 @@ int boot_get_cmdline (struct lmb *lmb, ulong *cmd_start,
ulong *cmd_end,
char *cmdline;
char *s;
- cmdline = (char *)lmb_alloc_base(lmb, CFG_BARGSIZE, 0xf,
+ cmdline = (char *)(ulong)lmb_alloc_base(lmb, CFG_BARGSIZE, 0xf,
CFG_BOOTMAPSZ + bootmap_base);
if (cmdline == NULL)
@@ -1125,7 +1130,7 @@ int boot_get_cmdline (struct lmb *lmb, ulong *cmd_start,
ulong *cmd_end,
*/
int boot_get_kbd (struct lmb *lmb, bd_t **kbd, ulong bootmap_base)
{
- *kbd = (bd_t *)lmb_alloc_base(lmb, sizeof(bd_t), 0xf,
+ *kbd = (bd_t *)(ulong)lmb_alloc_base(lmb, sizeof(bd_t), 0xf,
CFG_BOOTMAPSZ + bootmap_base);
if (*kbd == NULL)
return -1;
diff --git a/include/image.h b/include/image.h
index 664e51e..46138fa 100644
--- a/include/image.h
+++ b/include/image.h
@@ -379,7 +379,7 @@ int image_check_dcrc (image_header_t *hdr);
#ifndef USE_HOSTCC
int getenv_yesno (char *var);
ulong getenv_bootm_low(void);
-ulong getenv_bootm_size(void);
+phys_size_t getenv_bootm_size(void);
void memmove_wd (void *to, void *from, size_t len, ulong chunksz);
#endif
diff --git a/include/lmb.h b/include/lmb.h
index cc64cbb..03d7667 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -17,13 +17,13 @@
#define MAX_LMB_REGIONS 8
struct lmb_property {
- ulong base;
- ulong size;
+ phys_addr_t base;
+ phys_size_t size;
};
struct lmb_region {
unsigned long cnt;
- ulong size;
+ phys_size_t size;
struct lmb_property region[MAX_LMB_REGIONS+1];
};
@@ -35,16 +35,18 @@ struct lmb {
extern struct lmb lmb;
extern void lmb_init(struct lmb *lmb);
-extern long lmb_add(struct lmb *lmb, ulong base, ulong size);
-extern long lmb_reserve(struct lmb *lmb, ulong base, ulong size);
-extern ulong lmb_alloc(struct lmb *lmb, ulong size, ulong align);
-extern ulong lmb_alloc_base(struct lmb *lmb, ulong size, ulong align, ulong
max_addr);
-extern ulong __lmb_alloc_base(struct lmb *lmb, ulong size, ulong align, ulong
max_addr);
-extern int lmb_is_reserved(struct lmb *lmb, ulong addr);
+extern long lmb_add(struct lmb *lmb, phys_addr_t base
[U-Boot-Users] [PATCH 1/4] Change initdram() return type to phys_size_t
This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Patch is too large for the list, and is located at: http://gate.crashing.org/~galak/0001-Change-initdram-return-type-to-phys_size_t.patch - Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://sourceforge.net/services/buy/index.php ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH 2/4 V4] PPC: Change lib_ppc/bat_rw.c to use high bats
From: Becky Bruce [EMAIL PROTECTED]
Currently, this code only deals with BATs 0-3, which makes
it useless on systems that support BATs 4-7. Add the
support for these registers.
Signed-off-by: Becky Bruce [EMAIL PROTECTED]
---
No, I'm not striving for a world record in trivial patch resubmissions.
This fixes a typo where I write DBAT3 with a value intended for DBAT4,
which, you might imagine, causes much breakage. Fortunately, nobody but
me is running this code right now, so I only broke myself :)
include/asm-ppc/mmu.h |6 ++-
lib_ppc/bat_rw.c | 132 ++---
2 files changed, 97 insertions(+), 41 deletions(-)
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 49d6860..dc4d66c 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -140,7 +140,11 @@ extern void _tlbia(void); /* invalidate all TLB
entries */
typedef enum {
IBAT0 = 0, IBAT1, IBAT2, IBAT3,
- DBAT0, DBAT1, DBAT2, DBAT3
+ DBAT0, DBAT1, DBAT2, DBAT3,
+#ifdef CONFIG_HIGH_BATS
+ IBAT4, IBAT5, IBAT6, IBAT7,
+ DBAT4, DBAT5, DBAT6, DBAT7
+#endif
} ppc_bat_t;
extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
diff --git a/lib_ppc/bat_rw.c b/lib_ppc/bat_rw.c
index 912efa7..c87d8b2 100644
--- a/lib_ppc/bat_rw.c
+++ b/lib_ppc/bat_rw.c
@@ -29,46 +29,72 @@
int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
{
switch (bat) {
+ case DBAT0:
+ mtspr (DBAT0L, lower);
+ mtspr (DBAT0U, upper);
+ break;
case IBAT0:
mtspr (IBAT0L, lower);
mtspr (IBAT0U, upper);
break;
-
+ case DBAT1:
+ mtspr (DBAT1L, lower);
+ mtspr (DBAT1U, upper);
+ break;
case IBAT1:
mtspr (IBAT1L, lower);
mtspr (IBAT1U, upper);
break;
-
+ case DBAT2:
+ mtspr (DBAT2L, lower);
+ mtspr (DBAT2U, upper);
+ break;
case IBAT2:
mtspr (IBAT2L, lower);
mtspr (IBAT2U, upper);
break;
-
+ case DBAT3:
+ mtspr (DBAT3L, lower);
+ mtspr (DBAT3U, upper);
+ break;
case IBAT3:
mtspr (IBAT3L, lower);
mtspr (IBAT3U, upper);
break;
-
- case DBAT0:
- mtspr (DBAT0L, lower);
- mtspr (DBAT0U, upper);
+#ifdef CONFIG_HIGH_BATS
+ case DBAT4:
+ mtspr (DBAT4L, lower);
+ mtspr (DBAT4U, upper);
break;
-
- case DBAT1:
- mtspr (DBAT1L, lower);
- mtspr (DBAT1U, upper);
+ case IBAT4:
+ mtspr (IBAT4L, lower);
+ mtspr (IBAT4U, upper);
break;
-
- case DBAT2:
- mtspr (DBAT2L, lower);
- mtspr (DBAT2U, upper);
+ case DBAT5:
+ mtspr (DBAT5L, lower);
+ mtspr (DBAT5U, upper);
break;
-
- case DBAT3:
- mtspr (DBAT3L, lower);
- mtspr (DBAT3U, upper);
+ case IBAT5:
+ mtspr (IBAT5L, lower);
+ mtspr (IBAT5U, upper);
break;
-
+ case DBAT6:
+ mtspr (DBAT6L, lower);
+ mtspr (DBAT6U, upper);
+ break;
+ case IBAT6:
+ mtspr (IBAT6L, lower);
+ mtspr (IBAT6U, upper);
+ break;
+ case DBAT7:
+ mtspr (DBAT7L, lower);
+ mtspr (DBAT7U, upper);
+ break;
+ case IBAT7:
+ mtspr (IBAT7L, lower);
+ mtspr (IBAT7U, upper);
+ break;
+#endif
default:
return (-1);
}
@@ -82,46 +108,72 @@ int read_bat (ppc_bat_t bat, unsigned long *upper,
unsigned long *lower)
unsigned long register l;
switch (bat) {
+ case DBAT0:
+ l = mfspr (DBAT0L);
+ u = mfspr (DBAT0U);
+ break;
case IBAT0:
l = mfspr (IBAT0L);
u = mfspr (IBAT0U);
break;
-
+ case DBAT1:
+ l = mfspr (DBAT1L);
+ u = mfspr (DBAT1U);
+ break;
case IBAT1:
l = mfspr (IBAT1L);
u = mfspr (IBAT1U);
break;
-
+ case DBAT2:
+ l = mfspr (DBAT2L);
+ u = mfspr (DBAT2U);
+ break;
case IBAT2:
l = mfspr (IBAT2L);
u = mfspr (IBAT2U);
break;
-
+ case DBAT3:
+ l = mfspr (DBAT3L);
+ u = mfspr (DBAT3U);
+ break;
case IBAT3:
l = mfspr (IBAT3L);
u = mfspr (IBAT3U);
break
[U-Boot-Users] [PATCH] MPC512x: Change traps.c to not reference non-addressable memory
From: Becky Bruce [EMAIL PROTECTED] Currently, END_OF_RAM is used by the trap code to determine if we should attempt to access the stack pointer or not. However, on systems with a lot of RAM, only a subset of the RAM is guaranteed to be mapped in and accessible. Change END_OF_RAM to use get_effective_memsize() instead of using the raw ram size out of the bd. Signed-off-by: Becky Bruce [EMAIL PROTECTED] --- cpu/mpc512x/traps.c |8 +++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/cpu/mpc512x/traps.c b/cpu/mpc512x/traps.c index 8455c92..8000fab 100644 --- a/cpu/mpc512x/traps.c +++ b/cpu/mpc512x/traps.c @@ -34,7 +34,13 @@ DECLARE_GLOBAL_DATA_PTR; extern unsigned long search_exception_table(unsigned long); -#define END_OF_MEM (gd-bd-bi_memstart + gd-bd-bi_memsize) +/* + * End of addressable memory. This may be less than the actual + * amount of memory on the system if we're unable to keep all + * the memory mapped in. + */ +extern ulong get_effective_memsize(void); +#define END_OF_MEM (gd-bd-bi_memstart + get_effective_memsize()) /* * Trap Exception support -- 1.5.4.1 - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH] MPC86xx: Change traps.c to not reference non-addressable memory
From: Becky Bruce [EMAIL PROTECTED] Currently, END_OF_RAM is used by the trap code to determine if we should attempt to access the stack pointer or not. However, on systems with a lot of RAM, only a subset of the RAM is guaranteed to be mapped in and accessible. Change END_OF_RAM to use get_effective_memsize() instead of using the raw ram size out of the bd to prevent us from trying to access non-mapped memory. Signed-off-by: Becky Bruce [EMAIL PROTECTED] --- cpu/mpc86xx/traps.c |8 +++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c index 04c2e13..5695c3e 100644 --- a/cpu/mpc86xx/traps.c +++ b/cpu/mpc86xx/traps.c @@ -43,7 +43,13 @@ int (*debugger_exception_handler)(struct pt_regs *) = 0; /* Returns 0 if exception not found and fixup otherwise. */ extern unsigned long search_exception_table(unsigned long); -#define END_OF_MEM (gd-bd-bi_memstart + gd-bd-bi_memsize) +/* + * End of addressable memory. This may be less than the actual + * amount of memory on the system if we're unable to keep all + * the memory mapped in. + */ +extern ulong get_effective_memsize(void); +#define END_OF_MEM (gd-bd-bi_memstart + get_effective_memsize()) /* * Trap Exception support -- 1.5.4.1 - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH] MPC85xx: Change traps.c to not reference non-addressable memory
From: Becky Bruce [EMAIL PROTECTED]
Currently, END_OF_RAM is used by the trap code to determine if
we should attempt to access the stack pointer or not. However,
on systems with a lot of RAM, only a subset of the RAM is
guaranteed to be mapped in and accessible. Change END_OF_RAM
to use get_effective_memsize() instead of using the raw ram
size out of the bd.
Signed-off-by: Becky Bruce [EMAIL PROTECTED]
---
cpu/mpc85xx/traps.c |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c
index 2381fb0..fd36658 100644
--- a/cpu/mpc85xx/traps.c
+++ b/cpu/mpc85xx/traps.c
@@ -50,10 +50,12 @@ int (*debugger_exception_handler)(struct pt_regs *) = 0;
extern unsigned long search_exception_table(unsigned long);
/*
- * End of memory as shown by board info and determined by DDR setup.
+ * End of addressable memory. This may be less than the actual
+ * amount of memory on the system if we're unable to keep all
+ * the memory mapped in.
*/
-#define END_OF_MEM (gd-bd-bi_memstart + gd-bd-bi_memsize)
-
+extern ulong get_effective_memsize(void);
+#define END_OF_MEM (gd-bd-bi_memstart + get_effective_memsize())
static __inline__ void set_tsr(unsigned long val)
{
--
1.5.4.1
-
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Re: [U-Boot-Users] [PATCH] MPC85xx: Change traps.c to not reference non-addressable memory
On May 14, 2008, at 1:57 PM, Kim Phillips wrote: On Wed, 14 May 2008 13:10:04 -0500 [EMAIL PROTECTED] wrote: From: Becky Bruce [EMAIL PROTECTED] Currently, END_OF_RAM is used by the trap code to determine if we should attempt to access the stack pointer or not. However, on systems with a lot of RAM, only a subset of the RAM is guaranteed to be mapped in and accessible. Change END_OF_RAM to use get_effective_memsize() instead of using the raw ram size out of the bd. Signed-off-by: Becky Bruce [EMAIL PROTECTED] --- what, no love for 4xx, 83xx, and 74xx_7xx? The other platforms currently set a hard limit that should still be valid - I just changed the ones that were reading memsize directly out of the bd. can also be made a single patch for WD to apply directly. Sure, I just split it up in case there was some reason we shouldn't do it for one of them. -B - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 2/4 V3] PPC: Change lib_ppc/bat_rw.c to use high bats
On May 11, 2008, at 6:05 PM, Wolfgang Denk wrote: In message [EMAIL PROTECTED] you wrote: From: Becky Bruce [EMAIL PROTECTED] Currently, this code only deals with BATs 0-3, which makes it useless on systems that support BATs 4-7. Add the support for these registers. Just to be sure: I understand this code is for the next release (i.e. whatever comes after v.1.3.3), i. e. not for the upcoming v1.3.3? Right. There's no rush on this. Thanks! -Becky - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 3/4 V2] PPC: Add print_bats() to lib_ppc/bat_rw.c
Yeah, I noticed that this morning. I cut and pasted that particular block from another file, and somehow ended up with spaces. I'll respin this one. On May 9, 2008, at 10:29 AM, Scott Wood wrote: On Thu, May 08, 2008 at 07:02:38PM -0500, [EMAIL PROTECTED] wrote: +printf (\tIBAT0L = 0x%08X , mfspr (IBAT0L)); +printf (\tIBAT0U = 0x%08X\n, mfspr (IBAT0U)); +printf (\tDBAT0L = 0x%08X , mfspr (DBAT0L)); +printf (\tDBAT0U = 0x%08X\n, mfspr (DBAT0U)); +printf (\tIBAT1L = 0x%08X , mfspr (IBAT1L)); +printf (\tIBAT1U = 0x%08X\n, mfspr (IBAT1U)); +printf (\tDBAT1L = 0x%08X , mfspr (DBAT1L)); +printf (\tDBAT1U = 0x%08X\n, mfspr (DBAT1U)); +printf (\tIBAT2L = 0x%08X , mfspr (IBAT2L)); +printf (\tIBAT2U = 0x%08X\n, mfspr (IBAT2U)); +printf (\tDBAT2L = 0x%08X , mfspr (DBAT2L)); +printf (\tDBAT2U = 0x%08X\n, mfspr (DBAT2U)); +printf (\tIBAT3L = 0x%08X , mfspr (IBAT3L)); +printf (\tIBAT3U = 0x%08X\n, mfspr (IBAT3U)); +printf (\tDBAT3L = 0x%08X , mfspr (DBAT3L)); +printf (\tDBAT3U = 0x%08X\n, mfspr (DBAT3U)); Tabs, not spaces. Yeah, I noticed that this morning. I cut and pasted that particular block from another file, and somehow ended up with spaces instead of tabs - the printf at the beginning of the function has the same problem. I'll respin this one. Thanks! -B - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
Re: [U-Boot-Users] [PATCH 2/4 V2] PPC: Change lib_ppc/bat_rw.c to use high bats
On May 9, 2008, at 10:28 AM, Scott Wood wrote:
On Thu, May 08, 2008 at 07:02:23PM -0500, [EMAIL PROTECTED]
wrote:
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 49d6860..f836270 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -141,6 +141,10 @@ extern void _tlbia(void); /* invalidate
all
TLB entries */
typedef enum {
IBAT0 = 0, IBAT1, IBAT2, IBAT3,
DBAT0, DBAT1, DBAT2, DBAT3
+#ifdef CONFIG_HIGH_BATS
+, IBAT4, IBAT5, IBAT6, IBAT7,
+DBAT4, DBAT5, DBAT6, DBAT7
+#endif
C allows trailing commas on such lists; no need to move it inside the
ifdef.
Dangling commas bother me in the extreme. If this is the concensus,
I'll move it, but I prefer it where it is.
-B
-
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Re: [U-Boot-Users] [PATCH 2/4 V2] PPC: Change lib_ppc/bat_rw.c to use high bats
On May 9, 2008, at 2:14 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 14:45 Fri 09 May , Jerry Van Baren wrote:
Becky Bruce wrote:
On May 9, 2008, at 10:28 AM, Scott Wood wrote:
On Thu, May 08, 2008 at 07:02:23PM -0500, [EMAIL PROTECTED]
wrote:
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 49d6860..f836270 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -141,6 +141,10 @@ extern void _tlbia(void);/* invalidate
all
TLB entries */
typedef enum {
IBAT0 = 0, IBAT1, IBAT2, IBAT3,
DBAT0, DBAT1, DBAT2, DBAT3
+#ifdef CONFIG_HIGH_BATS
+ , IBAT4, IBAT5, IBAT6, IBAT7,
+ DBAT4, DBAT5, DBAT6, DBAT7
+#endif
C allows trailing commas on such lists; no need to move it inside
the
ifdef.
Dangling commas bother me in the extreme. If this is the concensus,
I'll move it, but I prefer it where it is.
-B
+1 for moving. Dangling commas is the second best thing in C. ;-)
+1 for moving. Dangling commas is the second best thing in C. ;-)
I also want to know what's the first best thing! I have to guess that
the dangling comma is really the fifteenth-best thing, or
something. but I don't want this thread to degenerate into a holy
war.
Ayway, point taken, and I'll move it. But I don't have to like it :)
Cheers,
B
-
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[U-Boot-Users] [PATCH 2/4 V3] PPC: Change lib_ppc/bat_rw.c to use high bats
From: Becky Bruce [EMAIL PROTECTED]
Currently, this code only deals with BATs 0-3, which makes
it useless on systems that support BATs 4-7. Add the
support for these registers.
Signed-off-by: Becky Bruce [EMAIL PROTECTED]
---
resend, moving comma in enum as requested on list
include/asm-ppc/mmu.h |6 ++-
lib_ppc/bat_rw.c | 132 ++---
2 files changed, 97 insertions(+), 41 deletions(-)
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 49d6860..dc4d66c 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -140,7 +140,11 @@ extern void _tlbia(void); /* invalidate all TLB
entries */
typedef enum {
IBAT0 = 0, IBAT1, IBAT2, IBAT3,
- DBAT0, DBAT1, DBAT2, DBAT3
+ DBAT0, DBAT1, DBAT2, DBAT3,
+#ifdef CONFIG_HIGH_BATS
+ IBAT4, IBAT5, IBAT6, IBAT7,
+ DBAT4, DBAT5, DBAT6, DBAT7
+#endif
} ppc_bat_t;
extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
diff --git a/lib_ppc/bat_rw.c b/lib_ppc/bat_rw.c
index 912efa7..c87d8b2 100644
--- a/lib_ppc/bat_rw.c
+++ b/lib_ppc/bat_rw.c
@@ -29,46 +29,72 @@
int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
{
switch (bat) {
+ case DBAT0:
+ mtspr (DBAT0L, lower);
+ mtspr (DBAT0U, upper);
+ break;
case IBAT0:
mtspr (IBAT0L, lower);
mtspr (IBAT0U, upper);
break;
-
+ case DBAT1:
+ mtspr (DBAT1L, lower);
+ mtspr (DBAT1U, upper);
+ break;
case IBAT1:
mtspr (IBAT1L, lower);
mtspr (IBAT1U, upper);
break;
-
+ case DBAT2:
+ mtspr (DBAT2L, lower);
+ mtspr (DBAT2U, upper);
+ break;
case IBAT2:
mtspr (IBAT2L, lower);
mtspr (IBAT2U, upper);
break;
-
+ case DBAT3:
+ mtspr (DBAT3L, lower);
+ mtspr (DBAT3U, upper);
+ break;
case IBAT3:
mtspr (IBAT3L, lower);
mtspr (IBAT3U, upper);
break;
-
- case DBAT0:
- mtspr (DBAT0L, lower);
- mtspr (DBAT0U, upper);
+#ifdef CONFIG_HIGH_BATS
+ case DBAT4:
+ mtspr (DBAT4L, lower);
+ mtspr (DBAT3U, upper);
break;
-
- case DBAT1:
- mtspr (DBAT1L, lower);
- mtspr (DBAT1U, upper);
+ case IBAT4:
+ mtspr (IBAT4L, lower);
+ mtspr (IBAT4U, upper);
break;
-
- case DBAT2:
- mtspr (DBAT2L, lower);
- mtspr (DBAT2U, upper);
+ case DBAT5:
+ mtspr (DBAT5L, lower);
+ mtspr (DBAT5U, upper);
break;
-
- case DBAT3:
- mtspr (DBAT3L, lower);
- mtspr (DBAT3U, upper);
+ case IBAT5:
+ mtspr (IBAT5L, lower);
+ mtspr (IBAT5U, upper);
break;
-
+ case DBAT6:
+ mtspr (DBAT6L, lower);
+ mtspr (DBAT6U, upper);
+ break;
+ case IBAT6:
+ mtspr (IBAT6L, lower);
+ mtspr (IBAT6U, upper);
+ break;
+ case DBAT7:
+ mtspr (DBAT7L, lower);
+ mtspr (DBAT7U, upper);
+ break;
+ case IBAT7:
+ mtspr (IBAT7L, lower);
+ mtspr (IBAT7U, upper);
+ break;
+#endif
default:
return (-1);
}
@@ -82,46 +108,72 @@ int read_bat (ppc_bat_t bat, unsigned long *upper,
unsigned long *lower)
unsigned long register l;
switch (bat) {
+ case DBAT0:
+ l = mfspr (DBAT0L);
+ u = mfspr (DBAT0U);
+ break;
case IBAT0:
l = mfspr (IBAT0L);
u = mfspr (IBAT0U);
break;
-
+ case DBAT1:
+ l = mfspr (DBAT1L);
+ u = mfspr (DBAT1U);
+ break;
case IBAT1:
l = mfspr (IBAT1L);
u = mfspr (IBAT1U);
break;
-
+ case DBAT2:
+ l = mfspr (DBAT2L);
+ u = mfspr (DBAT2U);
+ break;
case IBAT2:
l = mfspr (IBAT2L);
u = mfspr (IBAT2U);
break;
-
+ case DBAT3:
+ l = mfspr (DBAT3L);
+ u = mfspr (DBAT3U);
+ break;
case IBAT3:
l = mfspr (IBAT3L);
u = mfspr (IBAT3U);
break;
-
- case DBAT0:
- l = mfspr (DBAT0L);
- u = mfspr (DBAT0U);
+#ifdef CONFIG_HIGH_BATS
+ case DBAT4:
+ l = mfspr (DBAT4L);
+ u = mfspr (DBAT4U
[U-Boot-Users] [PATCH 3/4 V3] PPC: Add print_bats() to lib_ppc/bat_rw.c
From: Becky Bruce [EMAIL PROTECTED]
This function prints the values of all the BAT register
pairs - I needed this for debug earlier this week; adding it to
lib_ppc so others can use it (and add it to reginfo commands
if so desired).
Signed-off-by: Becky Bruce [EMAIL PROTECTED]
---
Resend - eliminate accidental spaces instead of tabs.
include/asm-ppc/mmu.h |1 +
lib_ppc/bat_rw.c | 41 +
2 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index dc4d66c..1e3c2cb 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -149,6 +149,7 @@ typedef enum {
extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
+extern void print_bats(void);
#endif /* __ASSEMBLY__ */
diff --git a/lib_ppc/bat_rw.c b/lib_ppc/bat_rw.c
index c87d8b2..548d064 100644
--- a/lib_ppc/bat_rw.c
+++ b/lib_ppc/bat_rw.c
@@ -183,3 +183,44 @@ int read_bat (ppc_bat_t bat, unsigned long *upper,
unsigned long *lower)
return (0);
}
+
+void print_bats(void)
+{
+ printf(BAT registers:\n);
+
+ printf (\tIBAT0L = 0x%08X , mfspr (IBAT0L));
+ printf (\tIBAT0U = 0x%08X\n, mfspr (IBAT0U));
+ printf (\tDBAT0L = 0x%08X , mfspr (DBAT0L));
+ printf (\tDBAT0U = 0x%08X\n, mfspr (DBAT0U));
+ printf (\tIBAT1L = 0x%08X , mfspr (IBAT1L));
+ printf (\tIBAT1U = 0x%08X\n, mfspr (IBAT1U));
+ printf (\tDBAT1L = 0x%08X , mfspr (DBAT1L));
+ printf (\tDBAT1U = 0x%08X\n, mfspr (DBAT1U));
+ printf (\tIBAT2L = 0x%08X , mfspr (IBAT2L));
+ printf (\tIBAT2U = 0x%08X\n, mfspr (IBAT2U));
+ printf (\tDBAT2L = 0x%08X , mfspr (DBAT2L));
+ printf (\tDBAT2U = 0x%08X\n, mfspr (DBAT2U));
+ printf (\tIBAT3L = 0x%08X , mfspr (IBAT3L));
+ printf (\tIBAT3U = 0x%08X\n, mfspr (IBAT3U));
+ printf (\tDBAT3L = 0x%08X , mfspr (DBAT3L));
+ printf (\tDBAT3U = 0x%08X\n, mfspr (DBAT3U));
+
+#ifdef CONFIG_HIGH_BATS
+ printf (\tIBAT4L = 0x%08X , mfspr (IBAT4L));
+ printf (\tIBAT4U = 0x%08X\n, mfspr (IBAT4U));
+ printf (\tDBAT4L = 0x%08X , mfspr (DBAT4L));
+ printf (\tDBAT4U = 0x%08X\n, mfspr (DBAT4U));
+ printf (\tIBAT5L = 0x%08X , mfspr (IBAT5L));
+ printf (\tIBAT5U = 0x%08X\n, mfspr (IBAT5U));
+ printf (\tDBAT5L = 0x%08X , mfspr (DBAT5L));
+ printf (\tDBAT5U = 0x%08X\n, mfspr (DBAT5U));
+ printf (\tIBAT6L = 0x%08X , mfspr (IBAT6L));
+ printf (\tIBAT6U = 0x%08X\n, mfspr (IBAT6U));
+ printf (\tDBAT6L = 0x%08X , mfspr (DBAT6L));
+ printf (\tDBAT6U = 0x%08X\n, mfspr (DBAT6U));
+ printf (\tIBAT7L = 0x%08X , mfspr (IBAT7L));
+ printf (\tIBAT7U = 0x%08X\n, mfspr (IBAT7U));
+ printf (\tDBAT7L = 0x%08X , mfspr (DBAT7L));
+ printf (\tDBAT7U = 0x%08X\n, mfspr (DBAT7U));
+#endif
+}
--
1.5.4.1
-
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[U-Boot-Users] [PATCH 2/4] PPC: Change lib_ppc/bat_rw.c to use high bats
From: Becky Bruce [EMAIL PROTECTED]
Currently, this code only deals with BATs 0-3, which makes
it useless on systems that support BATs 4-7. Add the
support for these registers.
Signed-off-by: Becky Bruce [EMAIL PROTECTED]
---
include/asm-ppc/mmu.h |4 ++
lib_ppc/bat_rw.c | 134 ++---
2 files changed, 97 insertions(+), 41 deletions(-)
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 49d6860..f836270 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -141,6 +141,10 @@ extern void _tlbia(void); /* invalidate all TLB
entries */
typedef enum {
IBAT0 = 0, IBAT1, IBAT2, IBAT3,
DBAT0, DBAT1, DBAT2, DBAT3
+#ifdef CONFIG_HIGH_BATS
+ , IBAT4, IBAT5, IBAT6, IBAT7,
+ DBAT4, DBAT5, DBAT6, DBAT7
+#endif
} ppc_bat_t;
extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
diff --git a/lib_ppc/bat_rw.c b/lib_ppc/bat_rw.c
index 912efa7..6288164 100644
--- a/lib_ppc/bat_rw.c
+++ b/lib_ppc/bat_rw.c
@@ -28,47 +28,73 @@
int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
{
- switch (bat) {
+ switch(bat) {
+ case DBAT0:
+ mtspr (DBAT0L, lower);
+ mtspr (DBAT0U, upper);
+ break;
case IBAT0:
mtspr (IBAT0L, lower);
mtspr (IBAT0U, upper);
break;
-
+ case DBAT1:
+ mtspr (DBAT1L, lower);
+ mtspr (DBAT1U, upper);
+ break;
case IBAT1:
mtspr (IBAT1L, lower);
mtspr (IBAT1U, upper);
break;
-
+ case DBAT2:
+ mtspr (DBAT2L, lower);
+ mtspr (DBAT2U, upper);
+ break;
case IBAT2:
mtspr (IBAT2L, lower);
mtspr (IBAT2U, upper);
break;
-
+ case DBAT3:
+ mtspr (DBAT3L, lower);
+ mtspr (DBAT3U, upper);
+ break;
case IBAT3:
mtspr (IBAT3L, lower);
mtspr (IBAT3U, upper);
break;
-
- case DBAT0:
- mtspr (DBAT0L, lower);
- mtspr (DBAT0U, upper);
+#ifdef CONFIG_HIGH_BATS
+ case DBAT4:
+ mtspr (DBAT4L, lower);
+ mtspr (DBAT3U, upper);
break;
-
- case DBAT1:
- mtspr (DBAT1L, lower);
- mtspr (DBAT1U, upper);
+ case IBAT4:
+ mtspr (IBAT4L, lower);
+ mtspr (IBAT4U, upper);
break;
-
- case DBAT2:
- mtspr (DBAT2L, lower);
- mtspr (DBAT2U, upper);
+ case DBAT5:
+ mtspr (DBAT5L, lower);
+ mtspr (DBAT5U, upper);
break;
-
- case DBAT3:
- mtspr (DBAT3L, lower);
- mtspr (DBAT3U, upper);
+ case IBAT5:
+ mtspr (IBAT5L, lower);
+ mtspr (IBAT5U, upper);
break;
-
+ case DBAT6:
+ mtspr (DBAT6L, lower);
+ mtspr (DBAT6U, upper);
+ break;
+ case IBAT6:
+ mtspr (IBAT6L, lower);
+ mtspr (IBAT6U, upper);
+ break;
+ case DBAT7:
+ mtspr (DBAT7L, lower);
+ mtspr (DBAT7U, upper);
+ break;
+ case IBAT7:
+ mtspr (IBAT7L, lower);
+ mtspr (IBAT7U, upper);
+ break;
+#endif
default:
return (-1);
}
@@ -82,46 +108,72 @@ int read_bat (ppc_bat_t bat, unsigned long *upper,
unsigned long *lower)
unsigned long register l;
switch (bat) {
+ case DBAT0:
+ l = mfspr (DBAT0L);
+ u = mfspr (DBAT0U);
+ break;
case IBAT0:
l = mfspr (IBAT0L);
u = mfspr (IBAT0U);
break;
-
+ case DBAT1:
+ l = mfspr (DBAT1L);
+ u = mfspr (DBAT1U);
+ break;
case IBAT1:
l = mfspr (IBAT1L);
u = mfspr (IBAT1U);
break;
-
+ case DBAT2:
+ l = mfspr (DBAT2L);
+ u = mfspr (DBAT2U);
+ break;
case IBAT2:
l = mfspr (IBAT2L);
u = mfspr (IBAT2U);
break;
-
+ case DBAT3:
+ l = mfspr (DBAT3L);
+ u = mfspr (DBAT3U);
+ break;
case IBAT3:
l = mfspr (IBAT3L);
u = mfspr (IBAT3U);
break;
-
- case DBAT0:
- l = mfspr (DBAT0L);
- u = mfspr (DBAT0U);
+#ifdef CONFIG_HIGH_BATS
+ case DBAT4:
+ l = mfspr (DBAT4L);
+ u = mfspr (DBAT4U);
break;
-
- case DBAT1:
- l = mfspr (DBAT1L
[U-Boot-Users] [PATCH 4/4] MPC86xx: Add bat registers to reginfo command
From: Becky Bruce [EMAIL PROTECTED]
Signed-off-by: Becky Bruce becky,[EMAIL PROTECTED]
---
cpu/mpc86xx/cpu.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index 3c74764..e26bf36 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -26,6 +26,7 @@
#include watchdog.h
#include command.h
#include asm/cache.h
+#include asm/mmu.h
#include mpc86xx.h
#include asm/fsl_law.h
@@ -268,13 +269,14 @@ dma_xfer(void *dest, uint count, void *src)
/*
* Print out the state of various machine registers.
- * Currently prints out LAWs and BR0/OR0
+ * Currently prints out LAWs, BR0/OR0, and BATs
*/
void mpc86xx_reginfo(void)
{
immap_t *immap = (immap_t *)CFG_IMMR;
ccsr_lbc_t *lbc = immap-im_lbc;
+ print_bats();
print_laws();
printf (Local Bus Controller Registers\n
--
1.5.4.1
-
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[U-Boot-Users] [PATCH 1/4] PPC: Create and use CONFIG_HIGH_BATS
From: Becky Bruce [EMAIL PROTECTED] Change all code that conditionally operates on high bat registers (that is, BATs 4-7) to look at CONFIG_HIGH_BATS instead of the myriad ways this is done now. Define the option for every config for which high bats are supported (and enabled by early boot, on parts where they're not always enabled) Signed-off-by: Becky Bruce [EMAIL PROTECTED] --- cpu/74xx_7xx/start.S |6 +++--- cpu/mpc83xx/start.S |6 +++--- include/configs/Alaska8220.h |2 ++ include/configs/BC3450.h |2 ++ include/configs/CPCI750.h |2 ++ include/configs/IceCube.h |2 ++ include/configs/MPC8313ERDB.h |2 ++ include/configs/MPC8315ERDB.h |1 + include/configs/MPC8323ERDB.h |1 + include/configs/MPC832XEMDS.h |2 ++ include/configs/MPC8349EMDS.h |1 + include/configs/MPC8349ITX.h |1 + include/configs/MPC8360EMDS.h |2 ++ include/configs/MPC8360ERDK.h |2 ++ include/configs/MPC837XEMDS.h |1 + include/configs/MPC837XERDB.h |2 ++ include/configs/MPC8610HPCD.h |1 + include/configs/MPC8641HPCN.h |1 + include/configs/PM520.h |2 ++ include/configs/TB5200.h |2 ++ include/configs/TOP5200.h |2 ++ include/configs/TQM5200.h |2 ++ include/configs/TQM834x.h |2 ++ include/configs/Total5200.h |2 ++ include/configs/Yukon8220.h |2 ++ include/configs/ads5121.h |2 ++ include/configs/aev.h |2 ++ include/configs/canmb.h |2 ++ include/configs/cm5200.h |2 ++ include/configs/cpci5200.h|2 ++ include/configs/hmi1001.h |2 ++ include/configs/inka4x0.h |2 ++ include/configs/jupiter.h |2 ++ include/configs/mcc200.h |2 ++ include/configs/mecp5200.h|2 ++ include/configs/motionpro.h |1 + include/configs/mpc7448hpc2.h |2 +- include/configs/munices.h |1 + include/configs/o2dnt.h |2 ++ include/configs/p3mx.h|1 + include/configs/pf5200.h |1 + include/configs/sbc8349.h |2 ++ include/configs/smmaco4.h |2 ++ include/configs/sorcery.h |2 ++ include/configs/spieval.h |2 ++ include/configs/uc101.h |2 ++ include/configs/v38b.h|2 ++ 47 files changed, 84 insertions(+), 7 deletions(-) diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S index b5834b9..42b0f72 100644 --- a/cpu/74xx_7xx/start.S +++ b/cpu/74xx_7xx/start.S @@ -316,7 +316,7 @@ invalidate_bats: mtspr IBAT1U, r0 mtspr IBAT2U, r0 mtspr IBAT3U, r0 -#ifdef CONFIG_750FX +#ifdef CONFIG_HIGH_BATS mtspr IBAT4U, r0 mtspr IBAT5U, r0 mtspr IBAT6U, r0 @@ -327,7 +327,7 @@ invalidate_bats: mtspr DBAT1U, r0 mtspr DBAT2U, r0 mtspr DBAT3U, r0 -#ifdef CONFIG_750FX +#ifdef CONFIG_HIGH_BATS mtspr DBAT4U, r0 mtspr DBAT5U, r0 mtspr DBAT6U, r0 @@ -414,7 +414,7 @@ setup_bats: mtspr DBAT3U, r3 isync -#ifdef CONFIG_750FX +#ifdef CONFIG_HIGH_BATS /* IBAT 4 */ addis r4, r0, [EMAIL PROTECTED] ori r4, r4, [EMAIL PROTECTED] diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 309eb30..c182174 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -557,7 +557,7 @@ invalidate_bats: mtspr IBAT1U, r0 mtspr IBAT2U, r0 mtspr IBAT3U, r0 -#if (CFG_HID2 HID2_HBE) +#ifdef CONFIG_HIGH_BATS mtspr IBAT4U, r0 mtspr IBAT5U, r0 mtspr IBAT6U, r0 @@ -568,7 +568,7 @@ invalidate_bats: mtspr DBAT1U, r0 mtspr DBAT2U, r0 mtspr DBAT3U, r0 -#if (CFG_HID2 HID2_HBE) +#ifdef CONFIG_HIGH_BATS mtspr DBAT4U, r0 mtspr DBAT5U, r0 mtspr DBAT6U, r0 @@ -655,7 +655,7 @@ setup_bats: mtspr DBAT3U, r3 isync -#if (CFG_HID2 HID2_HBE) +#ifdef CONFIG_HIGH_BATS /* IBAT 4 */ addis r4, r0, [EMAIL PROTECTED] ori r4, r4, [EMAIL PROTECTED] diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h index 3f2f614..38b962f 100644 --- a/include/configs/Alaska8220.h +++ b/include/configs/Alaska8220.h @@ -31,6 +31,8 @@ #define CONFIG_MPC8220 1 #define CONFIG_ALASKA8220 1 /* ... on Alaska board */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to determine the CPU speed. */ #define CFG_MPC8220_CLKIN 3000/* ... running at 30MHz */ diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 706c13e..b7574bf 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -61,6 +61,8 @@ #define BOOTFLAG_COLD 0x01/* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02/* Software reboot */ +#define CONFIG_HIGH_BATS 1
[U-Boot-Users] [PATCH 2/4 V2] PPC: Change lib_ppc/bat_rw.c to use high bats
From: Becky Bruce [EMAIL PROTECTED]
Currently, this code only deals with BATs 0-3, which makes
it useless on systems that support BATs 4-7. Add the
support for these registers.
Signed-off-by: Becky Bruce [EMAIL PROTECTED]
---
include/asm-ppc/mmu.h |4 ++
lib_ppc/bat_rw.c | 134 ++---
2 files changed, 97 insertions(+), 41 deletions(-)
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 49d6860..f836270 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -141,6 +141,10 @@ extern void _tlbia(void); /* invalidate all TLB
entries */
typedef enum {
IBAT0 = 0, IBAT1, IBAT2, IBAT3,
DBAT0, DBAT1, DBAT2, DBAT3
+#ifdef CONFIG_HIGH_BATS
+ , IBAT4, IBAT5, IBAT6, IBAT7,
+ DBAT4, DBAT5, DBAT6, DBAT7
+#endif
} ppc_bat_t;
extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
diff --git a/lib_ppc/bat_rw.c b/lib_ppc/bat_rw.c
index 912efa7..6288164 100644
--- a/lib_ppc/bat_rw.c
+++ b/lib_ppc/bat_rw.c
@@ -28,47 +28,73 @@
int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
{
- switch (bat) {
+ switch(bat) {
+ case DBAT0:
+ mtspr (DBAT0L, lower);
+ mtspr (DBAT0U, upper);
+ break;
case IBAT0:
mtspr (IBAT0L, lower);
mtspr (IBAT0U, upper);
break;
-
+ case DBAT1:
+ mtspr (DBAT1L, lower);
+ mtspr (DBAT1U, upper);
+ break;
case IBAT1:
mtspr (IBAT1L, lower);
mtspr (IBAT1U, upper);
break;
-
+ case DBAT2:
+ mtspr (DBAT2L, lower);
+ mtspr (DBAT2U, upper);
+ break;
case IBAT2:
mtspr (IBAT2L, lower);
mtspr (IBAT2U, upper);
break;
-
+ case DBAT3:
+ mtspr (DBAT3L, lower);
+ mtspr (DBAT3U, upper);
+ break;
case IBAT3:
mtspr (IBAT3L, lower);
mtspr (IBAT3U, upper);
break;
-
- case DBAT0:
- mtspr (DBAT0L, lower);
- mtspr (DBAT0U, upper);
+#ifdef CONFIG_HIGH_BATS
+ case DBAT4:
+ mtspr (DBAT4L, lower);
+ mtspr (DBAT3U, upper);
break;
-
- case DBAT1:
- mtspr (DBAT1L, lower);
- mtspr (DBAT1U, upper);
+ case IBAT4:
+ mtspr (IBAT4L, lower);
+ mtspr (IBAT4U, upper);
break;
-
- case DBAT2:
- mtspr (DBAT2L, lower);
- mtspr (DBAT2U, upper);
+ case DBAT5:
+ mtspr (DBAT5L, lower);
+ mtspr (DBAT5U, upper);
break;
-
- case DBAT3:
- mtspr (DBAT3L, lower);
- mtspr (DBAT3U, upper);
+ case IBAT5:
+ mtspr (IBAT5L, lower);
+ mtspr (IBAT5U, upper);
break;
-
+ case DBAT6:
+ mtspr (DBAT6L, lower);
+ mtspr (DBAT6U, upper);
+ break;
+ case IBAT6:
+ mtspr (IBAT6L, lower);
+ mtspr (IBAT6U, upper);
+ break;
+ case DBAT7:
+ mtspr (DBAT7L, lower);
+ mtspr (DBAT7U, upper);
+ break;
+ case IBAT7:
+ mtspr (IBAT7L, lower);
+ mtspr (IBAT7U, upper);
+ break;
+#endif
default:
return (-1);
}
@@ -82,46 +108,72 @@ int read_bat (ppc_bat_t bat, unsigned long *upper,
unsigned long *lower)
unsigned long register l;
switch (bat) {
+ case DBAT0:
+ l = mfspr (DBAT0L);
+ u = mfspr (DBAT0U);
+ break;
case IBAT0:
l = mfspr (IBAT0L);
u = mfspr (IBAT0U);
break;
-
+ case DBAT1:
+ l = mfspr (DBAT1L);
+ u = mfspr (DBAT1U);
+ break;
case IBAT1:
l = mfspr (IBAT1L);
u = mfspr (IBAT1U);
break;
-
+ case DBAT2:
+ l = mfspr (DBAT2L);
+ u = mfspr (DBAT2U);
+ break;
case IBAT2:
l = mfspr (IBAT2L);
u = mfspr (IBAT2U);
break;
-
+ case DBAT3:
+ l = mfspr (DBAT3L);
+ u = mfspr (DBAT3U);
+ break;
case IBAT3:
l = mfspr (IBAT3L);
u = mfspr (IBAT3U);
break;
-
- case DBAT0:
- l = mfspr (DBAT0L);
- u = mfspr (DBAT0U);
+#ifdef CONFIG_HIGH_BATS
+ case DBAT4:
+ l = mfspr (DBAT4L);
+ u = mfspr (DBAT4U);
break;
-
- case DBAT1:
- l = mfspr (DBAT1L
[U-Boot-Users] [PATCH 3/4 V2] PPC: Add print_bats() to lib_ppc/bat_rw.c
From: Becky Bruce [EMAIL PROTECTED]
This function prints the values of all the BAT register
pairs - I needed this for debug earlier this week; adding it to
lib_ppc so others can use it (and add it to reginfo commands
if so desired).
Signed-off-by: Becky Bruce [EMAIL PROTECTED]
---
include/asm-ppc/mmu.h |1 +
lib_ppc/bat_rw.c | 41 +
2 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index f836270..3af1d9c 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -149,6 +149,7 @@ typedef enum {
extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
+extern void print_bats(void);
#endif /* __ASSEMBLY__ */
diff --git a/lib_ppc/bat_rw.c b/lib_ppc/bat_rw.c
index 6288164..f317b25 100644
--- a/lib_ppc/bat_rw.c
+++ b/lib_ppc/bat_rw.c
@@ -183,3 +183,44 @@ int read_bat (ppc_bat_t bat, unsigned long *upper,
unsigned long *lower)
return (0);
}
+
+void print_bats(void)
+{
+ printf(BAT registers:\n);
+
+printf (\tIBAT0L = 0x%08X , mfspr (IBAT0L));
+printf (\tIBAT0U = 0x%08X\n, mfspr (IBAT0U));
+printf (\tDBAT0L = 0x%08X , mfspr (DBAT0L));
+printf (\tDBAT0U = 0x%08X\n, mfspr (DBAT0U));
+printf (\tIBAT1L = 0x%08X , mfspr (IBAT1L));
+printf (\tIBAT1U = 0x%08X\n, mfspr (IBAT1U));
+printf (\tDBAT1L = 0x%08X , mfspr (DBAT1L));
+printf (\tDBAT1U = 0x%08X\n, mfspr (DBAT1U));
+printf (\tIBAT2L = 0x%08X , mfspr (IBAT2L));
+printf (\tIBAT2U = 0x%08X\n, mfspr (IBAT2U));
+printf (\tDBAT2L = 0x%08X , mfspr (DBAT2L));
+printf (\tDBAT2U = 0x%08X\n, mfspr (DBAT2U));
+printf (\tIBAT3L = 0x%08X , mfspr (IBAT3L));
+printf (\tIBAT3U = 0x%08X\n, mfspr (IBAT3U));
+printf (\tDBAT3L = 0x%08X , mfspr (DBAT3L));
+printf (\tDBAT3U = 0x%08X\n, mfspr (DBAT3U));
+
+#ifdef CONFIG_HIGH_BATS
+ printf (\tIBAT4L = 0x%08X , mfspr (IBAT4L));
+ printf (\tIBAT4U = 0x%08X\n, mfspr (IBAT4U));
+ printf (\tDBAT4L = 0x%08X , mfspr (DBAT4L));
+ printf (\tDBAT4U = 0x%08X\n, mfspr (DBAT4U));
+ printf (\tIBAT5L = 0x%08X , mfspr (IBAT5L));
+ printf (\tIBAT5U = 0x%08X\n, mfspr (IBAT5U));
+ printf (\tDBAT5L = 0x%08X , mfspr (DBAT5L));
+ printf (\tDBAT5U = 0x%08X\n, mfspr (DBAT5U));
+ printf (\tIBAT6L = 0x%08X , mfspr (IBAT6L));
+ printf (\tIBAT6U = 0x%08X\n, mfspr (IBAT6U));
+ printf (\tDBAT6L = 0x%08X , mfspr (DBAT6L));
+ printf (\tDBAT6U = 0x%08X\n, mfspr (DBAT6U));
+ printf (\tIBAT7L = 0x%08X , mfspr (IBAT7L));
+ printf (\tIBAT7U = 0x%08X\n, mfspr (IBAT7U));
+ printf (\tDBAT7L = 0x%08X , mfspr (DBAT7L));
+ printf (\tDBAT7U = 0x%08X\n, mfspr (DBAT7U));
+#endif
+}
--
1.5.4.1
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[U-Boot-Users] [PATCH 4/4 V2] PPC: 86xx Add bat registers to reginfo command
From: Becky Bruce [EMAIL PROTECTED]
Signed-off-by: Becky Bruce [EMAIL PROTECTED]
---
cpu/mpc86xx/cpu.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index 3c74764..e26bf36 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -26,6 +26,7 @@
#include watchdog.h
#include command.h
#include asm/cache.h
+#include asm/mmu.h
#include mpc86xx.h
#include asm/fsl_law.h
@@ -268,13 +269,14 @@ dma_xfer(void *dest, uint count, void *src)
/*
* Print out the state of various machine registers.
- * Currently prints out LAWs and BR0/OR0
+ * Currently prints out LAWs, BR0/OR0, and BATs
*/
void mpc86xx_reginfo(void)
{
immap_t *immap = (immap_t *)CFG_IMMR;
ccsr_lbc_t *lbc = immap-im_lbc;
+ print_bats();
print_laws();
printf (Local Bus Controller Registers\n
--
1.5.4.1
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[U-Boot-Users] [PATCH] PPC: fix map_physmem build warning
map_physmem currently generates a warning when CONFIG_PHYS_64BIT is
enabled. This quiets the warning.
Signed-off-by: Becky Bruce [EMAIL PROTECTED]
---
include/asm-ppc/io.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index 00b7ec5..7cc28bf 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -251,7 +251,7 @@ extern inline void out_be32(volatile unsigned __iomem
*addr, int val)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
- return (void *)paddr;
+ return (void *)((unsigned long)paddr);
}
/*
--
1.5.4.1
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Re: [U-Boot-Users] SYNC definition problem
On Apr 11, 2008, at 5:27 PM, Yang Ronda wrote: Hi, I was trying to turn on I-Cache while u-boot is executing out of Flash on MPC5121 ADS board, and just found the board refused to boot. After debug and tried many different ways, we finally found that the root of the problem is the SYNC macro definition in u-boot include/ppc_asm.tmpl file. The SYNC was defined as #define SYNC \ sync; \ isync The problem isn't the macro definition. That macro is used all over the place - changing global macros to fix a single problem is not a good idea unless there's something inherently wrong with the macro. Which there isn't, in this case. By turning on I-cache on powerpc e300 core, ICE bit of HID0 needs to be set. Before setting ICE, an isync operation need to be issued. In the cpu/mpc512x/start.S file, this is done by using a 'SYNC' statement. But we found we need to add one more sync operation to guarantee isync is complete. You should only need a single isync before writing the ICE bit. I looked at that file, and everywhere I see a write to the ICE bit, there's no SYNC macro being used. Have you changed the code? It's likely that something completely different is causing your problem, and the extra sync is masking the problem. -Becky - This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH 0/7] 86xx: New law setup and updated reginfo patchset
This patchset adds support for the new law setup method in fsl_law.c to 86xx. The existing platforms (mpc8641hpcn, mpc8610hpcd, and sbc8641d) are converted to use the new method. The old support is them removed. A print_laws() function is then added to fsl_law.c, and then used to implement a rudimentary reginfo for 86xx. The first 2 patches in this set supersede these 2 previous patches sent to the list: mpc86xx: Rearrange start.S to allow use of new law code mpc86xx: Convert to using new law setup code The new patches are the same, but with cleaned-up commit logs. This patchset contains: 86xx: Rearrange the sequence in start.S for 86xx 86xx: Support new law setup and convert mpc8641 86xx: Convert mpc8610hpcd to new law setup method 86xx: Convert sbc8641d to use new law setup code 86xx: Remove old style law setup code for 86xx 86xx: Add print_laws function to fsl_law.c 86xx: Add reginfo command for mpc86xx Cheers, Becky - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ ___ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
[U-Boot-Users] [PATCH 7/7] 86xx: Add reginfo command
Signed-off-by: Becky Bruce [EMAIL PROTECTED]
---
common/cmd_reginfo.c | 10 --
cpu/mpc86xx/cpu.c | 24 +++-
include/configs/MPC8610HPCD.h |1 +
include/configs/MPC8641HPCN.h |1 +
include/configs/sbc8641d.h|1 +
5 files changed, 34 insertions(+), 3 deletions(-)
diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c
index bb6aa30..11af22b 100644
--- a/common/cmd_reginfo.c
+++ b/common/cmd_reginfo.c
@@ -31,6 +31,8 @@
#include mpc5xx.h
#elif defined (CONFIG_MPC5200)
#include mpc5xxx.h
+#elif defined (CONFIG_MPC86xx)
+extern void mpc86xx_reginfo(void);
#endif
int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -329,14 +331,18 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc,
char *argv[])
*(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
printf (\tSDRAMCS1: %08X\n,
*(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
-#endif /* CONFIG_MPC5200 */
+#elif defined(CONFIG_MPC86xx)
+ mpc86xx_reginfo();
+#endif /* CONFIG_MPC86xx */
+
return 0;
}
/**/
#if ( defined(CONFIG_8xx) || defined(CONFIG_405GP) || \
- defined(CONFIG_405EP) || defined(CONFIG_MPC5200) ) \
+ defined(CONFIG_405EP) || defined(CONFIG_MPC5200) || \
+ defined(CONFIG_MPC86xx)) \
defined(CONFIG_CMD_REGINFO)
U_BOOT_CMD(
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index 11354d3..e1b3c52 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -27,6 +27,7 @@
#include command.h
#include asm/cache.h
#include mpc86xx.h
+#include asm/fsl_law.h
#if defined(CONFIG_OF_FLAT_TREE)
#include ft_build.h
@@ -324,6 +325,27 @@ ft_cpu_setup(void *blob, bd_t *bd)
if (p != NULL)
memcpy(p, bd-bi_enet3addr, 6);
#endif
+#endif /* CONFIG_OF_FLAT_TREE */
+
+/*
+ * Print out the state of various machine registers.
+ * Currently prints out LAWs and BR0/OR0
+ */
+void mpc86xx_reginfo(void)
+{
+ immap_t *immap = (immap_t *)CFG_IMMR;
+ ccsr_lbc_t *lbc = immap-im_lbc;
+
+ print_laws();
+
+ printf (Local Bus Controller Registers\n
+ \tBR0\t0x%08X\tOR0\t0x%08X \n, in_be32(lbc-br0),
in_be32(lbc-or0));
+ printf(\tBR1\t0x%08X\tOR1\t0x%08X \n, in_be32(lbc-br1),
in_be32(lbc-or1));
+ printf(\tBR2\t0x%08X\tOR2\t0x%08X \n, in_be32(lbc-br2),
in_be32(lbc-or2));
+ printf(\tBR3\t0x%08X\tOR3\t0x%08X \n, in_be32(lbc-br3),
in_be32(lbc-or3));
+ printf(\tBR4\t0x%08X\tOR4\t0x%08X \n, in_be32(lbc-br4),
in_be32(lbc-or4));
+ printf(\tBR5\t0x%08X\tOR5\t0x%08X \n, in_be32(lbc-br5),
in_be32(lbc-or5));
+ printf(\tBR6\t0x%08X\tOR6\t0x%08X \n, in_be32(lbc-br6),
in_be32(lbc-or6));
+ printf(\tBR7\t0x%08X\tOR7\t0x%08X \n, in_be32(lbc-br7),
in_be32(lbc-or7));
}
-#endif
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 92b4e7b..3920147 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -315,6 +315,7 @@
#define CONFIG_NET_MULTI
#define CONFIG_CMD_NET
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_CMD_REGINFO
#define CONFIG_ULI526X
#ifdef CONFIG_ULI526X
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 55ed9a6..a8d0077 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -537,6 +537,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
#if defined(CFG_RAMBOOT)
#undef CONFIG_CMD_ENV
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 1c1e826..1991a8c 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -480,6 +480,7 @@
#include config_cmd_default.h
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
--
1.5.3.7
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[U-Boot-Users] [PATCH 4/7] 86xx: Convert sbc8641d to use new law setup code.
Signed-off-by: Becky Bruce [EMAIL PROTECTED]
---
board/sbc8641d/Makefile|2 +-
board/sbc8641d/law.c | 58
include/configs/sbc8641d.h |1 +
3 files changed, 60 insertions(+), 1 deletions(-)
create mode 100644 board/sbc8641d/law.c
diff --git a/board/sbc8641d/Makefile b/board/sbc8641d/Makefile
index a90b725..8ecc951 100644
--- a/board/sbc8641d/Makefile
+++ b/board/sbc8641d/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o
+COBJS := $(BOARD).o law.o
SOBJS := init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c
new file mode 100644
index 000..d403873
--- /dev/null
+++ b/board/sbc8641d/law.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/fsl_law.h
+#include asm/mmu.h
+
+/*
+ * LAW (Local Access Window) configuration:
+ *
+ * 0x_ DDR 256M
+ * 0x1000_ DDR2256M
+ * 0x8000_ PCI1 MEM512M
+ * 0xa000_ PCI2 MEM512M
+ * 0xc000_ RapidIO 512M
+ * 0xe200_ PCI1 IO 16M
+ * 0xe300_ PCI2 IO 16M
+ * 0xf800_ CCSRBAR 2M
+ * 0xfe00_ FLASH (boot bank) 32M
+ *
+ */
+
+
+struct law_entry law_table[] = {
+ SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
+ SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+ SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+ SET_LAW_ENTRY(4, 0xf800, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
+ SET_LAW_ENTRY(5, CFG_PCI1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
+ SET_LAW_ENTRY(6, CFG_PCI2_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
+ SET_LAW_ENTRY(7, 0xfe00, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
+ SET_LAW_ENTRY(8, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
+ SET_LAW_ENTRY(9, CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 54eac38..1c1e826 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -53,6 +53,7 @@
#define CONFIG_PCI11 /* PCIE controler 1 (slot 1) */
#define CONFIG_PCI21 /* PCIE controler 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT1 /* Use common FSL init code */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
--
1.5.3.7
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