subject:"Re\: stm32 external SRAM"

Re: stm32 external SRAM

2019-06-25 Thread Christian Mauderer



On 25/06/2019 04:35, Jython wrote:
> printf("data  test return %04x\n", memTestDataBus(0x6802));
> 
>    
>     printf("addr bus test return %04x\n",
> memTestAddressBus(0x6800, 1024*1024));
> 
> 
> memtest all passed at application mode,
> 
> when SRAM init function moves to bsp_start_hook_1 then not work
> Can i do init_main_osc in bsp_start_hook_1?

The function seems not to use any odd stuff so most likely yes. But make
sure that it doesn't need some initialized memory. Maybe you'll have to
take a look at it with objdump to make sure of that.

> 
> On Tue, Jun 18, 2019 at 1:25 PM Christian Mauderer
>  > wrote:
> 
> On 18/06/2019 07:17, Jython wrote:
> >     void SRAM_fsmc_setup(void)
> >     {
> >     unsigned char FSMC_Bank;
> >         int i = 0;
> >
> >         // enable port clk
> >         RCC_AHB1ENR |= 0x0f << 3;
> >         RCC_AHB3ENR |= 1;  // enable fsmc clock
> >
> >         // af A0-A18
> >         stm32f4_gpio_config temp = STM32F4_PIN_FSMC(5, 0,
> >     STM32F4_GPIO_AF_FSMC);
> >        
> >
> >         for(i = 0; i < 6; i++)  //pf0-5
> >         {
> >            
> >            
> >             temp.fields.pin_first = STM32F4_GPIO_PIN(5, i);
> >             temp.fields.pin_last = STM32F4_GPIO_PIN(5, i);
> >             stm32f4_gpio_set_config();
> >         }
> >
> >         // A6 PF12
> >         temp.fields.pin_first = STM32F4_GPIO_PIN(5, 12);
> >         temp.fields.pin_last = STM32F4_GPIO_PIN(5, 12);
> >         stm32f4_gpio_set_config();
> >
> >         // A7 PF13
> >         temp.fields.pin_first = STM32F4_GPIO_PIN(5, 13);
> >         temp.fields.pin_last = STM32F4_GPIO_PIN(5, 13);
> >         stm32f4_gpio_set_config();
> >
> >         // A8 PF14
> >         temp.fields.pin_first = STM32F4_GPIO_PIN(5, 14);
> >         temp.fields.pin_last = STM32F4_GPIO_PIN(5, 14);
> >         stm32f4_gpio_set_config();
> >
> >         // A9 PF15
> >         temp.fields.pin_first = STM32F4_GPIO_PIN(5, 15);
> >         temp.fields.pin_last = STM32F4_GPIO_PIN(5, 15);
> >         stm32f4_gpio_set_config();
> >
> >
> >         // PG0-5    A10-A15
> >         for(i = 0; i < 6; i++)
> >         {
> >             temp.fields.pin_first = STM32F4_GPIO_PIN(6, i);
> >             temp.fields.pin_last = STM32F4_GPIO_PIN(6, i);
> >             stm32f4_gpio_set_config();
> >
> >         }
> >
> >
> >         // a16 - pd11
> >         temp.fields.pin_first = STM32F4_GPIO_PIN(3, 11);
> >         temp.fields.pin_last = STM32F4_GPIO_PIN(3, 11);
> >         stm32f4_gpio_set_config();
> >
> >         //A17
> >         temp.fields.pin_first = STM32F4_GPIO_PIN(3, 12);
> >         temp.fields.pin_last = STM32F4_GPIO_PIN(3, 12);
> >         stm32f4_gpio_set_config();
> >         //A18
> >         temp.fields.pin_first = STM32F4_GPIO_PIN(3, 13);
> >         temp.fields.pin_last = STM32F4_GPIO_PIN(3, 13);
> >         stm32f4_gpio_set_config();
> >        
> >         // address bus end
> >
> >
> >         // dbus setting
> >         // D0 PD14
> >         temp.fields.pin_first = STM32F4_GPIO_PIN(3, 14);
> >         temp.fields.pin_last = STM32F4_GPIO_PIN(3, 14);
> >         stm32f4_gpio_set_config();
> >
> >         // D1 PD15
> >         temp.fields.pin_first = STM32F4_GPIO_PIN(3, 15);
> >         temp.fields.pin_last = STM32F4_GPIO_PIN(3, 15);
> >         stm32f4_gpio_set_config();
> >
> >         // D2 PD0
> >         temp.fields.pin_first = STM32F4_GPIO_PIN(3, 0);
> >         temp.fields.pin_last = STM32F4_GPIO_PIN(3, 0);
> >         stm32f4_gpio_set_config();
> >
> >         // D3 PD1
> >         temp.fields.pin_first = STM32F4_GPIO_PIN(3, 1);
> >         temp.fields.pin_last = STM32F4_GPIO_PIN(3, 1);
> >         stm32f4_gpio_set_config();
> >
> >         // D4-12  Pe7
> >         for(i = 4; i < 13; i++)
> >         {
> >             temp.fields.pin_first = STM32F4_GPIO_PIN(4, i+3);
> >             temp.fields.pin_last = STM32F4_GPIO_PIN(4, i+3);
> >             stm32f4_gpio_set_config();
> >         }
> >
> >         // d13 14 15   pd8
> >         for(i = 13; i < 16; i++)
> >         {
> >             temp.fields.pin_first = STM32F4_GPIO_PIN(3, i-5);
> >             temp.fields.pin_last = STM32F4_GPIO_PIN(3, i-5);
> >             stm32f4_gpio_set_config();
> >
> >         }
> >
> >        
> >         //pg10 ne3
> >         temp.fields.pin_first = STM32F4_GPIO_PIN(6, 10);
> >         temp.fields.pin_last = STM32F4_GPIO_PIN(6, 10);
> >         stm32f4_gpio_set_config();
> >
> >

Re: stm32 external SRAM

2019-06-24 Thread Jython

>
> printf("data  test return %04x\n", memTestDataBus(0x6802));
>
>
> printf("addr bus test return %04x\n", memTestAddressBus(0x6800,
> 1024*1024));


memtest all passed at application mode,

when SRAM init function moves to bsp_start_hook_1 then not work
Can i do init_main_osc in bsp_start_hook_1?

On Tue, Jun 18, 2019 at 1:25 PM Christian Mauderer <
christian.maude...@embedded-brains.de> wrote:

> On 18/06/2019 07:17, Jython wrote:
> > void SRAM_fsmc_setup(void)
> > {
> > unsigned char FSMC_Bank;
> > int i = 0;
> >
> > // enable port clk
> > RCC_AHB1ENR |= 0x0f << 3;
> > RCC_AHB3ENR |= 1;  // enable fsmc clock
> >
> > // af A0-A18
> > stm32f4_gpio_config temp = STM32F4_PIN_FSMC(5, 0,
> > STM32F4_GPIO_AF_FSMC);
> >
> >
> > for(i = 0; i < 6; i++)  //pf0-5
> > {
> >
> >
> > temp.fields.pin_first = STM32F4_GPIO_PIN(5, i);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(5, i);
> > stm32f4_gpio_set_config();
> > }
> >
> > // A6 PF12
> > temp.fields.pin_first = STM32F4_GPIO_PIN(5, 12);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(5, 12);
> > stm32f4_gpio_set_config();
> >
> > // A7 PF13
> > temp.fields.pin_first = STM32F4_GPIO_PIN(5, 13);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(5, 13);
> > stm32f4_gpio_set_config();
> >
> > // A8 PF14
> > temp.fields.pin_first = STM32F4_GPIO_PIN(5, 14);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(5, 14);
> > stm32f4_gpio_set_config();
> >
> > // A9 PF15
> > temp.fields.pin_first = STM32F4_GPIO_PIN(5, 15);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(5, 15);
> > stm32f4_gpio_set_config();
> >
> >
> > // PG0-5A10-A15
> > for(i = 0; i < 6; i++)
> > {
> > temp.fields.pin_first = STM32F4_GPIO_PIN(6, i);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(6, i);
> > stm32f4_gpio_set_config();
> >
> > }
> >
> >
> > // a16 - pd11
> > temp.fields.pin_first = STM32F4_GPIO_PIN(3, 11);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(3, 11);
> > stm32f4_gpio_set_config();
> >
> > //A17
> > temp.fields.pin_first = STM32F4_GPIO_PIN(3, 12);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(3, 12);
> > stm32f4_gpio_set_config();
> > //A18
> > temp.fields.pin_first = STM32F4_GPIO_PIN(3, 13);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(3, 13);
> > stm32f4_gpio_set_config();
> >
> > // address bus end
> >
> >
> > // dbus setting
> > // D0 PD14
> > temp.fields.pin_first = STM32F4_GPIO_PIN(3, 14);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(3, 14);
> > stm32f4_gpio_set_config();
> >
> > // D1 PD15
> > temp.fields.pin_first = STM32F4_GPIO_PIN(3, 15);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(3, 15);
> > stm32f4_gpio_set_config();
> >
> > // D2 PD0
> > temp.fields.pin_first = STM32F4_GPIO_PIN(3, 0);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(3, 0);
> > stm32f4_gpio_set_config();
> >
> > // D3 PD1
> > temp.fields.pin_first = STM32F4_GPIO_PIN(3, 1);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(3, 1);
> > stm32f4_gpio_set_config();
> >
> > // D4-12  Pe7
> > for(i = 4; i < 13; i++)
> > {
> > temp.fields.pin_first = STM32F4_GPIO_PIN(4, i+3);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(4, i+3);
> > stm32f4_gpio_set_config();
> > }
> >
> > // d13 14 15   pd8
> > for(i = 13; i < 16; i++)
> > {
> > temp.fields.pin_first = STM32F4_GPIO_PIN(3, i-5);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(3, i-5);
> > stm32f4_gpio_set_config();
> >
> > }
> >
> >
> > //pg10 ne3
> > temp.fields.pin_first = STM32F4_GPIO_PIN(6, 10);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(6, 10);
> > stm32f4_gpio_set_config();
> >
> > //NBL pe0 pe1
> > temp.fields.pin_first = STM32F4_GPIO_PIN(4, 0);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(4, 0);
> > stm32f4_gpio_set_config();
> >
> > temp.fields.pin_first = STM32F4_GPIO_PIN(4, 1);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(4, 1);
> > stm32f4_gpio_set_config();
> >
> > //pd4 NOE
> > temp.fields.pin_first = STM32F4_GPIO_PIN(3, 4);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(3, 4);
> > stm32f4_gpio_set_config();
> >
> > //pd5 NWE
> > temp.fields.pin_first = STM32F4_GPIO_PIN(3, 5);
> > temp.fields.pin_last = STM32F4_GPIO_PIN(3, 5);
> > stm32f4_gpio_set_config();
> >
> > //pd6 NWAIT
> > temp.fields.pin_first = STM32F4_GPIO_PIN(3, 6);
> >

Re: stm32 external SRAM

2019-06-17 Thread Jython

>
> void SRAM_fsmc_setup(void)
> {
> unsigned char FSMC_Bank;
> int i = 0;
>
> // enable port clk
> RCC_AHB1ENR |= 0x0f << 3;
> RCC_AHB3ENR |= 1;  // enable fsmc clock
>
> // af A0-A18
> stm32f4_gpio_config temp = STM32F4_PIN_FSMC(5, 0,
> STM32F4_GPIO_AF_FSMC);
>
>
> for(i = 0; i < 6; i++)  //pf0-5
> {
>
>
> temp.fields.pin_first = STM32F4_GPIO_PIN(5, i);
> temp.fields.pin_last = STM32F4_GPIO_PIN(5, i);
> stm32f4_gpio_set_config();
> }
>
> // A6 PF12
> temp.fields.pin_first = STM32F4_GPIO_PIN(5, 12);
> temp.fields.pin_last = STM32F4_GPIO_PIN(5, 12);
> stm32f4_gpio_set_config();
>
> // A7 PF13
> temp.fields.pin_first = STM32F4_GPIO_PIN(5, 13);
> temp.fields.pin_last = STM32F4_GPIO_PIN(5, 13);
> stm32f4_gpio_set_config();
>
> // A8 PF14
> temp.fields.pin_first = STM32F4_GPIO_PIN(5, 14);
> temp.fields.pin_last = STM32F4_GPIO_PIN(5, 14);
> stm32f4_gpio_set_config();
>
> // A9 PF15
> temp.fields.pin_first = STM32F4_GPIO_PIN(5, 15);
> temp.fields.pin_last = STM32F4_GPIO_PIN(5, 15);
> stm32f4_gpio_set_config();
>
>
> // PG0-5A10-A15
> for(i = 0; i < 6; i++)
> {
> temp.fields.pin_first = STM32F4_GPIO_PIN(6, i);
> temp.fields.pin_last = STM32F4_GPIO_PIN(6, i);
> stm32f4_gpio_set_config();
>
> }
>
>
> // a16 - pd11
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 11);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 11);
> stm32f4_gpio_set_config();
>
> //A17
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 12);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 12);
> stm32f4_gpio_set_config();
> //A18
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 13);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 13);
> stm32f4_gpio_set_config();
>
> // address bus end
>
>
> // dbus setting
> // D0 PD14
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 14);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 14);
> stm32f4_gpio_set_config();
>
> // D1 PD15
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 15);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 15);
> stm32f4_gpio_set_config();
>
> // D2 PD0
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 0);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 0);
> stm32f4_gpio_set_config();
>
> // D3 PD1
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 1);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 1);
> stm32f4_gpio_set_config();
>
> // D4-12  Pe7
> for(i = 4; i < 13; i++)
> {
> temp.fields.pin_first = STM32F4_GPIO_PIN(4, i+3);
> temp.fields.pin_last = STM32F4_GPIO_PIN(4, i+3);
> stm32f4_gpio_set_config();
> }
>
> // d13 14 15   pd8
> for(i = 13; i < 16; i++)
> {
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, i-5);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, i-5);
> stm32f4_gpio_set_config();
>
> }
>
>
> //pg10 ne3
> temp.fields.pin_first = STM32F4_GPIO_PIN(6, 10);
> temp.fields.pin_last = STM32F4_GPIO_PIN(6, 10);
> stm32f4_gpio_set_config();
>
> //NBL pe0 pe1
> temp.fields.pin_first = STM32F4_GPIO_PIN(4, 0);
> temp.fields.pin_last = STM32F4_GPIO_PIN(4, 0);
> stm32f4_gpio_set_config();
>
> temp.fields.pin_first = STM32F4_GPIO_PIN(4, 1);
> temp.fields.pin_last = STM32F4_GPIO_PIN(4, 1);
> stm32f4_gpio_set_config();
>
> //pd4 NOE
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 4);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 4);
> stm32f4_gpio_set_config();
>
> //pd5 NWE
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 5);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 5);
> stm32f4_gpio_set_config();
>
> //pd6 NWAIT
> temp.fields.pin_first = STM32F4_GPIO_PIN(3, 6);
> temp.fields.pin_last = STM32F4_GPIO_PIN(3, 6);
> stm32f4_gpio_set_config();
>
>
>
> //The SRAM is connected to the second FSMC BANK (NE2)
> FSMC_Bank = 1;
>
> STM32_FSMC_BCR3 |= 1<<12;
> STM32_FSMC_BCR3 |= 1<<4;  //16bit
>
> //
> STM32_FSMC_BTR3 |= 1<<8;  // Data-phase duration DATAST
> //STM32_FSMC_BTR3 |= ~(uint32_t)(1<<4);
> //STM32_FSMC_BTR3 &= ~(uint32_t)1;
> STM32_FSMC_BTR3 &= 0xff00;
>
>
> STM32_FSMC_BWTR3 = 0x0FFF;
> STM32_FSMC_BCR3 |= 1;  //memory bank enable
>
> #if 0
> /
> FSMC_Bank1->BTCR[FSMC_Bank+1] = (FSMC_BTR2_ADDSET_1) | (FSMC_BTR2_DATAST_0
> | FSMC_BTR2_DATAST_1);
>
>
>
> #endif
> }


  it is my later application code, i will try it ,  thanks!

On Tue, Jun 18, 2019 at 1:09 PM Christian Mauderer <
christian.maude...@embedded-brains.de> wrote:

> On 18/06/2019 03:25, Jython wrote:
> > my linkscmd is
> https://gist.github.com/goog/aad6dae4c418255dd6fb2b23bf2e6f08
> >
> > void BSP_START_TEXT_SECTION bsp_start_hook_1(void)
> > {
> >   SRAM_fsmc_setup();
> >   bsp_start_copy_sections();
> >   bsp_start_clear_bss();
> >
> >   /* At this point we

Re: stm32 external SRAM

2019-06-17 Thread Christian Mauderer

On 18/06/2019 03:25, Jython wrote:
> my linkscmd is https://gist.github.com/goog/aad6dae4c418255dd6fb2b23bf2e6f08
> 
> void BSP_START_TEXT_SECTION bsp_start_hook_1(void)
> {
>   SRAM_fsmc_setup();
>   bsp_start_copy_sections();
>   bsp_start_clear_bss();
> 
>   /* At this point we can use objects outside the .start section */
> }
> 
> 
> but now my code run disordered

Which one?

The SRAM_fsmc_setup()? In that case please note that you are in a very
early initialization step. So most system services won't work and global
variables are not initialized yet.

Or your later application code? In that case: Did you do a memory test
to check your RAM initialization? For example the routines from Michael
Barr from here work well:
http://www.esacademy.com/en/library/technical-articles-and-documents/miscellaneous/software-based-memory-testing.html

> 
> On Mon, Jun 17, 2019 at 2:45 PM Christian Mauderer
>  > wrote:
> 
> If you put any sections into the external RAM that need initialization,
> you have to init the RAM before the BSP copies it's sections. The STM32
> BSP copies it's sections in bsp_start_hook_1(). So either put it in
> bsp_start_hook_0 or in bsp_start_hook_1 before the copy_section calls.
> Attention: You can't use much in these functions. They are in a very
> early initialization stage. So be careful what you put there.
> 
> If you only want malloc to allocate memory from there, there might is a
> later point where you can do that.
> 
> On 17/06/2019 08:32, Jython wrote:
> > Thank you and the example! that is to say put extern sram init in
> > bsp_start( void ) function?
> >
> > On Mon, Jun 17, 2019 at 1:04 PM Christian Mauderer
> >  
> >  >> wrote:
> >
> >     On 17/06/2019 03:05, Jython wrote:
> >     > STM32:
> >     >     112KB at 2000 
> >     >     16KB at 2001 C000
> >     >
> >     > external sram : 1MB at 0x6800
> >     >
> >     >  does MEMORY layout support RAM2?
> >
> >     Hello Jython,
> >
> >     you can distribute the regions to the two RAMs. For example
> this BSP
> >     does that:
> >
> >   
>  
> https://git.rtems.org/rtems/tree/bsps/arm/lpc32xx/start/linkcmds.lpc32xx_phycore
> >
> >     Please note that you have to take a detailed look at what is
> used till
> >     your external RAM initialization run and what not. But if you
> put your
> >     external RAM initialization in an early enough step, you
> shouldn't get
> >     problems with that.
> >
> >     Best regards
> >
> >     Christian
> >
> >     >
> >     > On Fri, Jun 14, 2019 at 10:13 PM Christian Mauderer
> >     >  
> >      >
> >     >  
> >       >     >
> >     >     If you have already added the chip and it is initialized
> >     during startup,
> >     >     you most likely have to add a section for it in your linker
> >     command
> >     >     file. Depending on where your internal RAM is located and
> >     where the
> >     >     external one is: If they are continuous that can be enough.
> >     >
> >     >     Best regards
> >     >
> >     >     Christian
> >     >
> >     >     On 14/06/2019 04:42, Jython wrote:
> >     >     > we have added 1M ram by FSMC,  and want to manage it by
> >     system malloc
> >     >     > controler
> >     >     >
> >     >     > On Fri, Jun 14, 2019 at 10:26 AM Mr. Andrei Chichak
> >     >     mailto:gro...@chichak.ca>
> >
> >     
> >>
> >     >     > 
> >
> >     
>  wrote:
> >     >     >
> >     >     >     A 407 doesn’t normally have external RAM.
> >     >     >
> >     >     >     ARMs have flash at 0 and the 407 has RAM at 0x2000
> 
> >     as you
> >     >     >     discussed earlier.
> >     >     >
> >     >     >     If you want to work with external flash or RAM,
> you have

Re: stm32 external SRAM

2019-06-17 Thread Jython

my linkscmd is https://gist.github.com/goog/aad6dae4c418255dd6fb2b23bf2e6f08

void BSP_START_TEXT_SECTION bsp_start_hook_1(void)
> {
>   SRAM_fsmc_setup();
>   bsp_start_copy_sections();
>   bsp_start_clear_bss();
>
>   /* At this point we can use objects outside the .start section */
> }
>

but now my code run disordered

On Mon, Jun 17, 2019 at 2:45 PM Christian Mauderer <
christian.maude...@embedded-brains.de> wrote:

> If you put any sections into the external RAM that need initialization,
> you have to init the RAM before the BSP copies it's sections. The STM32
> BSP copies it's sections in bsp_start_hook_1(). So either put it in
> bsp_start_hook_0 or in bsp_start_hook_1 before the copy_section calls.
> Attention: You can't use much in these functions. They are in a very
> early initialization stage. So be careful what you put there.
>
> If you only want malloc to allocate memory from there, there might is a
> later point where you can do that.
>
> On 17/06/2019 08:32, Jython wrote:
> > Thank you and the example! that is to say put extern sram init in
> > bsp_start( void ) function?
> >
> > On Mon, Jun 17, 2019 at 1:04 PM Christian Mauderer
> >  > > wrote:
> >
> > On 17/06/2019 03:05, Jython wrote:
> > > STM32:
> > > 112KB at 2000 
> > > 16KB at 2001 C000
> > >
> > > external sram : 1MB at 0x6800
> > >
> > >  does MEMORY layout support RAM2?
> >
> > Hello Jython,
> >
> > you can distribute the regions to the two RAMs. For example this BSP
> > does that:
> >
> >
> https://git.rtems.org/rtems/tree/bsps/arm/lpc32xx/start/linkcmds.lpc32xx_phycore
> >
> > Please note that you have to take a detailed look at what is used
> till
> > your external RAM initialization run and what not. But if you put
> your
> > external RAM initialization in an early enough step, you shouldn't
> get
> > problems with that.
> >
> > Best regards
> >
> > Christian
> >
> > >
> > > On Fri, Jun 14, 2019 at 10:13 PM Christian Mauderer
> > >  > 
> > >  > >> wrote:
> > >
> > > If you have already added the chip and it is initialized
> > during startup,
> > > you most likely have to add a section for it in your linker
> > command
> > > file. Depending on where your internal RAM is located and
> > where the
> > > external one is: If they are continuous that can be enough.
> > >
> > > Best regards
> > >
> > > Christian
> > >
> > > On 14/06/2019 04:42, Jython wrote:
> > > > we have added 1M ram by FSMC,  and want to manage it by
> > system malloc
> > > > controler
> > > >
> > > > On Fri, Jun 14, 2019 at 10:26 AM Mr. Andrei Chichak
> > > mailto:gro...@chichak.ca>
> > >
> > > > 
> >  > > >
> > > > A 407 doesn’t normally have external RAM.
> > > >
> > > > ARMs have flash at 0 and the 407 has RAM at 0x2000 
> > as you
> > > > discussed earlier.
> > > >
> > > > If you want to work with external flash or RAM, you have
> > to set up
> > > > the FSMC or FMC to support it, but that isn’t a part of
> > the dev
> > > > board that Sebastian used for the BSP port.
> > > >
> > > > The external memory is going to be very specific to your
> > board.
> > > > Which board are you working with?
> > > >
> > > > A
> > > >
> > > > > On 2019-June-13, at 06:23, Christian Mauderer
> > > >  > 
> > >  > >
> > > >  > 
> > >  >  > > > >
> > > > > On 05/06/2019 02:55, Jython wrote:
> > > > >> Hello!
> > > > >>
> > > > >> 2. In the normal (non-debugging) case, the linker
> > > script still
> > > > >>places the
> > > > >>
> > > > >>.text section near zero, but places the start of
> the
> > > .data and
> > > > .bss
> > > > >>sections at the start location of the MPC555's
> > internal
> > > RAM. The
> > > > >>system startup code

Re: stm32 external SRAM

2019-06-17 Thread Christian Mauderer

If you put any sections into the external RAM that need initialization,
you have to init the RAM before the BSP copies it's sections. The STM32
BSP copies it's sections in bsp_start_hook_1(). So either put it in
bsp_start_hook_0 or in bsp_start_hook_1 before the copy_section calls.
Attention: You can't use much in these functions. They are in a very
early initialization stage. So be careful what you put there.

If you only want malloc to allocate memory from there, there might is a
later point where you can do that.

On 17/06/2019 08:32, Jython wrote:
> Thank you and the example! that is to say put extern sram init in
> bsp_start( void ) function?
> 
> On Mon, Jun 17, 2019 at 1:04 PM Christian Mauderer
>  > wrote:
> 
> On 17/06/2019 03:05, Jython wrote:
> > STM32:
> >     112KB at 2000 
> >     16KB at 2001 C000
> >
> > external sram : 1MB at 0x6800
> >
> >  does MEMORY layout support RAM2?
> 
> Hello Jython,
> 
> you can distribute the regions to the two RAMs. For example this BSP
> does that:
> 
> 
> https://git.rtems.org/rtems/tree/bsps/arm/lpc32xx/start/linkcmds.lpc32xx_phycore
> 
> Please note that you have to take a detailed look at what is used till
> your external RAM initialization run and what not. But if you put your
> external RAM initialization in an early enough step, you shouldn't get
> problems with that.
> 
> Best regards
> 
> Christian
> 
> >
> > On Fri, Jun 14, 2019 at 10:13 PM Christian Mauderer
> >  
> >  >> wrote:
> >
> >     If you have already added the chip and it is initialized
> during startup,
> >     you most likely have to add a section for it in your linker
> command
> >     file. Depending on where your internal RAM is located and
> where the
> >     external one is: If they are continuous that can be enough.
> >
> >     Best regards
> >
> >     Christian
> >
> >     On 14/06/2019 04:42, Jython wrote:
> >     > we have added 1M ram by FSMC,  and want to manage it by
> system malloc
> >     > controler
> >     >
> >     > On Fri, Jun 14, 2019 at 10:26 AM Mr. Andrei Chichak
> >     mailto:gro...@chichak.ca>
> >
> >     > 
>  >     >
> >     >     A 407 doesn’t normally have external RAM.
> >     >
> >     >     ARMs have flash at 0 and the 407 has RAM at 0x2000 
> as you
> >     >     discussed earlier.
> >     >
> >     >     If you want to work with external flash or RAM, you have
> to set up
> >     >     the FSMC or FMC to support it, but that isn’t a part of
> the dev
> >     >     board that Sebastian used for the BSP port.
> >     >
> >     >     The external memory is going to be very specific to your
> board.
> >     >     Which board are you working with?
> >     >
> >     >     A
> >     >
> >     >     > On 2019-June-13, at 06:23, Christian Mauderer
> >     >      
> >      >
> >     >      
> >       >     >     >
> >     >     > On 05/06/2019 02:55, Jython wrote:
> >     >     >> Hello!
> >     >     >>
> >     >     >>     2. In the normal (non-debugging) case, the linker
> >     script still
> >     >     >>        places the
> >     >     >>
> >     >     >>    .text section near zero, but places the start of the
> >     .data and
> >     >     .bss
> >     >     >>    sections at the start location of the MPC555's
> internal
> >     RAM. The
> >     >     >>    system startup code then configures the external
> RAM just
> >     >     after the
> >     >     >>    internal RAM in memory, forming one large block
> from the
> >     two RAM
> >     >     >>    devices.
> >     >     >>
> >     >     >> from https://devel.rtems.org/wiki/TBR/BSP/Ss555
> >     >     >>
> >     >     >> but i dont know how to configure the external RAM just
> >     after the
> >     >     >> internal RAM in memory?
> >     >     >> hope you could give me some guide!
> >     >     >> 
> >     >     >>
> >     >     >
> >     >     > Hello Jython,
> >     >     >
> >

Re: stm32 external SRAM

2019-06-17 Thread Jython

Thank you and the example! that is to say put extern sram init in
bsp_start( void ) function?

On Mon, Jun 17, 2019 at 1:04 PM Christian Mauderer <
christian.maude...@embedded-brains.de> wrote:

> On 17/06/2019 03:05, Jython wrote:
> > STM32:
> > 112KB at 2000 
> > 16KB at 2001 C000
> >
> > external sram : 1MB at 0x6800
> >
> >  does MEMORY layout support RAM2?
>
> Hello Jython,
>
> you can distribute the regions to the two RAMs. For example this BSP
> does that:
>
>
> https://git.rtems.org/rtems/tree/bsps/arm/lpc32xx/start/linkcmds.lpc32xx_phycore
>
> Please note that you have to take a detailed look at what is used till
> your external RAM initialization run and what not. But if you put your
> external RAM initialization in an early enough step, you shouldn't get
> problems with that.
>
> Best regards
>
> Christian
>
> >
> > On Fri, Jun 14, 2019 at 10:13 PM Christian Mauderer
> >  > > wrote:
> >
> > If you have already added the chip and it is initialized during
> startup,
> > you most likely have to add a section for it in your linker command
> > file. Depending on where your internal RAM is located and where the
> > external one is: If they are continuous that can be enough.
> >
> > Best regards
> >
> > Christian
> >
> > On 14/06/2019 04:42, Jython wrote:
> > > we have added 1M ram by FSMC,  and want to manage it by system
> malloc
> > > controler
> > >
> > > On Fri, Jun 14, 2019 at 10:26 AM Mr. Andrei Chichak
> > mailto:gro...@chichak.ca>
> > > >> wrote:
> > >
> > > A 407 doesn’t normally have external RAM.
> > >
> > > ARMs have flash at 0 and the 407 has RAM at 0x2000  as you
> > > discussed earlier.
> > >
> > > If you want to work with external flash or RAM, you have to
> set up
> > > the FSMC or FMC to support it, but that isn’t a part of the dev
> > > board that Sebastian used for the BSP port.
> > >
> > > The external memory is going to be very specific to your board.
> > > Which board are you working with?
> > >
> > > A
> > >
> > > > On 2019-June-13, at 06:23, Christian Mauderer
> > >  > 
> > >  > >> wrote:
> > > >
> > > > On 05/06/2019 02:55, Jython wrote:
> > > >> Hello!
> > > >>
> > > >> 2. In the normal (non-debugging) case, the linker
> > script still
> > > >>places the
> > > >>
> > > >>.text section near zero, but places the start of the
> > .data and
> > > .bss
> > > >>sections at the start location of the MPC555's internal
> > RAM. The
> > > >>system startup code then configures the external RAM just
> > > after the
> > > >>internal RAM in memory, forming one large block from the
> > two RAM
> > > >>devices.
> > > >>
> > > >> from https://devel.rtems.org/wiki/TBR/BSP/Ss555
> > > >>
> > > >> but i dont know how to configure the external RAM just
> > after the
> > > >> internal RAM in memory?
> > > >> hope you could give me some guide!
> > > >>
> > > >>
> > > >
> > > > Hello Jython,
> > > >
> > > > the documentation you linked is for an MPC. But your subject
> > line
> > > > mentions an STM32. What controller / BSP are you using?
> > > >
> > > > Best regards
> > > >
> > > > Christian Mauderer
> > > > --
> > > > 
> > > > embedded brains GmbH
> > > > Herr Christian Mauderer
> > > > Dornierstr. 4
> > > > D-82178 Puchheim
> > > > Germany
> > > > email: christian.maude...@embedded-brains.de
> > 
> > >  > >
> > > > Phone: +49-89-18 94 741 - 18
> > > > Fax:   +49-89-18 94 741 - 08
> > > > PGP: Public key available on request.
> > > >
> > > > Diese Nachricht ist keine geschäftliche Mitteilung im Sinne
> > des EHUG.
> > > > ___
> > > > users mailing list
> > > > users@rtems.org 
> > >
> > > > http://lists.rtems.org/mailman/listinfo/users
> > >
> > >
> > > ___
> > > users mailing list
> > > users@rtems.org 
> > >

Re: stm32 external SRAM

2019-06-16 Thread Christian Mauderer

On 17/06/2019 03:05, Jython wrote:
> STM32:
>     112KB at 2000 
>     16KB at 2001 C000
> 
> external sram : 1MB at 0x6800
> 
>  does MEMORY layout support RAM2?

Hello Jython,

you can distribute the regions to the two RAMs. For example this BSP
does that:

https://git.rtems.org/rtems/tree/bsps/arm/lpc32xx/start/linkcmds.lpc32xx_phycore

Please note that you have to take a detailed look at what is used till
your external RAM initialization run and what not. But if you put your
external RAM initialization in an early enough step, you shouldn't get
problems with that.

Best regards

Christian

> 
> On Fri, Jun 14, 2019 at 10:13 PM Christian Mauderer
>  > wrote:
> 
> If you have already added the chip and it is initialized during startup,
> you most likely have to add a section for it in your linker command
> file. Depending on where your internal RAM is located and where the
> external one is: If they are continuous that can be enough.
> 
> Best regards
> 
> Christian
> 
> On 14/06/2019 04:42, Jython wrote:
> > we have added 1M ram by FSMC,  and want to manage it by system malloc
> > controler
> >
> > On Fri, Jun 14, 2019 at 10:26 AM Mr. Andrei Chichak
> mailto:gro...@chichak.ca>
> > >> wrote:
> >
> >     A 407 doesn’t normally have external RAM.
> >
> >     ARMs have flash at 0 and the 407 has RAM at 0x2000  as you
> >     discussed earlier.
> >
> >     If you want to work with external flash or RAM, you have to set up
> >     the FSMC or FMC to support it, but that isn’t a part of the dev
> >     board that Sebastian used for the BSP port.
> >
> >     The external memory is going to be very specific to your board.
> >     Which board are you working with?
> >
> >     A
> >
> >     > On 2019-June-13, at 06:23, Christian Mauderer
> >      
> >      >> wrote:
> >     >
> >     > On 05/06/2019 02:55, Jython wrote:
> >     >> Hello!
> >     >>
> >     >>     2. In the normal (non-debugging) case, the linker
> script still
> >     >>        places the
> >     >>
> >     >>    .text section near zero, but places the start of the
> .data and
> >     .bss
> >     >>    sections at the start location of the MPC555's internal
> RAM. The
> >     >>    system startup code then configures the external RAM just
> >     after the
> >     >>    internal RAM in memory, forming one large block from the
> two RAM
> >     >>    devices.
> >     >>
> >     >> from https://devel.rtems.org/wiki/TBR/BSP/Ss555
> >     >>
> >     >> but i dont know how to configure the external RAM just
> after the
> >     >> internal RAM in memory?
> >     >> hope you could give me some guide!
> >     >> 
> >     >>
> >     >
> >     > Hello Jython,
> >     >
> >     > the documentation you linked is for an MPC. But your subject
> line
> >     > mentions an STM32. What controller / BSP are you using?
> >     >
> >     > Best regards
> >     >
> >     > Christian Mauderer
> >     > --
> >     > 
> >     > embedded brains GmbH
> >     > Herr Christian Mauderer
> >     > Dornierstr. 4
> >     > D-82178 Puchheim
> >     > Germany
> >     > email: christian.maude...@embedded-brains.de
> 
> >      >
> >     > Phone: +49-89-18 94 741 - 18
> >     > Fax:   +49-89-18 94 741 - 08
> >     > PGP: Public key available on request.
> >     >
> >     > Diese Nachricht ist keine geschäftliche Mitteilung im Sinne
> des EHUG.
> >     > ___
> >     > users mailing list
> >     > users@rtems.org 
> >
> >     > http://lists.rtems.org/mailman/listinfo/users
> >
> >
> > ___
> > users mailing list
> > users@rtems.org 
> > http://lists.rtems.org/mailman/listinfo/users
> >
> 
> -- 
> 
> embedded brains GmbH
> Herr Christian Mauderer
> Dornierstr. 4
> D-82178 Puchheim
> Germany
> email: christian.maude...@embedded-brains.de
> 
> Phone: +49-89-18 94 741 - 18
> Fax:   +49-89-18 94 741 - 08
> PGP: Public key available on request.
> 
> Diese

Re: stm32 external SRAM

2019-06-16 Thread Jython

STM32:
112KB at 2000 
16KB at 2001 C000

external sram : 1MB at 0x6800

 does MEMORY layout support RAM2?

On Fri, Jun 14, 2019 at 10:13 PM Christian Mauderer <
christian.maude...@embedded-brains.de> wrote:

> If you have already added the chip and it is initialized during startup,
> you most likely have to add a section for it in your linker command
> file. Depending on where your internal RAM is located and where the
> external one is: If they are continuous that can be enough.
>
> Best regards
>
> Christian
>
> On 14/06/2019 04:42, Jython wrote:
> > we have added 1M ram by FSMC,  and want to manage it by system malloc
> > controler
> >
> > On Fri, Jun 14, 2019 at 10:26 AM Mr. Andrei Chichak  > > wrote:
> >
> > A 407 doesn’t normally have external RAM.
> >
> > ARMs have flash at 0 and the 407 has RAM at 0x2000  as you
> > discussed earlier.
> >
> > If you want to work with external flash or RAM, you have to set up
> > the FSMC or FMC to support it, but that isn’t a part of the dev
> > board that Sebastian used for the BSP port.
> >
> > The external memory is going to be very specific to your board.
> > Which board are you working with?
> >
> > A
> >
> > > On 2019-June-13, at 06:23, Christian Mauderer
> >  > > wrote:
> > >
> > > On 05/06/2019 02:55, Jython wrote:
> > >> Hello!
> > >>
> > >> 2. In the normal (non-debugging) case, the linker script still
> > >>places the
> > >>
> > >>.text section near zero, but places the start of the .data and
> > .bss
> > >>sections at the start location of the MPC555's internal RAM.
> The
> > >>system startup code then configures the external RAM just
> > after the
> > >>internal RAM in memory, forming one large block from the two
> RAM
> > >>devices.
> > >>
> > >> from https://devel.rtems.org/wiki/TBR/BSP/Ss555
> > >>
> > >> but i dont know how to configure the external RAM just after the
> > >> internal RAM in memory?
> > >> hope you could give me some guide!
> > >>
> > >>
> > >
> > > Hello Jython,
> > >
> > > the documentation you linked is for an MPC. But your subject line
> > > mentions an STM32. What controller / BSP are you using?
> > >
> > > Best regards
> > >
> > > Christian Mauderer
> > > --
> > > 
> > > embedded brains GmbH
> > > Herr Christian Mauderer
> > > Dornierstr. 4
> > > D-82178 Puchheim
> > > Germany
> > > email: christian.maude...@embedded-brains.de
> > 
> > > Phone: +49-89-18 94 741 - 18
> > > Fax:   +49-89-18 94 741 - 08
> > > PGP: Public key available on request.
> > >
> > > Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des
> EHUG.
> > > ___
> > > users mailing list
> > > users@rtems.org 
> > > http://lists.rtems.org/mailman/listinfo/users
> >
> >
> > ___
> > users mailing list
> > users@rtems.org
> > http://lists.rtems.org/mailman/listinfo/users
> >
>
> --
> 
> embedded brains GmbH
> Herr Christian Mauderer
> Dornierstr. 4
> D-82178 Puchheim
> Germany
> email: christian.maude...@embedded-brains.de
> Phone: +49-89-18 94 741 - 18
> Fax:   +49-89-18 94 741 - 08
> PGP: Public key available on request.
>
> Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
>
___
users mailing list
users@rtems.org
http://lists.rtems.org/mailman/listinfo/users

Re: stm32 external SRAM

2019-06-14 Thread Christian Mauderer

If you have already added the chip and it is initialized during startup,
you most likely have to add a section for it in your linker command
file. Depending on where your internal RAM is located and where the
external one is: If they are continuous that can be enough.

Best regards

Christian

On 14/06/2019 04:42, Jython wrote:
> we have added 1M ram by FSMC,  and want to manage it by system malloc
> controler
> 
> On Fri, Jun 14, 2019 at 10:26 AM Mr. Andrei Chichak  > wrote:
> 
> A 407 doesn’t normally have external RAM.
> 
> ARMs have flash at 0 and the 407 has RAM at 0x2000  as you
> discussed earlier.
> 
> If you want to work with external flash or RAM, you have to set up
> the FSMC or FMC to support it, but that isn’t a part of the dev
> board that Sebastian used for the BSP port.
> 
> The external memory is going to be very specific to your board.
> Which board are you working with?
> 
> A
> 
> > On 2019-June-13, at 06:23, Christian Mauderer
>  > wrote:
> >
> > On 05/06/2019 02:55, Jython wrote:
> >> Hello!
> >>
> >>     2. In the normal (non-debugging) case, the linker script still
> >>        places the
> >>
> >>    .text section near zero, but places the start of the .data and
> .bss
> >>    sections at the start location of the MPC555's internal RAM. The
> >>    system startup code then configures the external RAM just
> after the
> >>    internal RAM in memory, forming one large block from the two RAM
> >>    devices.
> >>
> >> from https://devel.rtems.org/wiki/TBR/BSP/Ss555
> >>
> >> but i dont know how to configure the external RAM just after the
> >> internal RAM in memory?
> >> hope you could give me some guide!
> >> 
> >>
> >
> > Hello Jython,
> >
> > the documentation you linked is for an MPC. But your subject line
> > mentions an STM32. What controller / BSP are you using?
> >
> > Best regards
> >
> > Christian Mauderer
> > --
> > 
> > embedded brains GmbH
> > Herr Christian Mauderer
> > Dornierstr. 4
> > D-82178 Puchheim
> > Germany
> > email: christian.maude...@embedded-brains.de
> 
> > Phone: +49-89-18 94 741 - 18
> > Fax:   +49-89-18 94 741 - 08
> > PGP: Public key available on request.
> >
> > Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
> > ___
> > users mailing list
> > users@rtems.org 
> > http://lists.rtems.org/mailman/listinfo/users
> 
> 
> ___
> users mailing list
> users@rtems.org
> http://lists.rtems.org/mailman/listinfo/users
> 

-- 

embedded brains GmbH
Herr Christian Mauderer
Dornierstr. 4
D-82178 Puchheim
Germany
email: christian.maude...@embedded-brains.de
Phone: +49-89-18 94 741 - 18
Fax:   +49-89-18 94 741 - 08
PGP: Public key available on request.

Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
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Re: stm32 external SRAM

2019-06-13 Thread Jython

we have added 1M ram by FSMC,  and want to manage it by system malloc
controler

On Fri, Jun 14, 2019 at 10:26 AM Mr. Andrei Chichak 
wrote:

> A 407 doesn’t normally have external RAM.
>
> ARMs have flash at 0 and the 407 has RAM at 0x2000  as you discussed
> earlier.
>
> If you want to work with external flash or RAM, you have to set up the
> FSMC or FMC to support it, but that isn’t a part of the dev board that
> Sebastian used for the BSP port.
>
> The external memory is going to be very specific to your board. Which
> board are you working with?
>
> A
>
> > On 2019-June-13, at 06:23, Christian Mauderer <
> christian.maude...@embedded-brains.de> wrote:
> >
> > On 05/06/2019 02:55, Jython wrote:
> >> Hello!
> >>
> >> 2. In the normal (non-debugging) case, the linker script still
> >>places the
> >>
> >>.text section near zero, but places the start of the .data and .bss
> >>sections at the start location of the MPC555's internal RAM. The
> >>system startup code then configures the external RAM just after the
> >>internal RAM in memory, forming one large block from the two RAM
> >>devices.
> >>
> >> from https://devel.rtems.org/wiki/TBR/BSP/Ss555
> >>
> >> but i dont know how to configure the external RAM just after the
> >> internal RAM in memory?
> >> hope you could give me some guide!
> >>
> >>
> >
> > Hello Jython,
> >
> > the documentation you linked is for an MPC. But your subject line
> > mentions an STM32. What controller / BSP are you using?
> >
> > Best regards
> >
> > Christian Mauderer
> > --
> > 
> > embedded brains GmbH
> > Herr Christian Mauderer
> > Dornierstr. 4
> > D-82178 Puchheim
> > Germany
> > email: christian.maude...@embedded-brains.de
> > Phone: +49-89-18 94 741 - 18
> > Fax:   +49-89-18 94 741 - 08
> > PGP: Public key available on request.
> >
> > Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
> > ___
> > users mailing list
> > users@rtems.org
> > http://lists.rtems.org/mailman/listinfo/users
>
>
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Re: stm32 external SRAM

2019-06-13 Thread Mr. Andrei Chichak

A 407 doesn’t normally have external RAM.

ARMs have flash at 0 and the 407 has RAM at 0x2000  as you discussed 
earlier.

If you want to work with external flash or RAM, you have to set up the FSMC or 
FMC to support it, but that isn’t a part of the dev board that Sebastian used 
for the BSP port.

The external memory is going to be very specific to your board. Which board are 
you working with?

A

> On 2019-June-13, at 06:23, Christian Mauderer 
>  wrote:
> 
> On 05/06/2019 02:55, Jython wrote:
>> Hello!
>> 
>> 2. In the normal (non-debugging) case, the linker script still
>>places the 
>> 
>>.text section near zero, but places the start of the .data and .bss
>>sections at the start location of the MPC555's internal RAM. The
>>system startup code then configures the external RAM just after the
>>internal RAM in memory, forming one large block from the two RAM
>>devices.
>> 
>> from https://devel.rtems.org/wiki/TBR/BSP/Ss555
>> 
>> but i dont know how to configure the external RAM just after the
>> internal RAM in memory?
>> hope you could give me some guide!
>>  
>> 
> 
> Hello Jython,
> 
> the documentation you linked is for an MPC. But your subject line
> mentions an STM32. What controller / BSP are you using?
> 
> Best regards
> 
> Christian Mauderer
> -- 
> 
> embedded brains GmbH
> Herr Christian Mauderer
> Dornierstr. 4
> D-82178 Puchheim
> Germany
> email: christian.maude...@embedded-brains.de
> Phone: +49-89-18 94 741 - 18
> Fax:   +49-89-18 94 741 - 08
> PGP: Public key available on request.
> 
> Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
> ___
> users mailing list
> users@rtems.org
> http://lists.rtems.org/mailman/listinfo/users

___
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Re: stm32 external SRAM

2019-06-13 Thread Jython

HI, im using stm32f407


On Thu, Jun 13, 2019 at 8:23 PM Christian Mauderer <
christian.maude...@embedded-brains.de> wrote:

> On 05/06/2019 02:55, Jython wrote:
> > Hello!
> >
> >  2. In the normal (non-debugging) case, the linker script still
> > places the
> >
> > .text section near zero, but places the start of the .data and .bss
> > sections at the start location of the MPC555's internal RAM. The
> > system startup code then configures the external RAM just after the
> > internal RAM in memory, forming one large block from the two RAM
> > devices.
> >
> > from https://devel.rtems.org/wiki/TBR/BSP/Ss555
> >
> > but i dont know how to configure the external RAM just after the
> > internal RAM in memory?
> > hope you could give me some guide!
> >
> >
>
> Hello Jython,
>
> the documentation you linked is for an MPC. But your subject line
> mentions an STM32. What controller / BSP are you using?
>
> Best regards
>
> Christian Mauderer
> --
> 
> embedded brains GmbH
> Herr Christian Mauderer
> Dornierstr. 4
> D-82178 Puchheim
> Germany
> email: christian.maude...@embedded-brains.de
> Phone: +49-89-18 94 741 - 18
> Fax:   +49-89-18 94 741 - 08
> PGP: Public key available on request.
>
> Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
>
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Re: stm32 external SRAM

2019-06-13 Thread Christian Mauderer

On 05/06/2019 02:55, Jython wrote:
> Hello!
> 
>  2. In the normal (non-debugging) case, the linker script still
> places the 
> 
> .text section near zero, but places the start of the .data and .bss
> sections at the start location of the MPC555's internal RAM. The
> system startup code then configures the external RAM just after the
> internal RAM in memory, forming one large block from the two RAM
> devices.
> 
> from https://devel.rtems.org/wiki/TBR/BSP/Ss555
> 
> but i dont know how to configure the external RAM just after the
> internal RAM in memory?
> hope you could give me some guide!
>  
> 

Hello Jython,

the documentation you linked is for an MPC. But your subject line
mentions an STM32. What controller / BSP are you using?

Best regards

Christian Mauderer
-- 

embedded brains GmbH
Herr Christian Mauderer
Dornierstr. 4
D-82178 Puchheim
Germany
email: christian.maude...@embedded-brains.de
Phone: +49-89-18 94 741 - 18
Fax:   +49-89-18 94 741 - 08
PGP: Public key available on request.

Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
___
users mailing list
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Re: stm32 external SRAM

Re: stm32 external SRAM

Re: stm32 external SRAM

Re: stm32 external SRAM

Re: stm32 external SRAM

Re: stm32 external SRAM

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Re: stm32 external SRAM

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Re: stm32 external SRAM

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Re: stm32 external SRAM

Re: stm32 external SRAM

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