-
From: Jaroslav Kysela [mailto:[EMAIL PROTECTED]
Sent: Thursday, March 11, 2004 11:30 PM
To: Takashi Iwai
Cc: Gupta, Kshitij; [EMAIL PROTECTED]
Subject: Re: FW: [Alsa-devel] DMA producer/consumer
On Thu, 11 Mar 2004, Takashi Iwai wrote:
At Thu, 11 Mar 2004 18:43:39 +0100 (CET),
Jaroslav wrote
On Fri, 12 Mar 2004, Gupta, Kshitij wrote:
hi,
Even thought the SA11xx ARM platform DMA engine has a queueing
mechanism (as you mentioned), it is not being utilized. Since we are
queueing(or starting) the next dma transfer in the interrupt context, and we
recieve this interrupt only
to check this
before queueing a next period.
regards
-kshitij
-Original Message-
From: Jaroslav Kysela [mailto:[EMAIL PROTECTED]
Sent: Friday, March 12, 2004 3:03 PM
To: Gupta, Kshitij
Cc: Takashi Iwai; [EMAIL PROTECTED]
Subject: RE: FW: [Alsa-devel] DMA producer/consumer
On Fri, 12 Mar 2004
On Fri, 12 Mar 2004, Gupta, Kshitij wrote:
hi Jaroslav,
yeah I completely agree with you. We can always queue upfront, and
then in interrupt context queue next period. But the only issue I see is
that when we queue a next period, are we sure that the middle layer has
already filled
; [EMAIL PROTECTED]
Subject: RE: FW: [Alsa-devel] DMA producer/consumer
On Fri, 12 Mar 2004, Gupta, Kshitij wrote:
hi Jaroslav,
yeah I completely agree with you. We can always queue upfront, and
then in interrupt context queue next period. But the only issue I see is
that when we queue
On Fri, 12 Mar 2004, Gupta, Kshitij wrote:
hi,
No no I was asking about the transfer of data from Application to
the ring buffer (which is performed by ALSA middle layer), let me reframe
the doubt I have.
When we queue a next period to the DMA engine, we have no idea whether data
are
getting underruns consistently, even with very small period size (about 1k).
regards
-kshitij
-Original Message-
From: Jaroslav Kysela [mailto:[EMAIL PROTECTED]
Sent: Friday, March 12, 2004 3:45 PM
To: Gupta, Kshitij
Cc: Takashi Iwai; [EMAIL PROTECTED]
Subject: RE: FW: [Alsa-devel] DMA
On Fri, 12 Mar 2004, Gupta, Kshitij wrote:
hi,
:) maps almost perfectly ...thanx a lot. Only other doubt I had
was, why are we always getting underruns in case of ARM (as Russell also
pointed out that there are some cache coherency problems), but I am not able
to map cache coherency
At Thu, 11 Mar 2004 09:30:31 +0530,
Gupta, Kshitij wrote:
Any comments on this would be really helpful...
-Original Message-
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] Behalf Of Gupta,
Kshitij
Sent: Wednesday, March 10, 2004 5:06 PM
To: [EMAIL PROTECTED]
Subject:
On Thu, 11 Mar 2004, Takashi Iwai wrote:
unfortunately, the current implementation of ALSA PCM middle layer
isn't well suited for this kind of hardwares. it'll be a bit more
complicated than you think.
I don't think that's this case. I'm not sure, if the basic midlevel
mechanism is
On Thu, 11 Mar 2004, Takashi Iwai wrote:
At Thu, 11 Mar 2004 18:43:39 +0100 (CET),
Jaroslav wrote:
On Thu, 11 Mar 2004, Takashi Iwai wrote:
unfortunately, the current implementation of ALSA PCM middle layer
isn't well suited for this kind of hardwares. it'll be a bit more
At Thu, 11 Mar 2004 18:43:39 +0100 (CET),
Jaroslav wrote:
On Thu, 11 Mar 2004, Takashi Iwai wrote:
unfortunately, the current implementation of ALSA PCM middle layer
isn't well suited for this kind of hardwares. it'll be a bit more
complicated than you think.
I don't think that's
Any comments on this would be really helpful...
-Original Message-
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] Behalf Of Gupta,
Kshitij
Sent: Wednesday, March 10, 2004 5:06 PM
To: [EMAIL PROTECTED]
Subject: [Alsa-devel] DMA producer/consumer
hi,
A typical core pcm
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