This has some whitespace changes that don't seem to be related, please
get people to be a bit more careful.
(though I do realise this could be magic ifdef stuff that got ripped out :-)
Dave.
On 10 July 2018 at 10:37, Harry Wentland wrote:
> From: Eric Bernstein
>
> Signed-off-by: Eric Bernste
typo in subject.
On 10 July 2018 at 10:37, Harry Wentland wrote:
> From: Hersen Wu
>
> [Why]
> when hw team does phy parameters tuning, there is need to force dp
> link rate or lane count grater than the values from dp receiver to
> check dp tx. current debufs limit link rate, lane count no mo
On 07/09/2018 07:29 PM, Christian König wrote:
Am 09.07.2018 um 12:14 schrieb Zhang, Jerry (Junwei):
On 07/09/2018 04:55 PM, Christian König wrote:
Am 09.07.2018 um 09:48 schrieb Zhang, Jerry (Junwei):
On 07/09/2018 03:04 PM, Christian König wrote:
Am 09.07.2018 um 07:13 schrieb Zhang, Jerry
From: Ken Chalmers
[Why]
The previous code could allow through attempts to enable more streams
than there are timing generators, in designs where the number of pipes
is greater than the number of timing generators.
[How]
Compare the new stream count to the resource pool's timing generator
count,
From: Tony Cheng
Signed-off-by: Tony Cheng
Reviewed-by: Aric Cyr
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 1b36e763f3b0..
From: Eric Bernstein
Signed-off-by: Eric Bernstein
Reviewed-by: Dmytro Laktyushkin
Acked-by: Harry Wentland
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 1 -
drivers/gpu/drm/amd/display/dc/dc_stream.h| 1 +
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 59 +++
.
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
b/driver
From: Tony Cheng
Signed-off-by: Tony Cheng
Reviewed-by: Anthony Koo
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 721c5cdff38
From: Charlene Liu
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../dc/i2caux/dce110/i2c_hw_engine_dce110.c | 26 +++
.../dc/i2caux/dce110/i2c_hw_engine_dce110.h | 8 ++
From: "Leo (Sunpeng) Li"
[Why]
get_channel_status() can return 0 in returned_bytes, and report a
successful operation result. This is because it prunes the first status
byte out. This was preventing read_channel_reply() from being called
(due to the faulty condition), and consequently preventing
From: Dmytro Laktyushkin
DV updated their dml with an option to use max vstartup,
this updates dc dml with the same option
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 1 +
1 file changed, 1
From: Mikita Lipski
[why]
Add a switch statement to translate pp's powerlevel enum
to dc powerlevel statement enum
[how]
Add a translator function
Signed-off-by: Mikita Lipski
Reviewed-by: Sun peng Li
Acked-by: Harry Wentland
---
.../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 29 +++
From: Hugo Hu
[Why] Prevent unexpected color shows if DalMpVisualConfirm enable.
[How] Zero out color configuration data for DalMpVisualConfirm when initiating.
Signed-off-by: Hugo Hu
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer
From: David Francis
[Why]
Regamma/CTM tests require CRC support
[How]
The CRC registers that were used in DCE exist under different
names in DCN. The code was copied from DCE (in
dc/dce110/dce110_timing_generator.c) into DCN, and changed to
use the DCN register access helper functions.
Signed-
From: Hersen Wu
[Why]
when hw team does phy parameters tuning, there is need to force dp
link rate or lane count grater than the values from dp receiver to
check dp tx. current debufs limit link rate, lane count no more
than rx caps.
[How] remove force settings less than rx caps check
Signed-of
From: Dmytro Laktyushkin
[why]
Currently we do not turn off autocal when scaling is in bypass.
In case vbios enalbes auto scale and our first mode set is a non-scaled
mode we have autocal on causing screen corruption.
[how]
moves turning autocal off to be first thing done during scaler setup
Si
From: Yue Hin Lau
[WHY]
PNP cause bsod regression fix
[HOW]
Add NULL check
Signed-off-by: Yue Hin Lau
Reviewed-by: Hugo Hu
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drive
From: Yongqiang Sun
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c | 10 ++
.../gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h | 2 ++
2 files changed, 4 insertions(+), 8 deletions(-)
diff
From: Charlene Liu
[why]
"DalEnableHDMI20" set to 0, disallow HDMI YCbCr420 and pixel clock > 340Mhz
Default is enabled.
Signed-off-by: Charlene Liu
Reviewed-by: Jun Lei
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display
From: "Leo (Sunpeng) Li"
GCC 4.9 reports a 'missing braces around initializer' error. This is a
bug, documented here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119
Fix it by adding another brace.
Signed-off-by: Leo (Sunpeng) Li
Reviewed-by: Mikita Lipski
Acked-by: Harry Wentland
---
d
From: Charlene Liu
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 1 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h| 9 +++--
2 files changed, 8 insertions(+), 2 deletions(-)
From: Eric Bernstein
Separate HUBP surface size and rotation/mirror programming so that
HUBP revision without mirror/rotation do not access those register
fields.
Signed-off-by: Eric Bernstein
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Harry Wentland
---
.../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc
From: Fatemeh Darbehani
Signed-off-by: Fatemeh Darbehani
Reviewed-by: Aric Cyr
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 8 +++-
drivers/gpu/drm/amd/display/dc/dc_link.h | 2 +-
3 fil
From: Tony Cheng
add generic indirect register access following our register access pattern
this will make it easier to review code and programming sequence,
with all the complexity hidden in macro
Signed-off-by: Tony Cheng
Reviewed-by: Yongqiang Sun
Acked-by: Harry Wentland
---
drivers/gpu
From: Hersen Wu
function description
get/ set DP configuration: lane_count, link_rate, spread_spectrum
valid lane count value: 1, 2, 4
valid link rate value:
06h = 1.62Gbps per lane
0Ah = 2.7Gbps per lane
0Ch = 3.24Gbps per lane
14h = 5.4Gbps per lane
1Eh = 8.1Gbps per lane
de
DRM's DP helpers take care of dealing with the error code for us. In
order not to step on each other's toes we'll need to be able to simply
read auch channel replies without further logic based on return values.
Signed-off-by: Harry Wentland
Reviewed-by: Sun peng Li
Acked-by: Harry Wentland
---
This reverts commit 8a61bc085ffab3071c59efcbeff4044c034e7490.
Signed-off-by: Harry Wentland
---
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 20 ---
.../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 10 +++---
.../gpu/drm/amd/display/dc/inc/dc_link_ddc.h | 5 ++---
3 files
From: David Francis
Signed-off-by: David Francis
Reviewed-by: Charlene Liu
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
b/drivers/gpu/drm/amd/d
From: Tony Cheng
Signed-off-by: Tony Cheng
Reviewed-by: Yongqiang Sun
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 0cb7e10d2505..59985baac11
From: Eric Yang
[Why]
Megachip dockings accesses ddc line through display driver when
installing FW. Previously, we would fail every transaction because
link attached to mst branch did not have their ddc transaction type
set.
[How]
Set ddc transaction type when mst branch is connected.
Signed-o
From: "Leo (Sunpeng) Li"
[Why]
There is no point in keeping the AUX reply value in the raw format as
returned from reading the AUX_SW_DATA register.
[How]
Shift it within read_channel_reply(), where the register is read, before
returning it.
Signed-off-by: Leo (Sunpeng) Li
Reviewed-by: Harry W
Access to GPIO needs to be serialized. Aux transactions are already
serialized in DRM but we also need to serialize access to the GPIO pin
for purposes of DP dongle detection.
Call is_dp_sink_present through DM so we can lock correctly. This
follows the same pattern used for DPCD transactions.
Si
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 5 +++--
.../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c| 7 ---
drivers/gpu/drm/amd/display/dc/dcn10/
This reverts commit cc195141133ac3e767d930bedd8294ceebf1f10b.
Signed-off-by: Harry Wentland
---
.../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 9 -
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 7 +++
.../gpu/drm/amd/display/dc/i2caux/aux_engine.c| 15 +--
From: Tony Cheng
[WHY]
we were using 6 instances based on i2caux_dce110.c
[HOW]
pass in how many instances to ctor
Signed-off-by: Tony Cheng
Reviewed-by: Yongqiang Sun
Acked-by: Harry Wentland
---
.../gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c| 1 +
.../gpu/drm/amd/display/dc
From: Charlene Liu
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
b/drivers/gpu/drm/amd/display/
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
b/drivers/gpu/drm/amd/display/
From: "Jerry (Fangzhi) Zuo"
[Why]
Some monitors mark 4K@60 capable HDMI port only have 300MHz TMDS
maximum, but the edid includes 4K@60 mode in cea extension block.
[How]
To enable 4K@60, need to limit BW by allowing YCbCr420 ONLY mode.
Add YCbCr420 only support for monitors that do not fully su
From: Hersen Wu
bug fix: phy test PLTAT is special 80bit test pattern. The 80bit
data should be hard coded within driver so that user does not
need input the deata. previous driver does not have hard coded
80 bits pattern data for PLTPAT. Other than this PLTPAT, user
has to input 80 bits pattern
From: Hugo Hu
[WHY]
In eDP spec, the min duration in LCDVDD on-off-on sequence should be
500ms, some BOE panels need 700ms to pass.
[HOW]
Add patch to wait more time when eDP power on.
Signed-off-by: Hugo Hu
Reviewed-by: Charlene Liu
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/d
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 1 +
.../display/dc/dce110/dce110_hw_sequencer.c | 3 ++-
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 20 ---
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
b/drivers/gpu/drm/amd/display/d
From: Alvin lee
- define new dpcd address in drm
- implement new members in dpcd_caps to store values read from new dpcd address
Signed-off-by: Alvin lee
Reviewed-by: Harry Wentland
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 25 +++
drivers/gpu/drm/amd/display/dc/dc.h
From: Hersen Wu
function: get current DP PHY settings: voltage swing, pre-emphasis,
post-cursor2 (defined by VESA DP specification)
valid values: voltage swing: 0,1,2,3 pre-emphasis : 0,1,2,3
post cursor2 : 0,1,2,3
debugfs file phy_setings is located at /sys/kernel/debug/dri/0/DP-x
th
From: Tony Cheng
Signed-off-by: Tony Cheng
Reviewed-by: Charlene Liu
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c | 3 +--
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h | 4
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git
From: Krunoslav Kovac
DCN allows cursor multiplier when blending FP16 surface.
Signed-off-by: Krunoslav Kovac
Reviewed-by: Aric Cyr
Reviewed-by: Anthony Koo
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp
Currently we still go through DC code that does error checking, retries,
etc. There's no need for that since DRM already does that for us. This
simplifies the code a bit and makes it easier to debug.
This also ensures we correctly tell DRM how many bytes have actually
been read, as we should. This
From: Charlene Liu
Signed-off-by: Charlene Liu
Reviewed-by: Wesley Chalmers
Reviewed-by: Duke Du
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
b
From: Tony Cheng
in case we have very few pins in the table, check fails and we can't boot
Signed-off-by: Tony Cheng
Reviewed-by: Yongqiang Sun
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/
From: Hersen Wu
expose dc function to be called by linux dm
Signed-off-by: Hersen Wu
Reviewed-by: Sun peng Li
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 65
drivers/gpu/drm/amd/display/dc/dc_link.h | 17 +++
2 files changed, 82 insert
From: Nicholas Kazlauskas
- Removed dal/dm/dc loggers from linux, switched to kernel prints
- Modified functions that used these directly to use macros
- dc_logger support is completely dropped from Linux
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/d
From: Eric Bernstein
Signed-off-by: Eric Bernstein
Reviewed-by: Charlene Liu
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
b/drivers/gpu/drm/am
From: Tony Cheng
Signed-off-by: Tony Cheng
Reviewed-by: Aric Cyr
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 59985baac11e..
From: Hersen Wu
set PHY layer or Link layer test pattern
PHY test pattern is used for PHY SI check.
Link layer test will not affect PHY SI.
- normal video mode
0 = DP_TEST_PATTERN_VIDEO_MODE
- PHY test pattern supported
1 = DP_TEST_PATTERN_D102
2 = DP_TEST_PATTERN_SYMBOL_ERROR
3 =
From: Hugo Hu
Signed-off-by: Hugo Hu
Reviewed-by: Charlene Liu
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/driver
From: Charlene Liu
Signed-off-by: Charlene Liu
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
b/drivers/gpu/drm/amd/d
Summary of changes:
* Drop DC logger completely
* CRC support for DCN
* Leave aux.transfer error handling to DRM
* Debugfs to program DP PHY for CTS
Alvin lee (1):
drm/amd/display: read DP sink and DP branch hardware and firmware
revision from DPCD
Charlene Liu (6):
drm/amd/display: M
Acked-by: Alex Deucher
From: amd-gfx on behalf of Harry
Wentland
Sent: Monday, July 9, 2018 1:57 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry
Subject: [PATCH] drm/amd/pp: Send khz clock values to DC for smu7/8
The previous change wasn't covering s
On 2018-07-09 09:24 AM, Christian König wrote:
> This reverts commit 3fdadbfe1edf4168b2515083af5651c95aeb299d.
>
> It causes crashes on Tonga so revert it for now. Somebody with better
> knowledge
> of the code needs to take a closer look.
>
> Signed-off-by: Christian König
Acked-by: Harry Wen
The previous change wasn't covering smu 7 and 8 and therefore DC was
seeing wrong clock values.
This fixes an issue where the pipes seem to hang with a 4k DP and 1080p
HDMI display.
Fixes: c3df50abc84b ("drm/amd/pp: Convert clock unit to KHz as defined")
Signed-off-by: Harry Wentland
Cc:rex@
On Mon, 09 Jul 2018 18:05:09 +0200,
Qu, Jim wrote:
>
> Hi Takashi,
>
> Not intel, but it is AMD APU+ AMD GFX, the APU has a local HDMI port for
> extension. And dGPU is only for offloading render via PRIME.
>
> Originally, the HDA driver before v4.17, there is a bug, that all the audio
> is se
On Mon, 09 Jul 2018 18:03:48 +0200,
Alex Deucher wrote:
>
> On Mon, Jul 9, 2018 at 11:57 AM, Takashi Iwai wrote:
> > On Mon, 09 Jul 2018 17:53:19 +0200,
> > Qu, Jim wrote:
> >>
> >> Hi All,
> >>
> >> Here, I want to clarify the audio device is bound to iGPU. There is no
> >> audio codec for dGPU
On Mon, 09 Jul 2018 18:15:32 +0200,
Alex Deucher wrote:
>
> On Mon, Jul 9, 2018 at 12:06 PM, Lukas Wunner wrote:
> > On Mon, Jul 09, 2018 at 05:52:49PM +0200, Takashi Iwai wrote:
> >> On Mon, 09 Jul 2018 17:47:34 +0200, Lukas Wunner wrote:
> >> > Since v4.17, every time the GPU is powered up, the
On Mon, Jul 9, 2018 at 9:24 AM, Christian König
wrote:
> This reverts commit 3fdadbfe1edf4168b2515083af5651c95aeb299d.
>
> It causes crashes on Tonga so revert it for now. Somebody with better
> knowledge
> of the code needs to take a closer look.
>
> Signed-off-by: Christian König
Acked-by: Al
Series is:
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Leo Liu
Sent: Monday, July 9, 2018 12:11:38 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Leo
Subject: [PATCH 3/3] drm/amdgpu: move cache window setup after power and clock
resume
To make regist
On 2018-07-09 06:14 PM, Keith Packard wrote:
> Michel Dänzer writes:
>
>> From: Keith Packard
>>
>> Save any value of the kernel non-desktop property in the xf86Output
>> structure to avoid non-desktop outputs in the default configuration.
>>
>> [Also bump randrproto requirement to a version tha
On Mon, Jul 9, 2018 at 12:06 PM, Lukas Wunner wrote:
> On Mon, Jul 09, 2018 at 05:52:49PM +0200, Takashi Iwai wrote:
>> On Mon, 09 Jul 2018 17:47:34 +0200, Lukas Wunner wrote:
>> > Since v4.17, every time the GPU is powered up, the HDA controller is
>> > runtime resumed to PCI_D0. (See the call t
Michel Dänzer writes:
> From: Keith Packard
>
> Save any value of the kernel non-desktop property in the xf86Output
> structure to avoid non-desktop outputs in the default configuration.
>
> [Also bump randrproto requirement to a version that defines
> RR_PROPERTY_NON_DESKTOP - ajax]
>
> Signed-
Fixes: 22cc6c5e19 (drm/amdgpu: Add runtime VCN PG support)
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 4a3457236e85.
To make register read/write reliable. Along with the previous patch,
VCN will work with dpm disabled case.
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu
VCN won't get power off when only jpeg active
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index a66cd521a875..4a3457236e85 100644
--- a/
On Mon, Jul 09, 2018 at 05:52:49PM +0200, Takashi Iwai wrote:
> On Mon, 09 Jul 2018 17:47:34 +0200, Lukas Wunner wrote:
> > Since v4.17, every time the GPU is powered up, the HDA controller is
> > runtime resumed to PCI_D0. (See the call to pci_wakeup_bus() in
> > vga_switcheroo_runtime_resume() a
Hi Takashi,
Not intel, but it is AMD APU+ AMD GFX, the APU has a local HDMI port for
extension. And dGPU is only for offloading render via PRIME.
Originally, the HDA driver before v4.17, there is a bug, that all the audio is
set to CLIENT_DIS, so the when the dGPU suspend, the audio which is bo
On Mon, Jul 9, 2018 at 11:57 AM, Takashi Iwai wrote:
> On Mon, 09 Jul 2018 17:53:19 +0200,
> Qu, Jim wrote:
>>
>> Hi All,
>>
>> Here, I want to clarify the audio device is bound to iGPU. There is no audio
>> codec for dGPU.
>
> I'm confused. So you mean that the HDMI detection on Intel GPU
> doe
On Mon, 09 Jul 2018 17:59:00 +0200,
Alex Deucher wrote:
>
> On Mon, Jul 9, 2018 at 11:52 AM, Takashi Iwai wrote:
> > On Mon, 09 Jul 2018 17:47:34 +0200,
> > Lukas Wunner wrote:
> >>
> >> On Mon, Jul 09, 2018 at 05:04:22PM +0200, Takashi Iwai wrote:
> >> > On Mon, 09 Jul 2018 15:58:51 +0200, Alex
On Mon, Jul 9, 2018 at 11:52 AM, Takashi Iwai wrote:
> On Mon, 09 Jul 2018 17:47:34 +0200,
> Lukas Wunner wrote:
>>
>> On Mon, Jul 09, 2018 at 05:04:22PM +0200, Takashi Iwai wrote:
>> > On Mon, 09 Jul 2018 15:58:51 +0200, Alex Deucher wrote:
>> > > On Mon, Jul 9, 2018 at 6:16 AM, Qu, Jim wrote:
>
On Mon, 09 Jul 2018 17:56:43 +0200,
Daniel Vetter wrote:
>
> On Mon, Jul 09, 2018 at 05:04:22PM +0200, Takashi Iwai wrote:
> > On Mon, 09 Jul 2018 15:58:51 +0200,
> > Alex Deucher wrote:
> > >
> > > On Mon, Jul 9, 2018 at 6:16 AM, Qu, Jim wrote:
> > > > Hi Lukas,
> > > >
> > > > Thanks to your e
On Mon, 09 Jul 2018 17:53:19 +0200,
Qu, Jim wrote:
>
> Hi All,
>
> Here, I want to clarify the audio device is bound to iGPU. There is no audio
> codec for dGPU.
I'm confused. So you mean that the HDMI detection on Intel GPU
doesn't work with the hybrid GPUs? And no audio codec on discrete
G
On Mon, Jul 09, 2018 at 05:04:22PM +0200, Takashi Iwai wrote:
> On Mon, 09 Jul 2018 15:58:51 +0200,
> Alex Deucher wrote:
> >
> > On Mon, Jul 9, 2018 at 6:16 AM, Qu, Jim wrote:
> > > Hi Lukas,
> > >
> > > Thanks to your explanation, and see comments in line.
> > >
> > >
> > > Do you need to runti
Hi All,
Here, I want to clarify the audio device is bound to iGPU. There is no audio
codec for dGPU.
Thanks
JimQu
-邮件原件-
发件人: Lukas Wunner
发送时间: 2018年7月9日 23:48
收件人: Takashi Iwai
抄送: Alex Deucher ; alsa-de...@alsa-project.org;
amd-gfx@lists.freedesktop.org; Qu, Jim ;
dri-de...@li
On Mon, 09 Jul 2018 17:47:34 +0200,
Lukas Wunner wrote:
>
> On Mon, Jul 09, 2018 at 05:04:22PM +0200, Takashi Iwai wrote:
> > On Mon, 09 Jul 2018 15:58:51 +0200, Alex Deucher wrote:
> > > On Mon, Jul 9, 2018 at 6:16 AM, Qu, Jim wrote:
> > > > > You're saying above that the HDA controller isn't ru
On Mon, Jul 09, 2018 at 05:04:22PM +0200, Takashi Iwai wrote:
> On Mon, 09 Jul 2018 15:58:51 +0200, Alex Deucher wrote:
> > On Mon, Jul 9, 2018 at 6:16 AM, Qu, Jim wrote:
> > > > You're saying above that the HDA controller isn't runtime resumed on
> > > > hotplug of a display. Is that necessary t
On Mon, 09 Jul 2018 16:02:48 +0200,
Alex Deucher wrote:
>
> On Mon, Jul 9, 2018 at 6:16 AM, Qu, Jim wrote:
> > Hi Lukas,
> >
> > Thanks to your explanation, and see comments in line.
> >
> >
> > Do you need to runtime resume the HDA controller even if user space isn't
> > streaming audio? Why, a
On Mon, 09 Jul 2018 15:58:51 +0200,
Alex Deucher wrote:
>
> On Mon, Jul 9, 2018 at 6:16 AM, Qu, Jim wrote:
> > Hi Lukas,
> >
> > Thanks to your explanation, and see comments in line.
> >
> >
> > Do you need to runtime resume the HDA controller even if user space isn't
> > streaming audio? Why, a
On Mon, Jul 9, 2018 at 6:16 AM, Qu, Jim wrote:
> Hi Lukas,
>
> Thanks to your explanation, and see comments in line.
>
>
> Do you need to runtime resume the HDA controller even if user space isn't
> streaming audio? Why, and in which situation exactly?
>
> Jim: OEM system uses pactl to queiry aud
On Mon, Jul 9, 2018 at 6:16 AM, Qu, Jim wrote:
> Hi Lukas,
>
> Thanks to your explanation, and see comments in line.
>
>
> Do you need to runtime resume the HDA controller even if user space isn't
> streaming audio? Why, and in which situation exactly?
>
> Jim: OEM system uses pactl to queiry aud
This reverts commit 3fdadbfe1edf4168b2515083af5651c95aeb299d.
It causes crashes on Tonga so revert it for now. Somebody with better knowledge
of the code needs to take a closer look.
Signed-off-by: Christian König
---
.../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 2 +-
drivers/gpu/drm/a
On Wed 27-06-18 09:44:21, Michal Hocko wrote:
> This is the v2 of RFC based on the feedback I've received so far. The
> code even compiles as a bonus ;) I haven't runtime tested it yet, mostly
> because I have no idea how.
>
> Any further feedback is highly appreciated of course.
Any other feedba
Am 09.07.2018 um 12:14 schrieb Zhang, Jerry (Junwei):
On 07/09/2018 04:55 PM, Christian König wrote:
Am 09.07.2018 um 09:48 schrieb Zhang, Jerry (Junwei):
On 07/09/2018 03:04 PM, Christian König wrote:
Am 09.07.2018 um 07:13 schrieb Zhang, Jerry (Junwei):
On 07/06/2018 03:27 AM, Andrey Grodzo
Am 09.07.2018 um 12:30 schrieb Shirish S:
issue:
BUG_ON(ring->ring[offset] != 0x55aa55aa) is hit on resume from
S3 state.
fix & analysis:
fix is to check for valid job, which in continuation to the below patch:
113890e drm/amdgpu: cond_exec only for schedule with a job
Since cond_exec is not
it should be omited when coding.
Reviewed-by: Jim Qu
Thanks
JimQu
发件人: amd-gfx 代表 Shirish S
发送时间: 2018年7月9日 18:30:14
收件人: Liu, Monk; Deucher, Alexander; Koenig, Christian
抄送: amd-gfx@lists.freedesktop.org; S, Shirish
主题: [PATCH] drm/amdgpu: execute amd
issue:
BUG_ON(ring->ring[offset] != 0x55aa55aa) is hit on resume from
S3 state.
fix & analysis:
fix is to check for valid job, which in continuation to the below patch:
113890e drm/amdgpu: cond_exec only for schedule with a job
Since cond_exec is not initialised if there is no job,
0x55aa55aa i
Hi Lukas,
Thanks to your explanation, and see comments in line.
Do you need to runtime resume the HDA controller even if user space isn't
streaming audio? Why, and in which situation exactly?
Jim: OEM system uses pactl to queiry audio card and audio output sink, since
the audio has power dow
On 07/09/2018 04:55 PM, Christian König wrote:
Am 09.07.2018 um 09:48 schrieb Zhang, Jerry (Junwei):
On 07/09/2018 03:04 PM, Christian König wrote:
Am 09.07.2018 um 07:13 schrieb Zhang, Jerry (Junwei):
On 07/06/2018 03:27 AM, Andrey Grodzovsky wrote:
Extract and present the reposnsible proces
On Mon, Jul 09, 2018 at 08:52:33AM +, Qu, Jim wrote:
> Now, I found the audio device will auto suspend even if the gpu is active,
> and if I plug in a HDMI device it also do not resume back.
>
> 1. Did you encounter similar issue before?
> 2. audio will auto suspend as default at beginning of
Am 09.07.2018 um 09:48 schrieb Zhang, Jerry (Junwei):
On 07/09/2018 03:04 PM, Christian König wrote:
Am 09.07.2018 um 07:13 schrieb Zhang, Jerry (Junwei):
On 07/06/2018 03:27 AM, Andrey Grodzovsky wrote:
Extract and present the reposnsible process and thread when
VM_FAULT happens.
v2: Use get
Hi Lukas,
Our OEM report the issue also can be observed with v4.17rc7 of test platform,
and I also backported these 7 patches to v4.15, have confirmed the issue.
Now, I found the audio device will auto suspend even if the gpu is active, and
if I plug in a HDMI device it also do not resume back.
On 07/09/2018 03:04 PM, Christian König wrote:
Am 09.07.2018 um 07:13 schrieb Zhang, Jerry (Junwei):
On 07/06/2018 03:27 AM, Andrey Grodzovsky wrote:
Extract and present the reposnsible process and thread when
VM_FAULT happens.
v2: Use getter and setter functions.
Signed-off-by: Andrey Grodzo
From: Keith Packard
Save any value of the kernel non-desktop property in the xf86Output
structure to avoid non-desktop outputs in the default configuration.
[Also bump randrproto requirement to a version that defines
RR_PROPERTY_NON_DESKTOP - ajax]
Signed-off-by: Keith Packard
(Ported from xse
1 - 100 of 104 matches
Mail list logo