Change-Id: I43c50769557a9be932891e923f669f7993eeedf9
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c
Move the get vbios only before SDMA block early init to fix null pointer
about get vbios.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git
> -Original Message-
> From: amd-gfx On Behalf Of
> Prike Liang
> Sent: Friday, June 14, 2019 3:01 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liang, Prike ; Huang, Ray
> ; Feng, Kenneth ; Quan,
> Evan
> Subject: [PATCH] drm/amd/powerplay: detect version of smu backend
>
> Change-Id:
Hi all,
After commit abe882a39a9c ("drm/amd/display: fix issue with eDP not
detected on driver load") in -next, arm32 allyesconfig builds start
failing at link time:
arm-linux-gnueabi-ld: drivers/gpu/drm/amd/display/dc/core/dc_link.o: in
function `dc_link_detect':
dc_link.c:(.text+0x260c):
Done automatically with unexpand, plus some extra 7-space lines.
Signed-off-by: Ernst Sjöstrand
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 168 -
1 file changed, 84 insertions(+), 84 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
On Mon, Jun 17, 2019 at 10:18 AM Catalin Marinas
wrote:
>
> On Mon, Jun 17, 2019 at 09:57:36AM -0700, Evgenii Stepanov wrote:
> > On Mon, Jun 17, 2019 at 6:56 AM Catalin Marinas
> > wrote:
> > > On Wed, Jun 12, 2019 at 01:43:20PM +0200, Andrey Konovalov wrote:
> > > > From: Catalin Marinas
> >
Reported by smatch:
drivers/gpu/drm/amd/amdgpu/soc15.c:715 soc15_get_pcie_usage() warn:
inconsistent indenting
And a similar one in si.c.
Signed-off-by: Ernst Sjöstrand
---
drivers/gpu/drm/amd/amdgpu/si.c| 4 ++--
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++--
2 files changed, 4
Done automatically with unexpand.
Signed-off-by: Ernst Sjöstrand
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 158 -
1 file changed, 79 insertions(+), 79 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index
On 2019-06-14 9:52 p.m., Yang, Philip wrote:
> Under memory pressure, hmm_range_fault may return error code -ENOMEM
> or -EBUSY, change pr_info to pr_debug to remove unnecessary kernel log
> message because we will retry restore again.
>
> Call get_user_pages_done if TTM get user pages failed will
Ok no worries I'll fix it up and push it later today.
Btw I didn't use an inline cast because the macro kept breaking. I tried
variants of parentheses and nothing worked Odd...
Thanks,
Tom
On June 17, 2019 3:32:03 PM EDT, "Kuehling, Felix"
wrote:
On 2019-06-17 3:28 p.m., Christian
From: Charlene Liu
[Description]
dcn2 use fixed clocks and not program DPP CLK or Disp_CLK.
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 22 +--
From: hersen wu
during navi10 bring up, dwb causes system hang.
to continue debug major issue, disable dwb by
set num-dwb = 0. the hang issue is not reproduced now
by enable num-dwb =1. dc source is shared by all os.
win needs num-dwb = 1.
Signed-off-by: hersen wu
Acked-by: Alex Deucher
From: Charlene Liu
for future use
Signed-off-by: Charlene Liu
Reviewed-by: Chris Park
Acked-by: Bhawanpreet Lakha
Acked-by: Krunoslav Kovac
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Charlene Liu
for future use
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h | 2 ++
From: Thomas Lim
[Why]
For debugging underflow issues it can be useful to have asserts when the
underflow initially occurs.
[How]
Read the underflow status registers after actions that have a high risk
of causing underflow and assert that no underflow occurred. If underflow
occurred, clear the
From: Su Sung Chung
[why]
Before for raven and navi we are calling pp_smu functions for pme
[how]
refactor a code so we will call clk_mgr's enable_pme_wa function so we
can use pme_wa for future asics. This way we don't need to worry about
different ASIC since clk_mgr already have that
From: Dmytro Laktyushkin
mod_vmid is missing a destructor.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h | 2 ++
drivers/gpu/drm/amd/display/modules/vmid/vmid.c|
From: Eric Bernstein
expose this function for future use
Implementation of DCN3 DIO Link Encoder including
dpcs register headers.
Signed-off-by: Eric Bernstein
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
From: Nicholas Kazlauskas
[Why]
To prepare for the upcoming DRM plane color management properties
we need to correct a lot of wrong behavior and assumptions made for
CRTC color management.
The documentation added by this commit in amdgpu_dm_color explains
how the HW color pipeline works and its
From: Dmytro Laktyushkin
Currently vmid is decided internally inside dc. With the introduction
of new asics we are required to coordinate vmid use with external
components.
This change converts vmid logic to a DAL module allowing vmid to be
passed in as a parameter to DC.
Signed-off-by: Dmytro
From: Jun Lei
[why]
useful for debugging
[how]
plumb a debug option in dc
Signed-off-by: Jun Lei
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 4
drivers/gpu/drm/amd/display/dc/dc.h
From: Wesley Chalmers
[WHY]
This is meant to make it clearer that 0xf is not a valid OPP ID, and
that code making use of OPP IDs should not accept this value.
Signed-off-by: Wesley Chalmers
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
From: Jun Lei
[why]
value commited to by HW team is going to be higher
than pre-silicon, and will cause underflow if driver not
updated
[how]
update hardcoded value, update pstate switching logic
to fix case where with long uclk time we won't allow switch
even when we should
Signed-off-by: Jun
From: Nicholas Kazlauskas
[Why]
Almost every function in DC that works with stream state expects that
the current state on the stream is the one that it should be writing
out. These functions are typically triggered by specifying a particular
stream update - but the actual contents of the stream
From: Vitaly Prosyak
[Why & How]
Gamut map lib provides a wider gamut mapping options
vs BT2390
Signed-off-by: Vitaly Prosyak
Reviewed-by: Krunoslav Kovac
Acked-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
Acked-by: Vitaly Prosyak
Signed-off-by: Alex Deucher
---
From: Ilya Bakoulin
Fixes for the following:
- Incorrect pointer type (unsigned int instead of double)
- Incorrect DSC number of slices setting
Signed-off-by: Ilya Bakoulin
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
From: Joshua Aberback
[Why]
We want a test pattern to show up on screen when we're blanked and have
visual confirm enabled, for debugging. Raven does this, it's a mistake that
Navi does not.
[How]
- in "blank_pixel_data", set appropriate DPG pattern for visual confirm
- refactor DPG calls out
From: Yongqiang Sun
[Why]
The DCHub arbiter has a mechanism to dynamically rate limit the DCHub
request stream to the fabric. If the memory controller is fully utilized
and the DCHub requestors are well ahead of their amortized schedule,
then it is safe to prevent the next winner from being
From: Charlene Liu
Should do full update when display writeback is updated.
Signed-off-by: Charlene Liu
Reviewed-by: Duke Du
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 5 +
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 +++-
From: Joshua Aberback
[Why]
Plane disable gets calls when we enable blank. On DCN2, we blank by using
DPG to display a black colour instead of using OTG blank. DPG runs off the
OPP clock, therefore we shouldn't disable the OPP clock when disabling the
plane. We do need to disable the OPP clock
From: "Leo (Hanghong) Ma"
[Why]
To send sdp message immediately from a single slot.
[How]
Modify the generic SDP message interface, and use GSP4 to send immediate
sdp message.
Signed-off-by: Leo (Hanghong) Ma
Reviewed-by: Harry Wentland
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex
From: Wenjing Liu
Signed-off-by: Wenjing Liu
Reviewed-by: Nikola Cornij
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/include/dpcd_structs.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
From: Eric Bernstein
Add Alpha surface type for future use
Signed-off-by: Eric Bernstein
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Wenjing Liu
[why]
Current policy assumes virtual DPCD peer device as
an individual MST branch device with 1 input and 1 output.
However this is only true for virtual DP-to-DP peer device.
In general there are three types of virtual DP peer devices.
1. Sink peer device with virtual DPCD.
2.
From: Wenjing Liu
[why]
According to the latest specs, the max_target bpp sink
can support is 16 bpp.
[how]
update dsc max_target_bpp to 16
Signed-off-by: Wenjing Liu
Reviewed-by: Jun Lei
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
From: Ilya Bakoulin
SwathWidthCThisState is expected to be an unsigned int array.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Charlene Liu
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 2 +-
1 file changed, 1 insertion(+), 1
From: Charlene Liu
[Description]
Features that are desirable for minimizing the Global Sync Period:
DRR and lateflip
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
From: Charlene Liu
Signed-off-by: Charlene Liu
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dc_types.h| 8
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c| 3 ++-
From: Charlene Liu
add dwb stereo caps and ver for future use
Signed-off-by: Charlene Liu
Reviewed-by: Charlene Liu
Reviewed-by: Krunoslav Kovac
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 1 +
From: Ilya Bakoulin
DCN2.0 LB BPP should be 48 or 16BPC and max cursor width should be 256.
Also use populate_dml_pipes as functions pointer instead of using it directly
Signed-off-by: Ilya Bakoulin
Reviewed-by: Eric Bernstein
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
From: Charlene Liu
[Description]
dcn20 has num_dwb =1 in the res cap, but not created.
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Reviewed-by: Duke Du
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 1 -
From: Charlene Liu
[Description]
This is for DC_I2c arbitration use between HW use/SW use and DMCU use.
Signed-off-by: Charlene Liu
Reviewed-by: Krunoslav Kovac
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
From: Dmytro Laktyushkin
A regression was introduced when we set correct tile size
for the gfx9 swizzle mode. This resulted in incorrect
macro tile size.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
From: Martin Leung
[why]
when resetting pipes from 480p to dual-pipe 8k, modulo reg write for
video optimized rate updated one pipe without changing the other, causing
sync error
[how]
removed code from dcn2
Signed-off-by: Martin Leung
Reviewed-by: Jun Lei
Acked-by: Leo Li
Signed-off-by:
From: Ilya Bakoulin
[Why]
OPTC data format was left at its default value (444) when enabling
ODM combine. This caused issues with FPGA capture.
[How]
Write the OPTC_DATA_FORMAT field when enabling ODM combine.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Eric Bernstein
Acked-by: Leo Li
From: Samson Tam
[Why]
Emulating passive dongle on USB-C port causes issue on some asics.
[How]
Check for DP_IS_USB_C flag in bios parser and propagate it to
encoder features flags. If DP_IS_USB_C flag is set and it is trying to
emulate passive dongle, then return fail.
Signed-off-by: Samson
From: Nikola Cornij
[why]
A few of the new DSC DPCD caps were introduced by a DP 1.4a SCR in order
to give DSC branch decoders a chance to expose their maximum throughput
and maximum line width limitations.
Signed-off-by: Nikola Cornij
Reviewed-by: Wenjing Liu
Acked-by: Bhawanpreet Lakha
From: Eryk Brol
[Why]
In order to ensure that incoming flips are latched and
complete immediately, we need to program the vupdate
interrupt to come during the back porch of each frame.
[How]
Program the vupdate start_line to be in the back porch
like it's done for DCN1.
Signed-off-by: Eryk
From: Dmytro Laktyushkin
* add plane state null checks
* add and set update surface flags
*
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++
From: Charlene Liu
Signed-off-by: Charlene Liu
Reviewed-by: Duke Du
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c | 25 ---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.h| 4 +++
From: Jun Lei
[why]
Existing behavior has overlapping ranges resulting in path
dependent SMU selection
[how]
Make ranges non-overlapping, resulting in non-path dependent
selection
Signed-off-by: Jun Lei
Reviewed-by: Eric Yang
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
From: Jun Lei
[why]
current DML logic uses currently trained setting for number
of dp lanes in DML calculations. this is obviously flawed since
just because 1 lane is in use doesn't mean only 1 lane can be used
this causes mode validation to fail depending on current state,
which is incorrect
From: Nikola Cornij
[why]
With DSC power gating enabled, one of the register reads times out occasionally,
causing a DSC test to fail.
[how]
Disable DSC power gating in Diags.
NOTE: This has to be reverted once the problems with DSC power gating are
resolved.
Signed-off-by: Nikola Cornij
From: Dmytro Laktyushkin
The split condition is broken and will always activate
at the moment.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Jun Lei
Acked-by: Leo Li
Acked-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
1
From: Nikola Cornij
[why]
It was missing, although defined in DP spec
[how]
- Add handling of this value to DSC code
- Also remove unused file dsc_helpers.c
Signed-off-by: Nikola Cornij
Reviewed-by: Joshua Aberback
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
From: Charlene Liu
Different HW will need to init HUBP differently. For now, add a vtable
entry, and hook a NO-OP for DCN1 and DCN2.
In addition, future HW will need to access the HUBPREQ_DEBUG and
CUR_TTU_CNTL0 register for hubp_init. Add that here.
Signed-off-by: Charlene Liu
Reviewed-by:
From: Yongqiang Sun
Refactor programming watermark function:
Divided into urgent watermark, stutter watermark and pstate watermark.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
From: Wesley Chalmers
[WHY]
DCN code should make as few references to DCE as possible
[HOW]
Copy DCE110 implementation of find_first_free_match_stream_enc_for_link
into DCN10
Signed-off-by: Wesley Chalmers
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
From: Nikola Cornij
[why]
'Divide by zero' error happens when line size happens to be zero.
[how]
The code that makes sure line size minimum value can be 1 was already
present in DCN1 part of the driver, this is mearly a port to DCN2.
Signed-off-by: Nikola Cornij
Reviewed-by: Tony Cheng
From: Nikola Cornij
[why]
Currently DSC power gating is disabled by default because the power
transition doesn't happen, causing a crash on some systems
[how]
Fix the lack of power state transition and enable DSC power gating
by default.
Signed-off-by: Nikola Cornij
Reviewed-by: Martin Leung
From: Wenjing Liu
[why]
In compute dsc bandwidth range there is an uninitialized variable
[how]
Initialize the variable to the correct value.
Signed-off-by: Wenjing Liu
Reviewed-by: Nikola Cornij
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
From: Jun Lei
[why]
VM implemenation is missing conversion from HW values in hubbub
DM not passing actual PTB during flip
[how]
add proper HW conversion from logical values
fix cases where we programmed VA even though we are in PA
plumb in PTB from DM
Signed-off-by: Jun Lei
Reviewed-by: Tony
From: Wenjing Liu
[why]
dsc adjustment is allowed via stream update sequence.
dsc enablement is only allowed via commit stream sequence.
with the current unified dsc set function, it is hard
to determine which sequence it is called by.
The solution is to decouple dsc adjustment out of enablement
From: Dmytro Laktyushkin
It looks like mpo isn't properly disabled during odm, this change is
meant to fix that.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Nikola Cornij
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c |
From: Ilya Bakoulin
[Why]
The output_bpp pipe parameter was assigned an incorrect value
(color depth enum), and subsequently used to overwrite
the OutputBpp parameter calculated by DML. Seems like this had no
effect except with DSC enabled, which would make DML produce
bad outputs.
[How]
From: Wesley Chalmers
[WHY]
From DCE110 onward, we have the ability to assign DIG BE and FE
separately for any display connector type; before, we could only do this
for DP.
Signed-off-by: Wesley Chalmers
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
From: Tyler DiBattista
[Why]
these enums/structs will be used more generically in the future
so moving it to dc_hw_types and dc_types
Signed-off-by: Tyler DiBattista
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
From: Nikola Cornij
[why]
If a set is done, DSC settings are zeroed out, leading to no DSC for the modes
that require ODM, such as 8k60.
This was a regression introduced by 5a4f26295176bbfc776c75aaf0f6dd8ccf806958.
Signed-off-by: Nikola Cornij
Reviewed-by: Eric Bernstein
Acked-by:
From: Vitaly Prosyak
[Why & How]
Reuse existent code path (dcn1+) and in order to do that apply de gamma
in 1D blender LUT and re use MPC OGAM.
Follow up is required.
Signed-off-by: Vitaly Prosyak
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
Acked-by: Krunoslav Kovac
Acked-by: Vitaly
From: Aric Cyr
[Why]
GSL is being used to synchronize pipes when vsync is off but
on transition to vsync on during a mode change GSL is not
being reset correctly.
[How]
Disable GSL on any plane that is disabled.
Signed-off-by: Aric Cyr
Reviewed-by: Krunoslav Kovac
Acked-by: Bhawanpreet Lakha
From: Yongqiang Sun
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Leo Li
Acked-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h | 3 ---
1 file changed, 3 deletions(-)
diff --git
From: Nikola Cornij
[why]
There are ASICs that have fewer DSC engines than pipes, which makes
DSC a resource that should be used only if required.
[how]
Acquire DSC HW resource if required by stream and release when not
required anymore.
Signed-off-by: Nikola Cornij
Reviewed-by: Wenjing Liu
From: Thomas Lim
[Why]
Due to the generic introduction of seamless boot, the display is no
longer blanked upon boot. However, this causes corruption on some
systems that does not lock the memory in the non-secure boot case,
resulting in brief corruption on boot due to garbage being written into
From: Wenjing Liu
[why]
The current policy will always enable DSC to 12 bpp
regardless of if the current bandwidth is enough for MST displays.
This logic is not optimal because user will get lower quality output
if DSC compression is enabled.
This change to is to implement a DSC MST bandwidth
From: Josip Pavic
[Why]
ABM is currently not enabled on DCN2.
[How]
Update the register name list for DCN2 and un-comment the code that
creates the abm object.
Signed-off-by: Josip Pavic
Reviewed-by: Anthony Koo
Acked-by: Leo Li
Acked-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
From: Nikola Cornij
[why]
DSC target bpp precision is a decoder DPCD and an AMD encoder capability.
It must be taken into account when calculating target bitrate.
[how]
Add a DC DSC function that does this calculation.
Signed-off-by: Nikola Cornij
Reviewed-by: Wenjing Liu
Acked-by: Leo Li
From: hersen wu
[WHY] system crash when initialize dwb
current linux driver does not support dwb.
disable this feature for now.
[HOW] set num_dwb = 0 to disable dwb for now
Signed-off-by: hersen wu
Reviewed-by: Leo Li
Signed-off-by: Alex Deucher
---
From: Nikola Cornij
[why]
DSC resource has to be acquired before it can be used and simply copying
a reference to it is very likely to cause problems when accessing DSC.
[how]
Set DSC resource pointer to NULL to mark it as unused after primary pipe
resources were copied to the secondary ODM
From: hersen wu
[WHY] linux upstream already has interrupt vupdate for freesync
in dcn10. dcn20 interrupt shares the same source code as dcn10.
but dcn20 interrupt translator does not add vupdate interrupt.
this cause index of vupdate aarray be negative which causes
crash.
[HOW] add vupdate
From: Tyler DiBattista
[Why]
Some nightly tests are failing since the new value for fclk is a
bit too low. Also, a new test for the maximum downscale case was
needed.
[How]
Updated the default value for fclk to be 1.2GHz.
Signed-off-by: Tyler DiBattista
Reviewed-by: Eric Bernstein
Acked-by:
From: hersen wu
[WHY] system crash when initialize dwb
current linux driver does not support dwb.
disable this feature for now.
[HOW] set num_dwb = 0 to disable dwb for now
Signed-off-by: hersen wu
Reviewed-by: Leo Li
Signed-off-by: Alex Deucher
---
From: Joshua Aberback
We can split validation into three parts: getting voltage level, getting
watermarks, and rq/dlg calculations. The voltage level is enough to answer
the question "do we support this state", and the rest of it is to determine
what hardware programming is needed to support the
From: Vitaly Prosyak
[Why & How]
The follow up change
Improve some naming for fields and structs
Signed-off-by: Vitaly Prosyak
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
Acked-by: Vitaly Prosyak
Signed-off-by: Alex Deucher
---
.../drm/amd/display/modules/inc/mod_shared.h | 36
From: Joshua Aberback
[Why]
We used this change to investigate the performance of bandwidth validation,
it will be useful to have if we need to investigate further.
[How]
We use performance counter tick numbers to profile performance, they live
at dc->debug.bw_val_profile (set .enable in
From: Wenjing Liu
[why]
when an update programming sequence requires both
front end and back end pipe to be updated synchronously,
a global update lock needs to be set to ensure that
we don't get a frame with only front end update but
not the back end update.
[how]
setup global lock parameters
From: Yongqiang Sun
[Why]
Some register fields are not needed.
[How]
remove them
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 7 ++-
1 file changed, 2 insertions(+),
From: Vitaly Prosyak
Move flags from color_gamma.h to mod_shared.h
and add more options and setting structures
Signed-off-by: Vitaly Prosyak
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
Acked-by: Vitaly Prosyak
Signed-off-by: Alex Deucher
---
From: Dmytro Laktyushkin
We shouldnt need overhead on top of dppclk when setting fclk.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 9 ++---
1 file
From: Yongqiang Sun
Added some regs and exposed some functions for future use
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 2 +-
From: Nikola Cornij
[why]
This is now done in the original link bandwidth calculation and DSC
must not do this anymore.
[how]
Remove the line of code that should have been removed when transition
to correctly applying FEC overhead was made.
Signed-off-by: Nikola Cornij
Reviewed-by: Wenjing
From: Nikola Cornij
[why]
On at least some of the devices (e.g. Realtek scaler) we get a black screen if
1/16th
precision is used.
[how]
Work around it by reducing precision to 1/8th for N4:2:2 and 4:2:0 color
formats. This
is a safe workaround and would have a very mild impact on the
From: Wenjing Liu
Remove dc_dsc hack for MST policy
Signed-off-by: Wenjing Liu
Reviewed-by: Nikola Cornij
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 27 +
1 file changed, 6 insertions(+), 21 deletions(-)
From: Dmytro Laktyushkin
Currently dcn2+ validation will unconditionally print a failure
reason before validation completes. This change categorizes the
failure reason as a warning log and only prints at the end of
validation resolving false positives.
Signed-off-by: Dmytro Laktyushkin
From: Leo Li
[Why]
dcn*_disable_plane() doesn't unlock the pipe anymore, making the extra
lock unnecessary.
In addition - during full plane updates - all necessary pipes should be
locked/unlocked together when modifying hubp to avoid tearing in
pipesplit setups.
[How]
Remove redundant locks,
From: Leo Li
[Why]
Usage of this enum is DSC-only.
[How]
Guard it with CONFIG_DRM_AMD_DC_DSC_SUPPORT.
Signed-off-by: Leo Li
Reviewed-by: Harry Wentland
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h | 2 ++
1 file
From: Bob Yang
[Description]
swath_bytes_horz_wc should be 256/64/64 for 2160p 32bpp surface
Signed-off-by: Bob Yang
Reviewed-by: Charlene Liu
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c | 4 ++--
1 file changed, 2 insertions(+), 2
From: Vitaly Prosyak
[Why & How]
When TM is enabled with 3dlut, we apply conversion to
dcip3 in gamut remap matrix, if source area less than
dcip3. If it is bigger, we remap to bt2020. The added
flags will be used to facilitate this logic.
Signed-off-by: Vitaly Prosyak
Reviewed-by: Aric Cyr
From: Dmytro Laktyushkin
Currently dsc is validated not taking the image width limitation into
mind.
This change addresses that, but due to previous design being limited
to non odm dsc validation additional sequence changes are made.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Nikola
From: Charlene Liu
[Why]
Can not turn on two displays at the same time with the asic having only one DSC.
DC_DSC_RESOURCE allocation failed.
[Solution]
Only add_dsc if the timing is dsc capable based on diag_dc and num_dsc
Signed-off-by: Charlene Liu
Reviewed-by: Wesley Chalmers
Acked-by:
From: Ilya Bakoulin
Adding writeback_config enum to vba_vars_st, replacing old flag.
Initialize to dm_normal.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Charlene Liu
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 1 +
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