Reviewed-by: Aaron Liu
BR,
Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of
> Huang Rui
> Sent: Friday, January 17, 2020 3:48 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Ray
> ; Koenig, Christian
> Subject: [PATCH] drm/amdgpu: remove the
The alignment should match the page size for secure buffer, so we didn't
configure it anymore.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
Noticed this while testing 4 ports MST hub from StarTech.com.
While plugging in and display a MST monitor(Dell U2417H), change the MST
feature to off from OSD. Monitor then can't display anymore.
After analyzing, found out that the CSN reports the specific port from
Device with MST Branching Unit
[Why]
While handling LINK_ADDRESS reply, current code expects a peer device
can handle sideband message once the peer device type is reported as
DP_PEER_DEVICE_MST_BRANCHING. However, when the connected device is
a SST branch case, it can't handle the sideband message(MST_CAP=0 in
DPCD 00021h).
On Thu, Jan 16, 2020 at 06:00:54PM +0800, chen gong wrote:
> Move amdgpu_virt_kiq_rreg/amdgpu_virt_kiq_wreg function to amdgpu_gfx.c,
> and rename them to amdgpu_kiq_rreg/amdgpu_kiq_wreg.Make it generic and
> flexible.
>
Thanks.
Series are Reviewed-by: Huang Rui
> Signed-off-by: chen gong
>
[AMD Official Use Only - Internal Distribution Only]
Series is Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
From: amd-gfx on behalf of Hawking
Zhang
Sent: Friday, January 17, 2020 2:57 AM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander; Gao, Likun
Cc:
IMHO it's better to handle the size==0 case in amdgpu_bo_create_kernel_at().
在 1/17/2020 2:57 AM, Hawking Zhang 写道:
IP discovery is only supported in Navi series and onwards.
There is no need to reserve a portion of vram as discovery
tmr region for pre-Navi adapters.
Signed-off-by: Hawking
On 2020-01-16 8:09, Christian König wrote:
Coreboot seems to have a problem correctly setting up access to the stolen VRAM
on KV/KB. Use the direct access only when necessary.
I'm not sure what you mean by "necessary".
Signed-off-by: Christian König
---
Hi Dave, Daniel,
Last pull for 5.6. Mostly bug fixes.
The following changes since commit 688486a49cf500a193dfe15be9eb5aa468887769:
Merge tag 'amd-drm-next-5.6-2020-01-10-dp-mst-dsc' of
git://people.freedesktop.org/~agd5f/linux into drm-next (2020-01-13 17:14:34
+1000)
are available in the
[Why]
We need to set/get SRM and linux kernel is not suppose to write to the
storage, so we need to provide a interface.
[How]
Provide interface so usermode can set/get srm
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Rodrigo Siqueira
---
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 124
[Why]
We need to support SRM
[How]
Add the interface to the header file
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Rodrigo Siqueira
---
.../drm/amd/display/modules/hdcp/hdcp_psp.h | 26 ++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git
[Why]
We need this to create sysfs (followup patch)
[How]
Change the parameter
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 4 ++--
These patches adds support for SRM loading. By providing an interface to the
usermode
SRM has to be persistent and since the kernel cannot directly write to system
storage we need to provide an interface so that the usermode can do it for us
Bhawanpreet Lakha (5):
drm/amd/display: Pass
[Why]
we need to load SRM before we start HDCP. For S3 case the sysfs call will be
after we already enabled HDCP
[How]
Set srm before starting HDCP
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 7 +++
1 file
Call the cmd ids for set/get srm according to the sysfs call
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Rodrigo Siqueira
---
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 49 ++-
1 file changed, 48 insertions(+), 1 deletion(-)
diff --git
[Why]
When we disable a connector we don't explicitly remove it from the module so the
display is still cached(SW) in the hdcp_module.
SST: no issues because we can only have 1 display per link
MST: We have x displays per link, now if we disable 1 we don't remove it from
the
module so the
From: Nicholas Kazlauskas
[Why]
CW2 may already be programmed when coming back from S4. In this case
we want to unconditionally replace whatever DMCUB version is currently
enabled with the latest.
[How]
Check the hw_init flag to know whether or not we've previously executed
the initliazed
From: Brandon Syu
[Why]
Hardcoded fixed values are not proper.
[How]
Use enum values instead of fixed numbers.
Signed-off-by: Brandon Syu
Reviewed-by: Eric Yang
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 12 ++--
1 file changed, 6
From: Anthony Koo
[Why]
It has duplicate code for building regamma curve
[How]
Remove the duplicate code and use the same function for building regamma
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Reviewed-by: Krunoslav Kovac
Acked-by: Bhawanpreet Lakha
---
From: Wenjing Liu
[why]
FMT has limitation to support YCbCr420 with h_active greater than 4096.
[how]
Use odm combine to overcome the limitation.
Signed-off-by: Wenjing Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
.../dc/dml/dcn20/display_mode_vba_20.c| 19
From: Nicholas Kazlauskas
[Why]
Under some hardware initialization sequences the fb base/fb offset
provided can be zero or hardwareinit can happen too late.
We want to ensure that we always have the correct fb_base/fb_offset
when performing DMCUB hardware initialization so we can do DMCUB
From: Nicholas Kazlauskas
[Why]
These logically make sense more to be set after the DMCUB has been
reset rather than when we setup the inbox.
[How]
Move them into the reset callback.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
From: Wenjing Liu
[why]
MSA will be deprecated in the future.
Need to support VSC during DP test automation.
[how]
Do not disable VSC during DP test automation.
TODO - need to add VSC update on DM side on test request.
Signed-off-by: Wenjing Liu
Reviewed-by: Nikola Cornij
Acked-by:
From: Paul Hsieh
[Why]
Driver use pipe_ctx to reallocate payload may cause allocate
payload twice on same sink with split pipe.
[How]
Drvier must to check pipe_ctx is split pipe or not to avoid
reallocate payload twice on same sink.
Signed-off-by: Paul Hsieh
Reviewed-by: Tony Cheng
Acked-by:
From: Lewis Huang
[Why]
In HG mode, vbios didn't call DispController_Init to program NV1x
XTAL_REF_DIV value when ASIC_INIT, but driver read XTAL_REF_DIV
to calculate i2c reference frequency. it cause i2c frequency change
from 100kHz to 200kHz.
[How]
remove get_speed function and calculate
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Roman Li
[Why]
determine_update_type_for_commit() uses pointers to single instance
of local variable to fill scaling/color info for all planes updates.
This is a bug, that leads to incorrect update type for commit in case
of multiple planes per crtc.
Each plane should refer to separate
From: "Jerry (Fangzhi) Zuo"
[Why]
The types for dummyinteger1 and dummyinteger2 are unsigned
as part of the DML spec. They should not be long.
[How]
Make them unsigned int instead of long.
Signed-off-by: Jerry (Fangzhi) Zuo
Reviewed-by: Bhawanpreet Lakha
---
From: Wenjing Liu
[why]
On video test pattern request we need to update MSA and VSC so
it will match the requested test pattern dynamic range field.
[how]
Update dynamic range field in MSA and disable VSC as updating VSC
info packet is complicated and not required for test pattern purpose.
From: Isabel Zhang
[Why]
MPO isn't enabled on some 4k videos due to video source width is 4096
and the current limit is 3840.
[How]
Changed the limit to 4096.
Signed-off-by: Isabel Zhang
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
From: Nicholas Kazlauskas
[Why]
DMCUB command table doesn't support ATOM_ENABLE/ATOM_DISABLE anymore
so we never end up calling the DCN init path in DMCUB.
[How]
Map ATOM_ENABLE to ATOM_INIT only for DMCUB command table offloading.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Tony Cheng
Summary Of Changes
* Code fixes/cleanups
* i2c frequency refactor
* DMCUB changes
* Update type fix
Anthony Koo (1):
drm/amd/display: Refactor to remove diags specific rgam func
Aric Cyr (1):
drm/amd/display: 3.2.69
Brandon Syu (1):
drm/amd/display: fix rotation_angle to use enum values
From: Nicholas Kazlauskas
[Why]
If the command table isn't available then we can fallback to DMCUB
offloading if it's enabled and available.
[How]
Instead of assigning NULL for supported command table functions we can
fallback to the DMCUB when it's available.
Signed-off-by: Nicholas
From: Nicholas Kazlauskas
[Why]
For DMCUB enabled hardware DC has a dependency on DMCUB already being
running.
Command table offloading will fail on first modeset if DMCUB isn't
initialized first.
[How]
Perform DMCUB hardware initialization before DC.
Signed-off-by: Nicholas Kazlauskas
From: Haiyi Zhou
Switched to C-style comments for consistency
Signed-off-by: Haiyi Zhou
Reviewed-by: Reza Amini
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Sung Lee
[Why]
The DP 1.4a Spec requires that training pattern only under certain
specific conditions. Currently driver will re-send
training pattern every time voltage swing value changes,
but that should not be the case.
[How]
Do not re-send training pattern every time VS values
are
From: Lewis Huang
[Why]
Driver didn't init hw i2c speed cause hdcp hw cannot
send command, because the default value of speed register
is 0x2.
[How]
Restore the default speed when release i2c engine
Signed-off-by: Lewis Huang
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
From: Nicholas Kazlauskas
[Why]
We'll need this to perform a clean shutdown before unloading the driver.
[How]
It will call reset internally and set hw_init to false. It won't do
anything if the hardware isn't initialized.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Tony Cheng
Acked-by:
From: Wenjing Liu
[how]
Empty dsc enc caps when debug option is set to disable DSC.
Signed-off-by: Wenjing Liu
Reviewed-by: Nikola Cornij
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 3 ++-
2 files changed,
From: Sung Lee
[Why]
The DP 1.4a Spec requires that training pattern only under certain
specific conditions. Currently driver will re-send
training pattern every time voltage swing value changes,
but that should not be the case.
[How]
Do not re-send training pattern every time VS values
are
Summary Of Changes
* Code fixes/cleanups
* i2c frequency refactor
* DMCUB changes
* Update type fix
Anthony Koo (1):
drm/amd/display: Refactor to remove diags specific rgam func
Aric Cyr (1):
drm/amd/display: 3.2.69
Brandon Syu (1):
drm/amd/display: fix rotation_angle to use enum values
From: Wenjing Liu
[why]
On video test pattern request we need to update MSA and VSC so
it will match the requested test pattern dynamic range field.
[how]
Update dynamic range field in MSA and disable VSC as updating VSC
info packet is complicated and not required for test pattern purpose.
From: Nicholas Kazlauskas
[Why]
Under some hardware initialization sequences the fb base/fb offset
provided can be zero or hardwareinit can happen too late.
We want to ensure that we always have the correct fb_base/fb_offset
when performing DMCUB hardware initialization so we can do DMCUB
From: Wenjing Liu
[how]
Empty dsc enc caps when debug option is set to disable DSC.
Change-Id: I95e63c63bb0513a80144087c8327dcdcfa23c494
Signed-off-by: Wenjing Liu
Reviewed-by: Nikola Cornij
Acked-by: Bhawanpreet Lakha
IP-reviewed-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/dc.h
On Thu, Jan 16, 2020 at 1:57 PM Hawking Zhang wrote:
>
> discovery tmr size should be ASIC specific setting, instead
> of fixed 64KB for all ASICs.
>
> Signed-off-by: Hawking Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c |
On Thu, Jan 16, 2020 at 7:44 AM Christian König
wrote:
>
> Am 16.01.20 um 11:00 schrieb chen gong:
> > Move amdgpu_virt_kiq_rreg/amdgpu_virt_kiq_wreg function to amdgpu_gfx.c,
> > and rename them to amdgpu_kiq_rreg/amdgpu_kiq_wreg.Make it generic and
> > flexible.
> >
> > Signed-off-by: chen gong
discovery tmr size should be ASIC specific setting, instead
of fixed 64KB for all ASICs.
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 58 ++-
IP discovery is only supported in Navi series and onwards.
There is no need to reserve a portion of vram as discovery
tmr region for pre-Navi adapters.
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff
On Thu, Jan 16, 2020 at 12:27 PM Luben Tuikov wrote:
>
> On 2020-01-15 12:31, Alex Deucher wrote:
> > Switch to a blacklist so we can disable specific boards
> > that are problematic.
> >
> > Signed-off-by: Alex Deucher
> > ---
> > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 42
From: Sam Bobroff
[ Upstream commit 62d91dd2851e8ae2ca552f1b090a3575a4edf759 ]
The INTERRUPT_CNTL2 register expects a valid DMA address, but is
currently set with a GPU MC address. This can cause problems on
systems that detect the resulting DMA read from an invalid address
(found on a Power8
From: Sam Bobroff
[ Upstream commit 62d91dd2851e8ae2ca552f1b090a3575a4edf759 ]
The INTERRUPT_CNTL2 register expects a valid DMA address, but is
currently set with a GPU MC address. This can cause problems on
systems that detect the resulting DMA read from an invalid address
(found on a Power8
On 2020-01-15 12:31, Alex Deucher wrote:
> Switch to a blacklist so we can disable specific boards
> that are problematic.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 42 ---
> 1 file changed, 38 insertions(+), 4 deletions(-)
>
> diff
From: Sam Bobroff
[ Upstream commit 62d91dd2851e8ae2ca552f1b090a3575a4edf759 ]
The INTERRUPT_CNTL2 register expects a valid DMA address, but is
currently set with a GPU MC address. This can cause problems on
systems that detect the resulting DMA read from an invalid address
(found on a Power8
On 2020-01-16 09:43, Nirmoy Das wrote:
> This also replaces old artifacts with a correct one in drm_sched_entity_init()
> declaration
>
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/scheduler/sched_entity.c | 2 +-
> include/drm/gpu_scheduler.h | 10 +-
> 2 files
From: Sam Bobroff
[ Upstream commit 62d91dd2851e8ae2ca552f1b090a3575a4edf759 ]
The INTERRUPT_CNTL2 register expects a valid DMA address, but is
currently set with a GPU MC address. This can cause problems on
systems that detect the resulting DMA read from an invalid address
(found on a Power8
From: Dan Carpenter
[ Upstream commit 4ff17a1df7d550257972a838220a8af4611c8f2c ]
Smatch complains that we need to initialized "*cap" otherwise it can
lead to an uninitialized variable bug in the caller. This seems like a
reasonable warning and it doesn't hurt to silence it at least.
From: yu kuai
[ Upstream commit d0580c09c65cff211f589a40e08eabc62da463fb ]
Fixes gcc warning:
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:431: warning: Excess function
parameter 'sw' description in 'vcn_v2_5_disable_clock_gating'
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:550: warning: Excess function
On Thu, Jan 16, 2020 at 8:09 AM Christian König
wrote:
>
> Coreboot seems to have a problem correctly setting up access to the stolen
> VRAM
> on KV/KB. Use the direct access only when necessary.
>
> Signed-off-by: Christian König
Acked-by: Alex Deucher
> ---
>
Am 16.01.20 um 16:26 schrieb Alex Deucher:
On Wed, Jan 15, 2020 at 8:51 PM Li, Dennis wrote:
[AMD Official Use Only - Internal Distribution Only]
Hi, Alex,
it is better to refine the patch as a common function, not only used for
raven.
I originally had the name as
I'll test it out in a minute.
Tom
On 2020-01-16 10:28 a.m., Christian König wrote:
We don't need to return an error in this case.
Signed-off-by: Christian König
Fixes: d6932a4d86e4 drm/amdgpu: make sure to never allocate PDs/PTs for
invalidations
---
We don't need to return an error in this case.
Signed-off-by: Christian König
Fixes: d6932a4d86e4 drm/amdgpu: make sure to never allocate PDs/PTs for
invalidations
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git
On Wed, Jan 15, 2020 at 8:51 PM Li, Dennis wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi, Alex,
> it is better to refine the patch as a common function, not only used
> for raven.
I originally had the name as gfx_v9_0_check_disable_gfxoff(), but I
changed it to be
Am 16.01.20 um 15:43 schrieb Nirmoy Das:
This also replaces old artifacts with a correct one in drm_sched_entity_init()
declaration
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/scheduler/sched_entity.c | 2 +-
include/drm/gpu_scheduler.h | 10
On Wed, Jan 15, 2020 at 2:44 AM Daniel Drake wrote:
>
> On Thu, Dec 19, 2019 at 10:08 PM Alex Deucher wrote:
> > I think there may be some AMD specific handling needed in
> > drivers/acpi/sleep.c. My understanding from reading the modern
> > standby documents from MS is that each vendor needs
Reviewed-by: James Zhu for the series
James
On 2020-01-15 7:45 p.m., Leo Liu wrote:
Fixes: 8ae1e132 "drm/amdgpu/vcn: support multiple instance direct SRAM read and
write"
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 6 +++---
1 file changed, 3 insertions(+), 3
This also replaces old artifacts with a correct one in drm_sched_entity_init()
declaration
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/scheduler/sched_entity.c | 2 +-
include/drm/gpu_scheduler.h | 10 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git
Coreboot seems to have a problem correctly setting up access to the stolen VRAM
on KV/KB. Use the direct access only when necessary.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
Am 16.01.20 um 11:00 schrieb chen gong:
Move amdgpu_virt_kiq_rreg/amdgpu_virt_kiq_wreg function to amdgpu_gfx.c,
and rename them to amdgpu_kiq_rreg/amdgpu_kiq_wreg.Make it generic and
flexible.
Signed-off-by: chen gong
Alex has the last word on this since I'm not so deep into the KIQ, but
Reviewed-by: Christian König
Am 16.01.20 um 07:32 schrieb Xu, Feifei:
Reviewed-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of Pan, Xinhui
Sent: Thursday, January 16, 2020 2:10 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: add
On Thu, Jan 16, 2020 at 09:44:55AM +0100, Thomas Zimmermann wrote:
> Hi
>
> Am 15.01.20 um 15:49 schrieb Ville Syrjälä:
> > On Wed, Jan 15, 2020 at 01:16:34PM +0100, Thomas Zimmermann wrote:
> >> @@ -2020,3 +2042,193 @@ int drm_crtc_queue_sequence_ioctl(struct
> >> drm_device *dev, void *data,
Reading CP_MEM_SLP_CNTL register with RREG32_SOC15 macro will lead to
hang when GPU is in "gfxoff" state.
I do a uniform substitution here.
Signed-off-by: chen gong
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git
Reading some registers by mmio will result in hang when GPU is in
"gfxoff" state.This problem can be solved by GPU in "ring command
packages" way.
Signed-off-by: chen gong
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
2 files
Move amdgpu_virt_kiq_rreg/amdgpu_virt_kiq_wreg function to amdgpu_gfx.c,
and rename them to amdgpu_kiq_rreg/amdgpu_kiq_wreg.Make it generic and
flexible.
Signed-off-by: chen gong
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 96
Hi
Am 15.01.20 um 15:49 schrieb Ville Syrjälä:
> On Wed, Jan 15, 2020 at 01:16:34PM +0100, Thomas Zimmermann wrote:
>> The callback get_vblank_timestamp() is currently located in struct
>> drm_driver, but really belongs into struct drm_crtc_funcs. Add an
>> equivalent there. Driver will be
On 1/13/20 9:07 AM, Ville Syrjälä wrote:
> On Mon, Jan 13, 2020 at 08:20:42AM -0500, mikita.lip...@amd.com wrote:
>> From: Mikita Lipski
>>
>> [why]
>> Fix compilation warnings on i386 architecture:
>> undefined reference to `__udivdi3'
>> [how]
>> Switch DIV_ROUND_UP to DIV64_U64_ROUND_UP
>>
>>
Hi
Am 15.01.20 um 15:37 schrieb Ville Syrjälä:
> On Wed, Jan 15, 2020 at 01:16:33PM +0100, Thomas Zimmermann wrote:
>> VBLANK interrupts can be disabled immediately or with a delay, where the
>> latter is the default. The former option can be selected by setting
>> get_vblank_timestamp, and
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