[AMD Official Use Only - Internal Distribution Only]
Acked-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Wednesday, July 22, 2020 12:52 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/powerplay: add some
No, the change below is not a good idea.
-#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) ||
defined(SWSMU_CODE_LAYER_L4)
+#if defined(SWSMU_CODE_LAYER_L1) || defined(SWSMU_CODE_LAYER_L2) ||
+defined(SWSMU_CODE_LAYER_L3) || defined(SWSMU_CODE_LAYER_L4)
These are used to guard a
Fix below warnings reported by coccicheck:
./drivers/gpu/drm/drm_drv.c:819:2-7: WARNING: NULL check before some freeing
functions is not needed.
Fixes: 5dad34f3c444 ("drm: Cleanups after drmm_add_final_kfree rollout")
Signed-off-by: Li Heng
---
drivers/gpu/drm/drm_drv.c | 3 +--
1 file
Fix below warnings reported by coccicheck:
./drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:557:2-7:
WARNING: NULL check before some freeing functions is not needed.
Fixes: 4d55b0dd1cdd ("drm/amd/display: Add DCN3 CLK_MGR")
Signed-off-by: Li Heng
---
Please see my comment about the patch organization
> -Original Message-
> From: Chen, Guchun
> Sent: Thursday, July 23, 2020 11:39 AM
> To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org;
> Deucher, Alexander ; Zhang, Hawking
> ; Li, Dennis ; Yang, Stanley
> ; Clements, John
> Subject: RE:
It's Ok to have the valid_in_vf setting as 1 for now.
As I know the sriov support for sienna_cichlid is not ready now.
We can revise these when that comes.
Reviewed-by: Evan Quan
BR,
Evan
-Original Message-
From: Sheng, Wenhui
Sent: Tuesday, July 21, 2020 4:09 PM
To: Gao, Likun ;
[AMD Public Use]
Hi Dennis,
To be honest, your suggestion is considered when I start the design. My thought
is in actual world, bad page threshold is one static configuration, it should
be set once when probing.
So module parameter is one ideal choice for this.
Regards,
Guchun
-Original
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Evan Quan
-Original Message-
From: Gao, Likun
Sent: Tuesday, July 21, 2020 2:30 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Sheng, Wenhui
; Quan, Evan ; Gao, Likun
Subject: [PATCH] drm/amd/powerplay:
[AMD Public Use]
Thanks for review, Stanley.
Re: [Yang, Stanley] : It's better to compare con->bad_page_cnt_threshold with
max_length, the value of bad_page_cnt_threshold should not exceed max_length.
Correct, one guard is necessary. It will be patch v2.
Regards,
Guchun
-Original
[AMD Public Use]
Thanks for your review, Tao.
Please check my comments after yours.
Regards,
Guchun
-Original Message-
From: Zhou1, Tao
Sent: Thursday, July 23, 2020 10:51 AM
To: Chen, Guchun ; amd-gfx@lists.freedesktop.org; Deucher,
Alexander ; Zhang, Hawking ;
Li, Dennis ; Yang,
Hi Dave, Daniel,
Couple of fixes for 5.8.
The following changes since commit adbe8a3cae94a63e9f416795c750237a9b789124:
Merge tag 'amd-drm-fixes-5.8-2020-07-15' of
git://people.freedesktop.org/~agd5f/linux into drm-fixes (2020-07-17 13:29:00
+1000)
are available in the Git repository at:
[AMD Official Use Only - Internal Distribution Only]
> -Original Message-
> From: Chen, Guchun
> Sent: Wednesday, July 22, 2020 11:14 AM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> ; Zhang, Hawking ;
> Li, Dennis ; Yang, Stanley ;
> Zhou1, Tao ; Clements, John
>
> Cc:
[AMD Official Use Only - Internal Distribution Only]
Hi, Guchun,
It is better to let user be able to change amdgpu_bad_page_threshold with
sysfs, so that users no need to reboot system when they want to change their
strategy.
Best Regards
Dennis Li
-Original Message-
From:
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Leo Liu
From: Zhang, Boyuan
Sent: July 22, 2020 5:50 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Leo
Subject: [PATCH] drm/amdgpu: update dec ring test for VCN 3.0
[AMD Official Use Only - Internal Distribution Only]
To
[AMD Official Use Only - Internal Distribution Only]
To enable SW ring for VCN 3.0
Signed-off-by: Boyuan Zhang mailto:boyuan.zh...@amd.com>>
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Hi, Joerg,
On Wed, Jul 22, 2020 at 04:03:40PM +0200, Joerg Roedel wrote:
> On Mon, Jul 13, 2020 at 04:47:56PM -0700, Fenghua Yu wrote:
> > PASID is defined as a few different types in iommu including "int",
> > "u32", and "unsigned int". To be consistent and to match with uapi
> > definitions,
On Wed, Jul 22, 2020 at 10:25 AM Michel Dänzer wrote:
>
> On 2020-07-22 3:10 p.m., Kazlauskas, Nicholas wrote:
> > On 2020-07-22 8:51 a.m., Daniel Vetter wrote:
> >> On Wed, Jul 22, 2020 at 2:38 PM Michel Dänzer wrote:
> >>>
> >>> From: Michel Dänzer
> >>>
> >>> drm_atomic_crtc_check enforces
Add support for reporting thermal throttling events through SMI.
Also, add a counter to count the number of throttling interrupts
observed and report the count in the SMI event message.
Signed-off-by: Mukul Joshi
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 4 ++
On Wed, Jul 22, 2020 at 4:25 PM Michel Dänzer wrote:
>
> On 2020-07-22 3:10 p.m., Kazlauskas, Nicholas wrote:
> > On 2020-07-22 8:51 a.m., Daniel Vetter wrote:
> >> On Wed, Jul 22, 2020 at 2:38 PM Michel Dänzer wrote:
> >>>
> >>> From: Michel Dänzer
> >>>
> >>> drm_atomic_crtc_check enforces
Am 22.07.20 um 16:30 schrieb Thomas Hellström (Intel):
On 2020-07-22 16:23, Christian König wrote:
Am 22.07.20 um 16:07 schrieb Daniel Vetter:
On Wed, Jul 22, 2020 at 3:12 PM Thomas Hellström (Intel)
wrote:
On 2020-07-22 14:41, Daniel Vetter wrote:
I'm pretty sure there's more bugs, I just
On 2020-07-22 16:23, Christian König wrote:
Am 22.07.20 um 16:07 schrieb Daniel Vetter:
On Wed, Jul 22, 2020 at 3:12 PM Thomas Hellström (Intel)
wrote:
On 2020-07-22 14:41, Daniel Vetter wrote:
I'm pretty sure there's more bugs, I just haven't heard from them yet.
Also due to the opt-in
[AMD Public Use]
Hi Andrey,
Aha, thanks for your reminding, I ignore that comment. Let me update it later.
Regards,
Guchun
-Original Message-
From: Grodzovsky, Andrey
Sent: Wednesday, July 22, 2020 10:26 PM
To: Chen, Guchun ; amd-gfx@lists.freedesktop.org; Deucher,
Alexander ;
On 7/21/20 11:14 PM, Guchun Chen wrote:
Use sizeof to get actual size.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
On 2020-07-22 3:10 p.m., Kazlauskas, Nicholas wrote:
> On 2020-07-22 8:51 a.m., Daniel Vetter wrote:
>> On Wed, Jul 22, 2020 at 2:38 PM Michel Dänzer wrote:
>>>
>>> From: Michel Dänzer
>>>
>>> drm_atomic_crtc_check enforces that ::active can only be true if
>>> ::enable is as well.
>>>
>>>
Am 22.07.20 um 16:07 schrieb Daniel Vetter:
On Wed, Jul 22, 2020 at 3:12 PM Thomas Hellström (Intel)
wrote:
On 2020-07-22 14:41, Daniel Vetter wrote:
I'm pretty sure there's more bugs, I just haven't heard from them yet.
Also due to the opt-in nature of dma-fence we can limit the scope of
On Mon, Jul 13, 2020 at 04:47:56PM -0700, Fenghua Yu wrote:
> PASID is defined as a few different types in iommu including "int",
> "u32", and "unsigned int". To be consistent and to match with uapi
> definitions, define PASID and its variations (e.g. max PASID) as "u32".
> "u32" is also shorter
On Wed, Jul 22, 2020 at 3:12 PM Thomas Hellström (Intel)
wrote:
> On 2020-07-22 14:41, Daniel Vetter wrote:
> > Ah I think I misunderstood which options you want to compare here. I'm
> > not sure how much pain fixing up "dma-fence as memory fence" really
> > is. That's kinda why I want a lot more
Reviewed-by:
Kevin Wang
> 在 2020年7月22日，下午9:37，Kenneth Feng 写道：
>
> It's not necessary to retrieve the power features status when the
> asic is booted up the first time. This patch can have the features
> enablement status still checked in suspend/resume case and removed
> from the first boot
It's not necessary to retrieve the power features status when the
asic is booted up the first time. This patch can have the features
enablement status still checked in suspend/resume case and removed
from the first boot up sequence.
Signed-off-by: Kenneth Feng
---
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Tom St Denis
Sent: Wednesday, July 22, 2020 7:40 AM
To: amd-gfx@lists.freedesktop.org
Cc: StDenis, Tom
Subject: [PATCH] drm/amd/amdgpu: Fix compiler
On 2020-07-22 14:41, Daniel Vetter wrote:
Ah I think I misunderstood which options you want to compare here. I'm
not sure how much pain fixing up "dma-fence as memory fence" really
is. That's kinda why I want a lot more testing on my annotation
patches, to figure that out. Not much feedback
On 2020-07-22 8:51 a.m., Daniel Vetter wrote:
On Wed, Jul 22, 2020 at 2:38 PM Michel Dänzer wrote:
From: Michel Dänzer
drm_atomic_crtc_check enforces that ::active can only be true if
::enable is as well.
Signed-off-by: Michel Dänzer
Looks fine to me. The check is sufficiently old
On Wed, Jul 22, 2020 at 2:38 PM Michel Dänzer wrote:
>
> From: Michel Dänzer
>
> drm_atomic_crtc_check enforces that ::active can only be true if
> ::enable is as well.
>
> Signed-off-by: Michel Dänzer
modeset vs modereset is a bit an inglorious name choice ... since this
seems to be glue code
On Wed, Jul 22, 2020 at 2:22 PM Thomas Hellström (Intel)
wrote:
>
>
> On 2020-07-22 13:39, Daniel Vetter wrote:
> > On Wed, Jul 22, 2020 at 12:31 PM Thomas Hellström (Intel)
> > wrote:
> >>
> >> On 2020-07-22 11:45, Daniel Vetter wrote:
> >>> On Wed, Jul 22, 2020 at 10:05 AM Thomas Hellström
From: Michel Dänzer
drm_atomic_crtc_check enforces that ::active can only be true if
::enable is as well.
Signed-off-by: Michel Dänzer
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c| 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git
On 2020-07-22 13:39, Daniel Vetter wrote:
On Wed, Jul 22, 2020 at 12:31 PM Thomas Hellström (Intel)
wrote:
On 2020-07-22 11:45, Daniel Vetter wrote:
On Wed, Jul 22, 2020 at 10:05 AM Thomas Hellström (Intel)
wrote:
On 2020-07-22 09:11, Daniel Vetter wrote:
On Wed, Jul 22, 2020 at 8:45 AM
Fix this warning:
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.o
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h:29,
from drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h:26,
from drivers/gpu/drm/amd/amdgpu/amdgpu.h:43,
from
On Wed, Jul 22, 2020 at 12:31 PM Thomas Hellström (Intel)
wrote:
>
>
> On 2020-07-22 11:45, Daniel Vetter wrote:
> > On Wed, Jul 22, 2020 at 10:05 AM Thomas Hellström (Intel)
> > wrote:
> >>
> >> On 2020-07-22 09:11, Daniel Vetter wrote:
> >>> On Wed, Jul 22, 2020 at 8:45 AM Thomas Hellström
On 2020-07-22 11:45, Daniel Vetter wrote:
On Wed, Jul 22, 2020 at 10:05 AM Thomas Hellström (Intel)
wrote:
On 2020-07-22 09:11, Daniel Vetter wrote:
On Wed, Jul 22, 2020 at 8:45 AM Thomas Hellström (Intel)
wrote:
On 2020-07-22 00:45, Dave Airlie wrote:
On Tue, 21 Jul 2020 at 18:47,
On Wed, Jul 22, 2020 at 10:05 AM Thomas Hellström (Intel)
wrote:
>
>
> On 2020-07-22 09:11, Daniel Vetter wrote:
> > On Wed, Jul 22, 2020 at 8:45 AM Thomas Hellström (Intel)
> > wrote:
> >>
> >> On 2020-07-22 00:45, Dave Airlie wrote:
> >>> On Tue, 21 Jul 2020 at 18:47, Thomas Hellström (Intel)
On Wed, Jul 22, 2020 at 04:00:45PM +0800, Zhu, Changfeng wrote:
> From: changzhu
>
> From: Changfeng
>
> The below 3 messages are not supported on Renoir
> SMU_MSG_PrepareMp1ForShutdown
> SMU_MSG_PrepareMp1ForUnload
> SMU_MSG_PrepareMp1ForReset
>
> It needs to revert patch:
>
On Wed, Jul 22, 2020 at 04:15:52PM +0800, Christian König wrote:
> Am 21.07.20 um 12:29 schrieb Huang Rui:
> > This patch is to introduce vmhub funcs helper to add following callback
> > (print_l2_protection_fault_status). Each GC/MMHUB register specific
> > programming
> > should be in
Am 21.07.20 um 12:29 schrieb Huang Rui:
This patch is to introduce vmhub funcs helper to add following callback
(print_l2_protection_fault_status). Each GC/MMHUB register specific programming
should be in gfxhub/mmhub level.
Signed-off-by: Huang Rui
---
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Kenneth Feng
-Original Message-
From: Zhu, Changfeng
Sent: Wednesday, July 22, 2020 4:01 PM
To: amd-gfx@lists.freedesktop.org; Feng, Kenneth ; Huang,
Ray
Cc: Zhu, Changfeng
Subject: [PATCH] Revert
On 2020-07-22 09:11, Daniel Vetter wrote:
On Wed, Jul 22, 2020 at 8:45 AM Thomas Hellström (Intel)
wrote:
On 2020-07-22 00:45, Dave Airlie wrote:
On Tue, 21 Jul 2020 at 18:47, Thomas Hellström (Intel)
wrote:
On 7/21/20 9:45 AM, Christian König wrote:
Am 21.07.20 um 09:41 schrieb Daniel
Hello,
re-sending and copying full DL
On Wed, Jul 22, 2020 at 4:51 AM Alex Deucher wrote:
> On Mon, Jul 20, 2020 at 6:00 AM Mauro Rossi wrote:
> >
> > Hi Christian,
> >
> > On Mon, Jul 20, 2020 at 11:00 AM Christian König
> > wrote:
> > >
> > > Hi Mauro,
> > >
> > > I'm not deep into the
[AMD Official Use Only - Internal Distribution Only]
Hi Guchun,
Please see my comment inline.
> -Original Message-
> From: Chen, Guchun
> Sent: Wednesday, July 22, 2020 11:14 AM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> ; Zhang, Hawking
> ; Li, Dennis ; Yang,
> Stanley
[AMD Public Use]
Good points, I'll reorganize and resubmit the patch after Guchuns changes are in
From: Zhang, Hawking
Sent: Tuesday, July 21, 2020 7:11 PM
To: Clements, John ; amd-gfx list
; Chen, Guchun
Subject: RE: [PATCH] drm/amdgpu: add RAS EEPROM support for sienna chichlid
[AMD
On Wed, Jul 22, 2020 at 8:45 AM Thomas Hellström (Intel)
wrote:
>
>
> On 2020-07-22 00:45, Dave Airlie wrote:
> > On Tue, 21 Jul 2020 at 18:47, Thomas Hellström (Intel)
> > wrote:
> >>
> >> On 7/21/20 9:45 AM, Christian König wrote:
> >>> Am 21.07.20 um 09:41 schrieb Daniel Vetter:
> On
On 2020-07-22 00:45, Dave Airlie wrote:
On Tue, 21 Jul 2020 at 18:47, Thomas Hellström (Intel)
wrote:
On 7/21/20 9:45 AM, Christian König wrote:
Am 21.07.20 um 09:41 schrieb Daniel Vetter:
On Mon, Jul 20, 2020 at 01:15:17PM +0200, Thomas Hellström (Intel)
wrote:
Hi,
On 7/9/20 2:33 PM,
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