[PATCH 20/20] drm/amd/display: 3.2.136

From: Aric Cyr Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Stylon Wang --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index

[PATCH 19/20] drm/amd/display: [FW Promotion] Release 0.0.66

From: Anthony Koo Signed-off-by: Anthony Koo Reviewed-by: Anthony Koo Acked-by: Stylon Wang --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

[PATCH 18/20] drm/amd/display: Refactor and add visual confirm for HW Flip Queue

From: Wyatt Wood [Why] Visual confirm will indicate if driver is programming the surface address. Refactor is required because much of the visual confirm logic is buried deep in the mpcc files. In addition, visual confirm is not updated during fast updates. [How] In order to have visual confirm

[PATCH 17/20] drm/amd/display: Use the correct max downscaling value for DCN3.x family

From: Nikola Cornij [why] As per spec, DCN3.x can do 6:1 downscaling and DCN2.x can do 4:1. The max downscaling limit value for DCN2.x is 250, which means it's calculated as 1000 / 4 = 250. For DCN3.x this then gives 1000 / 6 = 167. [how] Set maximum downscaling limit to 167 for DCN3.x

[PATCH 16/20] drm/amd/display: Avoid get/put vblank when stream disabled

From: Wayne Lin [Why] amdgpu_dm_crtc_set_crc_source() will call amdgpu_dm_crtc_configure_crc_source() to enable/disable CRC generation. However, configuration will be deferred to stream enabled. If stream is not enabled, current flow will still try to get/put vblank refcount. [How] Return

[PATCH 15/20] drm/amd/display: Correct DPCD revision for eDP v1.4

From: Zhan Liu [Why] eDP version and DPCD revision are different. Per VESA spec, "The DPCD revision for eDP v1.4 is 13h". SUPPORTED_LINK_RATES is valid since eDP v1.4 (DPCD_REV_13). [How] Correct DPCD_REV for eDP v1.4. Signed-off-by: Zhan Liu Reviewed-by: Nikola Cornij Acked-by: Stylon Wang

[PATCH 14/20] drm/amd/display: Add Overflow check to skip MALL

From: Bhawanpreet Lakha [Why] In some small modes (<200pixels) the stutter period is really big and will cause overflow. In these cases we shouldnt try to enable MALL as it will exceeds range of hysteresis timer (this can be seen in some IGT tests where the plane size is small) [How] Compare

[PATCH 13/20] drm/amd/display: Refactor suspend/resume of Secure display

From: Wayne Lin [Why] Once set ROI and do suspend/resume, current flow will not enable OTG_CRC_CTL again due to we'll defer crc configuration when stream is enabled. [How] Remove current suspend/resume function and have logic implemented into amdgpu_dm_atomic_commit_tail() Signed-off-by: Wayne

[PATCH 12/20] drm/amd/display: consider channel coding in configure lttpr mode

From: Wenjing Liu [why] Some lttpr configuration steps are exclusive to 8b/10b channel coding mode. We need to take channel conding into account. Signed-off-by: Wenjing Liu Reviewed-by: George Shen Acked-by: Stylon Wang Acked-by: Wesley Chalmers ---

[PATCH 11/20] drm/amd/display: rename perform_link_training_int function

From: Wenjing Liu [why] The function's name doesn't represent what it actaully does. The function implements necessary steps for our hardware to transition from link training mode back to video idle mode. Therefore, rename the function as dp_transition_to_video_idle so everyone can understand

[PATCH 10/20] drm/amd/display: decide link training settings based on channel coding

From: Wenjing Liu [how] Rename initialize_training_settings to decide_training_settings. Call get link encoding format and decide training settings based on current channel coding. Signed-off-by: Wenjing Liu Reviewed-by: George Shen Acked-by: Stylon Wang ---

[PATCH 09/20] drm/amd/display: determine dp link encoding format from link settings

From: Wenjing Liu [how] Implement a function that determines link encoding format based on the link settings passed in. Signed-off-by: Wenjing Liu Reviewed-by: George Shen Acked-by: Stylon Wang --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 7 +++

[PATCH 08/20] drm/amd/display: Disconnect non-DP with no EDID

From: Chris Park [Why] Active DP dongles return no EDID when dongle is connected, but VGA display is taken out. Current driver behavior does not remove the active display when this happens, and this is a gap between dongle DTP and dongle behavior. [How] For active DP dongles and non-DP

[PATCH 07/20] drm/amd/display: Minor refactor of DP PHY test automation

From: George Shen [Why] Improve readability and maintainability of code. [How] Refactor test pattern size calculation out of function call parameter and store value in variable. Signed-off-by: George Shen Reviewed-by: Wenjing Liu Acked-by: Stylon Wang ---

[PATCH 06/20] drm/amd/display: Document set RECOUT operation

From: Rodrigo Siqueira During the investigation on how to add visual confirmation on top of the planes used by DCN, it becomes evident that the lack of information in the code makes this work unnecessarily complicated. This commit introduces a set of documentation related to the RECOUT operation

[PATCH 04/20] drm/amd/display: Remove legacy comments

From: Rodrigo Siqueira To improve the code readability, this commit removes a set of commented and not used functions for a long time. Notice that now we have the amdgpu_dm_dtn_log, which prints all the relevant information that we need. Signed-off-by: Rodrigo Siqueira Reviewed-by: Harry

[PATCH 05/20] drm/amd/display: Add kernel-doc to some hubp functions

From: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira Reviewed-by: Harry Wentland Acked-by: Stylon Wang --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c

[PATCH 03/20] drm/amd/display: Add documentation for power gate plane

From: Rodrigo Siqueira This commit introduces kernel documentation to some essential functions related to power gate control over planes. It also adds a macro to make one part of the code easy to understand. Signed-off-by: Rodrigo Siqueira Reviewed-by: Harry Wentland Acked-by: Stylon Wang

[PATCH 02/20] drm/amd/display: Add get_current_time interface to dmub_srv

From: Wyatt Wood [Why] Need to get current DMUB time. [How] Add get_current_time interface to dmub_srv. Signed-off-by: Wyatt Wood Reviewed-by: Aric Cyr Acked-by: Stylon Wang --- drivers/gpu/drm/amd/display/dc/core/dc.c | 39 ++-

[PATCH 01/20] drm/amd/display: treat memory as a single-channel for asymmetric memory V3

From: Hugo Hu Previous patch caused crash and had been reverted. This patch addresses the issue without regression. [Why] 1. Driver use umachannelnumber to calculate watermarks for stutter. In asymmetric memory config, the actual bandwidth is less than dual-channel. The bandwidth should be the

[PATCH 00/20] DC Patches May 17, 2021

This DC patchset brings improvements in multiple areas. In summary, we highlight: * DC v3.2.136 * Improvements across DP, DMUB, code documentation, suspend/resume, etc -- Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.66 Aric Cyr (1): drm/amd/display: 3.2.136 Bhawanpreet

Re: [PATCH] add vbios info query

On Thu, May 13, 2021 at 11:03 PM Gu, JiaWei (Will) wrote: > > [AMD Official Use Only - Internal Distribution Only] > > Hi Tom, > > Can you help review & merge this patch to bring vbios IOCTL usage in UMR back? > The patch is also attached. We need to wait until the kernel driver patch lands in

Re: [PATCH] drm/amdgpu: Fill adev->unique_id with data from PF2VF msg

On Thu, May 13, 2021 at 11:47 PM Gu, JiaWei (Will) wrote: > > [AMD Official Use Only - Internal Distribution Only] > > Hi Alex, > > unique_id is fetched from FUSE_DATA on hypervisor. > > Under my experiment, both multi-VF & single VF can still read FUSE_DATA to > get it. > But per David's info,

RE: [PATCH] drm/amdgpu: Fill adev->unique_id with data from PF2VF msg

[AMD Official Use Only - Internal Distribution Only] Hi Alex, unique_id is fetched from FUSE_DATA on hypervisor. Under my experiment, both multi-VF & single VF can still read FUSE_DATA to get it. But per David's info, guest shouldn't be able to read it (though it can currently)... So I

Re: [PATCH] drm/amdgpu: Fill adev->unique_id with data from PF2VF msg

unique_id is normally fetched from the SMU on bare metal. I guess in the SR-IOV case, this would come from the hypervisor since the SMU is not normally handled in the VF. That makes sense for multi-VF, but what about single VF? Are you sure the ordering is correct such that the SMU value won't

RE: [PATCH] add vbios info query

[AMD Official Use Only - Internal Distribution Only] Hi Tom, Can you help review & merge this patch to bring vbios IOCTL usage in UMR back? The patch is also attached. Thanks in advance, Jiawei -Original Message- From: Jiawei Gu Sent: Wednesday, May 12, 2021 11:35 AM To: StDenis, Tom

RE: [PATCH] drm/amdgpu: Fill adev->unique_id with data from PF2VF msg

[AMD Official Use Only - Internal Distribution Only] pinging -Original Message- From: Gu, JiaWei (Will) Sent: Thursday, May 13, 2021 7:01 PM To: Jiawei Gu ; amd-gfx@lists.freedesktop.org; Nieto, David M Cc: Deng, Emily Subject: RE: [PATCH] drm/amdgpu: Fill adev->unique_id with data

RE: [PATCH] drm/amdgpu: Register bad page handler for Aldebaran

[AMD Official Use Only - Internal Distribution Only] > -Original Message- > From: Borislav Petkov > Sent: Thursday, May 13, 2021 10:58 AM > To: Alex Deucher > Cc: Joshi, Mukul ; x86-ml ; > Kasiviswanathan, Harish ; lkml ker...@vger.kernel.org>; amd-gfx@lists.freedesktop.org >

RE: [PATCH] drm/amdgpu: Register bad page handler for Aldebaran

[AMD Official Use Only - Internal Distribution Only] > -Original Message- > From: Borislav Petkov > Sent: Thursday, May 13, 2021 5:53 AM > To: Joshi, Mukul > Cc: amd-gfx@lists.freedesktop.org; Kasiviswanathan, Harish > ; x86-ml ; lkml ker...@vger.kernel.org> > Subject: Re: [PATCH]

Re: [PATCH 2/2] drm/amdgpu: Poll of RAS errors asynchronously

On Thu, May 13, 2021 at 3:35 PM Luben Tuikov wrote: > > On 2021-05-13 4:00 a.m., Christian König wrote: > > Am 12.05.21 um 19:03 schrieb Luben Tuikov: > >> When using Vega 20 with RAS support and RAS is > >> enabled, the system interactivity is extremely > >> slow, to the point of being unusable.

Re: [PATCH 1/2] drm/amdgpu: Don't query CE and UE errors

On Thu, May 13, 2021 at 1:32 AM Luben Tuikov wrote: > > On QUERY2 IOCTL don't query counts of correctable > and uncorrectable errors, since when RAS is > enabled and supported on Vega20 server boards, > this takes insurmountably long time, in O(n^3), > which slows the system down to the point of

Re: [PATCH 1/2] drm/amdgpu: Don't query CE and UE errors

On 2021-05-13 3:56 a.m., Christian König wrote: > > Am 12.05.21 um 19:03 schrieb Luben Tuikov: >> On QUERY2 IOCTL don't query counts of correctable >> and uncorrectable errors, since when RAS is >> enabled and supported on Vega20 server boards, >> this takes insurmountably long time, in O(n^3), >>

Re: [PATCH 2/2] drm/amdgpu: Poll of RAS errors asynchronously

On 2021-05-13 4:00 a.m., Christian König wrote: > Am 12.05.21 um 19:03 schrieb Luben Tuikov: >> When using Vega 20 with RAS support and RAS is >> enabled, the system interactivity is extremely >> slow, to the point of being unusable. After >> debugging, it was determined that this is due to >> the

Re: [PATCH 1/5] drm/fourcc: Add 16 bpc fixed point framebuffer formats.

On Thu, May 6, 2021 at 8:37 AM Ville Syrjälä wrote: > > On Sat, Mar 20, 2021 at 04:09:47AM +0200, Ville Syrjälä wrote: > > On Fri, Mar 19, 2021 at 10:45:10PM +0100, Mario Kleiner wrote: > > > On Fri, Mar 19, 2021 at 10:16 PM Ville Syrjälä > > > wrote: > > > > > > > > On Fri, Mar 19, 2021 at

Re: [PATCH 1/2] drm/amdgpu: free resources on fence usage query

On Thu, May 13, 2021 at 1:45 PM David M Nieto wrote: > > Free the resources if the fence needs to be ignored > during the ratio calculation > > Signed-off-by: David M Nieto Series is: Reviewed-by: Alex Deucher Will push it momentarily. Alex > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c |

[PATCH 1/2] drm/amdgpu: free resources on fence usage query

Free the resources if the fence needs to be ignored during the ratio calculation Signed-off-by: David M Nieto --- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

[PATCH 2/2] drm/amdgpu: fix fence calculation (v2)

The proper metric for fence utilization over several contexts is an harmonic mean, but such calculation is prohibitive in kernel space, so the code approximates it. Because the approximation diverges when one context has a very small ratio compared with the other context, this change filter out

Re: [PATCH 2/2] drm/amdgpu: fix fence calculation

[AMD Official Use Only - Internal Distribution Only] DOS line endings? That is weird I corrected the issues that showed in checkpatch.pl (the > 80 lines) I'll re-upload From: Christian König Sent: Thursday, May 13, 2021 1:11 AM To: Nieto, David M ;

Re: [PATCH v3] drm/amdgpu: flush TLB if valid PDE turns into PTE

Am 2021-05-13 um 12:58 p.m. schrieb Philip Yang: > Mapping huge page, 2MB aligned address with 2MB size, uses PDE0 as PTE. > If previously valid PDE0, PDE0.V=1 and PDE0.P=0 turns into PTE, this > requires TLB flush, otherwise page table walker will not read updated > PDE0. > > Change page table

Re: [PATCH 2/2] drm/amdkfd: heavy-weight flush TLB after unmap

Am 2021-05-13 um 12:58 p.m. schrieb Philip Yang: > Need do a heavy-weight TLB flush to make sure we have no more dirty data > in the cache for the unmapped pages. > > Add flush_type parameter to amdgpu_amdkfd_flush_gpu_tlb_pasid. > > Signed-off-by: Philip Yang The series is Reviewed-by: Felix

[PATCH 2/2] drm/amdkfd: heavy-weight flush TLB after unmap

Need do a heavy-weight TLB flush to make sure we have no more dirty data in the cache for the unmapped pages. Add flush_type parameter to amdgpu_amdkfd_flush_gpu_tlb_pasid. Signed-off-by: Philip Yang --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 4 ++--

[PATCH 1/2] Revert "drm/amdkfd: flush TLB after updating GPU page table"

This reverts commit bcbc99676607d4ff9fd15f27481cb1794a567d65. After "drm/amdgpu: flush TLB if valid PDE turns into PTE" is checked in, this workaround is not needed. --- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 3 --- 1 file changed, 3 deletions(-) diff --git

[PATCH v3] drm/amdgpu: flush TLB if valid PDE turns into PTE

Mapping huge page, 2MB aligned address with 2MB size, uses PDE0 as PTE. If previously valid PDE0, PDE0.V=1 and PDE0.P=0 turns into PTE, this requires TLB flush, otherwise page table walker will not read updated PDE0. Change page table update mapping to return table_freed flag to indicate the

[pull] amdgpu, radeon drm-fixes-5.13

Hi Dave, Daniel, Fixes for 5.13. The following changes since commit 875d598db60ac81e768fdfd2c589f6209038488b: MAINTAINERS: Update address for Emma Anholt (2021-05-11 20:38:08 +0200) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git

Re: [PATCH v2 1/1] drm/dp_mst: Use kHz as link rate units when settig source max link caps at init

Reviewed-by: Lyude Paul Will let this sit on the list for a few days to see if anyone's got any objections and then I'll go ahead and push it On Wed, 2021-05-12 at 17:00 -0400, Nikola Cornij wrote: > [why] > Link rate in kHz is what is eventually required to calculate the link > bandwidth,

Re: [PATCH v2] drm/amdkfd: disable kfd debugfs node of hang_hws on vf mode

[AMD Official Use Only - Internal Distribution Only] thanks @Kuehling, Felix, I have also noticed this problem, in the multi-GPU environment, there is no working well. Best Regards, Kevin From: Kuehling, Felix Sent: Friday, May

Re: [PATCH v2] drm/amdkfd: disable kfd debugfs node of hang_hws on vf mode

This won't work. the kfd_debugfs directory is system-wide. So you cannot have a per-GPU criteria for creating it. You may have one GPU that probes successfully, another that fails. You still need the debugfs. If you have multiple GPUs probing successfully, you only want to create the debugfs node

Re: [PATCH] drm/amdgpu: Register bad page handler for Aldebaran

On Thu, May 13, 2021 at 10:57 AM Borislav Petkov wrote: > > On Thu, May 13, 2021 at 10:32:45AM -0400, Alex Deucher wrote: > > Right. The sys admin can query the bad page count and decide when to > > retire the card. > > Yap, although the driver should actively "tell" the sysadmin when some >

Re: [PATCH] drm/amdgpu: Register bad page handler for Aldebaran

On Thu, May 13, 2021 at 10:32:45AM -0400, Alex Deucher wrote: > Right. The sys admin can query the bad page count and decide when to > retire the card. Yap, although the driver should actively "tell" the sysadmin when some critical counts of retired VRAM pages are reached because I doubt all

Re: [PATCH v7 09/16] drm/amdgpu: Guard against write accesses after device removal

On Thu, May 13, 2021 at 10:47 AM Andrey Grodzovsky wrote: > > > > On 2021-05-12 4:50 p.m., Alex Deucher wrote: > > On Wed, May 12, 2021 at 4:30 PM Andrey Grodzovsky > > wrote: > >> > >> > >> > >> On 2021-05-12 4:17 p.m., Alex Deucher wrote: > >>> On Wed, May 12, 2021 at 10:27 AM Andrey

Re: [PATCH v7 09/16] drm/amdgpu: Guard against write accesses after device removal

On 2021-05-12 4:50 p.m., Alex Deucher wrote: On Wed, May 12, 2021 at 4:30 PM Andrey Grodzovsky wrote: On 2021-05-12 4:17 p.m., Alex Deucher wrote: On Wed, May 12, 2021 at 10:27 AM Andrey Grodzovsky wrote: This should prevent writing to memory or IO ranges possibly already allocated

Re: [PATCH] drm/amdgpu: Register bad page handler for Aldebaran

On Thu, May 13, 2021 at 10:17:47AM -0400, Alex Deucher wrote: > The bad pages are stored in an EEPROM on the board and the next time > the driver loads it reads the EEPROM so that it can reserve the bad > pages at init time so they don't get used again. And that works automagically on the next

Re: [PATCH] drm/amdgpu: Complete multimedia bandwidth interface

[AMD Official Use Only - Internal Distribution Only] Reviewed-by: Alex Deucher From: amd-gfx on behalf of Liu, Monk Sent: Thursday, May 13, 2021 7:50 AM To: Zhang, Bokun ; amd-gfx@lists.freedesktop.org Cc: Zhang, Bokun Subject: RE: [PATCH] drm/amdgpu:

Re: [PATCH] drm/amdgpu: Register bad page handler for Aldebaran

On Thu, May 13, 2021 at 10:30 AM Borislav Petkov wrote: > > On Thu, May 13, 2021 at 10:17:47AM -0400, Alex Deucher wrote: > > The bad pages are stored in an EEPROM on the board and the next time > > the driver loads it reads the EEPROM so that it can reserve the bad > > pages at init time so they

Re: [PATCH] drm/amdgpu: Register bad page handler for Aldebaran

On Thu, May 13, 2021 at 9:26 AM Borislav Petkov wrote: > > On Thu, May 13, 2021 at 03:20:36AM +, Joshi, Mukul wrote: > > Exporting smca_get_bank_type() works fine when CONFIG_X86_MCE_AMD is > > defined. > > I would need to put #ifdef CONFIG_X86_MCE_AMD in my code to compile the > > amdgpu >

Re: [PATCH] drm/amd/amdgpu: psp program IH_RB_CTRL on sienna_cichlid

[AMD Public Use] Acked-by: Alex Deucher From: YuBiao Wang Sent: Thursday, May 13, 2021 6:33 AM To: amd-gfx@lists.freedesktop.org Cc: Grodzovsky, Andrey ; Quan, Evan ; Chen, Horace ; Tuikov, Luben ; Koenig, Christian ; Deucher, Alexander ; Xiao, Jack ; Zhang,

RE: [PATCH 2/3] drm/amd/pm: Fix showing incorrect frequencies on aldebaran

[AMD Public Use] 3 nit-picks inline. Regards, Guchun -Original Message- From: amd-gfx On Behalf Of Lijo Lazar Sent: Thursday, May 13, 2021 5:48 PM To: amd-gfx@lists.freedesktop.org Cc: Wang, Kevin(Yang) ; Feng, Kenneth ; Zhang, Hawking Subject: [PATCH 2/3] drm/amd/pm: Fix showing

Re: [PATCH] drm/amdgpu: Register bad page handler for Aldebaran

On Thu, May 13, 2021 at 03:20:36AM +, Joshi, Mukul wrote: > Exporting smca_get_bank_type() works fine when CONFIG_X86_MCE_AMD is defined. > I would need to put #ifdef CONFIG_X86_MCE_AMD in my code to compile the amdgpu > driver when CONFIG_X86_MCE_AMD is not defined. > I can avoid all that by

Re: [PATCH 2/3] drm/amd/pm: Fix showing incorrect frequencies on aldebaran

[AMD Official Use Only - Internal Distribution Only] From: Lazar, Lijo Sent: Thursday, May 13, 2021 7:53 PM To: Wang, Kevin(Yang) ; amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking ; Feng, Kenneth Subject: Re: [PATCH 2/3] drm/amd/pm: Fix showing incorrect

Re: [PATCH 2/3] drm/amd/pm: Fix showing incorrect frequencies on aldebaran

On 5/13/2021 5:06 PM, Wang, Kevin(Yang) wrote: [AMD Official Use Only - Internal Distribution Only] *From:* Lazar, Lijo *Sent:* Thursday, May 13, 2021 5:47 PM *To:* amd-gfx@lists.freedesktop.org *Cc:* Zhang, Hawking

RE: [PATCH] drm/amdgpu: Complete multimedia bandwidth interface

[AMD Official Use Only - Internal Distribution Only] Reviewed-by: Monk liu Better get open source team's RB as well Thanks -- Monk Liu | Cloud-GPU Core team -- -Original Message- From: amd-gfx On

Re: [PATCH 2/3] drm/amd/pm: Fix showing incorrect frequencies on aldebaran

[AMD Official Use Only - Internal Distribution Only] From: Lazar, Lijo Sent: Thursday, May 13, 2021 5:47 PM To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking ; Feng, Kenneth ; Wang, Kevin(Yang) Subject: [PATCH 2/3] drm/amd/pm: Fix showing incorrect

RE: [PATCH] drm/amdgpu: Fill adev->unique_id with data from PF2VF msg

[AMD Official Use Only - Internal Distribution Only] Add David. -Original Message- From: Jiawei Gu Sent: Thursday, May 13, 2021 2:41 PM To: amd-gfx@lists.freedesktop.org Cc: Deng, Emily ; Gu, JiaWei (Will) Subject: [PATCH] drm/amdgpu: Fill adev->unique_id with data from PF2VF msg

[PATCH] drm/amd/amdgpu: psp program IH_RB_CTRL on sienna_cichlid

[Why] IH_RB_CNTL is blocked by PSP so we need to ask psp to help config it. [How] Move psp ip block before ih, and use psp to program IH_RB_CNTL under sriov. Signed-off-by: YuBiao Wang --- drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++-- drivers/gpu/drm/amd/amdgpu/nv.c

[PATCH 3/3] drm/amd/pm: Reset max GFX clock after disabling determinism

When determinism mode is disabled on aldebaran, max GFX clock will be reset to default max frequency value. Signed-off-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git

[PATCH 2/3] drm/amd/pm: Fix showing incorrect frequencies on aldebaran

Use the current and custom pstate frequencies to track the current and user-set min/max values in manual and determinism mode. Previously, only actual_* value was used to track the currrent and user requested value. The value will get reassigned whenever user requests a new value with

[PATCH 1/3] drm/amd/pm: Add custom/current freq to pstates

Add custom member for user requested custom frequency, level mask or min/max frequencies. Add curr member to keep track of the current active values. Signed-off-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 8 1 file changed, 8 insertions(+) diff --git

Re: [PATCH 2/2] drm/amdgpu: fix fence calculation

Am 12.05.21 um 21:45 schrieb David M Nieto: The proper metric for fence utilization over several contexts is an harmonic mean, but such calculation is prohibitive in kernel space, so the code approximates it. Because the approximation diverges when one context has a very small ratio compared

[PATCH v2] drm/amdkfd: disable kfd debugfs node of hang_hws on vf mode

v1: the kfd debugfs node is rely on kgd2kfd probe success, if not, the kfd_debugfs should not be created, and the node of "hang_hws" should be disabled on vf mode. v2: also move kfd_debugfs_fini() into kgd2kfd_device_exit() function. 1. move kfd_debugfs_init() function into kgd2kfd_probe()

Re: [PATCH v2] drm/amdgpu: flush TLB if valid PDE turns into PTE

Am 12.05.21 um 20:43 schrieb Philip Yang: Mapping huge page, 2MB aligned address with 2MB size, uses PDE0 as PTE. If previously valid PDE0, PDE0.V=1 and PDE0.P=0 turns into PTE, this requires TLB flush, otherwise page table walker will not read updated PDE0. Change page table update mapping

Re: [PATCH] drm/amdgpu: flush TLB if valid PDE turns into PTE

Am 12.05.21 um 20:40 schrieb philip yang: On 2021-05-12 11:54 a.m., Felix Kuehling wrote: Am 2021-05-12 um 8:38 a.m. schrieb Christian König: Am 12.05.21 um 14:34 schrieb Philip Yang: Mapping huge page, 2MB aligned address with 2MB size, uses PDE0 as PTE. If previously valid PDE0, PDE0.V=1

Re: [PATCH 2/2] drm/amdgpu: Poll of RAS errors asynchronously

Am 12.05.21 um 19:03 schrieb Luben Tuikov: When using Vega 20 with RAS support and RAS is enabled, the system interactivity is extremely slow, to the point of being unusable. After debugging, it was determined that this is due to the polling loop performed for AMDGPU_CTX_OP_QUERY_STATE2 under

Re: [PATCH 1/2] drm/amdgpu: Don't query CE and UE errors

Am 12.05.21 um 19:03 schrieb Luben Tuikov: On QUERY2 IOCTL don't query counts of correctable and uncorrectable errors, since when RAS is enabled and supported on Vega20 server boards, this takes insurmountably long time, in O(n^3), which slows the system down to the point of it being unusable

Re: [PATCH] drm/amdgpu: remove unsafe optimization to drop preamble ib

Am 13.05.21 um 05:21 schrieb Jiansong Chen: Take the situation with gfxoff, the optimization may cause corrupt CE ram contents. In addition emit_cntxcntl callback has similar optimization which firmware can handle properly even for power feature. NAK, it is the whole purpose of the preamble IB

[PATCH] drm/amdkfd: disable kfd debugfs node of hang_hws on vf mode

the kfd debugfs node is rely on kgd2kfd probe success, if not, the kfd_debugfs should not be created, and the node of "hang_hws" should be disabled on vf mode. 1. move kfd_debugfs_init() function into kgd2kfd_probe() function. 2. disable "hang_hws" debugfs node on vf mode. Signed-off-by: Kevin

[PATCH] drm/amdgpu: Fill adev->unique_id with data from PF2VF msg

Initialize unique_id from PF2VF under virtualization. Signed-off-by: Jiawei Gu --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index a57842689d42..96e269cbe326