On 2021-08-26 12:55 a.m., Liu, Monk wrote:
[AMD Official Use Only]
But for timer pending case (common case) your mod_delayed_work will effectively
do exactly the same if you don't use per job TTLs - you mod it to
sched->timeout value which resets the pending timer to again count from 0.
issue:
in cleanup_job the cancle_delayed_work will cancel a TO timer
even the its corresponding job is still running.
fix:
do not cancel the timer in cleanup_job, instead do the cancelling
only when the heading job is signaled, and if there is a "next" job
we start_timeout again.
v2:
further
[AMD Official Use Only]
>>But for timer pending case (common case) your mod_delayed_work will
>>effectively do exactly the same if you don't use per job TTLs - you mod it to
>> sched->timeout value which resets the pending timer to again count from 0.
Ny patch will only modify the timer
Hi Dave, Daniel,
A few last fixes for 5.14.
The following changes since commit daa7772d477ec658dc1fd9127549a7996d8e0c2b:
Merge tag 'amd-drm-fixes-5.14-2021-08-18' of
https://gitlab.freedesktop.org/agd5f/linux into drm-fixes (2021-08-20 15:13:56
+1000)
are available in the Git repository
On 2021-08-25 10:31 p.m., Liu, Monk wrote:
[AMD Official Use Only]
Hi Andrey
I'm not quite sure if I read you correctly
Seems to me you can only do it for empty pending list otherwise you risk
cancelling a legit new timer that was started by the next job or not restarting
timer at all
[AMD Official Use Only]
Hi Andrey
I'm not quite sure if I read you correctly
>>Seems to me you can only do it for empty pending list otherwise you risk
>>cancelling a legit new timer that was started by the next job or not
>>restarting timer at all since your timer was still pending when next
On Wed, Aug 25, 2021 at 9:10 PM Aurabindo Pillai
wrote:
>
> [Why & How]
> The DCN3 SoC parameter num_states was calculated but not saved into the
> object.
>
> Signed-off-by: Aurabindo Pillai
> Cc: sta...@vger.kernel.org
Please add:
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403
to
AMD polaris GPUs have an issue about audio noise on RKL platform,
they provide a commit to fix but for SMU7-based GPU still
need another module parameter,
modprobe amdgpu ppfeaturemask=0xfff7bffb
to avoid the module parameter, switch PCI_DPM by determining
intel platform in amd drm driver is a
AMD polaris GPUs have an issue about audio noise on RKL platform,
they provide a commit to fix but for SMU7-based GPU still
need another module parameter,
modprobe amdgpu ppfeaturemask=0xfff7bffb
to avoid the module parameter, switch PCI_DPM by determining
intel platform in amd drm driver is a
[AMD Official Use Only]
>> All we need to take care of is to cancel_delayed_work() when we know that
>> the job is completed.
That's why I want to remove the cancel_delayed_work in the beginning of
cleanup_job(), because in that moment we don't know if
There is a job completed (sched could be
[Why & How]
DML is initialized again unnecessarily after its done conditionally.
Remove the duplicate initialization
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 5 -
1 file changed, 5 deletions(-)
diff --git
From: Nicholas Kazlauskas
[Why]
This is a global parameter, not a per pipe parameter and it's useful
for experimenting with the prefetch schedule to be adjustable from
the SOC bb.
[How]
Add a parameter to the SOC bb, default is the existing policy for
all DCN. Fill it in when filling SOC bb
[Why & How]
The DCN3 SoC parameter num_states was calculated but not saved into the
object.
Signed-off-by: Aurabindo Pillai
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git
From: "Jerry (Fangzhi) Zuo"
[Why]
Drop hardcoded dispclk, dppclk, phyclk
[How]
Read the corresponding values from clock table entries already populated.
Signed-off-by: Jerry (Fangzhi) Zuo
Signed-off-by: Aurabindo Pillai
Cc: sta...@vger.kernel.org
---
[AMD Official Use Only]
Thanks for pointing out the mistake.
Reviewed-by: Fangzhi Zuo
-Original Message-
From: Deucher, Alexander
Sent: August 25, 2021 1:07 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zuo, Jerry
Subject: [PATCH] drm/amdgpu/display: fix logic
1) Generalize the function--if the user didn't set
i2c_address, still return true/false to indicate
whether VBIOS contains the RAS EEPROM address.
This function shouldn't evaluate whether the use
set the i2c_address pointer or not.
2) Don't touch the caller's i2c_address, unless
We can now process any RAS EEPROM address from
VBIOS. Generalize so as to compute the top three
bits of the 19-bit EEPROM address, from any byte
returned as the "i2c address" from VBIOS.
Cc: John Clements
Cc: Hawking Zhang
Cc: Alex Deucher
Signed-off-by: Luben Tuikov
---
On 8/25/2021 2:46 AM, Christoph Hellwig wrote:
On Tue, Aug 24, 2021 at 10:48:17PM -0500, Alex Sierra wrote:
} else {
- if (!(migrate->flags & MIGRATE_VMA_SELECT_SYSTEM))
+ if (!(migrate->flags & MIGRATE_VMA_SELECT_SYSTEM) &&
+
On 2021-08-25 8:11 a.m., Christian König wrote:
No, this would break that logic here.
See drm_sched_start_timeout() can be called multiple times, this is
intentional and very important!
The logic in queue_delayed_work() makes sure that the timer is only
started once and then never again.
On 8/22/21 6:19 PM, Jim Cromie wrote:
> Add a const void* data member to the struct, to allow attaching
> private data that will be used soon by a setter method (via kp->data)
> to perform more elaborate actions.
>
> To attach the data at compile time, add new macros:
>
>
On 8/22/21 6:20 PM, Jim Cromie wrote:
> DEFINE_DYNAMIC_DEBUG_CATEGORIES(name, var, bitmap_desc, @bit_descs)
> allows users to define a drm.debug style (bitmap) sysfs interface, and
> to specify the desired mapping from bits[0-N] to the format-prefix'd
> pr_debug()s to be controlled.
>
>
On 8/22/21 6:19 PM, Jim Cromie wrote:
> This patchset does 3 main things.
>
> Adds DEFINE_DYNAMIC_DEBUG_CATEGORIES to define bitmap => category
> control of pr_debugs, and to create their sysfs entries.
>
> Uses it in amdgpu, i915 to control existing pr_debugs according to
> their ad-hoc
On 8/25/21 4:15 AM, Vlastimil Babka wrote:
On 8/25/21 05:48, Alex Sierra wrote:
From: Ralph Campbell
ZONE_DEVICE struct pages have an extra reference count that complicates the
code for put_page() and several places in the kernel that need to check the
reference count to see that a page is
This new debugfs interface uses an IOCTL interface in order to pass
along state information like SRBM and GRBM bank switching. This
new interface also allows a full 32-bit MMIO address range which
the previous didn't. With this new design we have room to grow
the flexibility of the file as need
Commit 5de27e1d6755 ("drm/amd/display: Add DP 2.0 SST DC Support")
added a new check for DP 2.0 with a CONFIG_DRM_AMD_DC_DCN check
that removed a bunch of logic if CONFIG_DRM_AMD_DC_DCN was not set,
restore that logic.
Fixes: 5de27e1d6755 ("drm/amd/display: Add DP 2.0 SST DC Support")
Cc: Fangzhi
Applied. Thanks!
Alex
On Wed, Aug 25, 2021 at 10:09 AM Harry Wentland wrote:
>
> On 2021-08-25 7:36 a.m., Colin King wrote:
> > From: Colin Ian King
> >
> > There is a spelling mistake in a DC_LOG_WARNING message. Fix it.
> >
> > Signed-off-by: Colin Ian King
>
> Reviewed-by: Harry Wentland
On Wed, Aug 25, 2021 at 10:33 PM Alex Deucher wrote:
>
> On Wed, Aug 25, 2021 at 10:22 AM Lazar, Lijo wrote:
> >
> >
> >
> > On 8/25/2021 4:46 PM, Koba Ko wrote:
> > > On Wed, Aug 25, 2021 at 6:24 PM Jani Nikula
> > > wrote:
> > >>
> > >> On Wed, 25 Aug 2021, Koba Ko wrote:
> > >>> On Wed,
In preparation for FORTIFY_SOURCE performing compile-time and run-time
field bounds checking for memcpy(), memmove(), and memset(), avoid
intentionally writing across neighboring fields.
The "Board Parameters" members of the structs:
struct atom_smc_dpm_info_v4_5
struct
[Public]
Acked-by: Alex Deucher
From: Quan, Evan
Sent: Tuesday, August 24, 2021 11:58 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Chen, Guchun
; Quan, Evan
Subject: [PATCH] drm/amdgpu: reenable BACO support for 699F:C7 polaris12 SKU
This
On Tue, Aug 24, 2021 at 10:48:15PM -0500, Alex Sierra wrote:
> From: Ralph Campbell
>
> There are several places where ZONE_DEVICE struct pages assume a reference
> count == 1 means the page is idle and free. Instead of open coding this,
> add a helper function to hide this detail.
>
>
Currently AMDGPU_RING_PRIO_MAX is redefinition of a
max gfx hwip priority, this won't work well when we will
have a hwip with different set of priorities than gfx.
Also, HW ring priorities are different from ring priorities.
Create a global enum for ring priority levels which each
HWIP can use to
On 2021-08-25 2:43 a.m., Christian König wrote:
Am 24.08.21 um 23:01 schrieb Andrey Grodzovsky:
Handle all DMA IOMMU group related dependencies before the
group is removed and we try to access it after free.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
On Tue, Aug 24, 2021 at 10:48:15PM -0500, Alex Sierra wrote:
> From: Ralph Campbell
>
> There are several places where ZONE_DEVICE struct pages assume a reference
> count == 1 means the page is idle and free. Instead of open coding this,
> add a helper function to hide this detail.
>
>
[AMD Official Use Only]
I think it would be good to put the IOCTL structures in their own header to
make it easier to share with umr. No need to put it in uapi area though. We
also need a umr branch that utilizes this to upstream the changes.
Alex
From:
Am 2021-08-24 um 11:10 p.m. schrieb Sean Keely:
> On systems with multiple SH per SE compute_static_thread_mgmt_se#
> is split into independent masks, one for each SH, in the upper and
> lower 16 bits. We need to detect this and apply cu masking to each
> SH. The cu mask bits are assigned first
Am 25.08.21 um 15:09 schrieb Tom St Denis:
This new debugfs interface uses an IOCTL interface in order to pass
along state information like SRBM and GRBM bank switching. This
new interface also allows a full 32-bit MMIO address range which
the previous didn't. With this new design we have room
Am 2021-08-24 um 11:48 p.m. schrieb Alex Sierra:
> When CPU is connected throug XGMI, it has coherent
> access to VRAM resource. In this case that resource
> is taken from a table in the device gmc aperture base.
> This resource is used along with the device type, which could
> be DEVICE_PRIVATE
This new debugfs interface uses an IOCTL interface in order to pass
along state information like SRBM and GRBM bank switching. This
new interface also allows a full 32-bit MMIO address range which
the previous didn't. With this new design we have room to grow
the flexibility of the file as need
Am 2021-08-24 um 11:48 p.m. schrieb Alex Sierra:
> In this case, this is used to migrate pages from device memory, back to
> system memory. This particular device memory type should be accessible
> by the CPU, through IOMEM access. Typically, zone device public type
> memory falls into this
Am 2021-08-24 um 11:48 p.m. schrieb Alex Sierra:
> Ref counter from device pages is init to zero during memmap init zone.
> The first time a new device page is allocated to migrate data into it,
> its ref counter needs to be initialized to one.
>
> Signed-off-by: Alex Sierra
> ---
>
On Wed, Aug 25, 2021 at 10:22 AM Lazar, Lijo wrote:
>
>
>
> On 8/25/2021 4:46 PM, Koba Ko wrote:
> > On Wed, Aug 25, 2021 at 6:24 PM Jani Nikula
> > wrote:
> >>
> >> On Wed, 25 Aug 2021, Koba Ko wrote:
> >>> On Wed, Aug 25, 2021 at 5:22 PM Jani Nikula
> >>> wrote:
>
> On Wed, 25
On 8/25/2021 4:46 PM, Koba Ko wrote:
On Wed, Aug 25, 2021 at 6:24 PM Jani Nikula wrote:
On Wed, 25 Aug 2021, Koba Ko wrote:
On Wed, Aug 25, 2021 at 5:22 PM Jani Nikula wrote:
On Wed, 25 Aug 2021, Koba Ko wrote:
AMD polaris GPUs have an issue about audio noise on RKL platform,
they
On 2021-08-25 7:36 a.m., Colin King wrote:
> From: Colin Ian King
>
> There is a spelling mistake in a DC_LOG_WARNING message. Fix it.
>
> Signed-off-by: Colin Ian King
Reviewed-by: Harry Wentland
Harry
> ---
> drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +-
> 1 file
Am 25.08.21 um 15:35 schrieb Das, Nirmoy:
On 8/25/2021 2:29 PM, Christian König wrote:
Am 25.08.21 um 14:20 schrieb Lazar, Lijo:
On 8/25/2021 4:52 PM, Nirmoy Das wrote:
To get a hardware queue priority for a context, we are currently
mapping AMDGPU_CTX_PRIORITY_* to DRM_SCHED_PRIORITY_*
On 8/25/2021 2:29 PM, Christian König wrote:
Am 25.08.21 um 14:20 schrieb Lazar, Lijo:
On 8/25/2021 4:52 PM, Nirmoy Das wrote:
To get a hardware queue priority for a context, we are currently
mapping AMDGPU_CTX_PRIORITY_* to DRM_SCHED_PRIORITY_* and then
to hardware queue priority, which is
On Wed, Aug 25, 2021 at 4:01 AM Christian König
wrote:
>
> Am 25.08.21 um 09:44 schrieb Yifan Zhang:
> > amdgpu_bo_get_preferred_pin_domain was added to handle system memory
> > page tables. Since system memory pt/pd is disabled now, remove preferred
> > domain judgement to avoid confusion.
>
>
On 8/25/2021 4:52 PM, Nirmoy Das wrote:
To get a hardware queue priority for a context, we are currently
mapping AMDGPU_CTX_PRIORITY_* to DRM_SCHED_PRIORITY_* and then
to hardware queue priority, which is not the right way to do that
as DRM_SCHED_PRIORITY_* is software scheduler's priority
Please cc dri-devel on all scheduler patches. It's core functionality.
Alex
On Wed, Aug 25, 2021 at 12:14 AM Monk Liu wrote:
>
> the original logic is wrong that the timeout will not be retriggerd
> after the previous job siganled, and that lead to the scenario that all
> jobs in the same
From: Colin Ian King
There is a spelling mistake in a DC_LOG_WARNING message. Fix it.
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Tue, Aug 24, 2021 at 10:48:17PM -0500, Alex Sierra wrote:
> } else {
> - if (!(migrate->flags & MIGRATE_VMA_SELECT_SYSTEM))
> + if (!(migrate->flags & MIGRATE_VMA_SELECT_SYSTEM) &&
> + !(migrate->flags &
On Tue, Aug 24, 2021 at 10:48:17PM -0500, Alex Sierra wrote:
> In this case, this is used to migrate pages from device memory, back to
> system memory. This particular device memory type should be accessible
> by the CPU, through IOMEM access. Typically, zone device public type
> memory falls into
On Wed, Aug 25, 2021 at 5:22 PM Jani Nikula wrote:
>
> On Wed, 25 Aug 2021, Koba Ko wrote:
> > AMD polaris GPUs have an issue about audio noise on RKL platform,
> > they provide a commit to fix but for SMU7-based GPU still
> > need another module parameter,
> >
> > For avoiding the module
AMD polaris GPUs have an issue about audio noise on RKL platform,
they provide a commit to fix but for SMU7-based GPU still
need another module parameter,
For avoiding the module parameter, switch PCI_DPM by determining
intel platform in amd drm driver.
Fixes: 1a31474cdb48 ("drm/amd/pm:
Looks good,
Reviewed-by: Christoph Hellwig
This should probably be folded into patch 4.
On Wed, Aug 25, 2021 at 6:24 PM Jani Nikula wrote:
>
> On Wed, 25 Aug 2021, Koba Ko wrote:
> > On Wed, Aug 25, 2021 at 5:22 PM Jani Nikula
> > wrote:
> >>
> >> On Wed, 25 Aug 2021, Koba Ko wrote:
> >> > AMD polaris GPUs have an issue about audio noise on RKL platform,
> >> > they provide a
On 8/25/21 05:48, Alex Sierra wrote:
> From: Ralph Campbell
>
> ZONE_DEVICE struct pages have an extra reference count that complicates the
> code for put_page() and several places in the kernel that need to check the
> reference count to see that a page is not being used (gup, compaction,
>
On Tue, Aug 24, 2021 at 10:48:15PM -0500, Alex Sierra wrote:
> Signed-off-by: Ralph Campbell
> Signed-off-by: Alex Sierra
> Reviewed-by: Christoph Hellwig
> ---
> v3:
> [AS]: rename dax_layout_is_idle_page func to dax_page_unused
>
> v4:
> [AS]: This ref count functionality was missing on
Because AMD GPU have a issue on RKL platform,
driver needs to determine which intel platfomr is and
if the platform is RKL, disable PCIE_DPM for AMD polaris-series GPUs.
Move intel_pch.h to includ/drm
Ref: https://lists.freedesktop.org/archives/amd-gfx/2021-August/067413.html
Signed-off-by: Koba
On Tue, Aug 24, 2021 at 10:48:23PM -0500, Alex Sierra wrote:
> Add MEMORY_DEVICE_PUBLIC case to free_zone_device_page callback.
> Device public type memory case is now able to free its pages properly.
This really should go into patch 4. And it might make sense to introduce
Am 25.08.21 um 14:20 schrieb Lazar, Lijo:
On 8/25/2021 4:52 PM, Nirmoy Das wrote:
To get a hardware queue priority for a context, we are currently
mapping AMDGPU_CTX_PRIORITY_* to DRM_SCHED_PRIORITY_* and then
to hardware queue priority, which is not the right way to do that
as
No, this would break that logic here.
See drm_sched_start_timeout() can be called multiple times, this is
intentional and very important!
The logic in queue_delayed_work() makes sure that the timer is only
started once and then never again.
All we need to take care of is to
Sounds good enough to me. Just be extra careful should you extend this
with u64 or anything which depends on 32 vs 64 bit architecture (like
pointers and long) at some point.
Christian.
Am 25.08.21 um 13:31 schrieb Tom St Denis:
1 hole with u8, 0 holes with u32. Is good?
On Wed, Aug 25,
[AMD Official Use Only]
I think we should remove the cancel_delayed_work() in the beginning of the
cleanup_job().
Because by my patch the "mode_delayed_work" in cleanup_job is already doing its
duty to retrigger the TO timer accordingly
Thanks
--
[AMD Official Use Only]
>>The timeout started by queue_delayed_work() in drm_sched_start_timeout() is
>>paired with the cancel_delayed_work() in drm_sched_get_cleanup_job().
No that's wrong, see that when we are in cleanup_job(), assume we do not have
timeout on this sched (we are just keep
To get a hardware queue priority for a context, we are currently
mapping AMDGPU_CTX_PRIORITY_* to DRM_SCHED_PRIORITY_* and then
to hardware queue priority, which is not the right way to do that
as DRM_SCHED_PRIORITY_* is software scheduler's priority and it is
independent from a hardware queue
1 hole with u8, 0 holes with u32. Is good?
On Wed, Aug 25, 2021 at 7:16 AM Das, Nirmoy wrote:
>
> On 8/25/2021 1:09 PM, Christian König wrote:
>
> I suggest to give this command here at least a try (remembered the name
> after a moment):
>
> pahole drivers/gpu/drm/amd/amdgpu/amdgpu.o -C
Am 25.08.21 um 13:22 schrieb Nirmoy Das:
To get a hardware queue priority for a context, we are currently
mapping AMDGPU_CTX_PRIORITY_* to DRM_SCHED_PRIORITY_* and then
to hardware queue priority, which is not the right way to do that
as DRM_SCHED_PRIORITY_* is software scheduler's priority
On 8/25/2021 1:09 PM, Christian König wrote:
I suggest to give this command here at least a try (remembered the
name after a moment):
pahole drivers/gpu/drm/amd/amdgpu/amdgpu.o -C amdgpu_debugfs_regs2_iocdata
It has a rather nifty output with padding holes, byte addresses, cache
lines etc
I suggest to give this command here at least a try (remembered the name
after a moment):
pahole drivers/gpu/drm/amd/amdgpu/amdgpu.o -C amdgpu_debugfs_regs2_iocdata
It has a rather nifty output with padding holes, byte addresses, cache
lines etc for your structure.
Christian.
Am 25.08.21 um
I tested it by forcing bit patterns into the ioctl data and printing it out
in the kernel log. I'm not siloed into it one way or the other. I'll just
change it to u32.
On Wed, Aug 25, 2021 at 7:03 AM Christian König <
ckoenig.leichtzumer...@gmail.com> wrote:
> Using u8 is ok as well, just make
Using u8 is ok as well, just make sure that you don't have any hidden
padding.
Nirmoy had a tool to double check for paddings which I once more forgot
the name of.
Christian.
Am 25.08.21 um 12:40 schrieb Tom St Denis:
The struct works as is but I'll change them to u32. The offset is an
The struct works as is but I'll change them to u32. The offset is an
artefact of the fact this was an IOCTL originally. I'm working both ends
in parallel trying to make the changes at the same time because I'm only
submitting the kernel patch if I've tested it in userspace.
I'll send a v4 in a
On Wed, 25 Aug 2021, Koba Ko wrote:
> On Wed, Aug 25, 2021 at 5:22 PM Jani Nikula
> wrote:
>>
>> On Wed, 25 Aug 2021, Koba Ko wrote:
>> > AMD polaris GPUs have an issue about audio noise on RKL platform,
>> > they provide a commit to fix but for SMU7-based GPU still
>> > need another module
amdgpu_bo_get_preferred_pin_domain is used for page tables
creation, which is not involved with page pinning. And it is used in
more cases than display scanout, modify its documentation as well.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 2 +-
Am 25.08.21 um 11:14 schrieb Yifan Zhang:
amdgpu_bo_get_preferred_pin_domain is used for page tables
creation, which is not involved with page pinning. And it is used in
more cases than display scanout, modify its documentation as well.
Signed-off-by: Yifan Zhang
Reviewed-by: Christian König
On Wed, 25 Aug 2021, Koba Ko wrote:
> AMD polaris GPUs have an issue about audio noise on RKL platform,
> they provide a commit to fix but for SMU7-based GPU still
> need another module parameter,
>
> For avoiding the module parameter, switch PCI_DPM by determining
> intel platform in amd drm
On Wed, 25 Aug 2021, Koba Ko wrote:
> Because AMD GPU have a issue on RKL platform,
> driver needs to determine which intel platfomr is and
> if the platform is RKL, disable PCIE_DPM for AMD polaris-series GPUs.
>
> Move intel_pch.h to includ/drm
I don't know what the root cause is, or whether
[Public]
Hi Christian,
OK. Then I think we should modify the document for
amdgpu_bo_get_preferred_pin_domain since it is not only for display scanout,
right ?
/**
* amdgpu_bo_get_preferred_pin_domain - get preferred domain for scanout
* @adev: amdgpu device object
* @domain: allowed
Yes, good point. And we should probably also rename the functions since
page tables are not pinned at all.
Christian.
Am 25.08.21 um 10:04 schrieb Zhang, Yifan:
[Public]
Hi Christian,
OK. Then I think we should modify the document for
amdgpu_bo_get_preferred_pin_domain since it is not
Am 25.08.21 um 09:44 schrieb Yifan Zhang:
amdgpu_bo_get_preferred_pin_domain was added to handle system memory
page tables. Since system memory pt/pd is disabled now, remove preferred
domain judgement to avoid confusion.
Well I would rather keep that and enable system memory page tables again.
amdgpu_bo_get_preferred_pin_domain was added to handle system memory
page tables. Since system memory pt/pd is disabled now, remove preferred
domain judgement to avoid confusion.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 1 -
1 file changed, 1 deletion(-)
diff
Am 24.08.21 um 23:01 schrieb Andrey Grodzovsky:
Handle all DMA IOMMU group related dependencies before the
group is removed and we try to access it after free.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
Am 24.08.21 um 23:01 schrieb Andrey Grodzovsky:
This list will be used to capture all non VRAM BOs not
on LRU so when device is hot unplugged we can iterate
the list and unmap DMA mappings before device is removed.
Signed-off-by: Andrey Grodzovsky
Suggested-by: Christian König
---
Am 24.08.21 um 15:36 schrieb Tom St Denis:
This new debugfs interface uses an IOCTL interface in order to pass
along state information like SRBM and GRBM bank switching. This
new interface also allows a full 32-bit MMIO address range which
the previous didn't. With this new design we have
Well NAK to that approach. First of all your bug analyses is incorrect.
The timeout started by queue_delayed_work() in drm_sched_start_timeout()
is paired with the cancel_delayed_work() in drm_sched_get_cleanup_job().
So you must have something else going on here.
Then please don't use
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