[AMD Official Use Only - General]
Reviewed-by: Jack Xiao
Regards,
Jack
From: amd-gfx on behalf of Yifan Zhang
Sent: Sunday, 12 June 2022 12:31
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
Subject: [PATCH] drm/amdgpu: remove
Hi
I'm seeing the following warning when building agd5f's tree with clang 14:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:4940:6:
warning: unused variable 'i' [-Wunused-variable]
int i;
^
1 warning generated.
Which points to this revert
On Mon, 10 May 2021 at
> -Original Message-
> From: Harry Wentland
> Sent: Saturday, June 11, 2022 1:59 AM
> To: Pekka Paalanen ; sebast...@sebastianwick.net;
> Shankar, Uma
> Cc: Vitaly Prosyak ; Sharma, Shashank
> ; Lakha, Bhawanpreet
> ; Deucher, Alexander
> ; Alex Hung ; dri-devel
Amdgpu driver is used in an extensive range of devices, and each ASIC
has some specific configuration. As a result of this variety, sometimes
it is hard to identify the correct block that might cause the issue.
This commit expands the amdgpu kernel-doc to alleviate this issue by
introducing one
Multiple plane overlay is a feature supported by AMD hardware, but it
has specific details that deserve proper documentation. This commit
introduces a documentation that describes some of the features,
limitations, and use cases for this feature. Part of this documentation
came from some
In the DCN code, we constantly talk about hardware pipeline, pipeline,
or even just pipes, which is a concept that is not obvious to everyone.
For this reason, this commit expands the DCN overview explanation by
adding a new section that describes what a pipeline is from the DCN
perspective.
Cc:
This patchset introduces some new AMDGPU documentation. You will find:
1. A CSV table that maps which component version is part of some ASIC
families. This can be useful to narrow down bugs;
2. Some explanation about AMD Display Pipeline;
3. An explanation of Multiple Plane Overlay, which can
This seems to be a case of a Windows-centric commit description that doesn't
completely make sense for Linux.
The code-change doesn't currently affect any behavior on Linux. It just lays
the groundwork in DC to allow an implementation to do a memory-clock switching
decision based around VRR
Starting with GFX11, MES requires wptr BOs to be GTT allocated/mapped to
GART for usermode queues in order to support oversubscription. In the
case that work is submitted to an unmapped queue, MES must have a GART
wptr address to determine whether the queue should be mapped.
This change is
Store MES scheduler and MES KIQ version numbers in amdgpu_mes for GFX11.
Signed-off-by: Graham Sider
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 3 +++
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 12
2 files changed, 15 insertions(+)
diff --git
Update MES API to support oversubscription without aggregated doorbell
for usermode queues.
Signed-off-by: Graham Sider
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 1 +
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
[AMD Official Use Only - General]
+@Clark, Felipe
-Original Message-
From: Alex Deucher
Sent: June 13, 2022 10:34 AM
To: Vanzylldejong, Harry
Cc: VURDIGERENATARAJ, CHANDAN ; Michel Dänzer
; Mahfooz, Hamza ;
amd-gfx@lists.freedesktop.org; Wang, Chao-kai (Stylon) ;
Liu, HaoPing (Alan)
It should be noted that FAMS is an additional feature to enable mclk
switching in more marginal cases than would normally be possible.
Alex
On Mon, Jun 13, 2022 at 9:32 AM Vanzylldejong, Harry
wrote:
>
> [AMD Official Use Only - General]
>
> Hi Chandan,
>
> When using Firmware Assisted Memory
Ping?
On Fri, Jun 10, 2022 at 11:43 AM Alex Deucher wrote:
>
> Use the same pattern as the DML Makefile and while we are here
> add a missing x86 guard around the msse flags for DCN3.2.x.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile | 3 +--
>
On Mon, Jun 13, 2022 at 2:08 AM Christian König
wrote:
>
> Am 10.06.22 um 17:42 schrieb Alex Deucher:
> > Use the same pattern as the DML Makefile and while we are here
> > add a missing x86 guard around the msse flags for DCN3.2.x.
>
> IIRC the idea was to limit the whole float handling to the
[Public]
> -Original Message-
> From: Yu, Lang
> Sent: Friday, June 10, 2022 10:38 PM
> To: Sider, Graham
> Cc: amd-gfx@lists.freedesktop.org; Joshi, Mukul ;
> Kuehling, Felix ; Yang, Philip
>
> Subject: Re: [PATCH v2 2/3] drm/amdkfd: Enable GFX11 usermode queue
> oversubscription
>
>
[AMD Official Use Only - General]
Thanks for the great comments Felix--will apply these.
Best,
Graham
-Original Message-
From: Kuehling, Felix
Sent: Friday, June 10, 2022 7:06 PM
To: Sider, Graham ; amd-gfx@lists.freedesktop.org
Cc: Joshi, Mukul ; Yang, Philip
Subject: Re: [PATCH v2
[AMD Official Use Only - General]
Hi Chandan,
When using Firmware Assisted Memory clock Switching (FAMS), when the memory
clock is switched the frame rate is dropped for at least 1 frame,
sometimes 2-3 frames to make the V-Blank long enough to handle the period where
the GDDR6 memory is
[AMD Official Use Only - General]
> -Original Message-
> From: amd-gfx On Behalf Of Felix
> Kuehling
> Sent: Friday, June 10, 2022 4:54 PM
> To: Errabolu, Ramesh ; amd-
> g...@lists.freedesktop.org; Francis, David
> Subject: Re: [PATCH] drm/amdgpu: Fix error handling in
>
[Public]
Acked-by: Alex Deucher
From: Zhang, Yifan
Sent: Sunday, June 12, 2022 12:31 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
Subject: [PATCH] drm/amdgpu: remove redundant enable_mes/enable_mes_kiq setting
enable_mes and
[Public]
Hi all,
This week this patchset was tested on the following systems:
HP Envy 360, with Ryzen 5 4500U
Lenovo Thinkpad T14s Gen2, with AMD Ryzen 5 5650U
Sapphire Pulse RX5700XT
Reference AMD RX6800
Engineering board with Ryzen 9 5900H
These systems were tested on the following
Am 13.06.22 um 14:11 schrieb Michal Hocko:
[SNIP]
Alternative I could try to track the "owner" of a buffer (e.g. a shmem
file), but then it can happen that one processes creates the object and
another one is writing to it and actually allocating the memory.
If you can enforce that the owner is
Hi,
Can you please elaborate on why dynamic memory clock switching can affect Game
performance?
BR,
Chandan V N
>On 2022-06-10 22:52, Hamza Mahfooz wrote:
>> From: Harry VanZyllDeJong
>>
>> [WHY]
>> Game performace may be affected if dynamic memory clock switching is
>> enabled while
Am 13.06.22 um 09:45 schrieb Michal Hocko:
On Sat 11-06-22 10:06:18, Christian König wrote:
Am 10.06.22 um 16:16 schrieb Michal Hocko:
[...]
I could of course add something to struct page to track which memcg (or
process) it was charged against, but extending struct page is most likely a
Bas, the code was literally rejecting swizzle modes that were not in the
modifier list, which was incorrect. That's because the modifier list is a
subset of all supported swizzle modes.
Marek
On Sun, Jun 12, 2022 at 7:54 PM Bas Nieuwenhuizen
wrote:
> On Thu, Jun 9, 2022 at 4:27 PM Aurabindo
On 2022-06-11 09:19, Christian König wrote:
> Am 10.06.22 um 15:54 schrieb Michel Dänzer:
>> From: Michel Dänzer
>>
>> The commit below changed the TTM manager size unit from pages to
>> bytes, but failed to adjust the corresponding calculations in
>> amdgpu_ioctl.
>>
>> Fixes: dfa714b88eb0
Am 13.06.22 um 11:08 schrieb Michel Dänzer:
On 2022-06-11 10:06, Christian König wrote:
Am 10.06.22 um 16:16 schrieb Michal Hocko:
[...]
Just consider the above mentioned memcg driven model. It doesn't really
require to chase specific files and do some arbitrary math to share the
Am 13.06.22 um 10:41 schrieb Lang Yu:
On 06/13/ , Christian König wrote:
Am 13.06.22 um 10:26 schrieb Lang Yu:
On 06/13/ , Christian König wrote:
Am 13.06.22 um 09:59 schrieb Lang Yu:
We don't need to validate and map root PD specially here,
it would be validated and mapped by
Am 13.06.22 um 10:26 schrieb Lang Yu:
On 06/13/ , Christian König wrote:
Am 13.06.22 um 09:59 schrieb Lang Yu:
We don't need to validate and map root PD specially here,
it would be validated and mapped by amdgpu_vm_validate_pt_bos
if it is evicted.
I'm not sure if that's correct.
The resource must be on the LRU before ttm_lru_bulk_move_add() is called
and we need to check if the BO is pinned or not before adding it.
Additional to that we missed taking the LRU spinlock in ttm_bo_unpin().
Signed-off-by: Christian König
Acked-by: Luben Tuikov
---
Am 13.06.22 um 09:59 schrieb Lang Yu:
We don't need to validate and map root PD specially here,
it would be validated and mapped by amdgpu_vm_validate_pt_bos
if it is evicted.
I'm not sure if that's correct. Traditionally we have handled the root
PD differently to the rest in the VM.
It
On Sat, Jun 11, 2022 at 2:16 AM kernel test robot wrote:
>
> tree/branch:
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> branch HEAD: 6d0c806803170f120f8cb97b321de7bd89d3a791 Add linux-next
> specific files for 20220610
>
> Error/Warning reports:
>
>
The variable 'i' in function kfd_dev_create_p2p_links is only used in
codes that gaurded by '#if defined(CONFIG_HSA_AMD_P2P)' check. So adding
CONFIG_HSA_AMD_P2P #ifdef check around variable 'i' too.
Fixes the following w1 warning:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:1542:11:
We don't need to validate and map root PD specially here,
it would be validated and mapped by amdgpu_vm_validate_pt_bos
if it is evicted.
The special case is when turning a GFX VM to a compute VM,
if vm_update_mode changed, we need to map the root PD again.
So just move root PD mapping to
[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Chengming Gui
Sent: Monday, June 13, 2022 15:00
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhang, Hawking
Cc: Gui, Jack
Subject: [PATCH] Revert "drm/amdgpu/gmc11:
[AMD Official Use Only - General]
> -Original Message-
> From: Alex Deucher
> Sent: Saturday, June 11, 2022 12:08 AM
> To: Quan, Evan
> Cc: amd-gfx list ; Deucher, Alexander
> ; Gao, Likun ; Zhang,
> Hawking
> Subject: Re: [PATCH 2/2] drm/amd/pm: enable MACO support for SMU
> 13.0.0
Am 10.06.22 um 17:46 schrieb Alex Deucher:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:1542:11:
warning: variable 'i' set but not used [-Wunused-but-set-variable]
Reported-by: kernel test robot
Signed-off-by: Alex Deucher
Ideally we should put the code for this into a separate
Am 10.06.22 um 17:42 schrieb Alex Deucher:
Use the same pattern as the DML Makefile and while we are here
add a missing x86 guard around the msse flags for DCN3.2.x.
IIRC the idea was to limit the whole float handling to the DML and
remove it from the rest of the code.
But not sure if
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