Hi Jonathan,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm/drm-next]
[also build test WARNING on drm-exynos/exynos-drm-next drm-tip/drm-tip
next-20230327]
[cannot apply to drm-misc/drm-misc-next drm-intel/for-linux-next
drm-intel/for-linux-next-fixes
[Why]
Reset(mode1) failed as JPRG IP did not reinit under sriov.
[How]
Add JPEG IP block to sriov reinit function.
Signed-off-by: Yifan Zha
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
[AMD Official Use Only - General]
This patch is :
Reviewed-by: Yifan Zhang
Best Regards,
Yifan
-Original Message-
From: Huang, Tim
Sent: Friday, March 24, 2023 3:08 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Du, Xiaojian ; Ma, Li
; Huang, Tim
All chips that support RAS also support IP discovery, so
use the IP versions rather than a mix of IP versions and
asic types.
Signed-off-by: Alex Deucher
Cc: Luben Tuikov
---
.../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 72 ++-
1 file changed, 20 insertions(+), 52
On Mon, Mar 27, 2023 at 7:36 PM Caio Novais wrote:
>
> Compiling AMD GPU drivers displays a warning:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_capability.c:
> In function ‘dpcd_set_source_specific_data’:
>
On Mon, Mar 27, 2023 at 7:35 PM Caio Novais wrote:
>
> Compiling AMD GPU drivers displays two warnings:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource.c: In function
> ‘dcn32_acquire_post_bldn_3dlut’:
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource.c:1614:31:
On Mon, Mar 27, 2023 at 7:34 PM Caio Novais wrote:
>
> Compiling AMD GPU drivers displays a warning:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_link_encoder.c: In
> function ‘dcn10_link_encoder_update_mst_stream_allocation_table’:
>
On Mon, Mar 27, 2023 at 7:34 PM Caio Novais wrote:
>
> Compiling AMD GPU drivers displays a warning:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c: In function
> ‘amdgpu_mes_ctx_alloc_meta_data’:
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c:1099:13: warning: variable ‘r’ set
> but not used
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_capability.c:
In function ???dpcd_set_source_specific_data???:
drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_capability.c:1290:32:
warning: variable
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_rq_dlg_calc_31.c: In
function ???dml_rq_dlg_get_dlg_params???:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_rq_dlg_calc_31.c:905:14:
warning: variable ???scl_enable??? set but
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c: In
function ???dcn32_helper_calculate_mall_bytes_for_cursor???:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:62:18:
warning: variable
Compiling AMD GPU drivers displays two warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource.c: In function
???dcn32_acquire_post_bldn_3dlut???:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource.c:1614:31:
warning: variable ???state??? set but not used
Compiling AMD GPU drivers displays two warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_apg.c: In function
???apg31_se_audio_setup???:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_apg.c:117:18: warning:
variable ???channels??? set but not used [-Wunused-but-set-variable]
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c: In function
???dcn30_enable_writeback???:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:326:34: warning:
variable ???optc??? set but not used [-Wunused-but-set-variable]
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubp.c: In function
???hubp3_set_vm_system_aperture_settings???:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubp.c:50:30: warning:
variable ???mc_vm_apt_default??? set but not used
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_afmt.c: In function
???afmt3_se_audio_setup???:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_afmt.c:126:18: warning:
variable ???speakers??? set but not used [-Wunused-but-set-variable]
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_hwseq.c: In function
???dcn201_pipe_control_lock???:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_hwseq.c:544:22: warning:
variable ???hubp??? set but not used
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.c: In function
???dpp201_get_optimal_number_of_taps???:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.c:188:18: warning:
variable ???pixel_width??? set but not used
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_link_encoder.c: In
function ???dcn10_link_encoder_update_mst_stream_allocation_table???:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_link_encoder.c:1222:18:
warning: variable ???value0???
Compiling AMD GPU drivers displays a warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c: In function
???amdgpu_mes_ctx_alloc_meta_data???:
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c:1099:13: warning: variable ???r??? set
but not used [-Wunused-but-set-variable]
Get rid of it by removing the
This patchset cleans the code removing unused variables and one unused
function.
Caio Novais (12):
Remove unused variable 'r'
Remove unused variable 'value0'
Remove unused variable 'pixel_width'
Remove unused variable 'hubp'
Remove unused variable 'speakers'
Remove unused variable
Applied. Thanks!
On Fri, Mar 24, 2023 at 5:44 PM Alex Deucher wrote:
>
> On Tue, Mar 21, 2023 at 5:33 AM Thomas Zimmermann wrote:
> >
> > Hi
> >
> > Am 20.03.23 um 16:23 schrieb Alex Deucher:
> > > On Mon, Mar 20, 2023 at 11:19 AM Thomas Zimmermann
> > > wrote:
> > >>
> > >> Hi
> > >>
> > >>
With my comments on patches 8 and 21 addressed, patches 1-33 are
Reviewed-by: Felix Kuehling
Patch 34 needs a more thorough review and testing. It's not an essential
part of the patch series and can be finished later.
Regards,
Felix
On 2023-03-27 14:43, Jonathan Kim wrote:
Introduce
On 2023-03-27 14:43, Jonathan Kim wrote:
Legacy debug devices limited to pinning a single debug VMID for debugging
are the only devices that require disabling GFX OFF while accessing
debug registers. Debug devices that support multi-process debugging
rely on the hardware scheduler to update
On 2023-03-27 14:43, Jonathan Kim wrote:
From: Jay Cornwall
Trap handler behavior will differ when a debugger is attached.
Make the debug trap flag available in the trap handler TMA.
Update it when the debug trap ioctl is invoked.
v4: fix up comments to clarify flagging implementation.
v3:
On 2023-03-27 14:43, Jonathan Kim wrote:
The debugger for GFX9.4.1 uses kfd_suspend_all_processes to pause the
compute pipe line so it can safely toggle the SQ's implicit wait on
barrier setting during debug attach/detach to work around the wave
exception s_barrier race condition.
For mGPU
Reviewed-by: Marek Olšák
On Thu, Mar 23, 2023 at 5:41 PM Alex Deucher
wrote:
> Add UAPI to query the GFX shadow buffer requirements
> for preemption on GFX11. UMDs need to specify the shadow
> areas for preemption.
>
> v2: move into existing asic info query
> drop GDS as its use is
From: James Zhu
Add multiple jpeg rings support for vcn4_0_3
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 214 ---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h | 1 +
2 files changed, 147
From: James Zhu
Add multiple jpeg rings support.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 21 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 6 --
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
From: James Zhu
Add jpeg support for VCN4_0_3.
v2: squash in delayed work typo fix (Alex)
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 762 +++
From: James Zhu
Enable jpeg cg for VCN4_0_3.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
From: James Zhu
Enable vcn cg for VCN4_0_3.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index
From: James Zhu
Enable vcn DPG mode for VCN4_0_3.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
From: James Zhu
Enable vcn pg for VCN4_0_3.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index
From: James Zhu
Add vcn support for VCN4_0_3.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile |1 +
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 1438 +++
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.h |
From: James Zhu
Enable jpeg pg for VCN4_0_3.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
From: James Zhu
Add VCN4_0_3 firmware.
v2: fix fw name (Alex)
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git
This adds support for VCN 4.0.3. VCN is the media engine on AMD
GPUs. Patch 1 add new register headers and is too big for the
mailing list.
Hawking Zhang (1):
drm/amdgpu: add vcn v4_0_3 ip headers
James Zhu (10):
drm/amdgpu: add VCN4_0_3 firmware
drm/amdgpu/jpeg: add jpeg support for
From: Le Ma
Each XCD owns one GFXHUB.
v2: switch to the new VMHUB layout
Signed-off-by: Le Ma
Acked-by: Christian König
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git
From: Lijo Lazar
Use SOC15 API so that the register offset is calculated correctly.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Shiwu Zhang
To write regs on different GCDs, use the inst index.
Signed-off-by: Shiwu Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
From: James Zhu
Add more macro to support offset variant and
simplify macro SOC15_WAIT_ON_RREG.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 3 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 28 +
From: Le Ma
Add current/available compute partitin mode sysfs node.
v2: make the sysfs node as IP independent one in amdgpu_gfx.c
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
From: Amber Lin
New GC (v9.4.3) and ATHUB (v1.8.0) versions
are used. Add kgd_gfx_v9_4_3_*
functions if registers in use of kgd_gfx_v9_*
functions are changed or have different offset.
Signed-off-by: Amber Lin
Acked-by: Felix Kuehling
Reviewed-by: Mukul Joshi
Signed-off-by: Alex Deucher
---
From: Le Ma
Allocate different doorbell index for kiq/kcq rings
on each die
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 9 -
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 5 +
From: Shiwu Zhang
Add a module parameter to override the partition mode.
Signed-off-by: Shiwu Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 13 +
From: Le Ma
Each XCD needs to do gfxhub init
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 581 +--
1 file changed, 317 insertions(+), 264 deletions(-)
diff --git
From: Hawking Zhang
v1: Each partition has its own gfxhub or mmhub. adjust
the num of MAX_VMHUBS and the GFXHUB/MMHUB layout (Le)
v2: re-design the AMDGPU_GFXHUB/AMDGPU_MMHUB layout (Le)
v3: apply the gfxhub/mmhub layout to new IPs (Hawking)
v4: fix up gmc11 (Alex)
v5: rebase (Alex)
From: Le Ma
Each XCD has its own gfxhub.
v2: switch to the new VMHUB layout
v3: fix mistake
Signed-off-by: Le Ma
Reviewed-by: Christian König
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 58 ++--
1 file changed,
From: Shiwu Zhang
There are AMDGPU_MAX_VMHUBS of vmhub in maximum and need to init the
vm_inv_engs for all of them.
In this way, the below error can be ruled out.
[ 217.317752] amdgpu :02:00.0: amdgpu: no VM inv eng for ring sdma0
Signed-off-by: Shiwu Zhang
Reviewed-by: Christian Koenig
From: Le Ma
v1: To support multiple XCD case (Le)
v2: introduce xcc index to gfx_v11_0_select_sh_se (Hawking)
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 4 +--
From: Le Ma
To prepare for gc v9_4_3 specific feature.
v2: fix exports (Alex)
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2668 ++-
From: Le Ma
Skip KCQ setup on slave xcc as there's no use case.
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 59 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 +
From: Le Ma
Change those v9_4_3 interfaces which are exposed in gfx_v9_0.c.
For some active single-xcc emu models, the code path in
gfx_v9_0.c is better to keep reserved for a while.
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
From: Le Ma
Each XCD needs to be initialized respectively. The major changes are:
1. add iteration to do rlc/kiq/kcq init/fini for each xcd
2. load rlc/mec microcode to each xcd
3. add argument to specify xcc index in initialization functions
Signed-off-by: Le Ma
Reviewed-by: Hawking
From: Le Ma
Pass the xcc_id to AMDGPU_GFXHUB(x)
Signed-off-by: Le Ma
Reviewed-by: Christian König
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 +-
2 files changed, 2 insertions(+), 2
From: Le Ma
v1: To support multple XCD case (Le)
v2: unify naming style (Le)
v3: apply the changes to gc v11_0 (Hawking)
v4: apply the changes to gc SOC21 (Morris)
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Hawking Zhang
Signed-off-by: Morris Zhang
Signed-off-by: Alex
From: Le Ma
As the layout of VMHUB definition has been changed to cover multiple
XCD/AID case, the original num_vmhubs is not appropriate to do vmhub
iteration any more.
Drop num_vmhubs and introduce vmhubs_mask instead.
v2: switch to the new VMHUB layout
v3: use DECLARE_BITMAP to define
From: Le Ma
Assign value here as the num_xcd is referenced in some gfx9 common path.
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Le Ma
This will benifit the mqd indexing for kiq/kcq in multi XCD case.
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Le Ma
To support grbm select for multiple XCD case.
v2: unify naming style
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 10 +++
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 26
From: Le Ma
v1: Modify kiq_init/fini, mqd_sw_init/fini and
enable/disable_kcq to adapt to multi-die case.
Pass 0 as default to all asics with single xcc (Le)
v2: squash commits to avoid breaking the build (Le)
v3: unify naming style (Le)
v4: apply the changes to gc v11_0 (Hawking)
From: Le Ma
To allocate independent queue_bitmap for each XCD,
then the old bitmap policy can be continued to use
with a clear logic.
Use mec_bitmap[0] as default for all non-GC 9.4.3 IPs.
v2: squash commits to avoid breaking the build
v3: unify naming style
Signed-off-by: Le Ma
Reviewed-by:
From: Le Ma
v1: more kiq instances are a available in SOC (Le)
v2: squash commits to avoid breaking the build (Le)
v3: make the conversion for gfx/mec v11_0 (Hawking)
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
From: Le Ma
It looks better to place this field in ring
structure. Also drop the repeated ring funcs definitions
if there's no difference except for vmhub field.
v2: rename the field to vm_hub like others (Le)
v3: apply the changes to new ip blocks (Hawking)
v4: fix vcn sw ring (Alex)
From: Le Ma
Add some basic definitions and structure member. Inscrease MAX_WB slots
to 1024 to support the increasing number of rings for multiple partitions.
v2: unify naming style
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
[Why]
Fix the incorrect value for parameters used to enable multi plane
overlay support for DCN321
Fixes: 235c6763423 ("drm/amd/display: add DCN32/321 specific files for Display
Core")
Cc: sta...@vger.kernel.org
Signed-off-by: Aurabindo Pillai
---
From: Hawking Zhang
add gfx_funcs callbacks implemenation based on
gc_v9_4_3 ip headers
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 154 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.h | 1 +
2
From: Jay Cornwall
v1:
Check new exception bits in TRAPSTS register
Remove single step exception workaround, now part of
exception bits
v2:
GC 9.4.3 uses ttmp11 to store {1’b0, dispatch index [24:0],
wave_id_in_workgroup[5:0]}, so use ttmp13 instead of ttmp11 to
preserve ib_sts. (Laurent)
From: Hawking Zhang
all the gc v9_4_3 registers fall in gc_rlcpdec address range
have different relative offsets and base_idx from the ones
defined in gc v9_0 ip headers. gc_v9_0_rlc_funcs can not be
reused anymore for gc v9_4_3
v2: drop unused handshake function (Alex)
Signed-off-by: Hawking
From: Hawking Zhang
init asic funcs and cp/pg flags for GC 9.4.3
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
From: Amber Lin
GC 9.4.3 uses the hardware to update AQL queues read pointer, so
remove CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK flag from MQD if it's
GC 9.4.3, and keep it for other existing gfx9 ASICs.
Signed-off-by: Amber Lin
Acked-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
From: Hawking Zhang
Add common IP handling for GC 9.4.3
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
From: Graham Sider
Required for Thunk GFX version sysfs query.
Signed-off-by: Graham Sider
Reviewed-by: Amber Lin
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
From: Amber Lin
For GC 9.4.3, disable retry as default and XNACK can be different
modes per process.
Signed-off-by: Amber Lin
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 ++-
2 files
From: Amber Lin
On GC 9.4.3, DW 41 in MQD is repurposed as compute_tg_chunk_size
for cooperative dispatch. When it's a AQL queue, set compute_tg_chunk_size
as 1 to spread work groups evenly among XCCs. If it's PM4 queue, unset
compute_tg_chunk_size to disable cooperative mode.
v3: set
From: Hawking Zhang
Add initial KFD support
Convert a few structures to IP version checking (Hawking)
Signed-off-by: Elena Sakhnovitch
Signed-off-by: Hawking Zhang
Reviewed-by: Amber Lin
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 1 +
Hi,
That's a good fix. Some questions and comments below:
On 2023-03-27 11:20, Alan Liu wrote:
> [Why]
> After gpu-reset, sometimes the driver would fail to enable vblank irq,
> causing flip_done timed out and the desktop freezed.
>
> During gpu-reset, we will disable and enable vblank irq in
[AMD Official Use Only - General]
Thanks a lot Alex for reviewing the patch.
Best Regards,
Srini
-Original Message-
From: Alex Deucher
Sent: Tuesday, March 28, 2023 12:12 AM
To: SHANMUGAM, SRINIVASAN
Cc: Koenig, Christian ; Deucher, Alexander
; Limonciello, Mario ;
Mahfooz, Hamza ;
Legacy debug devices limited to pinning a single debug VMID for debugging
are the only devices that require disabling GFX OFF while accessing
debug registers. Debug devices that support multi-process debugging
rely on the hardware scheduler to update debug registers and do not run
into GFX OFF
Bump the minor version to declare debugging capability is now
available.
v2: bump to 1.13 after upstream rebase.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 1 -
include/uapi/linux/kfd_ioctl.h | 3 ++-
2 files changed, 2
Shader read, write and atomic memory operations can be alerted to the
debugger as an address watch exception.
Allow the debugger to pass in a watch point to a particular memory
address per device.
Note that there exists only 4 watch points per devices to date, so have
the KFD keep track of what
From: Jay Cornwall
Trap handler behavior will differ when a debugger is attached.
Make the debug trap flag available in the trap handler TMA.
Update it when the debug trap ioctl is invoked.
v4: fix up comments to clarify flagging implementation.
v3: Rebase for upstream
v2:
Add missing debug
Allow the debugger to set wave behaviour on to either normally operate,
halt at launch, trap on every instruction, terminate immediately or
stall on allocation.
v3: remove unrequired stall_launch reference in an earlier patch.
gfx off optimization will be addressed later.
v2: add gfx11 support
In order to inspect waves from the saved context at any point during a
debug session, the debugger must be able to preempt queues to trigger
context save by suspending them.
On queue suspend, the KFD will copy the context save header information
so that the debugger can correctly crawl the
Allow the debugger to set single memory and single ALU operations.
Some exceptions are imprecise (memory violations, address watch) in the
sense that a trap occurs only when the exception interrupt occurs and
not at the non-halting faulty instruction. Trap temporaries 0 & 1 save
the program
The debugger can attach to a process prior to HSA enablement (i.e.
inferior is spawned by the debugger and attached to immediately before
target process has been enabled for HSA dispatches) or it
can attach to a running target that is already HSA enabled. Either
way, the debugger needs to know
Add a debug operation that allows the debugger to send an exception
directly to runtime through a payload address.
For memory violations, normal vmfault signals will be applied to
notify runtime instead after passing in the saved exception data
when a memory violation was raised to the debugger.
Similar to queue snapshot, return an array of device information using
an entry_size check and return.
Unlike queue snapshots, the debugger needs to pass to correct number of
devices that exist. If it fails to do so, the KFD will return the
number of actual devices so that the debugger can make a
To enable HW debug mode per process, all devices must be debug enabled
successfully. If a failure occures, rewind the enablement of debug mode
on the enabled devices.
A power management scenario that needs to be considered is HW
debug mode setting during GFXOFF. During GFXOFF, these registers
Older HW only supports debugging on a single process because the
SPI debug mode setting registers are device global.
The HWS has supplied a single pinned VMID (0xf) for MAP_PROCESS
for debug purposes. To pin the VMID, the KFD will remove the VMID from
the HWS dynamic VMID allocation via
On GFX9.4.1, the implicit wait count instruction on s_barrier is
disabled by default in the driver during normal operation for
performance requirements.
There is a hardware bug in GFX9.4.1 where if the implicit wait count
instruction after an s_barrier instruction is disabled, any wave that
hits
Allow the debugger to query additional info based on an exception code.
For device exceptions, it's currently only memory violation information.
For process exceptions, it's currently only runtime information.
Queue exception only report the queue exception status.
The debugger has the option of
Allow the debugger to get a snapshot of a specified number of queues
containing various queue property information that is copied to the
debugger.
Since the debugger doesn't know how many queues exist at any given time,
allow the debugger to pass the requested number of snapshots as 0 to get
the
Due to a HW bug, waves in only half the shader arrays can enter trap.
When starting a debug session, relocate all waves to the first shader
array of each shader engine and mask off the 2nd shader array as
unavailable.
When ending a debug session, re-enable the 2nd shader array per
shader engine.
Unlike single process debug devices, multi-process debug devices allow
debug mode setting per-VMID (non-device-global).
Because the HWS manages PASID-VMID mapping, the new MAP_PROCESS API allows
the KFD to forward the required SPI debug register write requests.
To request a new debug mode
Similar to the F32 HWS, the RS64 HWS for GFX11 now supports a multi-process
debug API.
The skip_process_ctx_clear ADD_QUEUE requirement is to prevent the MES
from clearing the process context when the first queue is added to the
scheduler in order to maintain debug mode settings during queue
The debugger subscibes to nofication for requested exceptions on attach.
Allow the debugger to change its subsciption later on.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 3 ++
drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 36
This operation allows the debugger to override the enabled HW
exceptions on the device.
On debug devices that only support the debugging of a single process,
the HW exceptions are global and set through the SPI_GDBG_TRAP_MASK
register.
Because they are global, only address watch exceptions are
Allow the debugger to query a single queue, device and process
exception.
The KFD should also return the GPU or Queue id of the exception.
The debugger also has the option of clearing exceptions after
being queried.
Signed-off-by: Jonathan Kim
Reviewed-by: Felix Kuehling
---
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