On Fri, Apr 14, 2023 at 5:24 PM Bas Nieuwenhuizen
wrote:
>
> On Fri, Apr 14, 2023 at 11:18 PM Alex Deucher wrote:
> >
> > On Thu, Apr 13, 2023 at 10:25 AM Bas Nieuwenhuizen
> > wrote:
> > >
> > > This info would be used by radv to figure out when we need to
> > > split a submission into
Applied. Thanks!
Alex
On Fri, Apr 14, 2023 at 8:04 AM Tom Rix wrote:
>
> gcc with W=1 reports
> In file included from
> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0.c:36:
> ./drivers/gpu/drm/amd/amdgpu/../pm/swsmu/inc/smu_v13_0.h:66:18: error:
> ‘pmfw_decoded_link_width’ defined
On Fri, Apr 14, 2023 at 11:18 PM Alex Deucher wrote:
>
> On Thu, Apr 13, 2023 at 10:25 AM Bas Nieuwenhuizen
> wrote:
> >
> > This info would be used by radv to figure out when we need to
> > split a submission into multiple submissions. radv currently has
> > a limit of 192 which seems to work
On Thu, Apr 13, 2023 at 10:25 AM Bas Nieuwenhuizen
wrote:
>
> This info would be used by radv to figure out when we need to
> split a submission into multiple submissions. radv currently has
> a limit of 192 which seems to work for most gfx submissions, but
> is way too high for e.g. compute or
Em 13/04/2023 07:18, Pierre-Eric Pelloux-Prayer escreveu:
OpenGL EXT_robustness extension expects the driver to stop reporting
GUILTY_CONTEXT_RESET when the reset has completed and the GPU is ready
to accept submission again.
This commit adds a AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS flag,
Hi Alan,
Em 14/04/2023 13:22, Alan Liu escreveu:
[Why]
After gpu-reset, sometimes the driver would fail to enable vblank irq,
causing flip_done timed out and the desktop freezed.
During gpu-reset, we will disable and enable vblank irq in dm_suspend()
and dm_resume(). Later on in
Hi Dave, Daniel,
Last few changes for 6.4.
The following changes since commit 55bf14961db9da61220e6f04bc9919c94b1a6585:
Merge tag 'mediatek-drm-next-6.4' of
https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into
drm-next (2023-04-11 12:28:10 +0200)
are available in the Git
Currently, we allow the framebuffer for a given plane to move between
memory domains, however when that happens it causes the screen to
flicker, it is even possible for the framebuffer to change memory
domains on every plane update (causing a continuous flicker effect). So,
to fix this, don't
Log when Channel Equalization is successful,
and DP link training completed.
Cc: Aurabindo Pillai
Cc: Fangzhi Zuo
Signed-off-by: Srinivasan Shanmugam
---
v2:
- For consistency of the printed messages, either drop or keep %s for both the
lines - it is dropped (Aurabindo)
- For
[Why]
After gpu-reset, sometimes the driver would fail to enable vblank irq,
causing flip_done timed out and the desktop freezed.
During gpu-reset, we will disable and enable vblank irq in dm_suspend()
and dm_resume(). Later on in amdgpu_irq_gpu_reset_resume_helper(), we
will check irqs' refcount
cpp_check reports
drivers/gpu/drm/amd/display/modules/freesync/freesync.c:1143:17: style: Variable
'oldest_index' is assigned a value that is never used. [unreadVariable]
oldest_index = 0;
^
This variable is not used so remove.
Signed-off-by: Tom Rix
---
From: Aric Cyr
This DC version brings along:
- FW Release 0.0.162.0
- Enable FPO+Vactivate
- Support for VESA SCR on OLED
- Refactor DMUB commands
- Fixes in secure display, modeset, memleak and more
- Picked up missed patches in history
Acked-by: Qingqing Zhuo
Signed-off-by: Aric Cyr
---
From: Aurabindo Pillai
[Why]
Fixes the following warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hwseq.c: In function
‘dcn21_set_backlight_level’:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hwseq.c:229:18: warning:
unused variable ‘otg_inst’ [-Wunused-variable]
229
From: Po-Ting Chen
Base on PSRSU specification, every seletive update frame need to use two
SDP to indicate the frame active range. So we occupy another GSP1 for
PSRSU execution.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Po-Ting Chen
---
.../display/dc/dcn30/dcn30_dio_stream_encoder.c |
From: Nicholas Kazlauskas
[Why]
The bit for flip addr is being set causing the determination for
FAST vs MEDIUM to always return MEDIUM when plane info is provided
as a surface update. This causes extreme stuttering for the typical
atomic update path on Linux.
[How]
Don't use update_flags->raw
From: Aurabindo Pillai
DCN31 supports FAMS, but this was not correctly set to the hardware
setup sequence. This commit fixes this issue by setting the MCLK switch
capability based on the feature capability retrieved from the DMUB.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
From: Aurabindo Pillai
[Why]
Add Enum and documenation related to FAMS (Firmware Assisted Memclk
Switching) and CAB (Cache As Buffer)
Reviewed-by: Qingqing Zhuo
Reviewed-by: Leo Li
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 17 +++--
1
From: Zhongwei
[Why]
disable_vbios_mode_if_required() will set dpms_off to false during boot
when pixel clk dismatches with driver requires. This will cause extra
backlight on and off if OS call 2 times setmode.
[How]
Set dpms_off to true to keep power_off and let OS control backlight by
From: Igor Kravchenko
Add min_width, min_height fields to dc_plane_cap structure. Set values
to 16x16 for discrete ASICs, and 64x64 for others.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Igor Kravchenko
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 4 +++-
1 file changed, 3
From: Meenakshikumar Somasundaram
[Why]
Currently driver enables dmub outbox notification before oubox ISR is
registered. During boot scenario, sometimes dmub issues hpd outbox
message before driver registers ISR and those messages are missed.
[How]
Enable dmub outbox notification after outbox
From: Dmytro Laktyushkin
Dst_y can become negative in extreme odm 4to1 cases. While not strictly
invalid, this should be limited to 0 for rq/dlg/ttu calculation.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Dmytro Laktyushkin
---
.../gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
From: Aurabindo Pillai
DCN30 is missing a check for the pixel format 444 when using 16bits
before setting the flag that Viewport exceeds the surface.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 2 +-
1
From: Krunoslav Kovac
Enable 3-planes MPO for DCN321 by reporting max_slave_planes in DC caps
for each ASIC.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Krunoslav Kovac
---
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
From: Sherry Wang
[Why]
DML calculation is different from HW formula.
[How]
Correct the bug to keep it same as HW formula.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Sherry Wang
---
.../gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c| 4 ++--
From: Jasdeep Dhillon
[Why]
DCN32 resource contains code that uses FPU.
[How]
Moved code into DCN32 FPU
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Jasdeep Dhillon
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 6 ++
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h | 2
From: Aurabindo Pillai
Drop duplicate check for DET Swath in DCN32.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 1 -
1 file changed, 1 deletion(-)
diff --git
From: Aurabindo Pillai
Set DRAM clock change state if retraining is required.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Aurabindo Pillai
For pstate change, allow DML to loop through
all possible prefetch combinations so as to
support more display configurations. Set the max
and min prefetch modes to enable the sequence.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
---
From: Aurabindo Pillai
[Why]
Update bounding box values as per hardware spec
Fixes: 1951340bd31a ("drm/amd/display: Create dcn321_fpu file")
Acked-by: Leo Li
Signed-off-by: Aurabindo Pillai
---
.../amd/display/dc/dml/dcn321/dcn321_fpu.c| 24 +--
1 file changed, 12
From: Aurabindo Pillai
[WHY]
Low bpc timings are failing validation, port a patch to allow them to pass.
Signed-off-by: Dillon Varone
Acked-by: Aurabindo Pillai
---
.../dc/dml/dcn32/display_mode_vba_util_32.c| 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff
From: Aurabindo Pillai
[Why & How]
There's no need to clear GPINT register for DMUB
when releasing it from reset. Fix that.
Fixes: ac2e555e0a7f ("drm/amd/display: Add DMCUB source files and changes for
DCN32/321")
Reviewed-by: Leo Li
Signed-off-by: Aurabindo Pillai
---
From: Samson Tam
[Why]
Workaround for DMCUB front door load
[How]
Clear GPINT after reset so its consistent
Signed-off-by: Samson Tam
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
From: Aurabindo Pillai
[Why]
Fix CLK MGR early initialization and add logging.
Fixes: 265280b99822 ("drm/amd/display: add CLKMGR changes for DCN32/321")
Reviewed-by: Leo Li
Reviewed-by: Qingqing Zhuo
Signed-off-by: Aurabindo Pillai
---
From: Cruise Hung
[Why & How]
We missed resetting OUTBOX0 mailbox r/w pointer on DMUB reset.
Fix it.
Fixes: 6ecf9773a503 ("drm/amd/display: Fix DMUB outbox trace in S4")
Signed-off-by: Cruise Hung
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 2 ++
1 file
From: Alvin Lee
[Why]
- Implement interface to program DTBCLK DTO’s
according to reference DTBCLK returned by PMFW
- This is required because DTO programming
requires exact DTBCLK reference freq or it could
result in underflow
Acked-by: Aurabindo Pillai
Signed-off-by: Alvin Lee
---
From: Tianci Yin
[why]
Since the variable fpu_recursion_depth is per-CPU type, it has one copy
on each CPU, thread migration causes data consistency issue, then the
call trace shows up. And preemption disabling can't prevent migration.
[how]
Disable migration to ensure consistency of
From: Wesley Chalmers
[WHY]
Add log entry for when display refresh from MALL
settings are sent to SMU.
Fixes: 1664641ea946 ("drm/amd/display: Add logger for SMU msg")
Signed-off-by: Wesley Chalmers
Acked-by: Aurabindo Pillai
---
.../drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
From: Mikita Lipski
Extract edid's checksum and send it back for verification if EDID_TEST
is requested.
Signed-off-by: Mikita Lipski
Acked-by: Aurabindo Pillai
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 30 +--
1 file changed, 27 insertions(+), 3 deletions(-)
diff
From: hersen wu
[Why]
We were not returning -EINVAL on DSC atomic check fail. Add it.
Fixes: 71be4b16d39a ("drm/amd/display: dsc validate fail not pass to atomic
check")
Reviewed-by: Aurabindo Pillai
Signed-off-by: Hersen Wu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |
From: Aurabindo Pillai
[Why]
Remove incorrect early return in a device specific fifo reset workaround
Reviewed-by: Leo Li
Reviewed-by: Qingqing Zhuo
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 1 -
1 file changed, 1 deletion(-)
diff --git
From: Daniel Miess
[Why]
1. It could hit bandwidth limitdation under single dimm
memory when connecting 8K external monitor.
2. IsSupportedVidPn got validation failed with
2K240Hz eDP + 8K24Hz external monitor.
3. It's better to filter out such combination in
EnumVidPnCofuncModality
4. For short
From: Eric Yang
[Why]
If optimized init is done in FW. DCN init can be skipped in driver. This
need to be communicated between driver and fw and maintain backwards
compatibility.
[How]
Use DMUB scratch 0 bit 2 to indicate optimized init done in fw and
use DMUB scatch 4 bit 0 to indicate drive
From: Dmytro Laktyushkin
[Why & How]
Fix a typo for dcn315 line buffer bpp.
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Dmytro Laktyushkin
---
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Dmytro Laktyushkin
[Why & How]
Add options for dc odm debug.
Reviewed-by: Ariel Bernstein
Acked-by: Qingqing Zhuo
Signed-off-by: Dmytro Laktyushkin
---
drivers/gpu/drm/amd/display/dc/dc.h| 2 ++
drivers/gpu/drm/amd/display/dc/dc_stream.h | 5 +
2 files changed, 7
From: Alex Hung
[Why & How]
timing.dsc_cfg.num_slices_v can be zero and it is necessary to check
before using it.
This fixes the error "divide error: [#1] PREEMPT SMP NOPTI".
Reviewed-by: Aurabindo Pillai
Acked-by: Qingqing Zhuo
Signed-off-by: Alex Hung
---
From: Jingwen Zhu
[Why]
The eDP retrain will cause the DPCD 300 to be reset to default.
And cause the brightness can't be set correctly.
[How]
delete the call to edp panel power control in both
enable_link_output/disable_link_output entirely and
only call edp panel control in enable_link_dp and
From: Michael Mityushkin
[Why]
When link training during engine recovery, ASSR might fail causing panel
mode to be reset to default. This should not happen for eDP as it
will prevent the panel from turning back on.
[How]
Added dp_panel_mode to struct dc_link to remember previously applied
panel
From: Anthony Koo
- Add DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command
- Remove d3 entry event and instead check for stream mask
- dmu: Enable timeout recovery and detection for p-state
Acked-by: Qingqing Zhuo
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 9
From: Alvin Lee
[Description]
- Enable FPO + Vactive
Reviewed-by: George Shen
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 2 +-
2 files changed, 2
From: Nasir Osman
[why]
When we force ODM combine with DSC, we lose several
8 bit and 10 bit modes in validation and thus
not able to use HDR. This is due to the number of
horizontal slices used in DSC not properly being
accounted for currently when 2:1 ODM Combine is forced.
[how]
Enforce at
From: Alvin Lee
[Description]
- Since we do not use optimized watermark settings for MALL,
set D = A
- PMFW uses Set D for d0i3.1, so driver should make D = A for the
time being
- If we choose to optimize in the future we can set watermarks D
correctly
Reviewed-by: Jun Lei
Acked-by:
From: Michael Mityushkin
[Why]
Doing core_link_disable_stream or set_dpms_off when reinitializing
hardware causes issue to repro with external display connected. This is
unnecessary, blanking pixel data should be sufficient.
[How]
Call disable_pixel_data while reinitializing hardware instead of
From: Rodrigo Siqueira
To ensure that FAMS can be used, DC must check if there is VRR support.
This commit adds the required configuration to ensure FAMS can be executed in
the target system.
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by: Rodrigo Siqueira
---
From: Iswara Nagulendran
[HOW]
Write DPCD 721 bit 7 to high, and
the appropriate luminance level
to DPCD 734-736 if bit 4 from DPCD register
734 is high, indicating that the panel
luminance control is enabled from the panel side.
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
Signed-off-by:
From: Josip Pavic
[Why & How]
Consolidate dmub access to a single interface. This makes it easier to
add code in the future that needs to run every time a dmub command is
requested (e.g. instrumentation, locking etc).
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by:
From: Alvin Lee
[Description]
- Previous bug fix for audio issue included dtbclk and p-state
on the optimized boot path which is incorarect
- We only care about DISPCLK in the optimized vs. non-optimized
boot path to avoid audio issues
Reviewed-by: Saaem Rizvi
Acked-by: Qingqing Zhuo
From: Hersen Wu
[Why] hdcp are enabled for asics from raven. for old asics
which hdcp are not enabled, hdcp_workqueue are null. some
access to hdcp work queue are not guarded with pointer check.
[How] add hdcp_workqueue pointer check before access workqueue.
Reviewed-by: Bhawanpreet Lakha
From: Alvin Lee
[Description]
- Having excessively large margin causes failure in the static
schedulability check in some cases for SubVP + DRR
- 100us of DRR margin is sufficient based on a weeks worth of
stress testing on different display configs
Reviewed-by: Michael Strauss
Acked-by:
From: Josip Pavic
[Why & How]
If dmub command queuing fails due to the inbox being full, flush the
inbox and resubmit the comamnd. This was previously the default behavior
but was lost in a refactor.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Josip Pavic
---
From: Dmytro Laktyushkin
Increse to 6 as that is the max surfaces supported asics can have.
The is no practical use case yet, but this is valuable for pre-si
validation.
Reviewed-by: Ariel Bernstein
Acked-by: Qingqing Zhuo
Signed-off-by: Dmytro Laktyushkin
---
From: Alex Hung
[Why]
When IGT's kms_hdmi_inject forces EDID for HDMI audio, dc rejects the
request because virtual signal is not in dc_is_audio_capable_signal
function.
[How]
Includes SIGNAL_TYPE_VIRTUAL as audio capable.
Reviewed-by: Chao-kai Wang
Acked-by: Qingqing Zhuo
Signed-off-by:
From: Hersen Wu
[Why]
when amdgpu_dm_update_connector_after_detect is called
two times successively with valid sink, memory allocated of
aconnector->timing_requested for the first call is not free.
this causes memeleak.
[How]
allocate memory only when aconnector->timing_requested
is null.
From: Alan Liu
[Why]
Currently we don't check if secure display is enabled before we send
command to disable secure display in dmub. It will accidentally cause
some other igt tests to fail, eg, crtc-linear-degamma.
[How]
Refactor the code we reset the secure display state to check secure
From: Aurabindo Pillai
[Why]
When skipping full modeset since the only state change was a front porch
change, the DC commit sequence requires extra checks to handle non
existant plane states being asked to be removed from context.
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by:
From: Rodrigo Siqueira
When the commit a983d2631869 (drm/amd/display: Don't set dram clock
change requirement for SubVP) was merged, we missed some parts
associated with the MCLK switch. This commit adds all the missing parts.
Fixes: a983d2631869 (drm/amd/display: Don't set dram clock change
From: Josip Pavic
[Why & How]
Add code path to copy dmub caps to dc, which is missing on dcn31
Acked-by: Qingqing Zhuo
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 4
1 file changed, 4 insertions(+)
diff --git
From: Leon Huang
[Why]
set ABM pipe/backlight gets some issues when abm callback func pointers
are NULL. For some usecase, driver would like to control PWM level before
ABM resource is ready. However, recent flow refactor of ABM didn't
consider that use case.
[How]
Rollback flow that sending
From: Wesley Chalmers
[WHY]
It is possible to commit state multiple times in rapid succession with
FAMS enabled; if each of these commits were to set optimized_required,
then the user may see latency.
[HOW]
fw_based_mclk_switching is currently not used in dc->clk_mgr; use it
to track whether
From: Leon Huang
[Why]
Refactor ABM feature and implement inbox command for DMUB.
[How]
Implement the ioctl to send inbox command to DMUB.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Leon Huang
---
drivers/gpu/drm/amd/display/dc/dce/Makefile | 2 +-
From: Wesley Chalmers
[WHY]
Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
pipe commit can cause underflow.
[HOW]
Move DMUB p-state delegate into optimze_bandwidth; enabling FAMS sets
optimized_required.
This change expects that Freesync requests are blocked when
From: Rodrigo Siqueira
This commit replaces spaces with tabs in multiple functions and adjusts
the indentation in some other parts of the code to improve readability.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 44 ++---
From: Rodrigo Siqueira
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
From: Rodrigo Siqueira
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
From: Rodrigo Siqueira
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
From: Rodrigo Siqueira
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
From: Rodrigo Siqueira
When using FPO, there is some misconfiguration that happens for the lack
of configuration of the MCLK switch in some circumstances. This commit
adds the required field update when using the MCLK switch.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
From: Rodrigo Siqueira
All clock values came from firmware, but bounding box values can be
helpful in some debug situations. This commit updates some of the values
associated with clock speed and memory channels.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- FW Release 0.0.162.0
- Enable FPO+Vactivate
- Support for VESA SCR on OLED
- Refactor DMUB commands
- Fixes in secure display, modeset, memleak and more
- Picked up missed patches in history
Cc: Daniel Wheeler
On Tue, Apr 11, 2023 at 10:40 PM Mikhail Gavrilov
wrote:
>
> Hi,
> KASAN continues to find problems in the drm_sched_job_cleanup code at 6.3rc6.
> I not got any feedback in the thread
> https://lore.kernel.org/lkml/cabxgcsmvub2ra4d+k5cna0_2521tox++d4nmoukki4x2-q_...@mail.gmail.com/
> Therefore, I
Hi Christian, hi Thomas,
On Fri, Mar 10, 2023 at 11:42:56AM +0100, Thomas Hellström (Intel) wrote:
> Nice. This seems to have all we need for now for Xe as well, although not
> for i915 ATM.
A series to use drm_exec in Xe has been sent for review:
https://patchwork.freedesktop.org/series/116477/
gcc with W=1 reports
In file included from
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0.c:36:
./drivers/gpu/drm/amd/amdgpu/../pm/swsmu/inc/smu_v13_0.h:66:18: error:
‘pmfw_decoded_link_width’ defined but not used
[-Werror=unused-const-variable=]
66 | static const int
Am 13.04.23 um 16:22 schrieb Bas Nieuwenhuizen:
This info would be used by radv to figure out when we need to
split a submission into multiple submissions. radv currently has
a limit of 192 which seems to work for most gfx submissions, but
is way too high for e.g. compute or sdma.
Userspace is
Am 13.04.23 um 16:22 schrieb Bas Nieuwenhuizen:
And ensure each ring supports that many submissions. This makes
sure that we don't get surprises after the submission has been
scheduled where the ring allocation actually gets rejected.
My calculations on the existing limits:
COMPUTE v10: 128
Am 13.04.23 um 16:22 schrieb Bas Nieuwenhuizen:
To ensure it supports 192 IBs per submission, so we can keep a
simplified IB limit in the follow up patch without having to
look at IP or GPU version.
Signed-off-by: Bas Nieuwenhuizen
I've took the time and double checked the docs and the
[WHY]
Function "amdgpu_irq_update()" called by "amdgpu_device_ip_late_init()" is an
atomic context.
We shouldn't access registers through KIQ since "msleep()" may be called in
"amdgpu_kiq_rreg()".
[HOW]
Move function "amdgpu_virt_release_full_gpu()" after function
reless-legacy-ray_cs.c:warning:strncpy-specified-bound-equals-destination-size
|-- alpha-randconfig-r021-20230414
| |--
drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_validation.c:warning:variable-bw_needed-set-but-not-used
| `--
drivers-gpu-drm-amd-amdgpu-..-display-dc-link-link_valid
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