Patches 7-11 are
Reviewed-by: Felix Kuehling
On 2023-09-05 02:04, Christian König wrote:
The same PASID can be used by more than one VMID, reset each of them.
Use the common KIQ handling.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 66
On 2023-09-05 02:04, Christian König wrote:
Testing for reset is pointless since the reset can start right after the
test.
The same PASID can be used by more than one VMID, reset each of them.
Move the KIQ and all the workaround handling into common GMC code.
Signed-off-by: Christian König
On Fri, Sep 8, 2023 at 4:40 PM Timmy Tsai wrote:
>
> During jpeg init, CPU writes to frame buffer which can be cached by HDP,
> occasionally causing invalid header to be sent to MMSCH. Perform HDP flush
> after writing to frame buffer before continuing with jpeg init sequence.
>
> Signed-off-by:
On 2023-09-05 02:04, Christian König wrote:
Testing for reset is pointless since the reset can start right after the
test. Grab the reset semaphore instead.
The same PASID can be used by more than once VMID, build a mask of VMIDs
to reset instead of just restting the first one.
I think you
I think you mean "VMIDs to invalidate", not "VMIDs to reset". With that
fixed, the patch is
Acked-by: Felix Kuehling
On 2023-09-05 02:04, Christian König wrote:
Testing for reset is pointless since the reset can start right after the
test. Grab the reset semaphore instead.
The same PASID
During jpeg init, CPU writes to frame buffer which can be cached by HDP,
occasionally causing invalid header to be sent to MMSCH. Perform HDP flush
after writing to frame buffer before continuing with jpeg init sequence.
Signed-off-by: Timmy Tsai
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 3
[AMD Official Use Only - General]
Reviewed-by: Timmy Tsai
From: amd-gfx on behalf of Alex Deucher
Sent: Thursday, September 7, 2023 3:47 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/nbio4.3: set proper
[AMD Official Use Only - General]
Reviewed-by: Timmy Tsai
From: amd-gfx on behalf of Alex Deucher
Sent: Wednesday, September 6, 2023 11:36 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/soc21: don't remap HDP
From: Leo Chen
[ Upstream commit 026a71babf48efb6b9884a3a66fa31aec9e1ea54 ]
[Why & How]
HDMI TMDS does not have ODM support. Filtering 420 modes that
exceed the 4096 FMT limitation on DCN31 will resolve
intermittent corruptions issues.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Tom Chung
From: Leo Chen
[ Upstream commit 4c6107a653ccf361cb1b6ba35d558a1a5e6e57ac ]
[Why & How]
HDMI TMDS does not have ODM support. Filtering 420 modes that
exceed the 4096 FMT limitation on DCN314 will resolve
intermittent corruptions issues.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Tom Chung
From: Leo Chen
[ Upstream commit 026a71babf48efb6b9884a3a66fa31aec9e1ea54 ]
[Why & How]
HDMI TMDS does not have ODM support. Filtering 420 modes that
exceed the 4096 FMT limitation on DCN31 will resolve
intermittent corruptions issues.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Tom Chung
From: Austin Zheng
[ Upstream commit 4a30cc2bd281fa176a68b5305cd3695d636152ad ]
[Why]
Flash of corruption observed when UCLK switching after transitioning
from DTBCLK to DPREFCLK on subVP(DP) + subVP(HDMI) config
Scenario where DPREFCLK is required instead of DTBCLK is not expected
[How]
From: Leo Ma
[ Upstream commit 735688eb905db529efea0c78466fccc1461c3fde ]
[Why]
Screen underflows happen on 175hz timing for 3 plane overlay case.
[How]
Based on dst y prefetch value clamp to equ or oto for bandwidth
calculation.
Reviewed-by: Dillon Varone
Acked-by: Alex Hung
Signed-off-by:
From: Martin Tsai
[ Upstream commit 6917b0b711713b9d84d7e0844e9aa613997a51b2 ]
[Why]
Panels show corruption with high refresh rate timings when
ss is enabled.
[How]
Read down-spread percentage from lut to adjust dprefclk.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by:
From: Leo Chen
[ Upstream commit 4c6107a653ccf361cb1b6ba35d558a1a5e6e57ac ]
[Why & How]
HDMI TMDS does not have ODM support. Filtering 420 modes that
exceed the 4096 FMT limitation on DCN314 will resolve
intermittent corruptions issues.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Tom Chung
From: Leo Chen
[ Upstream commit 026a71babf48efb6b9884a3a66fa31aec9e1ea54 ]
[Why & How]
HDMI TMDS does not have ODM support. Filtering 420 modes that
exceed the 4096 FMT limitation on DCN31 will resolve
intermittent corruptions issues.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Tom Chung
From: Austin Zheng
[ Upstream commit 4a30cc2bd281fa176a68b5305cd3695d636152ad ]
[Why]
Flash of corruption observed when UCLK switching after transitioning
from DTBCLK to DPREFCLK on subVP(DP) + subVP(HDMI) config
Scenario where DPREFCLK is required instead of DTBCLK is not expected
[How]
From: Leo Ma
[ Upstream commit 735688eb905db529efea0c78466fccc1461c3fde ]
[Why]
Screen underflows happen on 175hz timing for 3 plane overlay case.
[How]
Based on dst y prefetch value clamp to equ or oto for bandwidth
calculation.
Reviewed-by: Dillon Varone
Acked-by: Alex Hung
Signed-off-by:
From: Martin Tsai
[ Upstream commit 6917b0b711713b9d84d7e0844e9aa613997a51b2 ]
[Why]
Panels show corruption with high refresh rate timings when
ss is enabled.
[How]
Read down-spread percentage from lut to adjust dprefclk.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by:
From: George Shen
[ Upstream commit 974764180838516f80a13257da67a1ec6afb87d4 ]
[Why]
Current BW calculations do not account for the additional padding added
for uncompressed pixel-to-symbol packing.
This results in X.Y being too low for 128b/132b SST streams in certain
scenarios. If X.Y is too
From: Alvin Lee
[ Upstream commit 2b1b838ea8e5437ef06a29818d16e9efdfaf0037 ]
[Description]
In overclocking scenarios the max memclk could be higher
than the DC mode limit. However, for configs that don't
support MCLK switching we need to set the max memclk to
the overclocked max instead of the
From: Leo Chen
[ Upstream commit 026a71babf48efb6b9884a3a66fa31aec9e1ea54 ]
[Why & How]
HDMI TMDS does not have ODM support. Filtering 420 modes that
exceed the 4096 FMT limitation on DCN31 will resolve
intermittent corruptions issues.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Tom Chung
From: Leo Chen
[ Upstream commit 4c6107a653ccf361cb1b6ba35d558a1a5e6e57ac ]
[Why & How]
HDMI TMDS does not have ODM support. Filtering 420 modes that
exceed the 4096 FMT limitation on DCN314 will resolve
intermittent corruptions issues.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Tom Chung
From: Austin Zheng
[ Upstream commit 4a30cc2bd281fa176a68b5305cd3695d636152ad ]
[Why]
Flash of corruption observed when UCLK switching after transitioning
from DTBCLK to DPREFCLK on subVP(DP) + subVP(HDMI) config
Scenario where DPREFCLK is required instead of DTBCLK is not expected
[How]
On 2023-09-05 02:04, Christian König wrote:
Move the SDMA workaround necessary for Navi 1x into a higher layer.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 48 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 5 +-
From: Leo Ma
[ Upstream commit 735688eb905db529efea0c78466fccc1461c3fde ]
[Why]
Screen underflows happen on 175hz timing for 3 plane overlay case.
[How]
Based on dst y prefetch value clamp to equ or oto for bandwidth
calculation.
Reviewed-by: Dillon Varone
Acked-by: Alex Hung
Signed-off-by:
From: Martin Tsai
[ Upstream commit 6917b0b711713b9d84d7e0844e9aa613997a51b2 ]
[Why]
Panels show corruption with high refresh rate timings when
ss is enabled.
[How]
Read down-spread percentage from lut to adjust dprefclk.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by:
From: Lijo Lazar
[ Upstream commit 6cb209ed68e45c8e4b71d97a037ac6b7dbce9b50 ]
Not all rings have scheduler associated. Only update scheduler data for
rings with scheduler. It could result in out of bound access as total
rings are more than those associated with particular IPs.
Signed-off-by:
From: George Shen
[ Upstream commit 974764180838516f80a13257da67a1ec6afb87d4 ]
[Why]
Current BW calculations do not account for the additional padding added
for uncompressed pixel-to-symbol packing.
This results in X.Y being too low for 128b/132b SST streams in certain
scenarios. If X.Y is too
From: Philip Yang
[ Upstream commit bf80d34b6c58ad1c4f76067ecd460a148eab9d39 ]
Retry faults are delegated to soft IH ring and then processed by
deferred worker. Current soft IH ring size PAGE_SIZE can store 128
entries, which may overflow and drop retry faults, causes HW stucks
because the
On Thu, Sep 07, 2023 at 03:44:39AM +, Lin, Wayne wrote:
> [AMD Official Use Only - General]
>
> > -Original Message-
> > From: Imre Deak
> > Sent: Friday, August 25, 2023 9:56 PM
> > To: Lin, Wayne
> > Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org;
> >
On 2023-09-05 02:04, Christian König wrote:
The KIQ code path was ignoring the second flush. Also avoid long lines and
re-calculating the register offsets over and over again.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 29 +--
1 file
On Fri, Sep 8, 2023 at 2:43 PM Tj wrote:
>
> On 23/08/2023 14:56, Deucher, Alexander wrote:
>
> >> -Original Message-
> >> From: amd-gfx On Behalf Of Tj
> >> Sent: Wednesday, August 23, 2023 4:54 AM
> >> To: amd-gfx@lists.freedesktop.org
> >> Subject: 6.5.0-rc7: RIP:
On 23/08/2023 14:56, Deucher, Alexander wrote:
-Original Message-
From: amd-gfx On Behalf Of Tj
Sent: Wednesday, August 23, 2023 4:54 AM
To: amd-gfx@lists.freedesktop.org
Subject: 6.5.0-rc7: RIP: 0010:radeon_gem_va_ioctl+0x3dc/0x4f0 [radeon]
Recently, and I think especially since
On 2023-09-08 13:45, Philip Yang wrote:
Otherwise GPU may access the mapping to cause IOMMU IO_PAGE_FAULT.
Remove dma mapping before free the mem attachment, to fix potential dma
mapping leaking if failed unmap from GPUs.
For queues restore path, because FW already flush TLB, it is safe to
Otherwise GPU may access the mapping to cause IOMMU IO_PAGE_FAULT.
Remove dma mapping before free the mem attachment, to fix potential dma
mapping leaking if failed unmap from GPUs.
For queues restore path, because FW already flush TLB, it is safe to
leave this unchanged.
Signed-off-by: Philip
To support oversubscription, MES FW expects WPTR BOs to
be mapped into GART, before they are submitted to usermode
queues. This patch adds a function for the same.
V4: fix the wptr value before mapping lookup (Bas, Christian).
V5: Addressed review comments from Christian:
- Either pin object
This patch adds code to cleanup any leftover userqueues which
a user might have missed to destroy due to a crash or any other
programming error.
Cc: Alex Deucher
Cc: Christian Koenig
Suggested-by: Bas Nieuwenhuizen
Signed-off-by: Bas Nieuwenhuizen
Signed-off-by: Shashank Sharma
---
The userspace sends us the doorbell object and the relative doobell
index in the object to be used for the usermode queue, but the FW
expects the absolute doorbell index on the PCI BAR in the MQD. This
patch adds a function to convert this relative doorbell index to
absolute doorbell index.
This
This patch adds new functions to map/unmap a usermode queue into
the FW, using the MES ring. As soon as this mapping is done, the
queue would be considered ready to accept the workload.
V1: Addressed review comments from Alex on the RFC patch series
- Map/Unmap should be IP specific.
V2:
The FW expects us to allocate at least one page as context
space to process gang, process, GDS and FW related work.
This patch creates a joint object for the same, and calculates
GPU space offsets of these spaces.
V1: Addressed review comments on RFC patch:
Alex: Make this function IP
A Memory queue descriptor (MQD) of a userqueue defines it in
the hw's context. As MQD format can vary between different
graphics IPs, we need gfx GEN specific handlers to create MQDs.
This patch:
- Introduces MQD handler functions for the usermode queues.
- Adds new functions to create and
This patch adds:
- A new IOCTL function to create and destroy
- A new structure to keep all the user queue data in one place.
- A function to generate unique index for the queue.
V1: Worked on review comments from RFC patch series:
- Alex: Keep a list of queues, instead of single queue per
This patch adds skeleton code for amdgpu usermode queue.
It contains:
- A new files with init functions of usermode queues.
- A queue context manager in driver private data.
V1: Worked on design review comments from RFC patch series:
(https://patchwork.freedesktop.org/series/112214/)
- Alex: Keep
From: Alex Deucher
This patch intorduces new UAPI/IOCTL for usermode graphics
queue. The userspace app will fill this structure and request
the graphics driver to add a graphics work queue for it. The
output of this UAPI is a queue id.
This UAPI maps the queue into GPU, so the graphics app can
This patch series introduces AMDGPU usermode queues for gfx workloads.
Usermode queues is a method of GPU workload submission into the graphics
hardware without any interaction with kernel/DRM schedulers. In this
method, a userspace graphics application can create its own workqueue
and submit it
Series is:
Reviewed-by: Alex Deucher
On Fri, Sep 8, 2023 at 10:56 AM Hamza Mahfooz wrote:
>
> From: Yifan Zhang
>
> Dropping bit 31:4 of page table base is wrong, it makes page table
> base points to wrong address if phys addr is beyond 64GB; dropping
> page_table_start/end bit 31:4 is
Series is
Acked-by: Harry Wentland
Harry
On 2023-09-08 10:55, Hamza Mahfooz wrote:
This reverts commit 5b7a256c982636ebc4f16b708b40ff56d33c8a86.
Since, we now have an actual fix for this issue, we can get rid of this
workaround as it can cause pin failures if enough VRAM isn't carved out
by
This reverts commit 5b7a256c982636ebc4f16b708b40ff56d33c8a86.
Since, we now have an actual fix for this issue, we can get rid of this
workaround as it can cause pin failures if enough VRAM isn't carved out
by the BIOS.
Cc: sta...@vger.kernel.org # 6.1+
Signed-off-by: Hamza Mahfooz
---
v2: new
From: Yifan Zhang
Dropping bit 31:4 of page table base is wrong, it makes page table
base points to wrong address if phys addr is beyond 64GB; dropping
page_table_start/end bit 31:4 is unnecessary since dcn20_vmid_setup
will do that. Also, while we are at it, cleanup the assignments using
On 09/06, Harry Wentland wrote:
> On 2023-08-10 12:02, Melissa Wen wrote:
> > Hi all,
> >
> > Here is the next version of our work to enable AMD driver-specific color
> > management properties [1][2]. This series is a collection of
> > contributions from Joshua, Harry, and me to enhance the AMD
On 09/06, Harry Wentland wrote:
>
>
> On 2023-08-10 12:03, Melissa Wen wrote:
> > Map the plane CTM driver-specific property to DC plane, instead of DC
> > stream. The remaining steps to program DPP block are already implemented
> > on DC shared-code.
> >
> > Signed-off-by: Melissa Wen
> > ---
On 2023-09-08 10:41, Melissa Wen wrote:
On 09/06, Harry Wentland wrote:
On 2023-08-10 12:03, Melissa Wen wrote:
Plane CTM for pre-blending color space conversion. Only enable
driver-specific plane CTM property on drivers that support both pre- and
post-blending gamut remap matrix, i.e.,
On 09/06, Harry Wentland wrote:
>
>
> On 2023-08-10 12:03, Melissa Wen wrote:
> > Plane CTM for pre-blending color space conversion. Only enable
> > driver-specific plane CTM property on drivers that support both pre- and
> > post-blending gamut remap matrix, i.e., DCN3+ family. Otherwise it
> >
On 2023-09-08 10:11, Melissa Wen wrote:
On 09/06, Harry Wentland wrote:
On 2023-08-10 12:02, Melissa Wen wrote:
From: Harry Wentland
The region and segment calculation was incapable of dealing
with regions of more than 16 segments. We first fix this.
Now that we can support regions up to
On 09/06, Harry Wentland wrote:
> On 2023-08-10 12:02, Melissa Wen wrote:
> > From: Harry Wentland
> >
> > The region and segment calculation was incapable of dealing
> > with regions of more than 16 segments. We first fix this.
> >
> > Now that we can support regions up to 256 elements we can
On 09/06, Harry Wentland wrote:
>
>
> On 2023-08-25 10:18, Melissa Wen wrote:
> > On 08/22, Pekka Paalanen wrote:
> >> On Thu, 10 Aug 2023 15:02:47 -0100
> >> Melissa Wen wrote:
> >>
> >>> Instead of relying on color block names to get the transfer function
> >>> intention regarding encoding
On 09/06, Harry Wentland wrote:
>
>
> On 2023-08-10 12:03, Melissa Wen wrote:
> > From: Joshua Ashton
> >
> > Need to funnel the color caps through to these functions so it can check
> > that the hardware is capable.
> >
> > v2:
> > - remove redundant color caps assignment on plane degamma
On 09/06, Harry Wentland wrote:
> On 2023-08-10 12:02, Melissa Wen wrote:
> > On AMD HW, 3D LUT always assumes a preceding shaper 1D LUT used for
> > delinearizing and/or normalizing the color space before applying a 3D
> > LUT. Add pre-defined transfer function to enable delinearizing content
> >
On 09/07, Pekka Paalanen wrote:
> On Wed, 6 Sep 2023 15:30:04 -0400
> Harry Wentland wrote:
>
> > On 2023-08-10 12:02, Melissa Wen wrote:
> > > Add 3D LUT property for plane gamma correction using a 3D lookup table.
> > > Since a 3D LUT has a limited number of entries in each dimension we want
>
[AMD Official Use Only - General]
Reviewed-by: Yang Wang
Best Regards,
Kevin
-Original Message-
From: Hawking Zhang
Sent: Friday, September 8, 2023 9:22 PM
To: amd-gfx@lists.freedesktop.org; Wang, Yang(Kevin)
Cc: Zhang, Hawking
Subject: [PATCH] drm/amdgpu: fallback to old RAS error
So driver doesn't generate incorrect message until
the new format is settled down for aqua_vanjaram
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
[AMD Official Use Only - General]
Will send out a new version soon. Ignore this one.
Regards,
Hawking
-Original Message-
From: Hawking Zhang
Sent: Friday, September 8, 2023 21:17
To: amd-gfx@lists.freedesktop.org; Wang, Yang(Kevin)
Cc: Zhang, Hawking
Subject: [PATCH] drm/amdgpu:
So driver doesn't generate incorrect message until
the new format is settled down for aqua_vanjaram
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
On Fri, Sep 8, 2023 at 7:05 AM Lijo Lazar wrote:
>
> On a full device reset, PSP FW gets unloaded. Hence restore the
> partition mode by placing a new request.
>
> Signed-off-by: Lijo Lazar
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5
>
On Thu, 7 Sep 2023 10:10:50 -0400
Harry Wentland wrote:
> On 2023-09-07 03:49, Pekka Paalanen wrote:
> > On Wed, 6 Sep 2023 16:15:10 -0400
> > Harry Wentland wrote:
> >
> >> On 2023-08-25 10:18, Melissa Wen wrote:
> >>> On 08/22, Pekka Paalanen wrote:
> On Thu, 10 Aug 2023
No functional modification involved.
drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dpms.c:2476
link_set_dpms_on() warn: if statement not indented.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6502
Signed-off-by: Jiapeng Chong
---
On a full device reset, PSP FW gets unloaded. Hence restore the
partition mode by placing a new request.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c| 28 --
[AMD Official Use Only - General]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Wang, Yang(Kevin)
Sent: Friday, September 8, 2023 16:39
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Wang, Yang(Kevin)
Subject: [PATCH v2 2/2] drm/amd/pm:
Am 08.09.23 um 10:46 schrieb Yifan Zhang:
dropping bit 31:4 of paget table base is wrong, it makes page table
base points to wrong address if phys addr is beyond 64GB; dropping
page_table_start/end bit 31:4 is unnecessary since dcn20_vmid_setup
will do that.
Signed-off-by: Yifan Zhang
Good
dropping bit 31:4 of paget table base is wrong, it makes page table
base points to wrong address if phys addr is beyond 64GB; dropping
page_table_start/end bit 31:4 is unnecessary since dcn20_vmid_setup
will do that.
Signed-off-by: Yifan Zhang
---
v1:
enable smu_v13_0_6 mca debug mode when UMC RAS feature is enabled.
v2:
use amdgpu_ras_is_supported() helper function instead bitmask check.
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 ++-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 26
update smu firmware header to support smu mca debug feature.
Signed-off-by: Yang Wang
---
.../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_6.h | 3 +++
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 3 ++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git
[AMD Official Use Only - General]
> -Original Message-
> From: amd-gfx On Behalf Of Yang
> Wang
> Sent: Friday, September 8, 2023 2:34 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Wang, Yang(Kevin) ; Zhang, Hawking
>
> Subject: [PATCH 2/2] drm/amd/pm: enable smu_v13_0_6 mca debug mode
>
Am 07.09.23 um 18:33 schrieb suijingfeng:
Hi,
On 2023/9/7 17:08, Christian König wrote:
I strongly suggest that you just completely drop this here
Drop this is OK, no problem. Then I will go to develop something else.
This version is not intended to merge originally, as it's a RFC.
Also,
Am 08.09.23 um 05:39 schrieb xinhui pan:
Some BOs might be pinned. So the first eviction's failure will abort the
suspend sequence. These pinned BOs will be unpined afterwards during
suspend.
That doesn't make much sense since pinned BOs don't cause eviction
failure here.
What exactly is
enable smu_v13_0_6 mca debug mode when UMC RAS feature is enabled.
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 ++-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 26 +++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git
update smu firmware header to support smu mca debug feature.
Signed-off-by: Yang Wang
---
.../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_6.h | 3 +++
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 3 ++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git
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