refresh
Acked-by: Alan Liu
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index ec7edb7087b4..41e68d694c17 100644
--- a/drivers/gpu/drm
From: Alvin Lee
[Description]
Since SubVP high refresh is now enabled, we must
fallback to SW cursor under if we're in a SubVP
high refresh config
Reviewed-by: Samson Tam
Acked-by: Alan Liu
Signed-off-by: Alvin Lee
---
.../gpu/drm/amd/display/dc/core/dc_stream.c | 35
to use the lowest link setting.
Reviewed-by: Wenjing Liu
Acked-by: Alan Liu
Signed-off-by: Zhikai Zhai
---
.../dc/link/protocols/link_dp_capability.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols
set_default_brightness_aux, check if cached values exists.
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Wenjing Liu
Acked-by: Alan Liu
Signed-off-by: Nicholas Susanto
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dc_types.h | 4
drivers/gpu/drm/amd
From: Daniel Miess
[Why & How]
Re-enable all RCO options now that all known issues with
RCO have been addressed
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alan Liu
Signed-off-by: Daniel Miess
---
.../amd/display/dc/dcn314/dcn314_resource.c| 18 +-
1 file change
From: Daniel Miess
[Why]
When RCO is enabled for symclk32_le we get failures during
DP2 link traing compliance tests.
[How]
Break out symclk32_le RCO into a separate function that is
called for hpo when link is enabled/disabled.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alan Liu
Signed-off
dmissable() and dcn32_subvp_vblank_admissable()
Reviewed-by: Alvin Lee
Acked-by: Alan Liu
Signed-off-by: Samson Tam
---
.../display/dc/dcn32/dcn32_resource_helpers.c | 24 +++
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 20 +---
2 files changed, 31 insertio
split for the platform which dcn resource is limited
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Alvin Lee
Acked-by: Alan Liu
Signed-off-by: Zhikai Zhai
---
drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c | 2 +-
1 file changed, 1 insertion(+), 1
stream updates need
to be cleared in case there is no stream update in
the next flip)
Reviewed-by: Samson Tam
Acked-by: Alan Liu
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git
From: Rodrigo Siqueira
Reduce stack size pointed by clang:
amdgpu_dm/amdgpu_dm.c:8655:13: error: stack frame size (1048) exceeds limit
(1024) in 'amdgpu_dm_atomic_commit_tail' [-Werror,-Wframe-larger-than]
Reviewed-by: Harry Wentland
Acked-by: Alan Liu
Signed-off-by: Rodrigo Siqueira
From: Reza Amini
[why]
Allow ABM states to be transferred across display
adapters for smooth display transitions.
[how]
We call DMUB to pause and get ABM states. We
transfer data to other gpu, and deliver data and
ask ABM to un-pause.
Reviewed-by: Harry Vanzylldejong
Acked-by: Alan Liu
osip Pavic
Acked-by: Alan Liu
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/d
From: Taimur Hassan
[Why]
Aux write was meant to be ASIC specific, and is
causing compliance failures on newer parts.
[How]
Make workaround specific to single ASIC.
Reviewed-by: Michael Strauss
Acked-by: Alan Liu
Signed-off-by: Taimur Hassan
---
drivers/gpu/drm/amd/display/dc/link
From: Alan Liu
[Why]
When 2 threads are doing commit_tail parallelly, one thread could
commit new streams to dc state but another thread remove it from dc
right away.
[How]
If we don't have new dm state change from commit_check, then we should
not call dc_commit_streams() in commit_tail. A new
From: George Shen
[Why]
There certain cases where the timing BW is dependent on the type of link
encoding in use. Thus to calculate the correct BW required for a given
timing, the link encoding should be added as a parameter.
Reviewed-by: Wenjing Liu
Acked-by: Alan Liu
Signed-off-by: George
Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alan Liu
Signed-off-by: Daniel Miess
---
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314
function to calculate stream overhead to timing BW calculation for
128b/132b SST cases.
Reviewed-by: Wenjing Liu
Acked-by: Alan Liu
Signed-off-by: George Shen
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 42 +
2 files
From: Meera Patel
This commit initializes uninitialized variables.
For some compilers uninitialized variable warnings are treated as Error.
Reviewed-by: Wenjing Liu
Acked-by: Alan Liu
Signed-off-by: Meera Patel
---
.../drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +-
drivers/gpu
From: Cruise Hung
[Why & How]
To query the bits and print them out for debug purposes.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alan Liu
Signed-off-by: Cruise Hung
---
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 4
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
From: George Shen
[Why]
Updating downspread factor to 0.3% to add additional margin to account
for potential link rate deviations (up to 300ppm as per the DP spec).
Reviewed-by: Wenjing Liu
Acked-by: Alan Liu
Signed-off-by: George Shen
---
drivers/gpu/drm/amd/display/include
is in use
Acked-by: Alan Liu
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 194f185e7798..819c326baefe 100644
--- a/drivers/gpu/drm/amd
From: Nicholas Kazlauskas
[Why]
Workaround to avoid accessing DMCUB state too early if the emulator
is in use - we don't support any of the features the caps are querying
with emulation anyway.
[How]
Guard the query if emulation is in use.
Reviewed-by: Charlene Liu
Acked-by: Alan Liu
Signed
From: Leo Ma
[Why]
Visual confirm color is not as expected for Autoa Color Management
feature test.
[How]
Calculate scaler recout data when visual confirm enabled to update
the visual confirm bar on the display.
Reviewed-by: Aric Cyr
Acked-by: Alan Liu
Signed-off-by: Leo Ma
---
drivers/gpu
From: Taimur Hassan
[Why & How]
Shouldn't be touching path for HW DMCUB when emulating.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alan Liu
Signed-off-by: Taimur Hassan
---
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff -
From: Taimur Hassan
[Why & How]
If there is no TG allocation we can dereference a NULL pointer when
checking if the TG is enabled.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alan Liu
Signed-off-by: Taimur Hassan
---
dri
From: Alan Liu
There is no need to calculate the VCO frequency. In our internal branch
we've hard-coded this for a while, so it's well-tested. This also allows
us to remove the now unused code for calculating the VCO frequency.
Reviewed-by: Harry Wentland
Acked-by: Alan Liu
Signed-off
From: Rodrigo Siqueira
After enable DRM_AMDGPU_WERROR, clang highlight multiple functions that
need to have `static`, and this commit address those issues and also
improve the indents.
Reviewed-by: Hamza Mahfooz
Acked-by: Alan Liu
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display
From: Rodrigo Siqueira
The get_engine_type is never used in the code, for this reason, this
commit drops this function.
Reviewed-by: Hamza Mahfooz
Acked-by: Alan Liu
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h | 2 --
1 file changed, 2 deletions
From: Rodrigo Siqueira
This commit improves the include of some header files to make them align
with other includes.
Reviewed-by: Hamza Mahfooz
Acked-by: Alan Liu
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/basics/conversion.c| 2 +-
drivers/gpu/drm/amd/display/dc
is set. HPD driven handling method is still kept.
Just hook up our handler to drm mgr->cbs->poll_hpd_irq().
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewed-by: Jerry Zuo
Acked-by: Alan Liu
Signed-off-by: Wayne Lin
---
.../gpu/drm/amd/display/amdgpu_dm/amdgp
From: Michael Strauss
[WHY]
Issue not display generic, required for multiple 2+ LTTPR link configurations.
[HOW]
Revert monitor patch change and remove delay for single LTTPR case
Reviewed-by: George Shen
Acked-by: Alan Liu
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc
.
Reviewed-by: Syed Hassan
Acked-by: Alan Liu
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu
Kazlauskas
Acked-by: Alan Liu
Signed-off-by: JinZe Xu
---
drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index 1a7b93e41e35..d8fcff0e5319 100644
for SubVP cases
* Fix DP2 link training failure with RCO
* Reenable all root clock gating options
* Cache backlight_millinits in link structure and setting brightness accordingly
* refine to decide the verified link setting
* Update SW cursor fallback for subvp high refresh
Cc: Daniel Wheeler
Alan Liu (2
s
- Change default Z8 watermark values
- Workaround wrong HDR colorimetry with some receivers
Acked-by: Alan Liu
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/a
From: Anthony Koo
- Add dmub boot options to disable ips states on init
Acked-by: Alan Liu
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc
From: George Shen
[Why]
Certain ports on DCN3.2 configs do not properly populate the BIOS
info table flag to indicate DP dual mode is unsupported.
[How]
Add a workaround to disable DP dual mode on the ports with the missing
BIOS info table flag.
Reviewed-by: Michael Strauss
Acked-by: Alan Liu
From: Leo Ma
This reverts commit 8552024d1e2a008b6df544845d09120cfea9508b.
A regression is found on this change, so revert it for the time being
and resubmit when issue is fixed.
Reviewed-by: Martin Leung
Acked-by: Alan Liu
Signed-off-by: Leo Ma
---
.../gpu/drm/amd/display/dc/core
From: Samson Tam
[Why]
Reading pipe_fuses from register may have invalid bits set, which may
affect the num_pipes erroneously.
[How]
Add read_pipes_fuses() call and filter bits based on expected number
of pipes.
Reviewed-by: Alvin Lee
Acked-by: Alan Liu
Signed-off-by: Samson Tam
From: Leo Chen
[Why & How]
Adding debug options to override Z8 watermark values for testing purposes.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alan Liu
Signed-off-by: Leo Chen
---
drivers/gpu/drm/amd/display/dc/dc.h | 4
drivers/gpu/drm/amd/display/dc/dml/d
From: Leo Chen
[Why & How]
Previous Z8 watermark values were causing flickering and OTC underflow.
Updating Z8 watermark values based on the measurement.
Reviewed-by: Nicholas Kazlauskas
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Alan Liu
Signed-off-by:
.
Reviewed-by: Aric Cyr
Acked-by: Alan Liu
Signed-off-by: Ilya Bakoulin
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 7 +++
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- FW Release 0.0.165.0
- Add w/a to disable DP dual mode on certain ports
- Revert "Update scaler recout data for visual confirm"
- Filter out invalid bits in pipe_fuses
- Adding debug option to override Z8
then
0 in amdgpu_irq_put().
v2:
- Add warning in amdgpu_irq_enable() if the irq is already disabled.
- Call dc_interrupt_set() in dm_set_vblank() to avoid refcount change
if it is in gpu-reset.
v3:
- Improve commit message and code comments.
Signed-off-by: Alan Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu
g less then
0 in amdgpu_irq_put().
v2:
- Add warning in amdgpu_irq_enable() if the irq is already disabled.
- Call dc_interrupt_set() in dm_set_vblank() to avoid refcount change
if it is in gpu-reset.
Signed-off-by: Alan Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 3 +++
.../d
g less then
0 in amdgpu_irq_put().
Signed-off-by: Alan Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c| 3 +++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 14 ++
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ir
-by: Alan Liu
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 12 ++--
.../gpu/drm/amd/display/dc/dcn32/dcn32_resource.c| 1 +
.../gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 1 +
4
and Gamut flag in VRR info
- Add margin for max vblank time for SubVP + DRR
- Populate DP2.0 output type for DML pipe
Acked-by: Alan Liu
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd
From: George Shen
[Why]
DCN3.2 DML logic uses a new output type for DP2.0,
which will enable validation to pass for higher BW
timings that require DP2.0 link rates.
[How]
Populate the DML pipe with DP2.0 output type if
the signal type of the pipe_ctx is 128b/132b.
Reviewed-by: Alvin Lee
From: Dillon Varone
[WHY?]
Data return times when using lowest memclk can be <= 60us, which can cause
underflow on high bandwidth displays with a workload.
[HOW?]
Enforce a minimum prefetch time during validation for low memclk modes.
Reviewed-by: Jun Lei
Acked-by: Alan Liu
Signed-
From: Mike Hsieh
[Why] FreeSync always use G2.2 EOTF and Native gamut
[How] Set EOTF and Gamut flags accordingly
Reviewed-by: Krunoslav Kovac
Acked-by: Alan Liu
Signed-off-by: Mike Hsieh
---
drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 8
1 file changed, 4 insertions
train if link is MST.
Reviewed-by: Mustapha Ghaddar
Acked-by: Alan Liu
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 8
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
From: Steve Su
[Why]
1. Port of gpio has different mapping.
[How]
1. Add a dummy entry in mapping table.
2. Fix incorrect mask bit field access.
Reviewed-by: Alvin Lee
Acked-by: Alan Liu
Signed-off-by: Steve Su
---
.../amd/display/dc/gpio/dcn32/hw_factory_dcn32.c | 14
From: Mustapha Ghaddar
[WHY]
Unlike DP or USBC, the USB4 link does not get its own encoder and
has to share therefore verify_caps is skipped.
[HOW]
Fix the fallback logic for automated tests and take that
into consideration for LT and LS.
Reviewed-by: Jun Lei
Acked-by: Alan Liu
Signed-off
From: Wesley Chalmers
[WHY]
Committing a state while performing DRR actions can cause underflow.
[HOW]
Disabled features performing DRR actions during state commit.
Need to follow-up on why DRR actions affect state commit.
Reviewed-by: Jun Lei
Acked-by: Alan Liu
Signed-off-by: Wesley
-by: Roman Li
Acked-by: Alan Liu
Signed-off-by: Nicholas Kazlauskas
---
.../dc/dcn314/dcn314_dio_stream_encoder.c | 24 ++-
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
b/drivers/gpu/drm/amd/display
-by: Jun Lei
Acked-by: Alan Liu
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 14 +-
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c | 8
.../drm/amd/display/dc/inc/hw/timing_generator.h | 1 +
3 files changed, 22 insertions(+), 1
the
FCLK deviation.
Reviewed-by: Aurabindo Pillai
Reviewed-by: Jun Lei
Acked-by: Alan Liu
Signed-off-by: Chaitanya Dhere
---
.../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | 2 +-
.../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h | 2 +-
2 files changed, 2
-by: Aric Cyr
Acked-by: Alan Liu
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 43 +++-
1 file changed, 20 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d446e6098948.
From: Aurabindo Pillai
[Why]
Bug was caused when moving variable from stack to heap because it was reusable
and garbage was left over, so we need to zero mem.
Reviewed-by: Martin Leung
Acked-by: Alan Liu
Signed-off-by: Aurabindo Pillai
Signed-off-by: Martin Leung
---
drivers/gpu/drm/amd
.
Reviewed-by: George Shen
Acked-by: Alan Liu
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 22 +++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core
From: Nawwar Ali
[WHY]
Previously driver use gamma 2.2 for 709 color space,
but the standard is to use gamma of 2.222
[HOW]
Change it gamma to 2.222
Reviewed-by: Krunoslav Kovac
Acked-by: Alan Liu
Signed-off-by: Nawwar Ali
---
drivers/gpu/drm/amd/display/modules/color
From: Nicholas Kazlauskas
[Why]
We're missing the helpers from dcn20 that would allow
overriding these with DC debug options.
[How]
Use dcn20_patch_bounding_box to support overriding all the
relevant values.
Reviewed-by: Jun Lei
Acked-by: Alan Liu
Signed-off-by: Nicholas Kazlauskas
From: Max Tseng
[Why]
PSR-SU requires extra conditions while cursor update.
Reviewed-by: Robin Chen
Acked-by: Alan Liu
Signed-off-by: Max Tseng
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 48
1 file changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/amd
From: Nicholas Kazlauskas
[Why & How]
New values requested by hardware after fine-tuning.
Update for all memory types.
Reviewed-by: Jun Lei
Acked-by: Alan Liu
Signed-off-by: Nicholas Kazlauskas
---
.../dc/clk_mgr/dcn314/dcn314_clk_mgr.c| 32 +--
.../amd/displa
.
Reviewed-by: Robin Chen
Acked-by: Alan Liu
Signed-off-by: Ryan Lin
---
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 5 +
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 6 +-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
b
From: Leo Ma
[Why && How]
We will need to differentiate vendor behavior in the future.
Reviewed-by: Chris Park
Acked-by: Alan Liu
Signed-off-by: Leo Ma
---
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/di
From: Alvin Lee
[Description]
- Wait for vblank during front end programming
for global sync to ensure all double buffer
updates take.
- This prevents underflow in some cases.
Reviewed-by: Martin Leung
Acked-by: Alan Liu
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn20
This DC patchset brings improvements in multiple areas. In summary, we have:
- Wait for VBLANK during pipe programming
- Adding HDMI SCDC DEVICE_ID define
- Cursor update refactor: PSR-SU support condition
- Update 709 gamma to 2.222 as stated in the standerd
- Consider dp
caller to
cover psp_prep_securedisplay_cmd_buf() and the code checking the return
status of command buffer.
Signed-off-by: Alan Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 9 +
drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c | 4
drivers/gpu/drm/amd/display
Define ixAZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA
Define AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK/SHIFT
Signed-off-by: Alan Liu
---
drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h | 1 +
drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h | 2 ++
2 files changed, 3
Define HDMI_ACP_SEND register shift/mask.
Signed-off-by: Alan Liu
---
drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h | 2 ++
drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h | 2 ++
drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h | 2 ++
drivers/gpu/drm
From: Martin Leung
why and how:
need to hook in new smu interfaces
cleaning up code that used old variables
Reviewed-by: Nevenko Stupar
Acked-by: Alan Liu
Signed-off-by: Martin Leung
---
.../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 13 +---
.../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
From: Melissa Wen
FPU operations in dcn10 was already moved to dml folder via calcs code.
However, dcn1_0_ip and dcn_1_0_soc with FPU componentd remains on dcn10.
Following previous changes to isolate FPU, this patch creates dcn10_fpu
files to isolate FPU-specific code and moves those structs to
From: Melissa Wen
dml/dcn20_fpu file centralizes all DCN2x functions that require FPU access.
Therefore, this patch moves FPU-related code from dcn21 to dcn20_fpu. These
include:
- dcn21_populate_dml_pipes_from_context()
- dcn21_validate_bandwidth_fp() and related:
- dcn21_calculate_wm(),
-
From: Melissa Wen
Move parts of dcn20 code that uses FPU to dml folder. It aims to isolate
FPU operations as described by series:
drm/amd/display: Introduce FPU directory inside DC
https://patchwork.freedesktop.org/series/93042/
This patch moves the following functions from dcn20_resource to
From: Leo Li
[Why]
On LNX, TO_CLK_MGR_INTERNAL() only works to get clk_mgr_internal from a
given clk_mgr. In clk_mgr_dcn316 struct, the clk_mgr_internal is already
a memeber by the alias 'base'
[How]
Use _mgr->base instead.
Reviewed-by: Harry Wentland
Acked-by: Alan Liu
Signed-off-by:
the assignment that we had backed up, so
just copy off of the now clean current state assignment after the
reset has occcurred with the new link_enc_cfg_copy() interface.
Fixes: 6d63fcc2a334 ("drm/amd/display: Reset link encoder assignments for GPU
reset")
Reviewed-by: Jimmy Kizito
Acked-by
From: Chris Park
[Why]
Virtualization enters blue screen of death (BSoD)
due to NULL res_pool object when accessing DSC
encoder capability.
[How]
Add NULL check to avoid blue screen of death.
Reviewed-by: Aric Cyr
Acked-by: Alan Liu
Signed-off-by: Chris Park
---
drivers/gpu/drm/amd/display
to add future flexibility
- fix deep color ratio
- add debug option to bypass ssinfo from bios for dcn315
Acked-by: Alan Liu
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc
From: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Alan Liu
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display
From: Charlene Liu
[why]
enable the support in driver, let the control by CMOS
Reviewed-by: Aric Cyr
Acked-by: Alan Liu
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c | 3
-by: George Shen
Acked-by: Alan Liu
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 49 ++-
1 file changed, 37 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core
From: Sung Joon Kim
[why]
Need to provide this workaround
only for type 1 passive dongle
[how]
Detect if dongle is type 1 or 2.
And use it to determine if w/a is needed.
Reviewed-by: Charlene Liu
Acked-by: Alan Liu
Signed-off-by: Sung Joon Kim
---
drivers/gpu/drm/amd/display/dc/core
From: Jingwen Zhu
[Why]
Screen shake on DCN3 night light SDR BR3.
[How]
Change the logic to use double buffer reisgter on gamut settings.
Reviewed-by: Krunoslav Kovac
Acked-by: Alan Liu
Signed-off-by: Jingwen Zhu
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c | 2 +-
1 file
From: Charlene Liu
[why]
dcn31x could use dcn31 sepcific which contains deep_color_ratio for dmub
Reviewed-by: Nevenko Stupar
Reviewed-by: Hansen Dsouza
Reviewed-by: Aric Cyr
Acked-by: Alan Liu
Signed-off-by: Charlene Liu
---
.../drm/amd/display/dc/dce/dce_clock_source.c | 127
tus update in dc_link_dp.c;
Reviewed-by: Wenjing Liu
Acked-by: Alan Liu
Signed-off-by: Leo (Hanghong) Ma
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 5 +
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 24 ++-
drivers/gpu/drm/amd/display/dc/dc_link.h | 36 +
drivers/gpu/drm/a
From: "Dhillon, Jasdeep"
[Why & How]
As part of the FPU isolation work documented in
https://patchwork.freedesktop.org/series/93042/, isolate
code that uses FPU in DCN303 to DML, where all FPU code
should locate.
Co-authored-by: Jasdeep Dhillon
Reviewed-by: Rodrigo Siqueira
Acke
.
Reviewed-by: Aric Cyr
Acked-by: Alan Liu
Signed-off-by: Wyatt Wood
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 74b05b3aef08
From: Dillon Varone
[WHY?] When adding/removng a plane to some configurations,
unsupported pipe programming can occur when moving to a new plane.
[HOW?]
Add a safe transistion state before programming new configuration.
Reviewed-by: Aric Cyr
Acked-by: Alan Liu
Signed-off-by: Dillon Varone
From: George Shen
[Why]
Unify naming for fixed VS workarounds.
[How]
Rename function to match naming convention.
Refactor code to remove unused function.
Reviewed-by: Wenjing Liu
Acked-by: Alan Liu
Signed-off-by: George Shen
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 55
From: "Charlene Liu"
[why]
Driver sends invalid deep color ratio to DMUB. Update it to the right
one by using another clock source construct.
Reviewed-by: Hansen Dsouza
Acked-by: Alan Liu
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c | 2
From: Hansen Dsouza
Fix enum mapping for deep color ratio
Reviewed-by: Charlene Liu
Acked-by: Alan Liu
Signed-off-by: Hansen Dsouza
---
.../drm/amd/display/dc/dce/dce_clock_source.c | 100 ++
.../drm/amd/display/dc/dce/dce_clock_source.h | 9 ++
.../drm/amd/display/dc
acquire
- Add minimal pipe split transition state
- Clean up fixed VS PHY test w/a function
- fix the clock source contruct for dcn315
- cleaning up smu_if to add future flexibility
- fix deep color ratio
- add debug option to bypass ssinfo from bios for dcn315
Acked-by: Alan
fine the EDID override
- [FW Promotion] Release 0.0.106.0
- Add verify_link_cap back for hdmi
Acked-by: Alan Liu
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/dri
From: Charlene Liu
[why]
hdmi specific: add verify link cap after retrive link cap.
Change-Id: Ifd7b72e4f1f4ba4501e1ca30785ce4abf3b857dc
Reviewed-by: Alvin Lee
Reviewed-by: Alvin Lee
Acked-by: Alan Liu
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3
From: Anthony Koo
Acked-by: Alan Liu
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index
From: jinzh
[Why]
We already get the SBIOS EDID via ACPI on KMD,
but after that, we just use the monitor EDID to set it HDR caps
[How]
Make the SBIOS EDID override to read_edid()
That can change the read EDID caps from the right EDID
Reviewed-by: Aric Cyr
Acked-by: Alan Liu
Signed-off
From: Robin Chen
[Why]
The deep sleep mode need to be disabled in some PSR scenario.
Reviewed-by: Anthony Koo
Acked-by: Alan Liu
Signed-off-by: Robin Chen
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b
From: "Shen, George"
[Why/How]
Refactor original w/a to unify naming and
simplify logic. This also re-enables the code
that was previously skipped due to the
disabling of the previous workaround logic.
Reviewed-by: Wenjing Liu
Reviewed-by: Nevenko Stupar
Acked-by: Alan Liu
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