From: Roman Li
[Why]
The break in apply_ctx_interdependent_lock() may potentially
lead to early break from the loop leaving update plane unlocked
[How]
Remove break
Signed-off-by: Roman Li
Reviewed-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 1 -
1 file changed, 1
From: Hersen Wu
[Why] old panel has been enabled for window driver but not linux.
[How] enable oled panel support for linux. this patch is dc part.
Signed-off-by: Hersen Wu
Reviewed-by: Harry Wentland
Reviewed-by: Hersen Wu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc
From: Joseph Gravenor
[why/how]
We found out that the register we read actually gets reset by SMU
after we loose power, meaning this always returns true
Signed-off-by: Joseph Gravenor
Reviewed-by: Eric Yang
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6
From: Yongqiang Sun
[Why]
Underflow is observed when plug in a 4K@60 monitor with
1366x768 eDP due to DPPCLK is too low.
[How]
Limit minimum DPPCLK to 100MHz.
Signed-off-by: Yongqiang Sun
Reviewed-by: Eric Yang
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21
creating resources.
Signed-off-by: Isabel Zhang
Reviewed-by: Eric Yang
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
b/drivers/gpu/drm/amd
From: Eric Bernstein
[Why]
Diagnostics team reported various issues found when enabling warnings as errors
[How]
Fix implicit conversions
Signed-off-by: Eric Bernstein
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2
fer header no longer exists in the DMUB service.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Hersen Wu
Acked-by: Bhawanpreet Lakha
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 61 +++
1 file changed, 61 insertions(+)
diff --git a/drivers/gpu/drm/amd/display
we don't check for 0, which is uninitialzed HW
default. since 0 is smaller than any value we need to program,
driver end up with not programming these registers
Signed-off-by: Tony Cheng
Reviewed-by: Yongqiang Sun
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
From: Anthony Koo
[Why]
Screen flickering when HDR switches between FP16 and ARGB2101010
[How]
Moved pipe_control_lock so stream update and plane update occur atomically
Signed-off-by: Anthony Koo
Signed-off-by: Lucy Li
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm
From: Anthony Koo
[Why]
DSC updates only set type to FULL UPDATE, but doesn't
flag the change
[How]
Add DSC flag update flag
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 19 ---
drivers/gpu/drm
From: Sung Lee
[WHY & HOW]
Previously drain clk was unconstrained and fill clk was constrained on fclk.
We want to change it to fill clk unconstrained and drain clock constrained
to dcfclk.
Signed-off-by: Sung Lee
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/dis
From: Charlene Liu
[why]
new HW engine mapping requirment use in PSP
[how]
report stream_enc_inst
Signed-off-by: Charlene Liu
Reviewed-by: Wenjing Liu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 ++-
drivers/gpu/drm/amd/display/dc/core
and the data register to correctly format
the commands.
Add the interface functions to dmub_srv for sending and receiving the
commands.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dmub/inc/dmub_gpint_cmd.h | 68
cked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 5 ++---
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 2 ++
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
b/drivers/gpu
Summary Of Changes
*DMCUB changes
*psr frame calculation fix
*fix compile warnings
*refactor front end programing
*enable OLED support in DC
Anthony Koo (3):
drm/amd/display: Split program front end part that occur outside lock
drm/amd/display: Indicate dsc updates explicitly
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index c489a863f108
and struct dc_init_data.mask to uint64_t.
Signed-off-by: David Galiffi
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index d00b72df469a
From: Anthony Koo
[Why]
Eventually want to lock at a higher level in stack.
To do this, we need to be able to isolate the parts that need to be done
after pipe unlock.
[How]
Split out programming that is done post unlock.
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet
-by: Eric Yang
Signed-off-by: Sung Lee
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 165 +-
.../amd/display/dc/dml/display_mode_structs.h | 3 +-
2 files changed, 127 insertions(+), 41 deletions(-)
diff --git a/drivers
From: Peikang Zhang
Description for DCHUBBUB_TEST_DEBUG_DATA is changed to avoid any future
confusions.
Signed-off-by: Peikang Zhang
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn10/dcn10_hubbub.c | 63 +--
1 file changed, 3 insertions
-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index cfbbaffa8654..a444fed94184 100644
-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7f6d3b0f9efc..6786d34f7d04 100644
--- a/drivers
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c| 4
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dmub/inc/dmub_gpint_cmd.h | 6
.../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 36 +++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_gpint_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc
-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 20 ++
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 27 ---
2 files changed, 20 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core
From: George Shen
[Why]
The call to dp_enable_link_phy are using default/invalid values for clock id
and link settings.
[How]
Move workaround code to after its parameter variables are determined.
Signed-off-by: George Shen
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm
From: Aric Cyr
[Why]
After locking refactor GSL is not acquired properly
resulting in immediate flip issues.
[How]
Do not copy old GSL state anymore since GSL is acquired
earlier now.
Signed-off-by: Aric Cyr
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index e8d126890d7e..d00b72df469a
From: Peikang Zhang
[Why]
int i can go out of boundary which will cause crash
[How]
Fixed the maximum value of i to avoid i going out of boundary
Signed-off-by: Peikang Zhang
Reviewed-by: Jun Lei
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c | 2 +-
1
From: Wyatt Wood
[Why]
Must know psr version during runtime.
[How]
Add set psr version message structures.
Signed-off-by: Wyatt Wood
Reviewed-by: Nicholas Kazlauskas
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +-
drivers/gpu/drm/amd/display/dc/dce
about sysfs file handling in the code
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Rodrigo Siqueira
---
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 179 +-
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.h| 6 +
2 files changed, 183 insertions(+), 2 deletions(-)
diff --git a/d
[Why]
We need this to create sysfs (followup patch)
[How]
Change the parameter
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 4 ++--
drivers/gpu/drm/amd
[Why]
we need to load SRM before we start HDCP. Because for S3 case the sysfs call
will be
after we have already enabled HDCP, so we might not be using the latest SRM
[How]
Set srm before starting HDCP.
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd
This is just a reference for the patches. not to be merged
Signed-off-by: Bhawanpreet Lakha
---
REFERENCE | 49 +
1 file changed, 49 insertions(+)
create mode 100644 REFERENCE
diff --git a/REFERENCE b/REFERENCE
new file mode 100644
index
the
interface provided by PSP
[How]
Add the interface to the header file, so the driver can use them
v2: update commit description
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Rodrigo Siqueira
---
.../drm/amd/display/modules/hdcp/hdcp_psp.h | 26 ++-
1 file changed, 25 insertions
Call the cmd ids for set/get srm according to the sysfs call
v2: Use define for the magic number
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Rodrigo Siqueira
---
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 50 ++-
1 file changed, 49 insertions(+), 1 deletion(-)
diff
Bhawanpreet Lakha (6):
drm/amd/display: Pass amdgpu_device instead of psp_context
drm/amd/display: update psp interface header
drm/amd/display: Add sysfs interface for set/get srm
drm/amd/display: Load srm before enabling HDCP
drm/amd/display: call psp set/get interfaces
drm/amd/display
On 2020-01-22 11:23 a.m., Alex Deucher wrote:
On Wed, Jan 22, 2020 at 11:12 AM Harry Wentland wrote:
On 2020-01-16 3:29 p.m., Bhawanpreet Lakha wrote:
These patches adds support for SRM loading. By providing an interface to the
usermode
SRM has to be persistent and since the kernel cannot
On 2020-01-17 2:23 p.m., Alex Deucher wrote:
On Thu, Jan 16, 2020 at 3:30 PM Bhawanpreet Lakha
wrote:
[Why]
We need to set/get SRM and linux kernel is not suppose to write to the
storage, so we need to provide a interface.
[How]
Provide interface so usermode can set/get srm
Signed-off
[Why]
We need to set/get SRM and linux kernel is not suppose to write to the
storage, so we need to provide a interface.
[How]
Provide interface so usermode can set/get srm
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Rodrigo Siqueira
---
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 124
[Why]
We need to support SRM
[How]
Add the interface to the header file
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Rodrigo Siqueira
---
.../drm/amd/display/modules/hdcp/hdcp_psp.h | 26 ++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd
[Why]
We need this to create sysfs (followup patch)
[How]
Change the parameter
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 4 ++--
drivers/gpu/drm/amd
These patches adds support for SRM loading. By providing an interface to the
usermode
SRM has to be persistent and since the kernel cannot directly write to system
storage we need to provide an interface so that the usermode can do it for us
Bhawanpreet Lakha (5):
drm/amd/display: Pass
[Why]
we need to load SRM before we start HDCP. For S3 case the sysfs call will be
after we already enabled HDCP
[How]
Set srm before starting HDCP
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 7 +++
1 file
Call the cmd ids for set/get srm according to the sysfs call
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Rodrigo Siqueira
---
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 49 ++-
1 file changed, 48 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display
the module has x display cached(SW).
If we try to enable HDCP, psp verification will fail because we are reporting x
displays while the HW only has x-1 display enabled
[How]
Check the callback for when we disable stream and call remove display.
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Rodrigo
routine.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
b/drivers/gpu/drm/amd/display/dmub/src
From: Brandon Syu
[Why]
Hardcoded fixed values are not proper.
[How]
Use enum values instead of fixed numbers.
Signed-off-by: Brandon Syu
Reviewed-by: Eric Yang
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 12 ++--
1 file changed, 6 insertions
From: Anthony Koo
[Why]
It has duplicate code for building regamma curve
[How]
Remove the duplicate code and use the same function for building regamma
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Reviewed-by: Krunoslav Kovac
Acked-by: Bhawanpreet Lakha
---
.../amd/display/modules
From: Wenjing Liu
[why]
FMT has limitation to support YCbCr420 with h_active greater than 4096.
[how]
Use odm combine to overcome the limitation.
Signed-off-by: Wenjing Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
.../dc/dml/dcn20/display_mode_vba_20.c| 19
command table offloading during first dc hardware init.
[How]
Read from the DCN registers. VBIOS already filled these in for us.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Wesley Chalmers
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dmub/inc/dmub_srv.h | 2 ++
.../gpu/drm/amd
From: Nicholas Kazlauskas
[Why]
These logically make sense more to be set after the DMCUB has been
reset rather than when we setup the inbox.
[How]
Move them into the reset callback.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm
-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 3bb1b481451b..a53e8fed56f3 100644
--- a/drivers
-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 260c0b62d37d..a50768a7ba68 100644
reference frequency at
set_speed functiton.
Signed-off-by: Lewis Huang
Reviewed-by: Jun Lei
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 68 ++-
1 file changed, 19 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 7d31dcb9e37f
scaling/color data.
[How]
Use arrays for plane properties.
Bundle all properties into a single structure to simplify memory allocation.
Signed-off-by: Roman Li
Reviewed-by: Nicholas Kazlauskas
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 64
From: "Jerry (Fangzhi) Zuo"
[Why]
The types for dummyinteger1 and dummyinteger2 are unsigned
as part of the DML spec. They should not be long.
[How]
Make them unsigned int instead of long.
Signed-off-by: Jerry (Fangzhi) Zuo
Reviewed-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/
.
Signed-off-by: Wenjing Liu
Reviewed-by: Nikola Cornij
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 37 ++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display
From: Isabel Zhang
[Why]
MPO isn't enabled on some 4k videos due to video source width is 4096
and the current limit is 3840.
[How]
Changed the limit to 4096.
Signed-off-by: Isabel Zhang
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn21
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/bios/command_table2.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
index c4ba6e84db65..629a07a2719b 100644
Summary Of Changes
* Code fixes/cleanups
* i2c frequency refactor
* DMCUB changes
* Update type fix
Anthony Koo (1):
drm/amd/display: Refactor to remove diags specific rgam func
Aric Cyr (1):
drm/amd/display: 3.2.69
Brandon Syu (1):
drm/amd/display: fix rotation_angle to use enum values
Kazlauskas
Reviewed-by: Wesley Chalmers
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/bios/command_table2.c | 74 ++-
1 file changed, 70 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
b/drivers/gpu/drm/amd/display/dc/bios
Reviewed-by: Hersen Wu
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm
From: Haiyi Zhou
Switched to C-style comments for consistency
Signed-off-by: Haiyi Zhou
Reviewed-by: Reza Amini
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd
are different. Only send it on the first iteration.
Signed-off-by: Sung Lee
Reviewed-by: Tony Cheng
Acked-by: Abdoulaye Berthe
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd
From: Lewis Huang
[Why]
Driver didn't init hw i2c speed cause hdcp hw cannot
send command, because the default value of speed register
is 0x2.
[How]
Restore the default speed when release i2c engine
Signed-off-by: Lewis Huang
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers
-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h | 15 +++
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 16
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
b/drivers/gpu/drm/amd/display/dmub/inc
From: Wenjing Liu
[how]
Empty dsc enc caps when debug option is set to disable DSC.
Signed-off-by: Wenjing Liu
Reviewed-by: Nikola Cornij
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 3 ++-
2 files changed
are different. Only send it on the first iteration.
Change-Id: I5d98439de574c73c98edf21fe1741b947a365bf5
Signed-off-by: Sung Lee
Reviewed-by: Tony Cheng
Acked-by: Abdoulaye Berthe
Acked-by: Bhawanpreet Lakha
IP-reviewed-by: Yongqiang Sun
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
1
Summary Of Changes
* Code fixes/cleanups
* i2c frequency refactor
* DMCUB changes
* Update type fix
Anthony Koo (1):
drm/amd/display: Refactor to remove diags specific rgam func
Aric Cyr (1):
drm/amd/display: 3.2.69
Brandon Syu (1):
drm/amd/display: fix rotation_angle to use enum values
.
Change-Id: Ie49c1d3b1c219aaff88f8185371a252e492e1697
Signed-off-by: Wenjing Liu
Reviewed-by: Nikola Cornij
Acked-by: Bhawanpreet Lakha
IP-reviewed-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 37 ++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git
command table offloading during first dc hardware init.
[How]
Read from the DCN registers. VBIOS already filled these in for us.
Change-Id: Iea84fd8bda3bff750e6aada75175711c01c6a256
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Wesley Chalmers
Acked-by: Bhawanpreet Lakha
IP-reviewed-by: Nicholas
From: Wenjing Liu
[how]
Empty dsc enc caps when debug option is set to disable DSC.
Change-Id: I95e63c63bb0513a80144087c8327dcdcfa23c494
Signed-off-by: Wenjing Liu
Reviewed-by: Nikola Cornij
Acked-by: Bhawanpreet Lakha
IP-reviewed-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/dc.h
s.
Check RID and set max voltage level to 0 if Pollock is detected.
Work around broken ASICREV_IS_RENOIR, IS_RAVEN2, etc. checks by
performing Dali/Pollock checks before they can be misidentified as RN.
Signed-off-by: Michael Strauss
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Huang Rui
---
[Why]
We are returning incorrect error code for validate h prime
[How]
Return the right Error code
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/modules
We are returning SUCCESS when hdcp_status != Success. Fix it.
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
b/drivers/gpu/drm/amd
[Why]
PSP needs session ID to destroy a session, In the case where we fail
create session we don't have a session ID
[How]
Set the session ID before returning
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 3 ++-
1 file changed, 2 insertions(+), 1
From: Jing Zhou
[why]
Most DP/HDMI monitors need more time to response rx_validation
request.
[how]
Add generic 1000ms delay.
Signed-off-by: Jing Zhou
Reviewed-by: Wenjing Liu
---
.../display/modules/hdcp/hdcp1_transition.c | 20 +++
1 file changed, 16 insertions(+), 4
Summary of changes
*Fix return codes
*Fix some displays failing authentication
Bhawanpreet Lakha (3):
drm/amd/display: fix psp return condition for hdcp module
drm/amd/display: Fix hdcp1 create session
drm/amd/display: Return correct Error code for validate h_prime
Jing Zhou (1):
drm/amd
From: Xiaodong Yan
[Why]
Some combined docks will always trigger CP_IRQ but there's nothing the driver
needs to take care of, but the CP_IRQ breaks the original hdcp state and
triggers the driver to restart the authentication.
[How]
Add the event type check before restart the authentication or
From: Michael Strauss
[WHY]
Some monitors trigger HDCP2.x timeout after reinitializing (e.g. toggling HDR)
by taking longer than expected to return h' (h prime)
Previously the 200ms watchdog timer retry count would hit
MAX_NUM_OF_ATTEMPTS (4), causing fallback to HDCP1.x
[HOW]
Adding a 1s delay
Hey Harry can you please take a look thanks
On 2019-11-08 5:01 p.m., Deucher, Alexander wrote:
Acked-by: Alex Deucher
*From:* amd-gfx on behalf of
Bhawanpreet Lakha
*Sent:* Friday, November 8, 2019 4:57 PM
*To:* amd
ok because we only need to check
the
ENABLED->DESIRED transition if a connector exists.
Fixes :cc5dae9f6286 drm/amd/display: Refactor HDCP to handle multiple displays
per link
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 3 +++
1 file changed,
load the ta firmware for navi10/12/14.
This is already being done for raven/picasso and
is needed for supporting hdcp on navi
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu
[Why]
These defines/macros exist already no need to redefine them
[How]
Use the defines/macros from drm_hdcp.h
-we share the rxstatus between HDMI and DP (2 bytes), But upstream
defines/macros for HDMI are for 1 byte. So we need to create a separate
rxstatus for HDMI
Signed-off-by: Bhawanpreet
ead to avoid this.
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
b/drivers/gpu/drm/amd/display/modules/h
: Add HDCP module" for 2.2
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/modules/hdcp/Makefile | 3 +-
.../gpu/drm/amd/display/modules/hdcp/hdcp.c | 86 +-
.../gpu/drm/amd/display/modules/hdcp/hdcp.h | 127 +++
.../display/modules/hdcp/hdcp2_execution.c| 881 +
[Why]
Before we had a disable_type1 flag, this forced HDCP 2.2 to type0
There was no way to force type1.
[How]
Remove disable_type1 flag and instead add a flag to force type0/1.
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c| 2 +-
.../gpu/drm/amd
drm_hdcp defines for the remaining structs
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/modules/hdcp/hdcp.h | 20 ++-
.../display/modules/hdcp/hdcp2_execution.c| 35 +++
.../drm/amd/display/modules/hdcp/hdcp_ddc.c | 2 +-
3 files changed, 24 insertions
).
So this method should be good enough to report HDCP status.
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 3 +--
.../gpu/drm/amd/display/modules/hdcp/hdcp.c| 18 ++
.../gpu/drm/amd/display/modules/inc/mod_hdcp.h | 4 ++--
3 files
[Why]
We need to log the state changes for 2.2
This patch extends the existing logging functions to handle
HDCP2.2.
[How]
We do this by adding if/else in the defines, and output the log
based on the hdcp version
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/modules/hdcp/hdcp_log.c
[Why]
We need these to read and write to aux/i2c, during
authentication
[How]
Create read/write functions for all the steps
(Eg, h_prime, paring_info etc)
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/modules/hdcp/hdcp_ddc.c | 326 ++
1 file changed, 326 insertions
[Why]
drm already has this define
[How]
drm Mask is 0x08 vs 0x0800. The reason is because drm mask
works on a byte.^^
===||
||
Since the first byte is always zero we can ignore it and only check the
second byte.
Signed-off-by: Bhawanpreet Lakha
[Why]
HDCP 2.2 was disabled, we need to enable it
[How]
-Update display topology to support 2.2
-Unset hdcp2.disable in update_config
-Change logic of event_update_property, now we set the property to be
ENABLED for any level of encryption (2.2 or 1.4).
Signed-off-by: Bhawanpreet Lakha
-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 ++-
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 53 ++-
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.h| 9 ++--
3 files changed, 40 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/amd
shown in dmesg
to know what went wrong.
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
b/drivers/gpu/drm/amd/display/modules/hdcp
e property if the
requirements are met
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 ++
.../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 17 +
.../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h | 4 ++--
.../gpu/drm/amd/display/mo
drm_hdcp.h
drm/amd/display: use drm defines for MAX CASCADE MASK
drm/amd/display: split rxstatus for hdmi and dp
-fix static analysis bug
drm/amd/display: Fix static analysis bug in validate_bksv
Bhawanpreet Lakha (14):
drm/amd/display: Add PSP block to verify HDCP2.2
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