[PATCH 1/6] drm/amd/display: Tidy up dce120_timing_generator_enable_advanced_request()

Simplify the function by removing identical looking code blocks. Signed-off-by: Tom St Denis --- .../display/dc/dce120/dce120_timing_generator.c| 37 +++--- 1 file changed, 12 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce120

[PATCH 4/6] drm/amd/display: Clean up indentation in dce120_tg_set_blank()

Signed-off-by: Tom St Denis --- .../drm/amd/display/dc/dce120/dce120_timing_generator.c | 16 +--- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120

[PATCH 3/4] drm/amd/amdgpu: Cleanup uvd_v4_2_soft_reset()

Use WREG32_FIELD instead. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index cd793c262674..d4e35ff8d9cd 100644 --- a

[PATCH 2/4] drm/amd/amdgpu: Tidy up uvd_v4_2_start()

Fix indentation and use WREG32_FIELD to clean up. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 19 ++- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index

[PATCH 4/4] drm/amd/amdgpu: Use 32/64-bit types for VCE2

The uintNN_t types were already in use except for a few spots. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index

[PATCH 1/4] drm/amd/amdgpu: Use 32/64-bit types in uvd42

Swap uNN for uintNN_t. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 8ab0f78794a5..eccf4c467fe1 100644

Small cleanups for UVD42 and VCE2

Rounding off the SI cleanups for now are small NFC edits to the uvd42 and vce2 drivers. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/2] drm/amd/amdgpu: Use 32/64-bit types in gmc6

On 16/05/17 06:51 AM, Christian König wrote: Am 15.05.2017 um 20:25 schrieb Tom St Denis: Swap uNN for uintNN_t. Signed-off-by: Tom St Denis Acked-by: Christian König Do we actually do something else than busy waiting for idle in one of the modules in the wait_for_idle callback? If no

[PATCH 2/2] drm/amd/amdgpu: Clean up gmc6 wait_for_idle

Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 81f5aa9ff719..27db0710e9ab 100644 --- a/drivers/gpu/drm/amd/amdgpu

[PATCH 1/2] drm/amd/amdgpu: Use 32/64-bit types in gmc6

Swap uNN for uintNN_t. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 62 +-- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index

[PATCH 1/2] drm/amd/amdgpu: Clean up 32/64-bit types in DCE6

Replace uNN with uintNN_t types. In various places uintNN_t was already used. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 204 +- 1 file changed, 102 insertions(+), 102 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

[PATCH 2/2] drm/amd/amdgpu: Tidy up static int dce_v6_0_get_num_crtc()

Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 11 +++ 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 1b6b9b22d780..ec7f7bb77f50 100644 --- a/drivers/gpu/drm/amd

Couple of cleanups for DCE6

Swap in uintNN_t types and a small clean up. Should be no functional changes. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH umr] Make error/bug messages have a more consistent presentation

Signed-off-by: Tom St Denis --- src/app/enum.c | 2 +- src/app/scan.c | 2 +- src/app/scan_log.c | 2 +- src/app/set_bit.c | 4 ++-- src/app/set_reg.c | 4 ++-- src/app/top.c | 2 +- src/lib/create_mmio_accel.c | 2

[PATCH 3/5] drm/amd/amdgpu: Tidy up of gfx_v6_0_setup_rb()

Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index b7a70551d49f..2463fcae35a7 100644 --- a/drivers/gpu/drm/amd

Small cleanups for gfx6

Various cleanups to coding style for gfx6. Should be no functional changes. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/5] drm/amd/amdgpu: gfx6 tidy up raster config

Clean up coding style in gfx_v6_0_write_harvested_raster_configs() Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 20 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu

[PATCH 5/5] drm/amd/amdgpu: Use modern 32/64-bit types in gfx6

Switch to uintNN_t from "uNN" types to be more consistent with modern coding styles. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 150 +- 1 file changed, 75 insertions(+), 75 deletions(-) diff --git a/drivers/gpu/drm/

[PATCH 1/5] drm/amd/amdgpu: Clean up GFX6 tilemode programming

Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 1556 ++--- 1 file changed, 676 insertions(+), 880 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 5d9e95bcd011..36a70e93b293 100644

[PATCH 4/5] drm/amd/amdgpu: Drop commented out stub function

Drop the function gmc_v6_0_init_compute_vmid() since it wasn't implemented and commented out. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/a

[PATCH umr] Add raven family to GFX sensors

Signed-off-by: Tom St Denis --- src/app/top.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/app/top.c b/src/app/top.c index a4d3aa8e699d..09ab5f40de0b 100644 --- a/src/app/top.c +++ b/src/app/top.c @@ -813,8 +813,8 @@ static void top_build_vi_program(struct umr_asic

Re: [PATCH 0/5] GFX9 KIQ

On 11/05/17 07:33 PM, Tom St Denis wrote: On 11/05/17 02:35 PM, Alex Deucher wrote: These are the laste of the gfx9 KIQ patches that haven't landed yet. Can someone with gfx9 capable hw test this (vega10 or raven)? This is needed to enable powergating on gfx9. Thanks, If nobody gets

Re: [PATCH 0/5] GFX9 KIQ

On 11/05/17 02:35 PM, Alex Deucher wrote: These are the laste of the gfx9 KIQ patches that haven't landed yet. Can someone with gfx9 capable hw test this (vega10 or raven)? This is needed to enable powergating on gfx9. Thanks, If nobody gets to it by morning I'll try it out first thing on my

Raven support added to umr

Hi all, I've pushed out a large commit which adds raven support to umr. Since it's quite large I've bypassed the list. The commit can be seen here: https://cgit.freedesktop.org/amd/umr/commit/?id=6acc89e4ec159de470af1ec1b9f53d4e97c562bb Cheers, Tom __

[PATCH umr] add new vega10 DIDs

--- src/lib/discover_by_did.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/lib/discover_by_did.c b/src/lib/discover_by_did.c index 2e06d5092847..7ecd7f353c92 100644 --- a/src/lib/discover_by_did.c +++ b/src/lib/discover_by_did.c @@ -221,7 +221,9 @@ static const struct { { 0x68

[PATCH] drm/amd/amdgpu: Find correct min clocks for vega10

Fixes: 1fe8f78d00589904b830a0ebd092c7810f625f00 Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay

[PATCH umr] Add 'no_kernel' option

MMIO registers (with bank selection) - reading wave status and SGPR registers Signed-off-by: Tom St Denis --- doc/umr.1 | 5 +++ src/app/main.c| 5 ++- src/app/scan.c| 6 +++- src/app/set_bit.c | 4 +++ src/app/set_reg.c | 4 +++ src/lib/discover.c

[PATCH umr] Avoid opening the DRM file by default

Opening the DRM file (/dev/dri/card%d) triggers all sorts of KMD work to happen which is not useful if the KMD is hung or not working. Since --top is the only user of the file currently we simply defer opening it until --top is invoked. Signed-off-by: Tom St Denis --- src/app/top.c | 7

Re: [PATCH] drm/amd/amdgpu: Print out ring name in dev_info

On 19/04/17 11:07 AM, Christian König wrote: Am 19.04.2017 um 17:03 schrieb Tom St Denis: So it's more obvious which rings are using which INV engines. Signed-off-by: Tom St Denis I wonder if we shouldn't stop printing the ring numbers completely in the ring and IB tests as well

[PATCH] drm/amd/amdgpu: Print out ring name in dev_info

So it's more obvious which rings are using which INV engines. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

[PATCH 1/2] drm/amd/amdgpu: Change comp GFXv6 ring name to remove space

umr expects the ring name to be a complete word. This also makes it consistent with GFXv7/8. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd

[PATCH 2/2] drm/amd/amdgpu: Change comp GFXv9 ring name to remove space

umr expects the ring name to be a complete word. This also makes it consistent with GFXv7/8. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd

Re: [PATCH 12/12] drm/amdgpu/gfx9: Switch baremetal to use KIQ for compute ring management. (v3)

On 18/04/17 01:00 PM, Andres Rodriguez wrote: +static int gfx_v9_0_kiq_kcq_disable(struct amdgpu_device *adev) +{ +struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; +uint32_t scratch, tmp = 0; +int r, i; + +r = amdgpu_gfx_scratch_get(adev, &scratch); +if (r) { +DRM_

[PATCH umr] Add support for decoding PKT3_COND_EXEC

Signed-off-by: Tom St Denis --- src/lib/ring_decode.c | 13 + 1 file changed, 13 insertions(+) diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c index 372bb43595b8..48d840643bf9 100644 --- a/src/lib/ring_decode.c +++ b/src/lib/ring_decode.c @@ -379,6 +379,19 @@ static void

Re: [PATCH umr] page_table_base_addr is not a page address on AI+

On 18/04/17 07:32 AM, Tom St Denis wrote: With that fixed I can read (non-cached) IBs from the libdrm test suite. Signed-off-by: Tom St Denis + pde_fields.pte_base_addr = (pde_entry & ((1ULL << 48) - 1)) & ~0xFFFULL; //pde_entry & 0xFF

[PATCH umr] page_table_base_addr is not a page address on AI+

With that fixed I can read (non-cached) IBs from the libdrm test suite. Signed-off-by: Tom St Denis --- src/lib/read_vram.c | 47 --- 1 file changed, 32 insertions(+), 15 deletions(-) diff --git a/src/lib/read_vram.c b/src/lib/read_vram.c index

[PATCH umr] Fix AI multiple level VM decoding

Obvious off by 1 also incorrect page table indecies. Also added a lot more debugging output which is off by default. Signed-off-by: Tom St Denis --- src/lib/read_vram.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/lib/read_vram.c b/src/lib

[PATCH umr] Add new AI+ field to RELEASE_MEM decoding

As well as add EVENT type decoding to human readable string. Signed-off-by: Tom St Denis --- src/lib/ring_decode.c | 66 --- 1 file changed, 63 insertions(+), 3 deletions(-) diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c index

Re: [PATCH] drm/amdgpu: Add kernel parameter to manage memory error handling.

On 13/04/17 11:38 AM, Panariti, David wrote: + Vilas -Original Message- From: Deucher, Alexander Sent: Wednesday, April 12, 2017 9:29 PM To: 'Michel Dänzer' ; Panariti, David Cc: amd-gfx@lists.freedesktop.org Subject: RE: [PATCH] drm/amdgpu: Add kernel parameter to manage memory error

[PATCH umr] Prevent reading sensors far too quickly.

On platforms without GPU_POWER sensors the thread reading sensors would proceed far too quickly. So it is now rate limited to 50Hz to be consistent. Signed-off-by: Tom St Denis --- src/app/top.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/app/top.c b

[PATCH umr] Add the ability to update the register/bitfield database at runtime. (v2)

other options/instance commands. It will ignore any updates for asics that aren't currently being used so you can specify multiple asic updates in a single file. Signed-off-by: Tom St Denis (v2): Considerable tidy up of code + add deletion support --- src/app/main.c

[PATCH umr] Add the ability to update the register/bitfield database at runtime.

ter any other options/instance commands. It will ignore any updates for asics that aren't currently being used so you can specify multiple asic updates in a single file. Signed-off-by: Tom St Denis --- src/app/main.c | 10 ++ src/lib/CMakeLists.txt | 1 + src/lib/update.c |

Port various SOC15 drivers over to new macros

This series ports a variety of vega10 drivers over to the new SOC15 macros and introduces a pair of OFFSET ready macros to help with MC related code. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/a

[PATCH 10/10] drm/amd/amdgpu: Port PSP v3.1 over to new SOC15 macros

Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 34 +- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index d351583785e5..34dbb60da752 100644

[PATCH 04/10] drm/amd/amdgpu: Port MMHUB over to new SOC15 macros

No functional changes. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 201 1 file changed, 100 insertions(+), 101 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index

[PATCH 06/10] drm/amd/amdgpu: Port VCE 4.0 over to new SOC15 macros

Note this commit also fixes a few typos in the commented out portions which were missing closing parenthesis on the original coding style. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 176 +- 1 file changed, 88 insertions(+), 88

[PATCH 03/10] drm/amd/amdgpu: Cleanup gfxhub read-modify-write patterns

Swap a couple of read/set/write patterns for WREG32_FIELD15. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu

[PATCH 05/10] drm/amd/amdgpu: Cleanup mmhub read-modify-write patterns

Change read/set/write patterns into WREG32_FIELD15 calls. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 11 +++ 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

[PATCH 01/10] drm/amd/amdgpu: Add offset variant to SOC15 macros

Allows reading/writing via SOC15 macros with offset for various register banks. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/soc15_common.h | 14 ++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu

[PATCH 02/10] drm/amd/amdgpu: Port GFXHUB over to new SOC15 macros

No functional changes in this patch. Simply re-writing read/writes into new macros. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 182 +++ 1 file changed, 91 insertions(+), 91 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu

[PATCH 09/10] drm/amd/amdgpu: Port NBIO v6.1 driver over to new SOC15 macros

Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 44 ++ 1 file changed, 18 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c index 97057f4a10de..57dd6aae4961 100644

[PATCH 08/10] drm/amd/amdgpu: Port GMC v9.0 driver to new SOC15 macros

As well swap a read/set/write pattern over to WREG32_FIELD15. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 11 --- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

[PATCH 07/10] drm/amd/amdgpu: Port UVD 7.0 over to new SOC15 macros

This patch also fixes some bugs in commented out code where parenthesis were missing on various SOC15 macros. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 206 +- 1 file changed, 103 insertions(+), 103 deletions(-) diff --git a/drivers

Re: [PATCH 2/2] drm/amd/amdgpu: Port gfx9 driver over to new read/write macros

On 07/04/17 08:05 AM, Christian König wrote: Am 07.04.2017 um 13:55 schrieb Tom St Denis: Signed-off-by: Tom St Denis Acked-by: Christian König . If I could get a RB by someone I could get going on the rest of the AI+ code. Tom --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 406

Re: [PATCH] drm/radeon: Make CIK support in Radeon conditional

On 07/04/17 12:01 PM, Felix Kuehling wrote: Advertise CIK PCI IDs only when they are not supported by amdgpu. Use the CONFIG_DRM_AMDGPU_CIK to check so that a single option in the kernel config keeps both drivers in sync. This is the simplest possible change. A more complete solution may want to

[PATCH 1/2] drm/amd/amdgpu: Introduce new read/write macros for SOC15

Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 --- drivers/gpu/drm/amd/amdgpu/soc15_common.h | 20 +++- 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h

[PATCH 2/2] drm/amd/amdgpu: Port gfx9 driver over to new read/write macros

Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 406 +- 1 file changed, 203 insertions(+), 203 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index cb6c7eb8a87e..d5492629d49a 100644

[PATCH] drm/amd/amdgpu: Clean up SOC15 addressing (v2)

Replace verbose SOC15 macros with simpler RREG32/WREG32_SOC15 macros to make the code a lot easier to read (and write). Signed-off-by: Tom St Denis v2: Moved SOC15 macros to soc15_common.h and removed VA_ARGS from RREG32_SOC15(). --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3

[PATCH umr] Add AI sensors to --top

Signed-off-by: Tom St Denis --- src/app/top.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/src/app/top.c b/src/app/top.c index b8a91e317ba5..96e33ff2e1da 100644 --- a/src/app/top.c +++ b/src/app/top.c @@ -252,6 +252,15 @@ static struct umr_bitfield

Re: [PATCH umr] Add initial AI VM decoding

ess >> (page_table_depth*9 + (12 + page_table_size - 4))); Would result in a 9-bit page size if say page_table_size was 1 which should actually be 13 bits (8KB). Tom On 06/04/17 02:14 PM, Tom St Denis wrote: On 06/04/17 02:11 PM, Deucher, Alexander wrote: -Original Message- From

Re: [PATCH umr] Add initial AI VM decoding

On 06/04/17 02:11 PM, Deucher, Alexander wrote: -Original Message- From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Tom St Denis Sent: Thursday, April 06, 2017 1:53 PM To: amd-gfx@lists.freedesktop.org Cc: StDenis, Tom Subject: [PATCH umr] Add initial AI VM

[PATCH umr] Add initial AI VM decoding

Tested with VMID0 decodings just fine. Haven't tried VMID1-15 yet. Signed-off-by: Tom St Denis --- src/lib/read_vram.c | 180 ++-- 1 file changed, 176 insertions(+), 4 deletions(-) diff --git a/src/lib/read_vram.c b/src/lib/read_vram.c

Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"

> To: Alex Deucher > Cc: Andres Rodriguez; Deucher, Alexander; Tom St Denis; amd- > g...@lists.freedesktop.org <mailto:g...@lists.freedesktop.org> > Subject: Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet" > > On 05/04/17 09:

Re: [PATCH 01/10] drm/amd/amdgpu: cleanup gfx_v9_0_init_queue()

On 05/04/17 10:15 AM, Christian König wrote: Am 05.04.2017 um 15:26 schrieb Tom St Denis: Introduce WREG32_FIELD15 macro for SOC15 architectures. Signed-off-by: Tom St Denis Reviewed-by: Christian König For the series or just 1/10? Tom --- drivers/gpu/drm/amd/amdgpu/amdgpu.h

[PATCH 02/10] drm/amd/amdgpu: cleanup gfx_v9_0_set_priv_inst_fault_state()

Use new WREG32_FIELD15 macro. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 +++ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 3888743bc868

[PATCH 04/10] drm/amd/amdgpu: cleanup gfx_v9_0_set_gfx_eop_interrupt_state()

Use new WREG32_FIELD15 macro. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 +++ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 257d0d320f54

[PATCH 08/10] drm/amd/amdgpu: cleanup gfx_v9_0_rlc_start()

Use new WREG32_FIELD15 macro Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 6bc9856e67a7..80700356474c 100644 --- a

[PATCH 10/10] drm/amd/amdgpu: cleanup gfx_v9_0_gpu_init()

Use new WREG32_FIELD15 macro Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 2dd32466919d..33df0dbe7052 100644 --- a

[PATCH 06/10] drm/amd/amdgpu: cleanup gfx_v9_0_kiq_init_register()

Use new WREG32_FIELD macro Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 +++- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ebd35af7f400..49527c0c2696

[PATCH 01/10] drm/amd/amdgpu: cleanup gfx_v9_0_init_queue()

Introduce WREG32_FIELD15 macro for SOC15 architectures. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 +++ 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b

[PATCH 03/10] drm/amd/amdgpu: cleanup gfx_v9_0_set_priv_reg_fault_state()

Use new WREG32_FIELD15 macro. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 14 +++--- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 714fd0f228cf..257d0d320f54

[PATCH 07/10] drm/amd/amdgpu: simplify gfx_v9_0_cp_gfx_enable()

Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 49527c0c2696..6bc9856e67a7 100644 --- a/drivers/gpu/drm/amd

[PATCH 05/10] drm/amd/amdgpu: Drop gfx_v9_0_print_status()

It's not used in gfx 6/7/8 so drop it from gfx 9 as well. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 175 +- 1 file changed, 1 insertion(+), 174 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/dr

[PATCH 09/10] drm/amd/amdgpu: cleanup gfx_v9_0_rlc_reset()

Use new WREG32_FIELD15 macro Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 80700356474c..2dd32466919d 100644

Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"

On 05/04/17 09:06 AM, Alex Deucher wrote: On Wed, Apr 5, 2017 at 7:30 AM, Tom St Denis wrote: My firmware is fw.VCE == .feature==0 .firmware==0x34040300 fw.UVD == .feature==0 .firmware==0x015b0b00 fw.MC == .feature==0 .firmware==0x fw.ME == .feature==46

Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"

wrote: -Original Message- From: Andres Rodriguez [mailto:andre...@gmail.com] Sent: Tuesday, April 04, 2017 4:01 PM To: Tom St Denis; Deucher, Alexander; StDenis, Tom; amd- g...@lists.freedesktop.org Subject: Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet" This is my info

Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"

n Behalf > > Of Andres Rodriguez > > Sent: Tuesday, April 04, 2017 3:39 PM > > To: StDenis, Tom; amd-gfx@lists.freedesktop.org > > Subject: Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet" > > > > > > > > On 2017-04-04 08:27

[PATCH 1/2] drm/amd/amdgpu: Fix psp_v3_1 compare sram

Had the wrong sense in the loop Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index 5191c45ffdf3..0900fdf0651b 100644 --- a

[PATCH 2/2] drm/amd/amdgpu: Clean up psp reload_quirk()

Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index 0900fdf0651b..c3588d1c7cb0 100644 --- a/drivers/gpu/drm/amd

[PATCH] drm/amd/amdgpu: Fix srbm_indexing in init/inactive hqd code

Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 5a8e8aea99b9..3571c4895120 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b

[PATCH 1/5] drm/amd/amdgpu: Clean up gfx_v8_0_kiq_set_interrupt_state()

Use new WREG32_FIELD_OFFSET() to clean up code. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 40 +++ 2 files changed, 15 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd

[PATCH 5/5] drm/amd/amdgpu: Clean up gfx_v8_0_mqd_init()

Clean up a toggle with ?:. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 46e2367405de..5a8e8aea99b9

[PATCH 3/5] drm/amd/amdgpu: clean up gfx_v8_0_kiq_init_register()

Swap read/write pattern for WREG32_FIELD() Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 12 +++- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 3c43c10d0ada

[PATCH 4/5] drm/amd/amdgpu: de-numberify HQD_ACTIVE check.

Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index d09d69b0d096..46e2367405de 100644 --- a/drivers/gpu/drm/amd/amdgpu

[PATCH 2/5] drm/amd/amdgpu: Clean up gfx_v8_0_inactive_hqd()

Swap read/write pattern for WREG32_FIELD() Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 595dc14019dd

Re: [RFC] Revert "drm/amdgpu/gfx8: Fix SET_RESOURCES packet"

On 03/04/17 04:25 PM, Andres Rodriguez wrote: Commit e579f56 results in a KCQ initialization error for polaris10 cards. Providing the full SET_RESOURCES packet instead of the truncated version fixes the problem. I think this patch may have been one of the stabs at fixing the KCQ suspend/resume e

Re: [PATCH] drm/amd/amdgpu: Correct ring wptr address in debugfs

On 29/03/17 01:46 PM, Christian König wrote: Am 29.03.2017 um 19:44 schrieb Tom St Denis: On 29/03/17 01:41 PM, Christian König wrote: Am 29.03.2017 um 19:07 schrieb Tom St Denis: On 29/03/17 01:07 PM, Tom St Denis wrote: On gfx9 hardware the value is not wrapped and is a 64-bit value. So

[PATCH] drm/amd/amdgpu: Correct ring wptr address in debugfs (v2)

On gfx9 hardware the value is not wrapped and is a 64-bit value. So we reduce it modulo the ring size. Signed-off-by: Tom St Denis (v2) use buf_mask instead of computing on the fly --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff

Re: [PATCH] drm/amd/amdgpu: Correct ring wptr address in debugfs

On 29/03/17 01:41 PM, Christian König wrote: Am 29.03.2017 um 19:07 schrieb Tom St Denis: On 29/03/17 01:07 PM, Tom St Denis wrote: On gfx9 hardware the value is not wrapped and is a 64-bit value. So we reduce it modulo the ring size. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd

Re: [PATCH] drm/amd/amdgpu: Correct ring wptr address in debugfs

On 29/03/17 01:07 PM, Tom St Denis wrote: On gfx9 hardware the value is not wrapped and is a 64-bit value. So we reduce it modulo the ring size. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a

[PATCH] drm/amd/amdgpu: Correct ring wptr address in debugfs

On gfx9 hardware the value is not wrapped and is a 64-bit value. So we reduce it modulo the ring size. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b

Re: [PATCH] drm/amdgpu: just disallow reading untouched registers

On 29/03/17 08:18 AM, Christian König wrote: Ping! Does anybody of you guys know what the background of those "untouched" registers is? That we leak uninitialized memory to userspace is a bit bad. I don't know the history but wouldn't reading these just read the MMIO registers? Or these are

Re: [PATCH umr] read all sensors in a thread

On 27/03/17 09:41 AM, Tom St Denis wrote: Eventually the GPU_POWER sensor will be rated at around 50Hz but that's still too slow to read from the main loop of umr's --top so we move all sensor operations to a thread. Signed-off-by: Tom St Denis --- src/app/t

[PATCH umr] read all sensors in a thread

Eventually the GPU_POWER sensor will be rated at around 50Hz but that's still too slow to read from the main loop of umr's --top so we move all sensor operations to a thread. Signed-off-by: Tom St Denis --- src/app/top.c | 110 +---

[PATCH umr] Add family text for family 141

Signed-off-by: Tom St Denis --- src/app/print_config.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/app/print_config.c b/src/app/print_config.c index 6dbe0d42b8dc..e295302ab7a3 100644 --- a/src/app/print_config.c +++ b/src/app/print_config.c @@ -91,6 +91,7 @@ static const struct

[PATCH umr] Add new AI CG bits to umr_print_config()

Signed-off-by: Tom St Denis --- src/app/print_config.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/app/print_config.c b/src/app/print_config.c index 6a4bf5dd594a..6dbe0d42b8dc 100644 --- a/src/app/print_config.c +++ b/src/app/print_config.c @@ -54,6 +54,12 @@ M

Re: amd-iommu: can't boot with amdgpu, AMD-Vi: Completion-Wait loop timed out

On 22/03/17 07:22 AM, 'j...@8bytes.org' wrote: On Tue, Mar 21, 2017 at 04:30:55PM +, Deucher, Alexander wrote: I am preparing a debug-patch that disables ATS for these GPUs so someone with such a chip can test it. Thanks Joerg. Here is a debug patch, using the hard hammer of disabling th

Re: amd-iommu: can't boot with amdgpu, AMD-Vi: Completion-Wait loop timed out

On 22/03/17 01:18 PM, Tom St Denis wrote: I tried this out but still got a lockup during init. I tried getting a dmesg log but it locked up before it outputted anything more (after the init). nvm. Even with iommu disabled it fails to boot. Stoney support dies occasionally on staging-4.9

Re: amd-iommu: can't boot with amdgpu, AMD-Vi: Completion-Wait loop timed out

On 21/03/17 12:25 PM, 'j...@8bytes.org' wrote: On Tue, Mar 21, 2017 at 04:17:40PM +, Deucher, Alexander wrote: -Original Message- From: 'j...@8bytes.org' [mailto:j...@8bytes.org] Sent: Tuesday, March 21, 2017 12:11 PM To: Deucher, Alexander Cc: Alex Deucher; Daniel Drake; Chris Chiu;

[PATCH umr] Try /dev/fmem first when reading system memory

On many platforms /dev/mem is restricted to PCI I/O space only. The /dev/fmem device driver can be found on github and it allows unrestricted access to physical memory. Signed-off-by: Tom St Denis --- src/lib/read_vram.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a

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