On 06/27/2018 02:10 PM, Flora Cui wrote:
Change-Id: Ic0dbd693bac093e54eb95b5e547c89b64a5743b8
Signed-off-by: Flora Cui
Good catch.
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdg
On 06/26/2018 11:53 PM, Felix Kuehling wrote:
Comments inline [FK]
On 2018-06-26 04:35 AM, Junwei Zhang wrote:
Instead of calling gart memory on every bo pin,
allocates it on demand
v2: fix error handling
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c|
On 06/26/2018 04:35 PM, Michel Dänzer wrote:
On 2018-06-26 10:28 AM, Zhang, Jerry (Junwei) wrote:
On 06/26/2018 03:46 PM, Michel Dänzer wrote:
On 2018-06-26 08:00 AM, Junwei Zhang wrote:
It could be got by amdgpu_bo_gpu_offset() if need
Signed-off-by: Junwei Zhang
[...]
@@ -931,7 +928,6
On 06/26/2018 03:42 PM, Michel Dänzer wrote:
On 2018-06-26 08:00 AM, Junwei Zhang wrote:
Instead of calling gart memory on every bo pin,
allocates it on demand
Signed-off-by: Junwei Zhang
[...]
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_disp
On 06/26/2018 03:46 PM, Michel Dänzer wrote:
On 2018-06-26 08:00 AM, Junwei Zhang wrote:
It could be got by amdgpu_bo_gpu_offset() if need
Signed-off-by: Junwei Zhang
[...]
@@ -931,7 +928,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32
domain,
* amdgpu_bo_pin - pin an &amdgpu
On 06/25/2018 05:07 PM, Michel Dänzer wrote:
From: Michel Dänzer
Without this, there could not be enough slots, which could trigger the
BUG_ON in reservation_object_add_shared_fence.
v2:
* Jump to the error label instead of returning directly (Jerry Zhang)
Cc: sta...@vger.kernel.org
Bugzilla:
On 06/23/2018 12:42 AM, Michel Dänzer wrote:
From: Michel Dänzer
Without this, there could not be enough slots, which could trigger the
BUG_ON in reservation_object_add_shared_fence.
Cc: sta...@vger.kernel.org
Bugzilla: https://bugs.freedesktop.org/106418
Reported-by: mikhail.v.gavri...@gmail.
On 06/19/2018 08:57 PM, Christian König wrote:
Always validating the VM PTs takes to much time. Only always validate
the per VM BOs for now.
Signed-off-by: Christian König
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
1 file changed, 1 insertion(+), 1 delet
On 06/19/2018 03:04 PM, Christian König wrote:
We need a commit message, something like "Avoid confusing the GART with the GTT
domain.".
Yeah, will add such kind of info.
Am 19.06.2018 um 06:41 schrieb Junwei Zhang:
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device
On 06/15/2018 03:22 PM, zhoucm1 wrote:
On 2018年06月15日 15:16, Zhang, Jerry wrote:
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
Christian K?nig
Sent: Friday, June 15, 2018 15:09
To: Zhou, David(ChunMing) ; amd-
g...@lists.freedesktop.org
Cc
On 06/12/2018 10:25 AM, zhoucm1 wrote:
On 2018年06月11日 21:23, Christian König wrote:
Per VM BOs share the reservation object with the PD and so need to
reserve a shared fence slot for the update.
Signed-off-by: Christian König
Reviewed-by: Chunming Zhou
Reviewed-by: Junwei Zhang
---
On 06/05/2018 04:54 PM, Christian König wrote:
Am 05.06.2018 um 10:47 schrieb Zhang, Jerry (Junwei):
On 06/05/2018 04:45 PM, Christian König wrote:
Am 04.06.2018 um 13:02 schrieb Michel Dänzer:
On 2018-06-04 12:59 PM, Christian König wrote:
We need to put the lose ends on the invalid list
On 06/05/2018 04:45 PM, Christian König wrote:
Am 04.06.2018 um 13:02 schrieb Michel Dänzer:
On 2018-06-04 12:59 PM, Christian König wrote:
We need to put the lose ends on the invalid list because it is possible
that we need to split up huge pages for them.
Signed-off-by: Christian König
Doe
On 06/05/2018 04:20 PM, zhoucm1 wrote:
On 2018年06月05日 16:14, Christian König wrote:
Am 05.06.2018 um 10:09 schrieb Junwei Zhang:
From: Christian König
(comments: I cannot receive amdgfx mail recently and reply the mail directly,
so send it out with my update v2, tested with Unigine Heaven,
On 06/05/2018 02:20 PM, Christian König wrote:
Hi Jerry,
Am 05.06.2018 um 03:50 schrieb Zhang, Jerry (Junwei):
[SNIP]
Can you check if the problem also vanishes when you disable the following
optimization in amdgpu_vm_update_ptes?
/* We don't need to update PTEs for
g for else
part, since the else part(reserved PRT range) bo_va is different from the target
one(tiled bo). so has to do bo update for else bo_va.
(under debugging...)
Thanks,
Christian.
Am 04.06.2018 um 11:51 schrieb Christian König:
Am 04.06.2018 um 10:19 schrieb Zhang, Jerry (Junwei):
On 06/04/2018 05:51 PM, Christian König wrote:
Am 04.06.2018 um 10:19 schrieb Zhang, Jerry (Junwei):
On 06/04/2018 03:48 PM, Christian König wrote:
Am 04.06.2018 um 09:02 schrieb Zhang, Jerry (Junwei):
On 06/04/2018 02:43 PM, Christian König wrote:
Actually that is not correct. According to
On 06/04/2018 03:48 PM, Christian König wrote:
Am 04.06.2018 um 09:02 schrieb Zhang, Jerry (Junwei):
On 06/04/2018 02:43 PM, Christian König wrote:
Actually that is not correct. According to the documentation the PRT flag should
work for huge pages as well.
Mmm, I checked the doc earlier
On 06/04/2018 02:43 PM, Christian König wrote:
Actually that is not correct. According to the documentation the PRT flag should
work for huge pages as well.
Mmm, I checked the doc earlier, didn't find the PRT flag for PDE.
In CTS PRT test, the reserved PRT mapping introduces huge page mapping,
On 05/25/2018 07:23 PM, Christian König wrote:
Am 25.05.2018 um 11:51 schrieb Zhang, Jerry (Junwei):
On 05/25/2018 05:35 PM, Christian König wrote:
Am 25.05.2018 um 10:23 schrieb Zhang, Jerry (Junwei):
On 05/25/2018 03:54 PM, Christian König wrote:
Am 25.05.2018 um 09:20 schrieb Zhang, Jerry
On 05/25/2018 05:35 PM, Christian König wrote:
Am 25.05.2018 um 10:23 schrieb Zhang, Jerry (Junwei):
On 05/25/2018 03:54 PM, Christian König wrote:
Am 25.05.2018 um 09:20 schrieb Zhang, Jerry (Junwei):
On 05/25/2018 02:44 PM, Christian König wrote:
NAK, that probably just fixed the symptom
On 05/25/2018 03:54 PM, Christian König wrote:
Am 25.05.2018 um 09:20 schrieb Zhang, Jerry (Junwei):
On 05/25/2018 02:44 PM, Christian König wrote:
NAK, that probably just fixed the symptom but not the underlying problem.
Somebody is accessing the page array when it should never be accessed
On 05/25/2018 02:44 PM, Christian König wrote:
NAK, that probably just fixed the symptom but not the underlying problem.
Somebody is accessing the page array when it should never be accessed.
If prime import as GTT bo by default(now it's CPU bo), it would happens quickly
when GTT sg bo creati
On 05/23/2018 01:45 PM, Huang Rui wrote:
Signed-off-by: Huang Rui
Acked-by: Alex Deucher
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1
On 05/17/2018 04:51 AM, Alex Deucher wrote:
Signed-off-by: Alex Deucher
Series is
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h | 4
drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h | 4
2 files changed, 8 insertions(+)
diff --
On 05/17/2018 04:51 AM, Alex Deucher wrote:
Signed-off-by: Alex Deucher
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h | 4
drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h | 4
2 files changed, 8 insertions(+)
diff --git a/drive
2, 3, 4, 5 are
Reviewed-by: Junwei Zhang
Patch 1:
could you show the reserving VM?
Patch 6:
I could read that code, but not sure the purpose.
Jerry
On 05/17/2018 05:49 PM, Christian König wrote:
Only the moved state needs a separate spin lock protection. All other
states are protected by res
On 05/10/2018 04:45 PM, zhoucm1 wrote:
On 2018年05月10日 13:07, Zhang, Jerry (Junwei) wrote:
On 05/09/2018 02:45 PM, Chunming Zhou wrote:
move implemenation from ttm to amdgpu driver. (suggested by Christian)
per-vm-lru is because of per-vm-bo, which has no chance to refresh lru, the
nagtive
On 05/10/2018 04:45 PM, zhoucm1 wrote:
On 2018年05月10日 13:07, Zhang, Jerry (Junwei) wrote:
On 05/09/2018 02:45 PM, Chunming Zhou wrote:
move implemenation from ttm to amdgpu driver. (suggested by Christian)
per-vm-lru is because of per-vm-bo, which has no chance to refresh lru, the
nagtive
On 05/11/2018 10:26 AM, zhoucm1 wrote:
On 2018年05月11日 10:19, Zhang, Jerry (Junwei) wrote:
On 05/11/2018 10:11 AM, zhoucm1 wrote:
On 2018年05月11日 09:21, Zhang, Jerry (Junwei) wrote:
On 05/10/2018 10:40 PM, Christian König wrote:
Am 10.05.2018 um 07:01 schrieb Junwei Zhang:
Expect to add
On 05/11/2018 10:11 AM, zhoucm1 wrote:
On 2018年05月11日 09:21, Zhang, Jerry (Junwei) wrote:
On 05/10/2018 10:40 PM, Christian König wrote:
Am 10.05.2018 um 07:01 schrieb Junwei Zhang:
Expect to add an evitable bo who has reservation object
to the correct lru[bo->priority] list
Nice ca
On 05/10/2018 10:40 PM, Christian König wrote:
Am 10.05.2018 um 07:01 schrieb Junwei Zhang:
Expect to add an evitable bo who has reservation object
to the correct lru[bo->priority] list
Nice catch, but since this affects only a very small use case can we just remove
and readd the BO to the LRU
On 05/09/2018 02:45 PM, Chunming Zhou wrote:
move implemenation from ttm to amdgpu driver. (suggested by Christian)
per-vm-lru is because of per-vm-bo, which has no chance to refresh lru, the
nagtive effect is game performance isn't stable.
so all per-vm-bo should have a default order, every per
On 05/04/2018 02:44 PM, Chunming Zhou wrote:
Shadow BO is located on GTT and its parent (PT and PD) BO could located on VRAM.
In some case, the BO on GTT could be evicted but the parent did not. This may
cause the shadow BO not be put in the evict list and could not be invalidate
correctly.
v2: s
-next but the problem is there is a table for both decode and
encode. That patch that is already on drm-next only adds the callback for
encode.
My patch adds the callback for decode as well. :-)
Cheers,
Tom
On 05/01/2018 09:44 PM, Zhang, Jerry (Junwei) wrote:
Hi Tom,
Ha, got your me
Hi Tom,
Ha, got your meaning.
Please check it with the latest drm-next from gerrit tomorrow.
Jerry
On 05/02/2018 09:41 AM, StDenis, Tom wrote:
Hi Jerry,
Like I said it's (now well) past EOD (meaning my workstation is powered off) so
I'll have to check tomorrow. But I do pull from gerrit dai
Hi Tom,
Do you mean you cannot find the patch from gerrit/amd-staging-dkms-next either?
I do find it.
the tip of gerrit/amd-staging-drm-next is
* bb54e82 2018-04-30 12:17:07 -0400 drm/amdgpu: Switch to interruptable wait
to recover from ring hang.
while the tip of freedesktop is
* a1100
Hi Tom,
Sound you get the code from freedesktop rather than the internal drm-next.
Unfortunately freedesktop looks delay to sync the code from internal drm-next.
That's the gap it happened as issue in the test.
Hi Alex,
Is that a issue for code syncing between freedesktop and internal drm-next?
Hi Tom,
It was landed in the latest drm-next, like
* 964933a 2018-04-27 10:26:09 +0800 drm/amdgpu/uvd7: add
emit_reg_write_reg_wait ring callback
Did you test with that included?
Please try to get the latest drm-next, if not.
They look the same issue from the log.
Jerry
On 05/02/2018 08:4
On 05/01/2018 09:34 PM, Tom St Denis wrote:
Hi all,
I've noticed that on the tip of drm-next vcn playback of video is broken (see
dmesg below). I've bisected it to this commit
It may be fixed here as a common issue.
* https://patchwork.freedesktop.org/patch/218909/
Jerry
[root@raven li
On 04/24/2018 03:35 PM, Chunming Zhou wrote:
Shadow BO is located on GTT and its parent (PT and PD) BO could located on VRAM.
In some case, the BO on GTT could be evicted but the parent did not. This may
cause the shadow BO not be put in the evict list and could not be invalidate
correctly.
Chan
On 04/24/2018 03:35 PM, Chunming Zhou wrote:
Change-Id: Ia3e57dbacff05f32b6c02e29aeadabd36f08028e
Signed-off-by: Chunming Zhou
Reviewed-by: Junwei Zhang
some trivial comments.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 75 ++
1 file changed, 40 insertion
On 04/26/2018 10:18 AM, Alex Deucher wrote:
From: Leo Liu
Signed-off-by: Leo Liu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
include/drm/amd_asic_type.h| 1 +
2 files changed, 2 insertions(+)
diff --git a/dr
On 04/20/2018 02:58 PM, Christian König wrote:
Am 20.04.2018 um 04:04 schrieb Zhang, Jerry (Junwei):
On 04/20/2018 09:50 AM, Zhang, Jerry (Junwei) wrote:
On 04/19/2018 07:06 PM, Christian König wrote:
Wouldn't it be simpler to just set MAX_CARDS_SUPPORTED to 128?
Perhaps it's 6
On 04/20/2018 09:50 AM, Zhang, Jerry (Junwei) wrote:
On 04/19/2018 07:06 PM, Christian König wrote:
Wouldn't it be simpler to just set MAX_CARDS_SUPPORTED to 128?
Perhaps it's 64 for card number.
Although CONTROL node is not used now, but only 64 slots are reserved for each
type.
On 04/19/2018 07:06 PM, Christian König wrote:
Wouldn't it be simpler to just set MAX_CARDS_SUPPORTED to 128?
Perhaps it's 64 for card number.
Although CONTROL node is not used now, but only 64 slots are reserved for each
type.
otherwise, we may prepare a patch to update to 128.
How do you th
On 04/19/2018 03:42 PM, Christian König wrote:
Am 19.04.2018 um 09:40 schrieb Zhang, Jerry (Junwei):
On 04/19/2018 03:06 PM, Christian König wrote:
Am 19.04.2018 um 08:53 schrieb Junwei Zhang:
v2: fix compiling warning
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu
On 04/19/2018 03:06 PM, Christian König wrote:
Am 19.04.2018 um 08:53 schrieb Junwei Zhang:
v2: fix compiling warning
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers
On 04/19/2018 02:26 PM, zhoucm1 wrote:
On 2018年04月19日 13:31, Junwei Zhang wrote:
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/driver
On 04/19/2018 10:30 AM, zhoucm1 wrote:
On 2018年04月19日 09:48, Zhang, Jerry (Junwei) wrote:
On 04/18/2018 06:37 PM, Chunming Zhou wrote:
Otherwise, cpu stuck for 22s with kernel panic.
Change-Id: I5b87cde662a4658c9ab253ba88d009c9628a44ca
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd
On 04/18/2018 06:37 PM, Chunming Zhou wrote:
Otherwise, cpu stuck for 22s with kernel panic.
Change-Id: I5b87cde662a4658c9ab253ba88d009c9628a44ca
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/driv
On 04/17/2018 01:54 PM, Chunming Zhou wrote:
amdgpu_bo_create has too many parameters, and used in
too many places. Collect them to one structure.
Good cleanup.
feel free to add my RB for the series.
Reviewed-by: Junwei Zhang
Change-Id: Ib2aa98ee37a70f3cb0d61eef1d336e89187554d5
Signed-off-
On 04/16/2018 05:19 PM, Christian König wrote:
Am 16.04.2018 um 11:04 schrieb Zhang, Jerry (Junwei):
On 04/16/2018 03:17 PM, Shirish S wrote:
amdgpu_ib_ring_tests() runs test IB's on rings at boot
contributes to ~500 ms of amdgpu driver's boot time.
This patch defers it and ensure
On 04/16/2018 03:17 PM, Shirish S wrote:
amdgpu_ib_ring_tests() runs test IB's on rings at boot
contributes to ~500 ms of amdgpu driver's boot time.
This patch defers it and ensures that its executed
in amdgpu_info_ioctl() if it wasn't scheduled.
V2: Use queue_delayed_work() & flush_delayed_wor
On 03/20/2018 07:25 PM, Rex Zhu wrote:
1. remove struct cgs_os_ops
2. delete cgs_linux.h
3. refine the irq code for vega10
Change-Id: I1b1b56c38596e632fe627c436a5072ae5b359b8c
Signed-off-by: Rex Zhu
Acked-by: Junwei Zhang
Nice to see that
Jerry
---
drivers/gpu/drm/amd/acp/include/acp_
Please adhere to the naming of Polaris12 in commit log as well.
thanks.
Jerry
On 03/21/2018 03:12 AM, Harry Wentland wrote:
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Bhawanpreet Lakha
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/calcs/dce_calc
Just a typo in commit log:
admgpu -> amdgpu
Jerry
On 02/03/2018 01:34 AM, Marek Olšák wrote:
From: Marek Olšák
---
amdgpu/amdgpu.h | 21 +
amdgpu/amdgpu_device.c | 14 ++
amdgpu/amdgpu_internal.h | 1 +
3 files changed, 36 insertions(+)
diff -
On 01/11/2018 10:50 AM, Chunming Zhou wrote:
Could I how to verify this is valid fix?
For now, check if there is no vm fault or any other side effect when loading
amdgpu with ngg=1.
Later development will be implemented with OGL team together.
Jerry
Regards,
David Zhou
On 2018年01月11日
Please ignore this one, a minor update is coming.
Sorry for annoyance.
Jerry
On 01/11/2018 09:44 AM, Junwei Zhang wrote:
v2: fix register access
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --gi
On 01/10/2018 04:57 PM, Christian König wrote:
Am 10.01.2018 um 09:18 schrieb Junwei Zhang:
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/dr
On 11/27/2017 07:29 PM, Feifei Xu wrote:
Remove folder amd/include/asic_reg/raven1 to avoid header files duplication.
Header files under this folder will be moved to asic_reg/.
Also removed some unused header files of raven1.
Patches are formated with flag --find-renames and --irreversible-dele
On 10/06/2017 11:35 PM, Yong Zhao wrote:
From: Yong Zhao
Without the additional bits set in PDEs/PTEs, the ATC memory access
would have failed on Raven.
Change-Id: I28429ef6d39cdb01dc6f17fea4264ee22d7121d4
Signed-off-by: Yong Zhao
Acked-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgp
On 09/30/2017 09:10 AM, Evan Quan wrote:
Change-Id: I598f8ab583fc9c7045a4852d6972df90a82f7472
Signed-off-by: Evan Quan
the series is
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers
On 09/21/2017 10:56 AM, Evan Quan wrote:
Change-Id: I28e9ca38b68234d0325a5b8a01d135649939c0af
Signed-off-by: Evan Quan
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgp
On 09/20/2017 02:22 PM, Evan Quan wrote:
Change-Id: I96cd1d463a5743f918a03cad5160ea0bbd908ad0
Signed-off-by: Evan Quan
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v
On 09/20/2017 02:22 PM, Evan Quan wrote:
Change-Id: Ia41bf64501557723fa811ad98a7b5630f12d9ed8
Signed-off-by: Evan Quan
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v
On 09/19/2017 04:30 PM, Christian König wrote:
I don't know why, but the HDP is generally not part of the register spec.
AFAIW, these regs may be used for HW guys to debug some special cases.
Usually they are not suggested to touch formally.
(e.g. GFX cannot access PRT unmap range, but with deb
looks fine to me, feel free to add my RB.
Reviewed-by: Junwei Zhang
BTW, we also has 1 or 2 patch to improve the name parsing.
Please also take a look.
Jerry
On 05/11/2017 05:10 AM, Li, Samuel wrote:
Also attach a sample ids file for reference. The names are from marketing, not
related to so
On 09/16/2017 05:37 AM, Alex Deucher wrote:
So it gets picked up properly by the kernel.
Signed-off-by: Alex Deucher
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
b/driver
On 09/11/2017 09:22 AM, Evan Quan wrote:
Change-Id: I9b7ebc99b7c75c03fb46d16c4c49348dd551325e
Signed-off-by: Evan Quan
The series patches is
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff -
On 09/02/2017 02:18 PM, Alex Deucher wrote:
Was only being assigned for vega10.
Signed-off-by: Alex Deucher
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/
On 08/31/2017 08:53 PM, Tom St Denis wrote:
Working on a series of tidy up patches for gfx_v9 and found this block in
gfx_v9_0_sw_init().
for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
ring = &adev->gfx.gfx_ring[i];
ring->ring_obj = NULL;
sprintf(ring->name, "gfx
On 07/31/2017 04:41 PM, Huang Rui wrote:
On Mon, Jul 31, 2017 at 04:10:10PM +0800, Zhang, Jerry wrote:
On 07/31/2017 01:57 PM, Huang Rui wrote:
On Fri, Jul 28, 2017 at 05:11:18PM +0800, Junwei Zhang wrote:
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 17 +++
On 07/31/2017 01:57 PM, Huang Rui wrote:
On Fri, Jul 28, 2017 at 05:11:18PM +0800, Junwei Zhang wrote:
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 17 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 22 ++
2 files changed, 36 ins
On 07/25/2017 11:30 AM, Alex Deucher wrote:
Needs to be done when the MC is set up.
v2: make consistent with other asics
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/a
the serial of patch are
Reviewed-by: Junwei Zhang
On 07/20/2017 03:36 PM, Huang Rui wrote:
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amd
On 07/20/2017 10:21 AM, Huang Rui wrote:
There are 8 scratch registers on gfx v9 (scrach_reg0 -> scratch_reg7).
Yeah, nice catch.
Reviewed-by: Junwei Zhang
Additionally it looks incorrect from gfx v6 till gfx9.
Could you fix them all?
Jerry
Signed-off-by: Huang Rui
---
drivers/gpu/drm
On 07/17/2017 07:45 PM, Huang Rui wrote:
On Mon, Jul 17, 2017 at 06:57:41PM +0800, Greg KH wrote:
On Mon, Jul 17, 2017 at 04:56:26PM +0800, Zhang, Jerry (Junwei) wrote:
> + sta...@vger.kernel.org
This is not the correct way to submit patches for inclusion in the
stable kernel tree. Ple
+ sta...@vger.kernel.org
On 07/17/2017 03:57 PM, Huang Rui wrote:
On Mon, Jul 17, 2017 at 03:52:10PM +0800, Huang Rui wrote:
On Fri, Jul 14, 2017 at 06:20:17PM +0800, Junwei Zhang wrote:
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +--
1 file changed, 1 inse
On 07/14/2017 10:43 PM, Deucher, Alexander wrote:
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Junwei Zhang
Sent: Friday, July 14, 2017 6:42 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Jerry
Subject: [PATCH 4/4] drm/amdgpu: add ring_dest
Thanks for update.
That's fine for me.
Feel free to add my RB.
Reviewed-by: Junwei Zhang
On 07/04/2017 04:20 AM, Alex Deucher wrote:
Rather than checking the CONGIG_MEMSIZE register as that may
not be reliable on some APUs.
v2: The scratch register is only used on CIK+
Reviewed-by: Christia
On 07/01/2017 05:32 AM, Alex Deucher wrote:
Rather than checking the CONGIG_MEMSIZE register as that may
not be reliable on some APUs.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/driv
the series is
Reviewed-by: Junwei Zhang
Jerry
On 07/05/2017 01:32 PM, Huang Rui wrote:
Signed-off-by: Huang Rui
---
Changes from V1 -> V2
- amdgpu_bo_free_kernel is safe even the bo is NULL, so remove the "if" check.
Thanks,
Ray
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 15 +-
On 07/04/2017 05:59 PM, Huang Rui wrote:
On Tue, Jul 04, 2017 at 05:39:51PM +0800, Zhang, Jerry wrote:
Hi Ray,
Thanks for your initial patch to enable PSP option for Raven.
To simplify it, we may leverage VEGA10 case for Raven directly.
And remove all Raven existing code under "case CHIP_RAVEN
Hi Ray,
Thanks for your initial patch to enable PSP option for Raven.
To simplify it, we may leverage VEGA10 case for Raven directly.
And remove all Raven existing code under "case CHIP_RAVEN"
How do you think about it?
Jerry
On 07/04/2017 04:35 PM, Huang Rui wrote:
In previous case, driver c
Yeah, when I had a glance at this func, flashed a similar idea.
A little comment inline, please confirm it.
Regards,
Jerry
On 07/04/2017 02:10 PM, Huang Rui wrote:
We would like to use a reserve vram to store all non-psp firmware data when it
is submmited. And needn't alloc/free when each firmw
On 06/13/2017 11:01 AM, Alex Deucher wrote:
This got lost when the code was revamped. Copy/paste bug from
gfx8.
Reported-by: Evan Quan
Fixes: 78c168342 (drm/amdgpu: allow split of queues with kfd at queue
granularity v4)
Signed-off-by: Alex Deucher
Reviewed-by: Junwei Zhang
---
drivers
On 05/24/2017 05:18 PM, Christian König wrote:
Am 18.05.2017 um 07:33 schrieb Zhang, Jerry (Junwei):
On 05/17/2017 05:22 PM, Christian König wrote:
[SNIP]
+static uint64_t gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
+{
+BUG_ON(addr & 0xF000FFFULL);
+re
On 05/17/2017 06:08 PM, Zhou, David(ChunMing) wrote:
Patch#2: Reviewed-by: Chunming Zhou
Patch#3: RB should be from Hawking, so Acked-by: Chunming Zhou
Patch#5 #6, are Reviewed-by: Chunming Zhou
Feel free to add my RB about Patch #2 ~ #5
Reviewed-by: Junwei Zhang
Jerry
For patch#7, f
On 05/17/2017 05:22 PM, Christian König wrote:
From: Christian König
Rename adjust_mc_addr to get_vm_pde and check the address bits in one place.
v2: handle vcn as well, keep setting the valid bit manually,
add a BUG_ON() for GMC v6, v7 and v8 as well.
Signed-off-by: Christian König
---
On 05/16/2017 03:51 PM, Christian König wrote:
Am 16.05.2017 um 06:58 schrieb Zhang, Jerry (Junwei):
On 05/15/2017 07:57 PM, Christian König wrote:
From: Christian König
I always wondered why this code uses the MC address. Now it came to me that
this is actually a bug and only works by
On 05/15/2017 07:57 PM, Christian König wrote:
From: Christian König
I always wondered why this code uses the MC address. Now it came to me that
this is actually a bug and only works by coincident because we used to have
VRAM mapped at zero.
Do you mean to use tbo address in general sw path a
That's fine to me, please feel free to add my RB.
Reviewed-by: Junwei Zhang
BTW, we also have some patches to improve it.
Please take a look if need.
Jerry
On 05/11/2017 05:10 AM, Li, Samuel wrote:
Also attach a sample ids file for reference. The names are from marketing, not
related to sou
Could you elaborate the reason? bug fix, or sth else?
Jerry
On 05/10/2017 03:31 PM, Chunming Zhou wrote:
before that, we have function to check if reset happens by using reset count.
Change-Id: I2e941dd35295d4210d57a9593d39b5ee9021be9f
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/am
On 05/10/2017 03:31 PM, Chunming Zhou wrote:
Change-Id: If24a62b9c3097c9b040225ab0e768145b7a3db1e
Signed-off-by: Chunming Zhou
I had same idea when read this code before.
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 92 +-
1 file c
On 05/10/2017 03:31 PM, Chunming Zhou wrote:
Change-Id: I0ccfa0e6de0cddbcca8dd85f2862240bc5ca02b3
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 1 -
drivers/gpu
On 05/10/2017 03:31 PM, Chunming Zhou wrote:
this is an improvement for previous patch, the sched_sync is to store fence
that could be skipped as scheduled, when job is executed, we didn't need
pipeline_sync if all fences in sched_sync are signalled, otherwise insert
pipeline_sync still.
Change
On 05/09/2017 04:19 PM, Chunming Zhou wrote:
Change-Id: I26d3a2794272ba94b25753d4bf367326d12f6939
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 5 -
3 files c
On 05/09/2017 04:14 PM, Chunming Zhou wrote:
The problem is that executing the jobs in the right order doesn't give you the
right result
because consecutive jobs executed on the same engine are pipelined.
In other words job B does it buffer read before job A has written it's result.
Change-Id:
On 05/09/2017 04:14 PM, Chunming Zhou wrote:
Change-Id: Iced391f5c24a79ad7aecae33e22ff089f68f1337
Signed-off-by: Chunming Zhou
Good catch!
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drive
201 - 300 of 371 matches
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