top.org
> Cc: Liu, Charlene ; Kotarac, Pavle
> ; Pierre-Loup Griffais ;
> Gutierrez, Agustin ; Cornij, Nikola
>
> Subject: RE: [PATCH] drm/amd/display: Shorten delay time to 1us while
> resetting
> FIFO
>
> [Public]
>
> Apologize for sending out the patch with the w
19 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Charlene ; Kotarac, Pavle
> ; Pierre-Loup Griffais ;
> Gutierrez, Agustin ; Cornij, Nikola
>
> Subject: [PATCH] drm/amd/display: Shorten delay time to 1us while resetting
> FIFO
>
> [Why]
> Current FIFO reset delay for dcn10 is
Acked-by: Alex Deucher
On Wed, Jan 19, 2022 at 5:19 PM Liu, Zhan wrote:
>
> [AMD Official Use Only]
>
> [Why]
> Current FIFO reset delay for dcn10 is 100us, which is too long
> and will fail atomic flip. As a result, there will be no display
> on boot.
>
> [How]
> Shorten delay time to 1us.
[AMD Official Use Only]
[Why]
Current FIFO reset delay for dcn10 is 100us, which is too long
and will fail atomic flip. As a result, there will be no display
on boot.
[How]
Shorten delay time to 1us. This also aligns with FIFO reset delay
on other ASICs.
Signed-off-by: Zhan Liu
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