Thanks for the info!
- Joshie ✨
On 9/30/21 18:33, Marek Olšák wrote:
The name is kind of correct. It means "64B with no 128B cache line
straddling", which really means just 64B independent blocks with a small
modification to support DCC image stores. They are not true 128B
independent
The name is kind of correct. It means "64B with no 128B cache line
straddling", which really means just 64B independent blocks with a small
modification to support DCC image stores. They are not true 128B
independent blocks.
Marek
On Thu, Sep 30, 2021 at 12:35 PM Joshua Ashton wrote:
> Can we
Can we please add documentation for this enum?
This was not necessarily a typo, but me misunderstanding and stuff it
working in my testing.
I guess I don't understand why hubp_ind_block_64b_no_128bcl is for 64b
&& 128b when it specifically says "no_128" in the name.
Is there something
I've also amended the version bump that I forgot to do:
-#define KMS_DRIVER_MINOR 43
+#define KMS_DRIVER_MINOR 44
Marek
On Thu, Sep 30, 2021 at 12:06 PM Alex Deucher wrote:
> Acked-by: Alex Deucher
>
> On Thu, Sep 30, 2021 at 11:50 AM Marek Olšák wrote:
> >
> > Hi,
> >
> > Just
Acked-by: Alex Deucher
On Thu, Sep 30, 2021 at 11:50 AM Marek Olšák wrote:
>
> Hi,
>
> Just discovered this typo. Please review.
>
> Thanks,
> Marek
Hi,
Just discovered this typo. Please review.
Thanks,
Marek
From 3abee824223e214d8a74c3f1b47a24e5ea9a9a34 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?=
Date: Thu, 30 Sep 2021 11:13:59 -0400
Subject: [PATCH] drm/amd/display: fix DCC settings for DCN3
MIME-Version: 1.0
