答复: [PATCH] drm/amd/powrplay: delete code set/unset deep_sleep/power_containment.

Reviewed-by: Ken Wang 发件人: amd-gfx 代表 Rex Zhu 发送时间: 2016年8月3日 14:42:01 收件人: amd-gfx@lists.freedesktop.org 抄送: Zhu, Rex 主题: [PATCH] drm/amd/powrplay: delete code set/unset

[PATCH 2/3] drm/amdgpu: remove RB1_BUSY bit checking

From: Rex Zhu This is a workaround to let VCE soft reset work. RB1_BUSY bit is always set, so remove its checking now, and we will depend on RB0_BUSY currently. After we find the root cause of RB1_BUSY, we can add it back. Change-Id: I0a4b622d8bc50f75d1a4187324cd2e9079c95013

[PATCH 1/3] drm/amdgpu: fix harvest config checking in vce3 check_soft_reset

Change-Id: I83a1cd8b19cbffc09c4e9b679b88cd65147446d5 Signed-off-by: Chunming Zhou --- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index

[PATCH xf86-video-ati] Wait for pending flips to complete before turning off an output or CRTC

From: Michel Dänzer At least with older kernels, the flip may never complete otherwise, which can result in us hanging in drmmode_set_mode_major. Fixes: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-ati/+bug/1577170 Signed-off-by: Michel Dänzer

[PATCH 3/3] drm/amdgpu: enable VCE soft reset

Change-Id: Ia3f60107f7257f834be961128793af9b8a0389da Signed-off-by: Chunming Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 - drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 3 --- 2 files changed, 4 deletions(-) diff --git

[PATCH 0/3] VCE3 soft reset working

VCE is always busy is since RB1_BUSY is always busy, now remove it. And enable VCE soft reset. Chunming Zhou (2): drm/amdgpu: fix harvest config checking in vce3 check_soft_reset drm/amdgpu: enable VCE soft reset Rex Zhu (1): drm/amdgpu: remove RB1_BUSY bit checking

Re: [PATCH] drm/amdgpu/gfx8: remove stale function declaration

Am 02.08.2016 um 03:58 schrieb zhoucm1: On 2016年08月02日 02:30, Alex Deucher wrote: This got leftover somehow when I cleaned this up. Signed-off-by: Alex Deucher Reviewed-by: Chunming Zhou Reviewed-by: Christian König

Re: [PATCH v2 0/3] drm/amdgpu: update golden setting of VI

Hi, I think it would be helpful for at least one liner explaining actually what is even getting "fixed" here? Obviously we assume, given that you work for AMD, these magics are correct however it does help in case of issue. Just for a motivating example, suppose a magic is technically correct as

[PATCH 2/6] drm/amd/amdgpu: Fix VCE CG order and resume defaults

CG was being enabled in reverse sense from dpm/powerplay. Also fix the default CLK_EN signal to enable all of the blocks. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

[PATCH 4/6] drm/amd/amdgpu: Move VCE bypass after MGCG test

Only issue bypass if MGCG enabled Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index

[PATCH 6/6] drm/amd/amdgpu: Enable VCE MGCG for Stoney

Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/vi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 5449a3c8c9eb..07ea150f85f4 100644 ---

[PATCH 3/6] drm/amd/amdgpu: Don't set VCE CG in startup

It's handled by DPM/PP properly. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 93604bb78257..9d1924e4e2bc

[PATCH 2/6] drm/amdgpu: Provide page_flip_target hook

From: Michel Dänzer Now we can program a flip during a vertical blank period, if it's the one targeted by the flip (or a later one). This allows simplifying amdgpu_flip_work_func considerably. Signed-off-by: Michel Dänzer ---

[PATCH 5/6] drm/radeon: Set MASTER_UPDATE_MODE to 0 again

From: Michel Dänzer With the previous change, it's safe to let page flips take effect anytime during a vertical blank period. This can avoid delaying a flip by a frame in some cases where we get to radeon_flip_work_func -> adev->mode_info.funcs->page_flip during a

[PATCH 13/13] drm/amdgpu: Set ip_blocks according variable amdgpu_virtual_display.

For virtual display feature, if user set the option "amdgpu.virtual_display=1" when load amdgpu.ko. Then need to set the ip_blocks with virtual display ip blocks. And when enable virtual display, the amdgpu_dal need to be set to zero. Signed-off-by: Emily Deng ---

[PATCH 06/13] drm/amdgpu: Initialize dce_virtual_crtc_funcs.

For virtual display feature, initialize dce_virtual_crtc_funcs. Signed-off-by: Emily Deng --- drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 30 ++ 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c

Re: [PATCH 00/11] add recovery entity

On 2016年08月03日 21:43, Christian König wrote: Well that is a clear NAK to this whole approach. Submitting the recovery jobs to the scheduler is reentrant because the scheduler is the one who originally signaled us of a timeout. we have reset all recovery jobs, right? Could we think those jobs

[PATCH 07/13] drm/amdgpu: Disable VGA render and crtc when init GMC.

For virtual display feature, when the GPU has DCE engine, need to disable the VGA render and CRTC, or it will hang when initialize GMC. Signed-off-by: Emily Deng --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 27

[PATCH 03/13] drm/amdgpu: Initialize dce_virtual_display_funcs.

For virtual display feature, initialize dce_virtual_display_funcs, which will be used in function dce_virtual_set_display_funcs. Signed-off-by: Emily Deng --- drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 222 +-- 1 file changed, 208 insertions(+),

[PATCH 01/13] drm/amdgpu: Add virtual connector and encoder macros.

For virtual display feature, add virtual connector and encoder macros. Signed-off-by: Emily Deng --- drivers/gpu/drm/amd/amdgpu/ObjectID.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/ObjectID.h

[PATCH 09/13] drm/amdgpu: Call pageflip irq funtion when receiced vsync interrupt.

For virtual display feature, as there is no dce engine, so no pageflip irq generated. So directly call pageflip irq funtion when received vysn interrupt. Signed-off-by: Emily Deng --- drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 10 +++--- 1 file changed, 7 insertions(+),

[PATCH 05/13] drm/amdgpu: Initialize dce_virtual_crtc_helper_funcs

For virtual display feature, initialize dce_virtual_crtc_helper_funcs. Signed-off-by: Emily Deng --- drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 137 +-- 1 file changed, 128 insertions(+), 9 deletions(-) diff --git

[PATCH 10/13] drm/amdgpu: Add DRM_MODE_CONNECTOR_VIRTUAL connector in amdgpu_connector_add.

For virtual display feature, add one connector type in amdgpu_connector_add. Signed-off-by: Emily Deng --- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 95 ++ 1 file changed, 95 insertions(+) diff --git

Re: [PATCH 00/11] add recovery entity and run queue

On 2016年08月03日 20:16, Edward O'Callaghan wrote: Hi, I didn't see any of my previous review remarks on your previous submission addresses in this submission of this series? Hi Edward, Sorry for that. Since these patch sets are big feature change and we need to pin down the approach of the

[PATCH 6/6] drm: Add DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags

From: Michel Dänzer These flags allow userspace to explicitly specify the target vertical blank period when a flip should take effect. Signed-off-by: Michel Dänzer --- Note that the previous patches in this series can avoid delaying page flips

[PATCH 3/6] drm/amdgpu: Set MASTER_UPDATE_MODE to 0 again

From: Michel Dänzer With the previous change, it's safe to let page flips take effect anytime during a vertical blank period. This can avoid delaying a flip by a frame in some cases where we get to amdgpu_flip_work_func -> adev->mode_info.funcs->page_flip during a

[PATCH 0/6] drm: Explicit target vblank seqno for page flips

The purpose of this series is to allow drivers to avoid unnecessarily delaying page flips, by explicitly telling the driver which vblank seqno a flip is supposed to take effect in. Patch 1 sets the target to the vblank seqno after the current one when the DRM_IOCTL_MODE_PAGE_FLIP ioctl is called,

[PATCH 1/6] drm: Add page_flip_target CRTC hook

From: Michel Dänzer Mostly the same as the existing page_flip hook, but takes an additional parameter specifying the target vertical blank period when the flip should take effect. Signed-off-by: Michel Dänzer --- drivers/gpu/drm/drm_crtc.c | 23

[PATCH 04/13] drm/amdgpu: Initialize crtc, pageflip irq funcs

For virtual display feature, initialize dce_virtual_crtc_irq_funcs, dce_virtual_pageflip_irq_funcs. As it has no dce engine, so the pageflip interrupt won't be generated, and the vsync interrupt will be generated by smu's periodic timer or software timer which will be implemented later.

[PATCH 02/13] drm/amdgpu: Initialize dce_virtual_ip_funcs

For virtual display feature, first need to initialize dce_virtual_ip_funcs, which will be used when set ip blocks. Signed-off-by: Emily Deng --- drivers/gpu/drm/amd/amdgpu/Makefile | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 5 +-

[PATCH 08/13] drm/amdgpu: Use software timer to generate vsync interrupt.

For virtual display feature, use the software timer to simulate the vsync interrupt. Signed-off-by: Emily Deng --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 33 ++--

[PATCH 11/13] drm/amdgpu: Define vitual display ip blocks.

For virtual display feature, define virtual display ip blocks, and set dce_virtual_ip_funcs to DCE block. Signed-off-by: Emily Deng --- drivers/gpu/drm/amd/amdgpu/cik.c | 341 +++ drivers/gpu/drm/amd/amdgpu/vi.c | 282

Re: [PATCH 2/6] drm/amd/amdgpu: Fix VCE CG order and resume defaults

The logic is a bit confusing at first. "gated" means that SW CG is enabled not that the clocks are turned off. When I sampled the registers in the original configuration the clocks were reading 100% when the core was active. It would read 0% when idle but only because power was gated. With

RE: [PATCH 4/6] drm/amd/amdgpu: Move VCE bypass after MGCG test

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Tom St Denis > Sent: Wednesday, August 03, 2016 11:52 AM > To: amd-gfx@lists.freedesktop.org > Cc: StDenis, Tom > Subject: [PATCH 4/6] drm/amd/amdgpu: Move VCE bypass after MGCG test > >

RE: [PATCH 2/6] drm/amd/amdgpu: Fix VCE CG order and resume defaults

Maybe add a comment to that effect. With that added, this patch is: Reviewed-by: Alex Deucher From: StDenis, Tom Sent: Wednesday, August 03, 2016 12:31 PM To: Deucher, Alexander; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 2/6] drm/amd/amdgpu: Fix VCE CG order

Re: [PATCH 1/6] drm/amd/amdgpu: fix indentation in vce3 CG

Am 03.08.2016 um 17:51 schrieb Tom St Denis: Signed-off-by: Tom St Denis This one is Reviewed-by: Christian König . For the rest I'm not deep enough into the topic to judge. Regards, Christian. --- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 13

RE: [PATCH] drm/amd/amdgpu: Partially revert change to UVD v3 CG

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Tom St Denis > Sent: Wednesday, August 03, 2016 12:47 PM > To: amd-gfx@lists.freedesktop.org > Cc: StDenis, Tom > Subject: [PATCH] drm/amd/amdgpu: Partially revert change to UVD v3 CG > >

RE: [PATCH 2/6] drm/amd/amdgpu: Fix VCE CG order and resume defaults

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Tom St Denis > Sent: Wednesday, August 03, 2016 11:52 AM > To: amd-gfx@lists.freedesktop.org > Cc: StDenis, Tom > Subject: [PATCH 2/6] drm/amd/amdgpu: Fix VCE CG order and resume > defaults >

RE: VCE3 MGCG for Stoney/Carrizo

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Tom St Denis > Sent: Wednesday, August 03, 2016 11:52 AM > To: amd-gfx@lists.freedesktop.org > Subject: VCE3 MGCG for Stoney/Carrizo > > These patches fix the MGCG initialization as well

Re: [PATCH 4/6] drm/amd/amdgpu: Move VCE bypass after MGCG test

Hi Alex, Ok, a similar change was introduced for UVD in 7a6526488b60283cec91852196a5423b1dfb14d8, should that be reverted in part too? Tom From: Deucher, Alexander Sent: Wednesday, August 3, 2016 12:27 To: 'Tom St Denis'; amd-gfx@lists.freedesktop.org Cc:

[PATCH] drm/amd/amdgpu: Partially revert change to UVD v3 CG

Partially undo changes made by commit: drm/amd/amdgpu: don't track state in UVD clockgating To keep bypass even if CG flags are not set. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff

[PATCH] drm/amdgpu: Fix memory trashing if UVD ring test fails

fence_put was called on an uninitialized variable. Signed-off-by: Jay Cornwall --- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

Re: [PATCH] drm/amdgpu: Fix memory trashing if UVD ring test fails

Am 03.08.2016 um 20:39 schrieb Jay Cornwall: fence_put was called on an uninitialized variable. Signed-off-by: Jay Cornwall Good catch, patch is Reviewed-by: Christian König Regards, Christian. --- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 3

Re: [PATCH 00/13] shadow page table support

Patch #1 looks like a fix to me, please add my rb and push ASAP. You should separate such fixes from bugger sets, send out individually and maybe ping Alex to review and add them to his fixes branch. Patch #2: + amdgpu_ttm_placement_init(adev, , +

Re: [PATCH 00/11] add recovery entity

Well that is a clear NAK to this whole approach. Submitting the recovery jobs to the scheduler is reentrant because the scheduler is the one who originally signaled us of a timeout. Why not submit the recovery jobs to the hardware ring directly? Regards, Christian. Am 28.07.2016 um 12:13

Re: [PATCH 00/11] add recovery entity and run queue

Hi, I didn't see any of my previous review remarks on your previous submission addresses in this submission of this series? Kind Regards, Edward. On 08/02/2016 05:51 PM, Chunming Zhou wrote: > every vm has itself recovery entity, which is used to reovery page table from > their shadow. > They

Re: [PATCH v2 0/3] drm/amdgpu: update golden setting of VI

Well, usually they are just the recommended settings from the hardware team which try to fix or improve things by changing the default values for the registers. I work for AMD and sometimes it isn't clear to me either what those changes are good for. E.g. I would need to dig though a whole

Re: [PATCH v2 2/2] drm/amdgpu: expose AMDGPU_GEM_CREATE_VRAM_CLEARED to user space

Am 01.08.2016 um 15:59 schrieb Alex Deucher: On Mon, Aug 1, 2016 at 1:27 AM, Flora Cui wrote: I'll push if no objection Reviewed-by: Alex Deucher Sorry for the delay, been on vacation last week. Patch is Reviewed-by: Christian König

Re: [PATCH 0/3] VCE3 soft reset working

Reviewed-by: Christian König for the whole series. Regards, Christian. Am 03.08.2016 um 09:51 schrieb Chunming Zhou: VCE is always busy is since RB1_BUSY is always busy, now remove it. And enable VCE soft reset. Chunming Zhou (2): drm/amdgpu: fix harvest config

Re: [PATCH v2 0/3] drm/amdgpu: update golden setting of VI

I forgot to say, if this is clear to everyone else but me you can just ignore my noise here :p On 08/03/2016 10:06 PM, Edward O'Callaghan wrote: > Hi, > > I think it would be helpful for at least one liner explaining actually > what is even getting "fixed" here? Obviously we assume, given that

Re: [PATCH 00/10] GART table recovery

On 2016年08月03日 22:01, Christian König wrote: Well patch #10 is incorrect. The SA BO will be set to NULL by amdgpu_sa_bo_free(), so it can't be freed twice and so you can't reference the fence twice. I see. But amdgpu_job_free_resources still shouldn't be called twice, right? That's an