Re: [PATCH] drm/amdgpu/dce_virtual: remove error message for vega10

2017-07-25 Thread Christian König 

Am 25.07.2017 um 11:50 schrieb Xiangliang.Yu:

Vega10 also support virtual display, remove the error message.

Signed-off-by: Xiangliang.Yu 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c 
b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 6487e40..5e6d6be 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -501,6 +501,8 @@ static int dce_virtual_hw_init(void *handle)
  #endif
/* no DCE */
break;
+   case CHIP_VEGA10:
+   break;
default:
DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", 
adev->asic_type);
}



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Re: 答复: [PATCH 1/4] drm/amdgpu/gmc6: disable legacy vga features in gmc init (v2)

2017-07-25 Thread Christian König 
The term "legacy VGA" sounds like the whole render functionality which 
actually isn't part of the GMC AFAIK.


But what Alex primary disables here is the old VGA BAR in the CPU 
address space and that is part of the GMC (or at least related to it).


BTW: Patch are Acked-by: Christian König .

Christian.

Am 25.07.2017 um 11:26 schrieb Qu, Jim:

Hi Christian:

Could you share your minds when you are on second glance?

Thanks
JimQu


发件人: amd-gfx  代表 Christian König 

发送时间: 2017年7月25日 17:17
收件人: Alex Deucher; amd-gfx@lists.freedesktop.org
抄送: Deucher, Alexander
主题: Re: [PATCH 1/4] drm/amdgpu/gmc6: disable legacy vga features in gmc init 
(v2)

Am 25.07.2017 um 05:30 schrieb Alex Deucher:

Needs to be done when the MC is set up.

v2: make consistent with other asics

Signed-off-by: Alex Deucher 

On first glance it kind of looks a bit odd to have that in the GMC code,
but on second glance it actually makes sense.

Christian.


---
   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 14 +-
   1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 117c4835..ab0a104 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -249,7 +249,19 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
   dev_warn(adev->dev, "Wait for MC idle timedout !\n");
   }

- WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK);
+ if (adev->mode_info.num_crtc) {
+ u32 tmp;
+
+ /* Lockout access through VGA aperture*/
+ tmp = RREG32(mmVGA_HDP_CONTROL);
+ tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
+ WREG32(mmVGA_HDP_CONTROL, tmp);
+
+ /* disable VGA render */
+ tmp = RREG32(mmVGA_RENDER_CONTROL);
+ tmp &= ~VGA_VSTATUS_CNTL;
+ WREG32(mmVGA_RENDER_CONTROL, tmp);
+ }
   /* Update configuration */
   WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
  adev->mc.vram_start >> 12);


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[PATCH 5/8] drm/amdgpu: According hardware design revert vce and uvd doorbell assignment

2017-07-25 Thread Xiangliang . Yu 
From: Frank Min 

Now uvd doorbell is from 0xf8-0xfb and vce doorbell is from 0xfc-0xff

Signed-off-by: Frank Min 
Signed-off-by: Xiangliang.Yu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   | 18 +-
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c |  6 --
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c |  6 +++---
 3 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index fe96236..d287621 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -680,15 +680,15 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
/* overlap the doorbell assignment with VCN as they are  mutually 
exclusive
 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
 */
-   AMDGPU_DOORBELL64_RING0_1 = 0xF8,
-   AMDGPU_DOORBELL64_RING2_3 = 0xF9,
-   AMDGPU_DOORBELL64_RING4_5 = 0xFA,
-   AMDGPU_DOORBELL64_RING6_7 = 0xFB,
-
-   AMDGPU_DOORBELL64_UVD_RING0_1 = 0xFC,
-   AMDGPU_DOORBELL64_UVD_RING2_3 = 0xFD,
-   AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFE,
-   AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFF,
+   AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
+   AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
+   AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
+   AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
+
+   AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
+   AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
+   AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
+   AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
 
AMDGPU_DOORBELL64_MAX_ASSIGNMENT  = 0xFF,
AMDGPU_DOORBELL64_INVALID = 0x
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index ab447e8..590c3f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -435,13 +435,15 @@ static int uvd_v7_0_sw_init(void *handle)
return r;
}
 
-
for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
ring = >uvd.ring_enc[i];
sprintf(ring->name, "uvd_enc%d", i);
if (amdgpu_sriov_vf(adev)) {
ring->use_doorbell = true;
-   ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 
2;
+   if (i == 0)
+   ring->doorbell_index = 
AMDGPU_DOORBELL64_UVD_RING0_1 * 2;
+   else
+   ring->doorbell_index = 
AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1;
}
r = amdgpu_ring_init(adev, ring, 512, >uvd.irq, 0);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 9e0050d..34c2281 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -446,11 +446,11 @@ static int vce_v4_0_sw_init(void *handle)
/* DOORBELL only works under SRIOV */
ring->use_doorbell = true;
if (i == 0)
-   ring->doorbell_index = 
AMDGPU_DOORBELL64_RING0_1 * 2;
+   ring->doorbell_index = 
AMDGPU_DOORBELL64_VCE_RING0_1 * 2;
else if (i == 1)
-   ring->doorbell_index = 
AMDGPU_DOORBELL64_RING2_3 * 2;
+   ring->doorbell_index = 
AMDGPU_DOORBELL64_VCE_RING2_3 * 2;
else
-   ring->doorbell_index = 
AMDGPU_DOORBELL64_RING2_3 * 2 + 1;
+   ring->doorbell_index = 
AMDGPU_DOORBELL64_VCE_RING2_3 * 2 + 1;
}
r = amdgpu_ring_init(adev, ring, 512, >vce.irq, 0);
if (r)
-- 
2.7.4

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[PATCH 3/8] drm/amdgpu/vce4: Remove vce interrupt enable related code for sriov

2017-07-25 Thread Xiangliang . Yu 
From: Frank Min 

Interrupt enable is contained in vce init table and this register could
not be accessed in secure ASICs, so just remove it.

Signed-off-by: Frank Min 
Signed-off-by: Xiangliang.Yu 
---
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 28532e3..9e0050d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -992,11 +992,13 @@ static int vce_v4_0_set_interrupt_state(struct 
amdgpu_device *adev,
 {
uint32_t val = 0;
 
-   if (state == AMDGPU_IRQ_STATE_ENABLE)
-   val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
+   if (!amdgpu_sriov_vf(adev)) {
+   if (state == AMDGPU_IRQ_STATE_ENABLE)
+   val |= 
VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
 
-   WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val,
-   ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
+   WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val,
+   
~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
+   }
return 0;
 }
 
-- 
2.7.4

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[PATCH] drm/amdgpu/dce_virtual: remove error message for vega10

2017-07-25 Thread Xiangliang . Yu 
Vega10 also support virtual display, remove the error message.

Signed-off-by: Xiangliang.Yu 
---
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c 
b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 6487e40..5e6d6be 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -501,6 +501,8 @@ static int dce_virtual_hw_init(void *handle)
 #endif
/* no DCE */
break;
+   case CHIP_VEGA10:
+   break;
default:
DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", 
adev->asic_type);
}
-- 
2.7.4

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[PATCH 8/8] drm/amdgpu/sdma4: Enable sdma poll mem addr on vega10 for SRIOV

2017-07-25 Thread Xiangliang . Yu 
From: Frank Min 

While doing flr on VFs, there is possibility to lost the doorbell
writing for sdma, so enable poll mem for sdma, then sdma fw would
check the pollmem holding wptr.

Signed-off-by: Frank Min 
Signed-off-by: Xiangliang.Yu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  3 +++
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 48 --
 2 files changed, 49 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d287621..79d46fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1208,6 +1208,9 @@ struct amdgpu_sdma_instance {
 
struct amdgpu_ring  ring;
boolburst_nop;
+   struct amdgpu_bo*poll_mem_bo;
+   uint64_t*poll_mem_cpuaddr;
+   uint64_tpoll_mem_gpuaddr;
 };
 
 struct amdgpu_sdma {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 591f3e7..563be32 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -35,6 +35,7 @@
 #include "vega10/MMHUB/mmhub_1_0_offset.h"
 #include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
 #include "vega10/HDP/hdp_4_0_offset.h"
+#include "vega10/NBIO/nbio_6_1_offset.h"
 #include "raven1/SDMA0/sdma0_4_1_default.h"
 
 #include "soc15_common.h"
@@ -287,6 +288,7 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring 
*ring)
  */
 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 {
+   int i;
struct amdgpu_device *adev = ring->adev;
 
DRM_DEBUG("Setting write pointer\n");
@@ -303,6 +305,16 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring 
*ring)
adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 
2);
DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
ring->doorbell_index, ring->wptr << 2);
+
+   if (amdgpu_sriov_vf(adev)) {
+   for (i = 0; i < adev->sdma.num_instances; i++) {
+   if (>sdma.instance[i].ring == ring) {
+   
*adev->sdma.instance[i].poll_mem_cpuaddr = ring->wptr << 2;
+   WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
+  
mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL), 0);
+   }
+   }
+   }
WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
} else {
int me = (ring == >adev->sdma.instance[0].ring) ? 0 : 1;
@@ -573,7 +585,7 @@ static void sdma_v4_0_enable(struct amdgpu_device *adev, 
bool enable)
 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   u32 rb_cntl, ib_cntl;
+   u32 rb_cntl, ib_cntl, wptr_poll_addr_lo, wptr_poll_addr_hi, 
wptr_poll_cntl;
u32 rb_bufsz;
u32 wb_offset;
u32 doorbell;
@@ -687,6 +699,19 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
 
if (adev->mman.buffer_funcs_ring == ring)
amdgpu_ttm_set_active_vram_size(adev, 
adev->mc.real_vram_size);
+
+   if (amdgpu_sriov_vf(adev)) {
+   wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
+   wptr_poll_addr_lo = RREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO));
+   wptr_poll_addr_lo = REG_SET_FIELD(wptr_poll_addr_lo, 
SDMA0_GFX_RB_WPTR_POLL_ADDR_LO, ADDR,
+   
lower_32_bits(adev->sdma.instance[i].poll_mem_gpuaddr) >> 2);
+   wptr_poll_addr_hi = 
upper_32_bits(adev->sdma.instance[i].poll_mem_gpuaddr);
+   wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 
SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
+
+   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), wptr_poll_addr_lo);
+   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), wptr_poll_addr_hi);
+   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
+   }
}
 
return 0;
@@ -1247,6 +1272,20 @@ static int sdma_v4_0_sw_init(void *handle)
 (i == 0) ?
 AMDGPU_SDMA_IRQ_TRAP0 :
 AMDGPU_SDMA_IRQ_TRAP1);
+
+   if (amdgpu_sriov_vf(adev)) {
+   r = amdgpu_bo_create_kernel(adev, 8, PAGE_SIZE,
+   AMDGPU_GEM_DOMAIN_VRAM, 
>sdma.instance[i].poll_mem_bo,
+

[PATCH 4/8] drm/amdgpu: Skip uvd and vce ring test for SRIOV

2017-07-25 Thread Xiangliang . Yu 
From: Frank Min 

Since rptr would not be accessed on later secure asics in sriov, remove
the ring test.

Signed-off-by: Frank Min 
Signed-off-by: Xiangliang.Yu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 4 ++--
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c   | 3 +++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index b692ad4..c855366 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -937,9 +937,9 @@ int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
unsigned i;
int r, timeout = adev->usec_timeout;
 
-   /* workaround VCE ring test slow issue for sriov*/
+   /* skip ring test for sriov*/
if (amdgpu_sriov_vf(adev))
-   timeout *= 10;
+   return 0;
 
r = amdgpu_ring_alloc(ring, 16);
if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index fbf7b412..ab447e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -165,6 +165,9 @@ static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring 
*ring)
unsigned i;
int r;
 
+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
r = amdgpu_ring_alloc(ring, 16);
if (r) {
DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n",
-- 
2.7.4

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[PATCH 7/8] drm/amdgpu/uvd7: optimize uvd initialization sequence for SRIOV

2017-07-25 Thread Xiangliang . Yu 
From: Frank Min 

1.Since in sriov there is no need of decoding, so skip the related code;
2.Vcpu boot up and umc enable need to take at the end of the init sequence;

Signed-off-by: Frank Min 
Signed-off-by: Xiangliang.Yu 
---
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 58 +++
 1 file changed, 11 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 590c3f0..3b64951 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -745,11 +745,9 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
init_table += header->uvd_table_offset;
 
ring = >uvd.ring;
+   ring->wptr = 0;
size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 
-   /* disable clock gating */
-   MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_POWER_STATUS),
-  
~UVD_POWER_STATUS__UVD_PG_MODE_MASK, 0);
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_STATUS),
   0x, 0x0004);
/* mc resume*/
@@ -786,12 +784,6 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_VCPU_CACHE_SIZE2),
AMDGPU_UVD_STACK_SIZE + 
(AMDGPU_UVD_SESSION_SIZE * 40));
 
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_UDEC_ADDR_CONFIG),
-   adev->gfx.config.gb_addr_config);
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_UDEC_DB_ADDR_CONFIG),
-   adev->gfx.config.gb_addr_config);
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_UDEC_DBW_ADDR_CONFIG),
-   adev->gfx.config.gb_addr_config);
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
/* mc resume end*/
 
@@ -828,17 +820,6 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
   
UVD_LMI_CTRL__REQ_MODE_MASK |
   0x0010L));
 
-   /* disable byte swapping */
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_LMI_SWAP_CNTL), 0);
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_MP_SWAP_CNTL), 0);
-
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_MPC_SET_MUXA0), 0x40c2040);
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_MPC_SET_MUXA1), 0x0);
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_MPC_SET_MUXB0), 0x40c2040);
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_MPC_SET_MUXB1), 0x0);
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_MPC_SET_ALU), 0);
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_MPC_SET_MUX), 0x88);
-
/* take all subblocks out of reset, except VCPU */
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_SOFT_RESET),

UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
@@ -847,15 +828,6 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_VCPU_CNTL),
UVD_VCPU_CNTL__CLK_EN_MASK);
 
-   /* enable UMC */
-   MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_LMI_CTRL2),
-  
~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
-
-   /* boot up the VCPU */
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_SOFT_RESET), 0);
-
-   MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_STATUS), 0x02, 0x02);
-
/* enable master interrupt */
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_MASTINT_EN),
   
~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
@@ -868,32 +840,24 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device 
*adev)
/* force RBC into idle state */
size = order_base_2(ring->ring_size);
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
-   tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
-   tmp =

[PATCH 6/8] drm/amdgpu/vce4: optimize vce 4.0 init table sequence for SRIOV

2017-07-25 Thread Xiangliang . Yu 
From: Frank Min 

Optimize init table sequence for sriov.

Signed-off-by: Frank Min 
Signed-off-by: Xiangliang.Yu 
---
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 34c2281..b2c0d70 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -278,7 +278,8 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev)
 
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_LMI_CTRL2), ~0x100, 0);
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_SYS_INT_EN),
-  0x, 
VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
+  
VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK,
+  
VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
 
/* end of MC_RESUME */
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_STATUS),
-- 
2.7.4

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Re: [PATCH 1/4] drm/amdgpu/gmc6: disable legacy vga features in gmc init (v2)

2017-07-25 Thread Christian König 

Am 25.07.2017 um 05:30 schrieb Alex Deucher:

Needs to be done when the MC is set up.

v2: make consistent with other asics

Signed-off-by: Alex Deucher 


On first glance it kind of looks a bit odd to have that in the GMC code, 
but on second glance it actually makes sense.


Christian.


---
  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 14 +-
  1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 117c4835..ab0a104 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -249,7 +249,19 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
dev_warn(adev->dev, "Wait for MC idle timedout !\n");
}
  
-	WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK);

+   if (adev->mode_info.num_crtc) {
+   u32 tmp;
+
+   /* Lockout access through VGA aperture*/
+   tmp = RREG32(mmVGA_HDP_CONTROL);
+   tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
+   WREG32(mmVGA_HDP_CONTROL, tmp);
+
+   /* disable VGA render */
+   tmp = RREG32(mmVGA_RENDER_CONTROL);
+   tmp &= ~VGA_VSTATUS_CNTL;
+   WREG32(mmVGA_RENDER_CONTROL, tmp);
+   }
/* Update configuration */
WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
   adev->mc.vram_start >> 12);



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[PATCH 2/8] drm/amdgpu: Enable uvd and vce gpu re-init for SRIOV gpu reset

2017-07-25 Thread Xiangliang . Yu 
From: Frank Min 

Add uvd and vce re-init after gpu reset.

Signed-off-by: Frank Min 
Signed-off-by: Xiangliang.Yu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  | 3 +--
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c  | 4 +---
 3 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9c0f4cc..fe6783e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1953,7 +1953,8 @@ static int amdgpu_sriov_reinit_late(struct amdgpu_device 
*adev)
AMD_IP_BLOCK_TYPE_DCE,
AMD_IP_BLOCK_TYPE_GFX,
AMD_IP_BLOCK_TYPE_SDMA,
-   AMD_IP_BLOCK_TYPE_VCE,
+   AMD_IP_BLOCK_TYPE_UVD,
+   AMD_IP_BLOCK_TYPE_VCE
};
 
for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index e2b17cb..fbf7b412 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -894,9 +894,8 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
header->uvd_table_size = table_size;
 
-   return uvd_v7_0_mmsch_start(adev, >virt.mm_table);
}
-   return -EINVAL; /* already initializaed ? */
+   return uvd_v7_0_mmsch_start(adev, >virt.mm_table);
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 9b1de6b..28532e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -300,11 +300,9 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev)
memcpy((void *)init_table, , sizeof(struct 
mmsch_v1_0_cmd_end));
table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
header->vce_table_size = table_size;
-
-   return vce_v4_0_mmsch_start(adev, >virt.mm_table);
}
 
-   return -EINVAL; /* already initializaed ? */
+   return vce_v4_0_mmsch_start(adev, >virt.mm_table);
 }
 
 /**
-- 
2.7.4

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[PATCH 1/8] drm/amdgpu: Clear vce ring wptr for SRIOV

2017-07-25 Thread Xiangliang . Yu 
From: Frank Min 

MMSCH FW need to get the wptr from 0 after it get the mailbox request
from driver, since every time kick the mailbox, mmsch thinks that it
is the first time engine start to initialize.

Signed-off-by: Frank Min 
Signed-off-by: Xiangliang.Yu 
---
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 6 +-
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 6 +-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 987b958..e2b17cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -685,6 +685,11 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
/* 4, set resp to zero */
WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
 
+   WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0);
+   adev->wb.wb[adev->uvd.ring_enc[0].wptr_offs] = 0;
+   adev->uvd.ring_enc[0].wptr = 0;
+   adev->uvd.ring_enc[0].wptr_old = 0;
+
/* 5, kick off the initialization and wait until 
VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x1001);
 
@@ -702,7 +707,6 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
dev_err(adev->dev, "failed to init MMSCH, 
mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
return -EBUSY;
}
-   WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0);
 
return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 1ecd6bb..9b1de6b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -173,6 +173,11 @@ static int vce_v4_0_mmsch_start(struct amdgpu_device *adev,
/* 4, set resp to zero */
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0);
 
+   WDOORBELL32(adev->vce.ring[0].doorbell_index, 0);
+   adev->wb.wb[adev->vce.ring[0].wptr_offs] = 0;
+   adev->vce.ring[0].wptr = 0;
+   adev->vce.ring[0].wptr_old = 0;
+
/* 5, kick off the initialization and wait until 
VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 
0x1001);
 
@@ -190,7 +195,6 @@ static int vce_v4_0_mmsch_start(struct amdgpu_device *adev,
dev_err(adev->dev, "failed to init MMSCH, 
mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
return -EBUSY;
}
-   WDOORBELL32(adev->vce.ring[0].doorbell_index, 0);
 
return 0;
 }
-- 
2.7.4

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Re: [PATCH 4/4] drm/amdgpu/gmc9: disable legacy vga features in gmc init

2017-07-25 Thread Huang Rui 
On Tue, Jul 25, 2017 at 01:06:42PM +0800, Huang Rui wrote:
> On Tue, Jul 25, 2017 at 04:06:00AM +, Deucher, Alexander wrote:
> > > -Original Message-
> > > From: Alex Deucher [mailto:alexdeuc...@gmail.com]
> > > Sent: Monday, July 24, 2017 11:31 PM
> > > To: amd-gfx@lists.freedesktop.org
> > > Cc: Deucher, Alexander
> > > Subject: [PATCH 4/4] drm/amdgpu/gmc9: disable legacy vga features in gmc
> > > init
> > > 
> > > Needs to be done when the MC is set up.
> > > 
> > > Signed-off-by: Alex Deucher 
> > 
> > Can someone see if this patch fixes the problem with the lower 8 MB of vram 
> > on vega10?  I think this may explain what was messing with vram on resume 
> > that caused us to reserve the first 8 MB of vram.
> > 
> 
> Let me have a try. The start of vram overwrite is probably still caused by
> VGA mode. So, here, you disable it at first.
> 

This patch doesn't fix the start 8 MB of vram corruption.
But I just found the 8M corruption issue only encountered when DC is disabled.

Thanks,
Ray
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Re: [PATCH] drm/amdgpu: fix spelling mistake: "suuport"-> "support"

2017-07-25 Thread Christian König 

Am 25.07.2017 um 00:45 schrieb Colin King:

From: Colin Ian King 

Trivial fix to spelling mistake in WARN_ONCE message

Signed-off-by: Colin Ian King 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 5795f81369f0..06f11e2a32af 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1301,7 +1301,7 @@ static int amdgpu_vm_update_ptes(struct 
amdgpu_pte_update_params *params,
  
  		if (params->shadow) {

if (WARN_ONCE(use_cpu_update,
-   "CPU VM update doesn't suuport shadow pages"))
+   "CPU VM update doesn't support shadow pages"))
return 0;
  
  			if (!pt->shadow)



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