On 22/01/18 01:42 AM, Chunming Zhou wrote:
On 2018年01月20日 02:23, Tom St Denis wrote:
On 19/01/18 01:14 PM, Tom St Denis wrote:
Hi all,
In the function ttm_bo_cleanup_refs() it seems possible to get to
line 551 without entering the block on 516 which means you'll be
unlocking a mutex that
There seems to be a design flaw with this since the address of the
static CSA is never exported anywhere.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 15 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 6 --
2 files
1MB should be more than enough, currently we use about 8K.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
Reserve VA space at the top for older generations as well.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 3 ++-
Previously if a PTE was hit with V=0 the decoder would stop.
Now it continues but only if you're doing a --vm-decode.
Signed-off-by: Tom St Denis
Reported-by: Christian König
---
src/lib/read_vram.c | 8
1 file changed, 4 insertions(+), 4
When ring special operations aren't available we can fallback to the
generic ASIC operations.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git
Change-Id: Ieaa45fa9cfcdb9dec68dd777d27daac675d94a00
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/include/soc15ip.h | 1343 -
1 file changed, 1343 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/include/soc15ip.h
diff --git
Change-Id: I9b3a56147dfc00830a0229bf59990bfe9e8a7e95
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
Change-Id: I886747dbfea9eec4f3f7f8af8ce99f04c2a8f1b7
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c| 3 ++-
drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c | 3 ++-
All HDP invalidation and most flush can now be replaced by the generic
ASIC function.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 7 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1
This adds an optional ring to the invalidate_hdp and flush_hdp
callbacks. If the ring isn't specified or the emit_wreg function not
available the HDP operation will be done with the CPU otherwise by
writing on the ring.
Signed-off-by: Christian König
---
That constant needs to be 64bits.
Fixes: amdgpu: use the high VA range if possible v2
Signed-off-by: Christian König
---
amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c
index
Change-Id: I4abff0cc4cd1ffcbc7a571d3eed9df12b3ff7b7c
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
ip base could be different per ASIC since from soc15. split soc15
header into common ip/hw_id header and asic specific ip offset header
Change-Id: I54e5856e1b99d4e313e61328c0fcd85cdd3b3267
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/include/soc15_hw_ip.h |
Am 22.01.2018 um 13:15 schrieb Hawking Zhang:
ip base could be different per ASIC since from soc15. split soc15
header into common ip/hw_id header and asic specific ip offset header
Change-Id: I54e5856e1b99d4e313e61328c0fcd85cdd3b3267
Signed-off-by: Hawking Zhang
On 2018-01-22 12:22 PM, Alex Deucher wrote:
> The preinstall callback didn't do anything because not all
> of the IPs were initialized when it was called.
>
> Move the postinstall setup into sequence in the driver.
>
> The uninstall callback disabled all interrupt source, but
> it got called too
Am 22.01.2018 um 20:38 schrieb Samuel Li:
Add display to the name for consistency.
Signed-off-by: Samuel Li
Nice cleanup, series is Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 41 -
Tested-By: Mikita Lipski
Thanks,
Nick
From: Grodzovsky, Andrey
Sent: Monday, January 22, 2018 1:36:01 PM
To: Wentland, Harry; Alex Deucher; amd-gfx@lists.freedesktop.org; Lipski, Mikita
Cc: Deucher, Alexander
Subject: Re: [PATCH]
Add display to the name for consistency.
Signed-off-by: Samuel Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h| 4 ++--
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c |
Add display to the name for consistency.
Signed-off-by: Samuel Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 41 -
1 file changed, 22 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
Add display to the name for consistency.
Signed-off-by: Samuel Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h| 6 +++---
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
Add display to the name for consistency.
Signed-off-by: Samuel Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 +-
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 2 +-
Add display to the name for consistency.
Signed-off-by: Samuel Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 8
drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 6 +++---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
3 files changed, 8
Add display to the name for consistency.
Signed-off-by: Samuel Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h| 2 +-
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 +-
Add display to the name for consistency.
Signed-off-by: Samuel Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
3 files changed, 5 insertions(+), 5
Add display to the name for consistency.
Signed-off-by: Samuel Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h| 10 +-
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 +-
Add display to the name for consistency.
Signed-off-by: Samuel Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 11 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h| 8
3 files changed, 11
Rename as amdgpu_display_update_priority for consistency.
Signed-off-by: Samuel Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +-
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 +-
Add display to the name for consistency.
Signed-off-by: Samuel Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 10 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c| 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 3 ++-
3 files changed, 11
Add display to the name for consistency.
Signed-off-by: Samuel Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 8
Add display to the name for consistency.
Signed-off-by: Samuel Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 +-
On 22/01/18 09:03 AM, Tom St Denis wrote:
I've rolled back quite a ways from the tip of drm-next (to
196f74897ba79f6d586894519f09796447d95be5) which is ~1700 commits back
from the tip and still get the attached KASAN report every time.
I'm running piglit with DRI_PRIME=1 with the max size
Am 22.01.2018 um 18:22 schrieb Alex Deucher:
The preinstall callback didn't do anything because not all
of the IPs were initialized when it was called.
Move the postinstall setup into sequence in the driver.
The uninstall callback disabled all interrupt source, but
it got called too late in
+ Mikita who verified the patch.
Andrey
On 01/22/2018 01:34 PM, Harry Wentland wrote:
On 2018-01-22 12:22 PM, Alex Deucher wrote:
The preinstall callback didn't do anything because not all
of the IPs were initialized when it was called.
Move the postinstall setup into sequence in the
Change-Id: I1e798d0fbb7e2023d6619f515a9cfaf029b62b6d
Signed-off-by: Chunming Zhou
---
amdgpu/amdgpu.h| 21 +
amdgpu/amdgpu_cs.c | 16
2 files changed, 21 insertions(+), 16 deletions(-)
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
As we debug into the code, we found that the calls of glreadpixels function
returns a large number of pixels which value are '0'. It means that when the
problem appear, the call of glreadpixels function will get wrong pixels from
framebuffer. But we still confused why and when the problem
On Mon, Jan 22, 2018 at 8:45 AM, Huang Rui wrote:
> It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN only can be issued on
> queue 0.
>
> Signed-off-by: Huang Rui
> Acked-by: Hawking Zhang
> Reviewed-by: Alex Deucher
Hi Andrey,
I've checked to revert this change and use Alex's change on switching irq
destruction sequence and it worked no problem.
You can reject this change if Alex's change is pulled in.
Thanks,
Nick
From: Grodzovsky, Andrey
Sent: Friday, January 19, 2018
KFD currently hard-codes MEC2, Pipe0, Queue0 for the HIQ. (For some
reason KFD numbers MECs starting from 1, not 0.)
So that narrows your choice for KIQ on MEC2 down to pipe == 1, queue == 0.
Regards,
Felix
On 2018-01-22 08:45 AM, Huang Rui wrote:
> It must use queue id 0, because
Acked-by: Alex Deucher
From: amd-gfx on behalf of Harry
Wentland
Sent: Monday, January 22, 2018 4:27 PM
To: amd-gfx@lists.freedesktop.org; Grodzovsky, Andrey; Cheng,
Reviewed-by: Marek Olšák
Marek
On Mon, Jan 22, 2018 at 6:36 PM, Michel Dänzer wrote:
> From: Michel Dänzer
>
> We were incorrectly interpreting the tiling information.
>
> Reported-by: Marek Olšák
>
On Mon, Jan 22, 2018 at 12:36 PM, Michel Dänzer wrote:
> From: Michel Dänzer
>
> We were incorrectly interpreting the tiling information.
>
> Reported-by: Marek Olšák
> Signed-off-by: Michel Dänzer
On Mon, Jan 22, 2018 at 3:20 PM, Drew Davenport wrote:
> I was doing some debugging and found that /sys/kernel/debug/dri/0/state
> doesn't get created for amdgpu. After a bit of digging around I found that
> the DRIVER_ATOMIC feature flag gets set in dm_early_init in
On Mon, Jan 22, 2018 at 12:53 PM, Andres Rodriguez wrote:
>
>
> On 2018-01-22 08:45 AM, Huang Rui wrote:
>>
>> It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN only can be issued
>> on
>> queue 0.
>>
>> Signed-off-by: Huang Rui
>> Acked-by: Hawking
On Mon, Jan 22, 2018 at 2:42 PM, Christian König
wrote:
> Am 22.01.2018 um 20:38 schrieb Samuel Li:
>>
>> Add display to the name for consistency.
>>
>> Signed-off-by: Samuel Li
>
>
> Nice cleanup, series is Acked-by: Christian König
On Tue, Jan 23, 2018 at 06:28:52AM +0800, Kuehling, Felix wrote:
> KFD currently hard-codes MEC2, Pipe0, Queue0 for the HIQ. (For some
> reason KFD numbers MECs starting from 1, not 0.)
>
> So that narrows your choice for KIQ on MEC2 down to pipe == 1, queue == 0.
>
Yes, actually, we use mec2
On 01/22/2018 06:23 PM, Andrew Morton wrote:
On Thu, 18 Jan 2018 11:47:48 -0500 Andrey Grodzovsky
wrote:
Hi, this series is a revised version of an RFC sent by Christian König
a few years ago. The original RFC can be found at
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
Christian K?nig
Sent: Monday, January 22, 2018 6:44 PM
To: Liu, Monk ; amd-gfx@lists.freedesktop.org
Subject: [PATCH 3/3] drm/amdgpu: move static CSA address to top of address
Acked-by: Chunming Zhou for series.
On 2018年01月22日 18:00, Christian König wrote:
All HDP invalidation and most flush can now be replaced by the generic
ASIC function.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h
On Thu, 18 Jan 2018 11:47:48 -0500 Andrey Grodzovsky
wrote:
> Hi, this series is a revised version of an RFC sent by Christian König
> a few years ago. The original RFC can be found at
> https://lists.freedesktop.org/archives/dri-devel/2015-September/089778.html
>
>
Any bug introduced by original design ? I don't see why 8MB- 8KB as the start
vm address of CSA has any trouble compared with top range ? Besides, please
note that you also need modify gfx8/9 source to align emit_cs/de_meta with your
change
From: He, Roger
anyway I prefer no change on that part unless there issues or bug need to fix
by the change.
the CSA address is for use by CPG h/w not s/w, and since 8MB is a reserved
range for each VM I don't see
it's a design flaw with it
From: Liu, Monk
Sent: Tuesday,
On Sun, Jan 21, 2018 at 7:46 AM, Lukas Wunner wrote:
> amdgpu_device_init() calls vga_switcheroo_init_domain_pm_ops() either
> if the device has the PowerXpress flag set or if the user has set the
> "runpm" module param to 1.
>
> However amdgpu_device_fini() calls
On 2018-01-22 09:57 AM, Andrey Grodzovsky wrote:
> You guys just need to revert it on dal-dev branch and don't promote to
> amd-staging-drm-next.
>
K. I'll leave it out of amd-staging-drm-next and we'll revert on our internal
branch.
Thanks for following up on this and good to hear we found a
NP.
Alex just a reminder to push your patch from SWDEV-143068 into the tree.
Thanks,
Andrey
On 01/22/2018 10:53 AM, Harry Wentland wrote:
On 2018-01-22 09:57 AM, Andrey Grodzovsky wrote:
You guys just need to revert it on dal-dev branch and don't promote to
amd-staging-drm-next.
K.
On Mon, Jan 22, 2018 at 7:18 AM, Christian König
wrote:
> That constant needs to be 64bits.
>
> Fixes: amdgpu: use the high VA range if possible v2
>
> Signed-off-by: Christian König
Reviewed-by: Alex Deucher
This will skip to the next page boundary (assumes page=4K right now) if
in --vm-decode mode.
Signed-off-by: Tom St Denis
Reported-by: Christian König
---
src/lib/read_vram.c | 25 +
1 file changed, 21 insertions(+), 4
On 01/18/2018 10:49 AM, James Zhu wrote:
Add Polaris version check if firmware support UVD encode
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 21 +
1 file changed, 21 insertions(+)
diff --git
It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN only can be issued on
queue 0.
Signed-off-by: Huang Rui
Acked-by: Hawking Zhang
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8 ++--
1
Am 22.01.2018 um 13:56 schrieb Tom St Denis:
Previously if a PTE was hit with V=0 the decoder would stop.
Now it continues but only if you're doing a --vm-decode.
Signed-off-by: Tom St Denis
Reported-by: Christian König
Acked-by: Christian
I've rolled back quite a ways from the tip of drm-next (to
196f74897ba79f6d586894519f09796447d95be5) which is ~1700 commits back
from the tip and still get the attached KASAN report every time.
I'm running piglit with DRI_PRIME=1 with the max size memory tests disabled.
Tom
[0.00]
You guys just need to revert it on dal-dev branch and don't promote to
amd-staging-drm-next.
So NAK for the change.
Thanks,
Andrey
On 01/22/2018 09:38 AM, Lipski, Mikita wrote:
Hi Andrey,
I've checked to revert this change and use Alex's change on switching
irq destruction sequence
The preinstall callback didn't do anything because not all
of the IPs were initialized when it was called.
Move the postinstall setup into sequence in the driver.
The uninstall callback disabled all interrupt source, but
it got called too late in the driver sequence and caused problems
with IPs
Thanks for verifying. Sent out for review.
Alex
From: Grodzovsky, Andrey
Sent: Monday, January 22, 2018 11:01:36 AM
To: Wentland, Harry; Lipski, Mikita; amd-gfx@lists.freedesktop.org; Deucher,
Alexander
Subject: Re: [PATCH 15/24] drm/amd/display: Fix deadlock
On 2018-01-22 08:45 AM, Huang Rui wrote:
It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN only can be issued on
queue 0.
Signed-off-by: Huang Rui
Acked-by: Hawking Zhang
Reviewed-by: Alex Deucher
---
On 2018-01-22 03:14 AM, Mario Kleiner wrote:
> Ok, 3rd revision, now with per-x-screen drmmode_crtc_funcs rec
> and set_gamma = NULL in the depth 30 case. Also back to Fredrik's
> original exa 10 bit patch, just with his signed-off tacked on.
>
> Tested with single and dual x-screen, depth 24,
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