Re: [PATCH v4] drm/amdgpu/vg20:support new UVD FW version naming convention

[Alex Deucher]

On Tue, Jun 12, 2018 at 11:46 AM, James Zhu  wrote:
> Vega20 UVD Firmware has a new version naming convention:
>   [31, 30] for encode interface major
>   [29, 24] for encode interface minor
>   [15, 8] for decode interface minor
>   [7, 0] for hardware family id
>
> Signed-off-by: James Zhu 

This patch breaks adev->uvd.fw_version which is used elsewhere and
causes build warnings. E.g.,

if (adev->asic_type >= CHIP_VEGA20 || (version_major > 0x01) ||
((version_major == 0x01) && (version_minor >= 0x50)))
adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;

adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
(family_id << 8));

version_major and version_minor are undefined in some cases.

Alex


> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 21 -
>  1 file changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> index bcf68f8..630e273 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> @@ -208,10 +208,21 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
>
> hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
> family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
> -   version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
> -   version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
> -   DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
> -   version_major, version_minor, family_id);
> +
> +   if (adev->asic_type < CHIP_VEGA20) {
> +   version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 
> 0xff;
> +   version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
> +   DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: 
> %hu\n",
> +   version_major, version_minor, family_id);
> +   } else {
> +   unsigned int enc_major, enc_minor, dec_minor;
> +
> +   dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
> +   enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f;
> +   enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3;
> +   DRM_INFO("Found UVD firmware ENC: %hu.%hu DEC: .%hu Family 
> ID: %hu\n",
> +   enc_major, enc_minor, dec_minor, family_id);
> +   }
>
> /*
>  * Limit the number of UVD handles depending on microcode major
> @@ -219,7 +230,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
>  * instances support is 1.80. So all subsequent versions should
>  * also have the same support.
>  */
> -   if ((version_major > 0x01) ||
> +   if (adev->asic_type >= CHIP_VEGA20 || (version_major > 0x01) ||
> ((version_major == 0x01) && (version_minor >= 0x50)))
> adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
>
> --
> 2.7.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: Update function level documentation for GPUVM.

[Alex Deucher]

On Wed, Jun 13, 2018 at 4:03 PM, Andrey Grodzovsky
 wrote:
> Add documentation for missed parameters.
>
> Signed-off-by: Andrey Grodzovsky 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 12 
>  1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 6d22942..bdd6ffb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -347,6 +347,7 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm)
>   * @vm: VM to clear BO from
>   * @bo: BO to clear
>   * @level: level this BO is at
> + * @pte_support_ats: indicate ATS support from PTE
>   *
>   * Root PD needs to be reserved when calling this.
>   *
> @@ -673,6 +674,7 @@ bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring 
> *ring,
>   * amdgpu_vm_flush - hardware flush the vm
>   *
>   * @ring: ring to use for flush
> + * @job:  related job
>   * @need_pipe_sync: is pipe sync needed
>   *
>   * Emit a VM flush when it is necessary.
> @@ -1763,6 +1765,7 @@ static void amdgpu_vm_prt_put(struct amdgpu_device 
> *adev)
>   * amdgpu_vm_prt_cb - callback for updating the PRT status
>   *
>   * @fence: fence for the callback
> + * @_cb: the callback function
>   */
>  static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb 
> *_cb)
>  {
> @@ -2041,6 +2044,7 @@ static void amdgpu_vm_bo_insert_map(struct 
> amdgpu_device *adev,
>   * @bo_va: bo_va to store the address
>   * @saddr: where to map the BO
>   * @offset: requested offset in the BO
> + * @size: BO size

For clarify:
BO size in bytes

>   * @flags: attributes of pages (read/write/valid/etc.)
>   *
>   * Add a mapping of the BO at the specefied addr into the VM.
> @@ -2104,6 +2108,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
>   * @bo_va: bo_va to store the address
>   * @saddr: where to map the BO
>   * @offset: requested offset in the BO
> + * @size: BO size

Same here.

With those fixed:
Reviewed-by: Alex Deucher 

>   * @flags: attributes of pages (read/write/valid/etc.)
>   *
>   * Add a mapping of the BO at the specefied addr into the VM. Replace 
> existing
> @@ -2322,6 +2327,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device 
> *adev,
>   * amdgpu_vm_bo_lookup_mapping - find mapping by address
>   *
>   * @vm: the requested VM
> + * @addr: the address
>   *
>   * Find a mapping by it's address.
>   *
> @@ -2380,6 +2386,7 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
>   *
>   * @adev: amdgpu_device pointer
>   * @bo: amdgpu buffer object
> + * @evicted: is the BO evicted
>   *
>   * Mark @bo as invalid.
>   */
> @@ -2445,6 +2452,10 @@ static uint32_t amdgpu_vm_get_block_size(uint64_t 
> vm_size)
>   *
>   * @adev: amdgpu_device pointer
>   * @vm_size: the default vm size if it's set auto
> + * @fragment_size_default: Default PTE fragment size
> + * @max_level: max VMPT level
> + * @max_bits: max address space size in bits
> + *
>   */
>  void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
>uint32_t fragment_size_default, unsigned max_level,
> @@ -2512,6 +2523,7 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, 
> uint32_t vm_size,
>   * @adev: amdgpu_device pointer
>   * @vm: requested vm
>   * @vm_context: Indicates if it GFX or Compute context
> + * @pasid: Process address space identifier
>   *
>   * Init @vm fields.
>   *
> --
> 2.7.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu: Update function level documentation for GPUVM.

[Andrey Grodzovsky]

Add documentation for missed parameters.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 6d22942..bdd6ffb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -347,6 +347,7 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm)
  * @vm: VM to clear BO from
  * @bo: BO to clear
  * @level: level this BO is at
+ * @pte_support_ats: indicate ATS support from PTE
  *
  * Root PD needs to be reserved when calling this.
  *
@@ -673,6 +674,7 @@ bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
  * amdgpu_vm_flush - hardware flush the vm
  *
  * @ring: ring to use for flush
+ * @job:  related job
  * @need_pipe_sync: is pipe sync needed
  *
  * Emit a VM flush when it is necessary.
@@ -1763,6 +1765,7 @@ static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
  * amdgpu_vm_prt_cb - callback for updating the PRT status
  *
  * @fence: fence for the callback
+ * @_cb: the callback function
  */
 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
 {
@@ -2041,6 +2044,7 @@ static void amdgpu_vm_bo_insert_map(struct amdgpu_device 
*adev,
  * @bo_va: bo_va to store the address
  * @saddr: where to map the BO
  * @offset: requested offset in the BO
+ * @size: BO size
  * @flags: attributes of pages (read/write/valid/etc.)
  *
  * Add a mapping of the BO at the specefied addr into the VM.
@@ -2104,6 +2108,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
  * @bo_va: bo_va to store the address
  * @saddr: where to map the BO
  * @offset: requested offset in the BO
+ * @size: BO size
  * @flags: attributes of pages (read/write/valid/etc.)
  *
  * Add a mapping of the BO at the specefied addr into the VM. Replace existing
@@ -2322,6 +2327,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device 
*adev,
  * amdgpu_vm_bo_lookup_mapping - find mapping by address
  *
  * @vm: the requested VM
+ * @addr: the address
  *
  * Find a mapping by it's address.
  *
@@ -2380,6 +2386,7 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
  *
  * @adev: amdgpu_device pointer
  * @bo: amdgpu buffer object
+ * @evicted: is the BO evicted
  *
  * Mark @bo as invalid.
  */
@@ -2445,6 +2452,10 @@ static uint32_t amdgpu_vm_get_block_size(uint64_t 
vm_size)
  *
  * @adev: amdgpu_device pointer
  * @vm_size: the default vm size if it's set auto
+ * @fragment_size_default: Default PTE fragment size
+ * @max_level: max VMPT level
+ * @max_bits: max address space size in bits
+ *
  */
 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
   uint32_t fragment_size_default, unsigned max_level,
@@ -2512,6 +2523,7 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, 
uint32_t vm_size,
  * @adev: amdgpu_device pointer
  * @vm: requested vm
  * @vm_context: Indicates if it GFX or Compute context
+ * @pasid: Process address space identifier
  *
  * Init @vm fields.
  *
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: Add Dell Inspiron 5575/5775 back to atpx quirk table

[Kai-Heng Feng]

at 01:41, Alex Deucher  wrote:


On Tue, Jun 5, 2018 at 2:47 AM, Kai-Heng Feng
 wrote:

The original issue on these laptops was about _PR3, not audio controller
prevents gfx auto suspending.


Have you verified that this this patch is still necessary with the HDA
driver fix in place?


Yes I did. And the HDA fix doesn't work for these laptops.

The HDA fix is to let HDA controller can be runtime suspended. OTOH, the  
ATPX quirk is to fix the "atombios stuck" for these laptops.


Kai-Heng



Alex


Commit 444d95f0eeef ("Partially revert: drm/amdgpu: add atpx quirk
handling (v2)") breaks these laptops:

[   29.572055] [drm:atom_op_jump [amdgpu]] *ERROR* atombios stuck in  
loop for more than 5secs aborting
[   29.572738] [drm:amdgpu_atom_execute_table_locked [amdgpu]] *ERROR*  
atombios stuck executing 7C36 (len 272, WS 0, PS 4) @ 0x7C7F
[   29.573436] [drm:amdgpu_atom_execute_table_locked [amdgpu]] *ERROR*  
atombios stuck executing 6444 (len 70, WS 0, PS 8) @ 0x646A
[   29.574125] [drm:amdgpu_device_resume [amdgpu]] *ERROR* amdgpu asic  
init failed

[   29.991377] amdgpu :01:00.0: Wait for MC idle timedout !
[   30.407480] amdgpu :01:00.0: Wait for MC idle timedout !
[   30.417279] [drm] PCIE GART of 256M enabled (table at  
0x00F4).

[   30.426550] amdgpu: [powerplay] smu not running, upload firmware again
[   30.435710] BUG: unable to handle kernel paging request at  
a52b90080fec
[   30.436982] IP: smu7_populate_single_firmware_entry.isra.5+0x65/0xe0  
[amdgpu]

[   30.438056] PGD 14e942067 P4D 14e942067 PUD 0
[   30.439280] Oops: 0002 [#1] SMP NOPTI
[   30.440339] Modules linked in: cmac bnep nls_iso8859_1 arc4  
ath10k_pci ath10k_core rtsx_usb_ms memstick dell_wmi uvcvideo  
sparse_keymap videobuf2_vmalloc dell_laptop videobuf2_memops dell_smbios  
dell_wmi_descriptor videobuf2_v4l2 btusb btrtl wmi_bmof joydev dcdbas  
btbcm dell_smm_hwmon videobuf2_common kvm_amd btintel ath videodev  
snd_hda_codec_realtek snd_hda_codec_hdmi snd_hda_codec_generic cdc_acm  
mac80211 media bluetooth snd_hda_intel kvm snd_hda_codec snd_hwdep  
irqbypass snd_hda_core ecdh_generic crct10dif_pclmul snd_pcm  
crc32_pclmul snd_seq ghash_clmulni_intel pcbc snd_timer snd_seq_device  
aesni_intel cfg80211 snd aes_x86_64 soundcore input_leds crypto_simd  
cryptd tpm_crb hid_multitouch ucsi_acpi glue_helper typec_ucsi serio_raw  
typec video i2c_piix4 mac_hid dell_rbtn shpchp wmi parport_pc ppdev
[   30.445678]  lp parport autofs4 btrfs xor zstd_decompress  
zstd_compress xxhash raid6_pq dm_mirror dm_region_hash dm_log amdkfd  
amd_iommu_v2 amdgpu rtsx_usb_sdmmc rtsx_usb chash i2c_algo_bit gpu_sched  
drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops ttm drm  
r8169 ahci libahci i2c_hid mii hid
[   30.448702] CPU: 7 PID: 1021 Comm: gpu-manager Not tainted  
4.16.0-rc7+ #1
[   30.450256] Hardware name: Dell Inc. Inspiron 5775/Inspiron 5775,  
BIOS 1.1.0 03/26/2018
[   30.451959] RIP:  
0010:smu7_populate_single_firmware_entry.isra.5+0x65/0xe0 [amdgpu]

[   30.453492] RSP: 0018:a50f816f3a58 EFLAGS: 00010246
[   30.455116] RAX: 008c RBX: a52b90080fec RCX:  

[   30.456676] RDX: 0004 RSI: 0004 RDI:  
917dfb3a5a90
[   30.458203] RBP: a50f816f3aa8 R08: 917dfb3a5a90 R09:  
00033930
[   30.459727] R10:  R11: 0412 R12:  
0003
[   30.461246] R13: 917dfb194c14 R14: 917dfac65000 R15:  
05fe
[   30.462733] FS:  7f5248978700() GS:917e0edc()  
knlGS:

[   30.464302] CS:  0010 DS:  ES:  CR0: 80050033
[   30.465830] CR2: a52b90080fec CR3: 0001358c2000 CR4:  
003406e0

[   30.467468] Call Trace:
[   30.469068]  smu7_request_smu_load_fw+0xa9/0x360 [amdgpu]
[   30.470630]  ? vga_switcheroo_fini_domain_pm_ops+0x20/0x20
[   30.472416]  iceland_start_smu+0x39/0x70 [amdgpu]
[   30.473492]  hwmgr_resume+0x2b/0xa0 [amdgpu]
[   30.474500]  pp_resume+0x15/0x20 [amdgpu]
[   30.475472]  amdgpu_device_ip_resume_phase2+0x58/0xb0 [amdgpu]
[   30.476431]  amdgpu_device_resume+0xd8/0x370 [amdgpu]
[   30.477379]  ? __pci_set_master+0x34/0xe0
[   30.478345]  ? vga_switcheroo_fini_domain_pm_ops+0x20/0x20
[   30.479317]  amdgpu_pmops_runtime_resume+0x76/0xa0 [amdgpu]
[   30.480265]  pci_pm_runtime_resume+0x76/0xb0
[   30.481216]  vga_switcheroo_runtime_resume+0x59/0x60
[   30.482201]  __rpm_callback+0xc4/0x200
[   30.483179]  ? vga_switcheroo_fini_domain_pm_ops+0x20/0x20
[   30.484075]  rpm_callback+0x24/0x80
[   30.485025]  ? vga_switcheroo_fini_domain_pm_ops+0x20/0x20
[   30.486005]  rpm_resume+0x499/0x6a0
[   30.486946]  __pm_runtime_resume+0x4e/0x80
[   30.487880]  pci_config_pm_runtime_get+0x53/0x60
[   30.488789]  pci_read_config+0x8f/0x280
[   30.489771]  sysfs_kf_bin_read+0x4a/0x70
[   30.490750]  kernfs_fop_read+0xa9/0x190
[   30.491648]  __vfs_read+0x37/0x160
[   30.492579]  ? security_file_permission+0x9b/0xc0
[   

Re: [PATCH] drm/amdgpu: Add Dell Inspiron 5575/5775 back to atpx quirk table

[Alex Deucher]

On Wed, Jun 13, 2018 at 2:27 PM, Kai-Heng Feng
 wrote:
> at 01:41, Alex Deucher  wrote:
>
>> On Tue, Jun 5, 2018 at 2:47 AM, Kai-Heng Feng
>>  wrote:
>>>
>>> The original issue on these laptops was about _PR3, not audio controller
>>> prevents gfx auto suspending.
>>
>>
>> Have you verified that this this patch is still necessary with the HDA
>> driver fix in place?
>
>
> Yes I did. And the HDA fix doesn't work for these laptops.
>
> The HDA fix is to let HDA controller can be runtime suspended. OTOH, the
> ATPX quirk is to fix the "atombios stuck" for these laptops.

I'll just drop the original patch.

Thanks,

Alex

>
> Kai-Heng
>
>
>>
>> Alex
>>
>>> Commit 444d95f0eeef ("Partially revert: drm/amdgpu: add atpx quirk
>>> handling (v2)") breaks these laptops:
>>>
>>> [   29.572055] [drm:atom_op_jump [amdgpu]] *ERROR* atombios stuck in loop
>>> for more than 5secs aborting
>>> [   29.572738] [drm:amdgpu_atom_execute_table_locked [amdgpu]] *ERROR*
>>> atombios stuck executing 7C36 (len 272, WS 0, PS 4) @ 0x7C7F
>>> [   29.573436] [drm:amdgpu_atom_execute_table_locked [amdgpu]] *ERROR*
>>> atombios stuck executing 6444 (len 70, WS 0, PS 8) @ 0x646A
>>> [   29.574125] [drm:amdgpu_device_resume [amdgpu]] *ERROR* amdgpu asic
>>> init failed
>>> [   29.991377] amdgpu :01:00.0: Wait for MC idle timedout !
>>> [   30.407480] amdgpu :01:00.0: Wait for MC idle timedout !
>>> [   30.417279] [drm] PCIE GART of 256M enabled (table at
>>> 0x00F4).
>>> [   30.426550] amdgpu: [powerplay] smu not running, upload firmware again
>>> [   30.435710] BUG: unable to handle kernel paging request at
>>> a52b90080fec
>>> [   30.436982] IP: smu7_populate_single_firmware_entry.isra.5+0x65/0xe0
>>> [amdgpu]
>>> [   30.438056] PGD 14e942067 P4D 14e942067 PUD 0
>>> [   30.439280] Oops: 0002 [#1] SMP NOPTI
>>> [   30.440339] Modules linked in: cmac bnep nls_iso8859_1 arc4 ath10k_pci
>>> ath10k_core rtsx_usb_ms memstick dell_wmi uvcvideo sparse_keymap
>>> videobuf2_vmalloc dell_laptop videobuf2_memops dell_smbios
>>> dell_wmi_descriptor videobuf2_v4l2 btusb btrtl wmi_bmof joydev dcdbas btbcm
>>> dell_smm_hwmon videobuf2_common kvm_amd btintel ath videodev
>>> snd_hda_codec_realtek snd_hda_codec_hdmi snd_hda_codec_generic cdc_acm
>>> mac80211 media bluetooth snd_hda_intel kvm snd_hda_codec snd_hwdep irqbypass
>>> snd_hda_core ecdh_generic crct10dif_pclmul snd_pcm crc32_pclmul snd_seq
>>> ghash_clmulni_intel pcbc snd_timer snd_seq_device aesni_intel cfg80211 snd
>>> aes_x86_64 soundcore input_leds crypto_simd cryptd tpm_crb hid_multitouch
>>> ucsi_acpi glue_helper typec_ucsi serio_raw typec video i2c_piix4 mac_hid
>>> dell_rbtn shpchp wmi parport_pc ppdev
>>> [   30.445678]  lp parport autofs4 btrfs xor zstd_decompress
>>> zstd_compress xxhash raid6_pq dm_mirror dm_region_hash dm_log amdkfd
>>> amd_iommu_v2 amdgpu rtsx_usb_sdmmc rtsx_usb chash i2c_algo_bit gpu_sched
>>> drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops ttm drm r8169
>>> ahci libahci i2c_hid mii hid
>>> [   30.448702] CPU: 7 PID: 1021 Comm: gpu-manager Not tainted 4.16.0-rc7+
>>> #1
>>> [   30.450256] Hardware name: Dell Inc. Inspiron 5775/Inspiron 5775, BIOS
>>> 1.1.0 03/26/2018
>>> [   30.451959] RIP:
>>> 0010:smu7_populate_single_firmware_entry.isra.5+0x65/0xe0 [amdgpu]
>>> [   30.453492] RSP: 0018:a50f816f3a58 EFLAGS: 00010246
>>> [   30.455116] RAX: 008c RBX: a52b90080fec RCX:
>>> 
>>> [   30.456676] RDX: 0004 RSI: 0004 RDI:
>>> 917dfb3a5a90
>>> [   30.458203] RBP: a50f816f3aa8 R08: 917dfb3a5a90 R09:
>>> 00033930
>>> [   30.459727] R10:  R11: 0412 R12:
>>> 0003
>>> [   30.461246] R13: 917dfb194c14 R14: 917dfac65000 R15:
>>> 05fe
>>> [   30.462733] FS:  7f5248978700() GS:917e0edc()
>>> knlGS:
>>> [   30.464302] CS:  0010 DS:  ES:  CR0: 80050033
>>> [   30.465830] CR2: a52b90080fec CR3: 0001358c2000 CR4:
>>> 003406e0
>>> [   30.467468] Call Trace:
>>> [   30.469068]  smu7_request_smu_load_fw+0xa9/0x360 [amdgpu]
>>> [   30.470630]  ? vga_switcheroo_fini_domain_pm_ops+0x20/0x20
>>> [   30.472416]  iceland_start_smu+0x39/0x70 [amdgpu]
>>> [   30.473492]  hwmgr_resume+0x2b/0xa0 [amdgpu]
>>> [   30.474500]  pp_resume+0x15/0x20 [amdgpu]
>>> [   30.475472]  amdgpu_device_ip_resume_phase2+0x58/0xb0 [amdgpu]
>>> [   30.476431]  amdgpu_device_resume+0xd8/0x370 [amdgpu]
>>> [   30.477379]  ? __pci_set_master+0x34/0xe0
>>> [   30.478345]  ? vga_switcheroo_fini_domain_pm_ops+0x20/0x20
>>> [   30.479317]  amdgpu_pmops_runtime_resume+0x76/0xa0 [amdgpu]
>>> [   30.480265]  pci_pm_runtime_resume+0x76/0xb0
>>> [   30.481216]  vga_switcheroo_runtime_resume+0x59/0x60
>>> [   30.482201]  __rpm_callback+0xc4/0x200
>>> [   30.483179]  ? vga_switcheroo_fini_domain_pm_ops+0x20/0x20
>>> [   30.484075]  rpm_callback+0x24/0x80
>>> [   30.485025]  ? 

Re: [PATCH 2/2] drm/doc: Make naming consistent for Core Driver Infrastructure

[Alex Deucher]

On Mon, Jun 4, 2018 at 5:11 AM, Michel Dänzer  wrote:
>
> Adding dri-devel.
>

Any opinions?

Alex

>
> On 2018-06-01 08:03 PM, Alex Deucher wrote:
>> Use chapter rather than section to align with the rst markup.
>>
>> Signed-off-by: Alex Deucher 
>> ---
>>  Documentation/gpu/amdgpu.rst | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
>> index 1d726b90a619..e99732553c71 100644
>> --- a/Documentation/gpu/amdgpu.rst
>> +++ b/Documentation/gpu/amdgpu.rst
>> @@ -8,7 +8,7 @@ Next (GCN) architecture.
>>  Core Driver Infrastructure
>>  ==
>>
>> -This section covers core driver infrastructure.
>> +This chapter covers core driver infrastructure.
>>
>>  PRIME Buffer Sharing
>>  
>
> I don't mind either way, but I copied the "section" wording from i915.rst.
>
>
> --
> Earthling Michel Dänzer   |   http://www.amd.com
> Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: Add Dell Inspiron 5575/5775 back to atpx quirk table

[Alex Deucher]

On Tue, Jun 5, 2018 at 2:47 AM, Kai-Heng Feng
 wrote:
> The original issue on these laptops was about _PR3, not audio controller
> prevents gfx auto suspending.

Have you verified that this this patch is still necessary with the HDA
driver fix in place?

Alex

>
> Commit 444d95f0eeef ("Partially revert: drm/amdgpu: add atpx quirk
> handling (v2)") breaks these laptops:
>
> [   29.572055] [drm:atom_op_jump [amdgpu]] *ERROR* atombios stuck in loop for 
> more than 5secs aborting
> [   29.572738] [drm:amdgpu_atom_execute_table_locked [amdgpu]] *ERROR* 
> atombios stuck executing 7C36 (len 272, WS 0, PS 4) @ 0x7C7F
> [   29.573436] [drm:amdgpu_atom_execute_table_locked [amdgpu]] *ERROR* 
> atombios stuck executing 6444 (len 70, WS 0, PS 8) @ 0x646A
> [   29.574125] [drm:amdgpu_device_resume [amdgpu]] *ERROR* amdgpu asic init 
> failed
> [   29.991377] amdgpu :01:00.0: Wait for MC idle timedout !
> [   30.407480] amdgpu :01:00.0: Wait for MC idle timedout !
> [   30.417279] [drm] PCIE GART of 256M enabled (table at 0x00F4).
> [   30.426550] amdgpu: [powerplay] smu not running, upload firmware again
> [   30.435710] BUG: unable to handle kernel paging request at a52b90080fec
> [   30.436982] IP: smu7_populate_single_firmware_entry.isra.5+0x65/0xe0 
> [amdgpu]
> [   30.438056] PGD 14e942067 P4D 14e942067 PUD 0
> [   30.439280] Oops: 0002 [#1] SMP NOPTI
> [   30.440339] Modules linked in: cmac bnep nls_iso8859_1 arc4 ath10k_pci 
> ath10k_core rtsx_usb_ms memstick dell_wmi uvcvideo sparse_keymap 
> videobuf2_vmalloc dell_laptop videobuf2_memops dell_smbios 
> dell_wmi_descriptor videobuf2_v4l2 btusb btrtl wmi_bmof joydev dcdbas btbcm 
> dell_smm_hwmon videobuf2_common kvm_amd btintel ath videodev 
> snd_hda_codec_realtek snd_hda_codec_hdmi snd_hda_codec_generic cdc_acm 
> mac80211 media bluetooth snd_hda_intel kvm snd_hda_codec snd_hwdep irqbypass 
> snd_hda_core ecdh_generic crct10dif_pclmul snd_pcm crc32_pclmul snd_seq 
> ghash_clmulni_intel pcbc snd_timer snd_seq_device aesni_intel cfg80211 snd 
> aes_x86_64 soundcore input_leds crypto_simd cryptd tpm_crb hid_multitouch 
> ucsi_acpi glue_helper typec_ucsi serio_raw typec video i2c_piix4 mac_hid 
> dell_rbtn shpchp wmi parport_pc ppdev
> [   30.445678]  lp parport autofs4 btrfs xor zstd_decompress zstd_compress 
> xxhash raid6_pq dm_mirror dm_region_hash dm_log amdkfd amd_iommu_v2 amdgpu 
> rtsx_usb_sdmmc rtsx_usb chash i2c_algo_bit gpu_sched drm_kms_helper 
> syscopyarea sysfillrect sysimgblt fb_sys_fops ttm drm r8169 ahci libahci 
> i2c_hid mii hid
> [   30.448702] CPU: 7 PID: 1021 Comm: gpu-manager Not tainted 4.16.0-rc7+ #1
> [   30.450256] Hardware name: Dell Inc. Inspiron 5775/Inspiron 5775, BIOS 
> 1.1.0 03/26/2018
> [   30.451959] RIP: 0010:smu7_populate_single_firmware_entry.isra.5+0x65/0xe0 
> [amdgpu]
> [   30.453492] RSP: 0018:a50f816f3a58 EFLAGS: 00010246
> [   30.455116] RAX: 008c RBX: a52b90080fec RCX: 
> 
> [   30.456676] RDX: 0004 RSI: 0004 RDI: 
> 917dfb3a5a90
> [   30.458203] RBP: a50f816f3aa8 R08: 917dfb3a5a90 R09: 
> 00033930
> [   30.459727] R10:  R11: 0412 R12: 
> 0003
> [   30.461246] R13: 917dfb194c14 R14: 917dfac65000 R15: 
> 05fe
> [   30.462733] FS:  7f5248978700() GS:917e0edc() 
> knlGS:
> [   30.464302] CS:  0010 DS:  ES:  CR0: 80050033
> [   30.465830] CR2: a52b90080fec CR3: 0001358c2000 CR4: 
> 003406e0
> [   30.467468] Call Trace:
> [   30.469068]  smu7_request_smu_load_fw+0xa9/0x360 [amdgpu]
> [   30.470630]  ? vga_switcheroo_fini_domain_pm_ops+0x20/0x20
> [   30.472416]  iceland_start_smu+0x39/0x70 [amdgpu]
> [   30.473492]  hwmgr_resume+0x2b/0xa0 [amdgpu]
> [   30.474500]  pp_resume+0x15/0x20 [amdgpu]
> [   30.475472]  amdgpu_device_ip_resume_phase2+0x58/0xb0 [amdgpu]
> [   30.476431]  amdgpu_device_resume+0xd8/0x370 [amdgpu]
> [   30.477379]  ? __pci_set_master+0x34/0xe0
> [   30.478345]  ? vga_switcheroo_fini_domain_pm_ops+0x20/0x20
> [   30.479317]  amdgpu_pmops_runtime_resume+0x76/0xa0 [amdgpu]
> [   30.480265]  pci_pm_runtime_resume+0x76/0xb0
> [   30.481216]  vga_switcheroo_runtime_resume+0x59/0x60
> [   30.482201]  __rpm_callback+0xc4/0x200
> [   30.483179]  ? vga_switcheroo_fini_domain_pm_ops+0x20/0x20
> [   30.484075]  rpm_callback+0x24/0x80
> [   30.485025]  ? vga_switcheroo_fini_domain_pm_ops+0x20/0x20
> [   30.486005]  rpm_resume+0x499/0x6a0
> [   30.486946]  __pm_runtime_resume+0x4e/0x80
> [   30.487880]  pci_config_pm_runtime_get+0x53/0x60
> [   30.488789]  pci_read_config+0x8f/0x280
> [   30.489771]  sysfs_kf_bin_read+0x4a/0x70
> [   30.490750]  kernfs_fop_read+0xa9/0x190
> [   30.491648]  __vfs_read+0x37/0x160
> [   30.492579]  ? security_file_permission+0x9b/0xc0
> [   30.493530]  vfs_read+0x93/0x130
> [   30.494445]  SyS_pread64+0x95/0xb0
> [   30.495347]  do_syscall_64+0x6d/0x120

Re: [PATCH] drm/amdgpu: Use real power source in powerplay instand of hardcode

[Alex Deucher]

On Mon, Jun 4, 2018 at 4:48 AM, Rex Zhu  wrote:
> 1. move ac_power to struct pm from dpm, so can be shared with powerplay
> 2. remove power_source in powerplay, use adev->pm.ac_power instand.
> 3. update ac_power before dispatch power task.
>
> Signed-off-by: Rex Zhu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h|  2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 21 +++--
>  drivers/gpu/drm/amd/amdgpu/ci_dpm.c| 12 
>  drivers/gpu/drm/amd/amdgpu/kv_dpm.c|  2 +-
>  drivers/gpu/drm/amd/amdgpu/si_dpm.c|  4 +--
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c|  1 -
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   |  6 ++--
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |  5 +--
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |  2 --
>  .../gpu/drm/amd/powerplay/inc/pp_power_source.h| 36 
> --
>  10 files changed, 27 insertions(+), 64 deletions(-)
>  delete mode 100644 drivers/gpu/drm/amd/powerplay/inc/pp_power_source.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> index dd6203a..9acfbee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> @@ -402,7 +402,6 @@ struct amdgpu_dpm {
> u32 tdp_adjustment;
> u16 load_line_slope;
> bool power_control;
> -   bool ac_power;
> /* special states active */
> boolthermal_active;
> booluvd_active;
> @@ -439,6 +438,7 @@ struct amdgpu_pm {
> struct amd_pp_display_configuration pm_display_cfg;/* set by dc */
> uint32_tsmu_prv_buffer_size;
> struct amdgpu_bo*smu_prv_buffer;
> +   bool ac_power;
>  };
>
>  #define R600_SSTU_DFLT   0
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index b455da4..1c49103 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -68,11 +68,11 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device 
> *adev)
> if (adev->pm.dpm_enabled) {
> mutex_lock(>pm.mutex);
> if (power_supply_is_system_supplied() > 0)
> -   adev->pm.dpm.ac_power = true;
> +   adev->pm.ac_power = true;
> else
> -   adev->pm.dpm.ac_power = false;
> +   adev->pm.ac_power = false;
> if (adev->powerplay.pp_funcs->enable_bapm)
> -   amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
> +   amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
> mutex_unlock(>pm.mutex);
> }
>  }
> @@ -1878,6 +1878,14 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device 
> *adev)
> amdgpu_fence_wait_empty(ring);
> }
>
> +   mutex_lock(>pm.mutex);
> +   /* update battery/ac status */
> +   if (power_supply_is_system_supplied() > 0)
> +   adev->pm.ac_power = true;
> +   else
> +   adev->pm.ac_power = false;
> +   mutex_unlock(>pm.mutex);
> +
> if (adev->powerplay.pp_funcs->dispatch_tasks) {
> if (!amdgpu_device_has_dc_support(adev)) {
> mutex_lock(>pm.mutex);
> @@ -1898,14 +1906,7 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device 
> *adev)
> } else {
> mutex_lock(>pm.mutex);
> amdgpu_dpm_get_active_displays(adev);
> -   /* update battery/ac status */
> -   if (power_supply_is_system_supplied() > 0)
> -   adev->pm.dpm.ac_power = true;
> -   else
> -   adev->pm.dpm.ac_power = false;
> -
> amdgpu_dpm_change_power_state_locked(adev);
> -
> mutex_unlock(>pm.mutex);
> }
>  }
> diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c 
> b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> index a266dcf..b6248c0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> @@ -951,12 +951,12 @@ static void ci_apply_state_adjust_rules(struct 
> amdgpu_device *adev,
> else
> pi->battery_state = false;
>
> -   if (adev->pm.dpm.ac_power)
> +   if (adev->pm.ac_power)
> max_limits = >pm.dpm.dyn_state.max_clock_voltage_on_ac;
> else
> max_limits = >pm.dpm.dyn_state.max_clock_voltage_on_dc;
>
> -   if (adev->pm.dpm.ac_power == false) {
> +   if (adev->pm.ac_power == false) {
> for (i = 0; i < ps->performance_level_count; i++) {
> if (ps->performance_levels[i].mclk > max_limits->mclk)
> ps->performance_levels[i].mclk = 
> 

Re: [PATCH] drm/amdgpu: Partially revert commit 2dc80b006

[Jan Vesely]

thank you. Every effort to make the patches easier to follow is appreciated.

Jan

On Wed, Jun 13, 2018 at 10:39 AM, Zhu, Rex  wrote:

> Hi Jan,
>
>
> Thanks for your suggestion. Obvious the patch title was inappropriate. I
> will update it.
>
> In fact, I originally plan to send this patch internally for discussion.
> So just thought that "Revert x" can cause the attention.
>
> Best Regards
> Rex
>
>
>
>
> --
> *From:* jv...@scarletmail.rutgers.edu  on
> behalf of Jan Vesely 
> *Sent:* Wednesday, June 13, 2018 9:30 PM
> *To:* Koenig, Christian
> *Cc:* Zhu, Rex; amd-gfx list
> *Subject:* Re: [PATCH] drm/amdgpu: Partially revert commit 2dc80b006
>
> Hi,
>
> can you please improve the commit message?
> seeing "Revert $HASH" conveys zero information about the code change.
> I'm sorry for bringing this up again, but following AMDGPU/Radeon driver
> development is an exercise in frustration for anyone who is not on AMD's
> payroll.
> git commit logs like:
> "revert XYZ" or "fix bug #123" make it really cumbersome to actually look
> at history and pick interesting/breaking commits.
>
> thanks,
> Jan
>
> On Wed, Jun 13, 2018 at 8:46 AM, Christian König <
> ckoenig.leichtzumer...@gmail.com> wrote:
>
> Am 13.06.2018 um 13:40 schrieb Rex Zhu:
>
> Move the CG enablement out of delay worker thread.
>
> 1. CG/PG enablement are part of gpu hw ip initialize, we should
> wait for them complete. otherwise, there are some potential conflicts,
> for example, Suspend and CG enablement concurrently.
> 2. better run ib test after hw initialize completely. That is to say,
> ib test should be after CG/PG enablement. otherwise, the test will
> not cover the cg/pg/poweroff enable case.
>
> Signed-off-by: Rex Zhu 
>
>
> Yeah, that thought came to my mind as well.
>
> Essentially the IB test should simulate a submission from userspace to
> make sure that the stack is working as expected. I think it was just moved
> before CG/PG to avoid issues with that, which is actually not very clever.
>
> Patch is Reviewed-by: Christian König , but
> there could be some fallout we could need to deal with.
>
> Thanks,
> Christian.
>
>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 --
>   1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 9647f54..90b78c7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1709,10 +1709,6 @@ static int amdgpu_device_ip_late_set_cg_state(struct
> amdgpu_device *adev)
> if (amdgpu_emu_mode == 1)
> return 0;
>   - r = amdgpu_ib_ring_tests(adev);
> -   if (r)
> -   DRM_ERROR("ib ring test failed (%d).\n", r);
> -
> for (i = 0; i < adev->num_ip_blocks; i++) {
> if (!adev->ip_blocks[i].status.valid)
> continue;
> @@ -1793,6 +1789,9 @@ static int amdgpu_device_ip_late_init(struct
> amdgpu_device *adev)
> }
> }
>   + amdgpu_device_ip_late_set_cg_state(adev);
> +   amdgpu_device_ip_late_set_pg_state(adev);
> +
> queue_delayed_work(system_wq, >late_init_work,
>msecs_to_jiffies(AMDGPU_RESUME_MS));
>   @@ -1921,8 +1920,11 @@ static void 
> amdgpu_device_ip_late_init_func_handler(struct
> work_struct *work)
>   {
> struct amdgpu_device *adev =
> container_of(work, struct amdgpu_device,
> late_init_work.work);
> -   amdgpu_device_ip_late_set_cg_state(adev);
> -   amdgpu_device_ip_late_set_pg_state(adev);
> +   int r;
> +
> +   r = amdgpu_ib_ring_tests(adev);
> +   if (r)
> +   DRM_ERROR("ib ring test failed (%d).\n", r);
>   }
> /**
>
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 4/7] drm/amd/pp: Add gfx pg support in smu through set_powergating_by_smu

[Zhu, Rex]

-   if (adev->powerplay.pp_funcs->powergate_mmhub)
-   amdgpu_dpm_powergate_mmhub(adev);
+   if (adev->powerplay.pp_funcs->set_powergating_by_smu)
+   amdgpu_dpm_set_powergating_by_smu(adev, 
AMD_IP_BLOCK_TYPE_GMC, 0);

Move this change to  patch3.



From: amd-gfx  on behalf of Rex Zhu 

Sent: Wednesday, June 13, 2018 7:18 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 4/7] drm/amd/pp: Add gfx pg support in smu through 
set_powergating_by_smu

gfx ip block can call set_powergating_by_smu to set gfx pg state if
necessary.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 --
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c   |  4 ++--
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 16 
 3 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 807ee0d..916776a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5591,14 +5591,12 @@ static int gfx_v8_0_late_init(void *handle)
 static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device 
*adev,
bool enable)
 {
-   if ((adev->asic_type == CHIP_POLARIS11) ||
+   if (((adev->asic_type == CHIP_POLARIS11) ||
 (adev->asic_type == CHIP_POLARIS12) ||
-   (adev->asic_type == CHIP_VEGAM))
+   (adev->asic_type == CHIP_VEGAM)) &&
+   adev->powerplay.pp_funcs->set_powergating_by_smu)
 /* Send msg to SMU via Powerplay */
-   amdgpu_device_ip_set_powergating_state(adev,
-  AMD_IP_BLOCK_TYPE_SMC,
-  enable ?
-  AMD_PG_STATE_GATE : 
AMD_PG_STATE_UNGATE);
+   amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, 
enable);

 WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 377f536..85cf2f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -471,8 +471,8 @@ void mmhub_v1_0_update_power_gating(struct amdgpu_device 
*adev,
 RENG_EXECUTE_ON_REG_UPDATE, 1);
 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, 
pctl1_reng_execute);

-   if (adev->powerplay.pp_funcs->powergate_mmhub)
-   amdgpu_dpm_powergate_mmhub(adev);
+   if (adev->powerplay.pp_funcs->set_powergating_by_smu)
+   amdgpu_dpm_set_powergating_by_smu(adev, 
AMD_IP_BLOCK_TYPE_GMC, 0);

 } else {
 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index f68551f..cb2dd7c 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1184,6 +1184,21 @@ static int pp_dpm_powergate_mmhub(void *handle)
 return hwmgr->hwmgr_func->powergate_mmhub(hwmgr);
 }

+static int pp_dpm_powergate_gfx(void *handle, bool gate)
+{
+   struct pp_hwmgr *hwmgr = handle;
+
+   if (!hwmgr || !hwmgr->pm_en)
+   return 0;
+
+   if (hwmgr->hwmgr_func->powergate_gfx == NULL) {
+   pr_info("%s was not implemented.\n", __func__);
+   return 0;
+   }
+
+   return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate);
+}
+
 static int pp_set_powergating_by_smu(void *handle,
 uint32_t block_type, bool gate)
 {
@@ -1201,6 +1216,7 @@ static int pp_set_powergating_by_smu(void *handle,
 pp_dpm_powergate_mmhub(handle);
 break;
 case AMD_IP_BLOCK_TYPE_GFX:
+   ret = pp_dpm_powergate_gfx(handle, gate);
 break;
 default:
 break;
--
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
amd-gfx Info Page - 
freedesktop.org
lists.freedesktop.org
Subscribing to amd-gfx: Subscribe to amd-gfx by filling out the following form. 
Use of all freedesktop.org lists is subject to our Code of Conduct.



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: fix typo in amdgpu_mn.c comments

[Christian König]

Am 13.06.2018 um 16:56 schrieb Slava Abramov:

In doc comments for struct amdgpu_mn: destrution -> destruction

Signed-off-by: Slava Abramov 


Good catch, Reviewed-by: Christian König .


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index 417923ba8de6..b2a9716fa41f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -58,7 +58,7 @@
   * @adev: amdgpu device pointer
   * @mm: process address space
   * @mn: MMU notifier structur
- * @work: destrution work item
+ * @work: destruction work item
   * @node: hash table node to find structure by adev and mn
   * @lock: rw semaphore protecting the notifier nodes
   * @objects: interval tree containing amdgpu_mn_nodes


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu: fix typo in amdgpu_mn.c comments

[Slava Abramov]

In doc comments for struct amdgpu_mn: destrution -> destruction

Signed-off-by: Slava Abramov 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index 417923ba8de6..b2a9716fa41f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -58,7 +58,7 @@
  * @adev: amdgpu device pointer
  * @mm: process address space
  * @mn: MMU notifier structur
- * @work: destrution work item
+ * @work: destruction work item
  * @node: hash table node to find structure by adev and mn
  * @lock: rw semaphore protecting the notifier nodes
  * @objects: interval tree containing amdgpu_mn_nodes
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: Partially revert commit 2dc80b006

[Zhu, Rex]

Hi Jan,


Thanks for your suggestion. Obvious the patch title was inappropriate. I will 
update it.

In fact, I originally plan to send this patch internally for discussion.  So 
just thought that "Revert x" can cause the attention.

Best Regards
Rex





From: jv...@scarletmail.rutgers.edu  on behalf 
of Jan Vesely 
Sent: Wednesday, June 13, 2018 9:30 PM
To: Koenig, Christian
Cc: Zhu, Rex; amd-gfx list
Subject: Re: [PATCH] drm/amdgpu: Partially revert commit 2dc80b006

Hi,

can you please improve the commit message?
seeing "Revert $HASH" conveys zero information about the code change.
I'm sorry for bringing this up again, but following AMDGPU/Radeon driver 
development is an exercise in frustration for anyone who is not on AMD's 
payroll.
git commit logs like:
"revert XYZ" or "fix bug #123" make it really cumbersome to actually look at 
history and pick interesting/breaking commits.

thanks,
Jan

On Wed, Jun 13, 2018 at 8:46 AM, Christian König 
mailto:ckoenig.leichtzumer...@gmail.com>> 
wrote:
Am 13.06.2018 um 13:40 schrieb Rex Zhu:
Move the CG enablement out of delay worker thread.

1. CG/PG enablement are part of gpu hw ip initialize, we should
wait for them complete. otherwise, there are some potential conflicts,
for example, Suspend and CG enablement concurrently.
2. better run ib test after hw initialize completely. That is to say,
ib test should be after CG/PG enablement. otherwise, the test will
not cover the cg/pg/poweroff enable case.

Signed-off-by: Rex Zhu mailto:rex@amd.com>>

Yeah, that thought came to my mind as well.

Essentially the IB test should simulate a submission from userspace to make 
sure that the stack is working as expected. I think it was just moved before 
CG/PG to avoid issues with that, which is actually not very clever.

Patch is Reviewed-by: Christian König 
mailto:christian.koe...@amd.com>>, but there could be 
some fallout we could need to deal with.

Thanks,
Christian.


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 --
  1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9647f54..90b78c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1709,10 +1709,6 @@ static int amdgpu_device_ip_late_set_cg_state(struct 
amdgpu_device *adev)
if (amdgpu_emu_mode == 1)
return 0;
  - r = amdgpu_ib_ring_tests(adev);
-   if (r)
-   DRM_ERROR("ib ring test failed (%d).\n", r);
-
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.valid)
continue;
@@ -1793,6 +1789,9 @@ static int amdgpu_device_ip_late_init(struct 
amdgpu_device *adev)
}
}
  + amdgpu_device_ip_late_set_cg_state(adev);
+   amdgpu_device_ip_late_set_pg_state(adev);
+
queue_delayed_work(system_wq, >late_init_work,
   msecs_to_jiffies(AMDGPU_RESUME_MS));
  @@ -1921,8 +1920,11 @@ static void 
amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
  {
struct amdgpu_device *adev =
container_of(work, struct amdgpu_device, 
late_init_work.work);
-   amdgpu_device_ip_late_set_cg_state(adev);
-   amdgpu_device_ip_late_set_pg_state(adev);
+   int r;
+
+   r = amdgpu_ib_ring_tests(adev);
+   if (r)
+   DRM_ERROR("ib ring test failed (%d).\n", r);
  }
/**

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v2] Update function level documentation for GPUVM v2

[Andrey Grodzovsky]

Thanks guys, note taken.

Andrey


On 06/13/2018 10:01 AM, Christian König wrote:

Am 13.06.2018 um 15:57 schrieb Michel Dänzer:

On 2018-06-13 03:52 PM, Andrey Grodzovsky wrote:

Yea, will take care of this, this particular warning is all over the
place when you compile so I didn't notice my own among others.

To avoid that problem, I recommend generating documentation first
without one's patches applied, then (without cleaning the generated
documentation first) again with them applied. The second run should only
re-generate things affected by one's patches, so it should be easy to
spot any warnings related to them.


You can also just issue an "touch $file" command to force only 
regeneration the file you're interested in.


Christian.


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v2] Update function level documentation for GPUVM v2

[Christian König]

Am 13.06.2018 um 15:57 schrieb Michel Dänzer:

On 2018-06-13 03:52 PM, Andrey Grodzovsky wrote:

Yea, will take care of this, this particular warning is all over the
place when you compile so I didn't notice my own among others.

To avoid that problem, I recommend generating documentation first
without one's patches applied, then (without cleaning the generated
documentation first) again with them applied. The second run should only
re-generate things affected by one's patches, so it should be easy to
spot any warnings related to them.


You can also just issue an "touch $file" command to force only 
regeneration the file you're interested in.


Christian.
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v2] Update function level documentation for GPUVM v2

[Michel Dänzer]

Hi Andrey,


On 2018-06-12 04:05 PM, Andrey Grodzovsky wrote:
> Add/update function level documentation and add reference to amdgpu_vm.c
> in amdgpu.rst
> 
> v2:
> Fix reference in rst file.
> Fix compilation warnings.
> Add space between function names and params list where
> it's missing.
> 
> Signed-off-by: Andrey Grodzovsky 

The warnings below now appear while generating documentation, can you
fix these up?


./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:359: warning: Function parameter or 
member 'pte_support_ats' not described in 'amdgpu_vm_clear_bo'  

 
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:697: warning: Function parameter or 
member 'job' not described in 'amdgpu_vm_flush'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1781: warning: Function parameter or 
member '_cb' not described in 'amdgpu_vm_prt_cb'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2070: warning: Function parameter or 
member 'size' not described in 'amdgpu_vm_bo_map'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2134: warning: Function parameter or 
member 'size' not described in 'amdgpu_vm_bo_replace_map'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2347: warning: Function parameter or 
member 'addr' not described in 'amdgpu_vm_bo_lookup_mapping'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2401: warning: Function parameter or 
member 'evicted' not described in 'amdgpu_vm_bo_invalidate'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2465: warning: Function parameter or 
member 'fragment_size_default' not described in 'amdgpu_vm_adjust_size'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2465: warning: Function parameter or 
member 'max_level' not described in 'amdgpu_vm_adjust_size'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2465: warning: Function parameter or 
member 'max_bits' not described in 'amdgpu_vm_adjust_size'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2536: warning: Function parameter or 
member 'pasid' not described in 'amdgpu_vm_init'


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v2] Update function level documentation for GPUVM v2

[Michel Dänzer]

On 2018-06-13 03:52 PM, Andrey Grodzovsky wrote:
> Yea, will take care of this, this particular warning is all over the
> place when you compile so I didn't notice my own among others.

To avoid that problem, I recommend generating documentation first
without one's patches applied, then (without cleaning the generated
documentation first) again with them applied. The second run should only
re-generate things affected by one's patches, so it should be easy to
spot any warnings related to them.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amd/pp: Add S3 support for OD feature

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Rex Zhu 

Sent: Wednesday, June 13, 2018 6:34:44 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH] drm/amd/pp: Add S3 support for OD feature

make custom values survive when S3 sleep transitions.
so not reset the od table if it is not null.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 126 +++--
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |  79 +++--
 2 files changed, 107 insertions(+), 98 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 00614d0..b73e200 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -885,6 +885,60 @@ static void smu7_setup_voltage_range_from_vbios(struct 
pp_hwmgr *hwmgr)
 data->odn_dpm_table.max_vddc = max_vddc;
 }

+static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
+{
+   struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+   struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
+   struct phm_ppt_v1_information *table_info =
+   (struct phm_ppt_v1_information *)(hwmgr->pptable);
+   uint32_t i;
+
+   struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
+   struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
+
+   if (table_info == NULL)
+   return;
+
+   for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
+   if (odn_table->odn_core_clock_dpm_levels.entries[i].clock !=
+   
data->dpm_table.sclk_table.dpm_levels[i].value) {
+   data->need_update_smu7_dpm_table |= 
DPMTABLE_OD_UPDATE_SCLK;
+   break;
+   }
+   }
+
+   for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
+   if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
+   
data->dpm_table.mclk_table.dpm_levels[i].value) {
+   data->need_update_smu7_dpm_table |= 
DPMTABLE_OD_UPDATE_MCLK;
+   break;
+   }
+   }
+
+   dep_table = table_info->vdd_dep_on_mclk;
+   odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table 
*)&(odn_table->vdd_dependency_on_mclk);
+
+   for (i = 0; i < dep_table->count; i++) {
+   if (dep_table->entries[i].vddc != 
odn_dep_table->entries[i].vddc) {
+   data->need_update_smu7_dpm_table |= 
DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
+   return;
+   }
+   }
+
+   dep_table = table_info->vdd_dep_on_sclk;
+   odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table 
*)&(odn_table->vdd_dependency_on_sclk);
+   for (i = 0; i < dep_table->count; i++) {
+   if (dep_table->entries[i].vddc != 
odn_dep_table->entries[i].vddc) {
+   data->need_update_smu7_dpm_table |= 
DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
+   return;
+   }
+   }
+   if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
+   data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
+   data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | 
DPMTABLE_OD_UPDATE_MCLK;
+   }
+}
+
 static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 {
 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -904,10 +958,13 @@ static int smu7_setup_default_dpm_tables(struct pp_hwmgr 
*hwmgr)

 /* initialize ODN table */
 if (hwmgr->od_enabled) {
-   smu7_setup_voltage_range_from_vbios(hwmgr);
-   smu7_odn_initial_default_setting(hwmgr);
+   if (data->odn_dpm_table.max_vddc) {
+   smu7_check_dpm_table_updated(hwmgr);
+   } else {
+   smu7_setup_voltage_range_from_vbios(hwmgr);
+   smu7_odn_initial_default_setting(hwmgr);
+   }
 }
-
 return 0;
 }

@@ -3717,8 +3774,9 @@ static int smu7_trim_single_dpm_states(struct pp_hwmgr 
*hwmgr,
 uint32_t i;

 for (i = 0; i < dpm_table->count; i++) {
-   if ((dpm_table->dpm_levels[i].value < low_limit)
-   || (dpm_table->dpm_levels[i].value > high_limit))
+   /*skip the trim if od is enabled*/
+   if (!hwmgr->od_enabled && (dpm_table->dpm_levels[i].value < 
low_limit
+   || dpm_table->dpm_levels[i].value > high_limit))
 dpm_table->dpm_levels[i].enabled = false;
 else
 dpm_table->dpm_levels[i].enabled = true;
@@ -3762,10 +3820,8 @@ static int smu7_generate_dpm_level_enable_mask(
 

Re: [PATCH v2] Update function level documentation for GPUVM v2

[Andrey Grodzovsky]

Yea, will take care of this, this particular warning is all over the 
place when you compile so I didn't notice my own among others.


Andrey


On 06/13/2018 09:48 AM, Michel Dänzer wrote:

Hi Andrey,


On 2018-06-12 04:05 PM, Andrey Grodzovsky wrote:

Add/update function level documentation and add reference to amdgpu_vm.c
in amdgpu.rst

v2:
Fix reference in rst file.
Fix compilation warnings.
Add space between function names and params list where
it's missing.

Signed-off-by: Andrey Grodzovsky 

The warnings below now appear while generating documentation, can you
fix these up?


./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:359: warning: Function parameter or 
member 'pte_support_ats' not described in 'amdgpu_vm_clear_bo'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:697: warning: Function parameter or 
member 'job' not described in 'amdgpu_vm_flush'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1781: warning: Function parameter or 
member '_cb' not described in 'amdgpu_vm_prt_cb'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2070: warning: Function parameter or 
member 'size' not described in 'amdgpu_vm_bo_map'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2134: warning: Function parameter or 
member 'size' not described in 'amdgpu_vm_bo_replace_map'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2347: warning: Function parameter or 
member 'addr' not described in 'amdgpu_vm_bo_lookup_mapping'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2401: warning: Function parameter or 
member 'evicted' not described in 'amdgpu_vm_bo_invalidate'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2465: warning: Function parameter or 
member 'fragment_size_default' not described in 'amdgpu_vm_adjust_size'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2465: warning: Function parameter or 
member 'max_level' not described in 'amdgpu_vm_adjust_size'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2465: warning: Function parameter or 
member 'max_bits' not described in 'amdgpu_vm_adjust_size'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2536: warning: Function parameter or 
member 'pasid' not described in 'amdgpu_vm_init'




___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amd/pp: Remove SAMU support in powerplay

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Rex Zhu 

Sent: Wednesday, June 13, 2018 3:34:05 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH] drm/amd/pp: Remove SAMU support in powerplay

As the SAMU ip was not supported in linux,
so delete the SAMU support in powerplay on
asics Bonarire/Hawwii/Tonga/Fiji/Polaris/vegam.

Signed-off-by: Rex Zhu 
---
 .../amd/powerplay/hwmgr/smu7_clockpowergating.c| 54 --
 .../amd/powerplay/hwmgr/smu7_clockpowergating.h|  1 -
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   |  1 -
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h   |  1 -
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h |  1 -
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h |  2 -
 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c   | 35 -
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 74 ---
 .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c  | 10 ---
 .../drm/amd/powerplay/smumgr/polaris10_smumgr.c| 86 --
 .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c| 80 
 .../gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c| 85 -
 12 files changed, 430 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
index 6d72a56..4149562 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
@@ -39,13 +39,6 @@ static int smu7_enable_disable_vce_dpm(struct pp_hwmgr 
*hwmgr, bool enable)
 PPSMC_MSG_VCEDPM_Disable);
 }

-static int smu7_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
-{
-   return smum_send_msg_to_smc(hwmgr, enable ?
-   PPSMC_MSG_SAMUDPM_Enable :
-   PPSMC_MSG_SAMUDPM_Disable);
-}
-
 static int smu7_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
 {
 if (!bgate)
@@ -60,13 +53,6 @@ static int smu7_update_vce_dpm(struct pp_hwmgr *hwmgr, bool 
bgate)
 return smu7_enable_disable_vce_dpm(hwmgr, !bgate);
 }

-static int smu7_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
-{
-   if (!bgate)
-   smum_update_smc_table(hwmgr, SMU_SAMU_TABLE);
-   return smu7_enable_disable_samu_dpm(hwmgr, !bgate);
-}
-
 int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr)
 {
 if (phm_cf_want_uvd_power_gating(hwmgr))
@@ -107,35 +93,15 @@ static int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
 return 0;
 }

-static int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
-{
-   if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-   PHM_PlatformCaps_SamuPowerGating))
-   return smum_send_msg_to_smc(hwmgr,
-   PPSMC_MSG_SAMPowerOFF);
-   return 0;
-}
-
-static int smu7_powerup_samu(struct pp_hwmgr *hwmgr)
-{
-   if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-   PHM_PlatformCaps_SamuPowerGating))
-   return smum_send_msg_to_smc(hwmgr,
-   PPSMC_MSG_SAMPowerON);
-   return 0;
-}
-
 int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr)
 {
 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);

 data->uvd_power_gated = false;
 data->vce_power_gated = false;
-   data->samu_power_gated = false;

 smu7_powerup_uvd(hwmgr);
 smu7_powerup_vce(hwmgr);
-   smu7_powerup_samu(hwmgr);

 return 0;
 }
@@ -195,26 +161,6 @@ void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
 }
 }

-int smu7_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate)
-{
-   struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
-   if (data->samu_power_gated == bgate)
-   return 0;
-
-   data->samu_power_gated = bgate;
-
-   if (bgate) {
-   smu7_update_samu_dpm(hwmgr, true);
-   smu7_powerdown_samu(hwmgr);
-   } else {
-   smu7_powerup_samu(hwmgr);
-   smu7_update_samu_dpm(hwmgr, false);
-   }
-
-   return 0;
-}
-
 int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
 const uint32_t *msg_id)
 {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
index 1ddce02..be7f66d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
@@ -29,7 +29,6 @@
 void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
 void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
 int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr);
-int smu7_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate);
 int smu7_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
 int 

Re: [PATCH] drm/amdgpu: Partially revert commit 2dc80b006

[William Lewis]

On 06/13/2018 08:30 AM, Jan Vesely wrote:
Hi,

can you please improve the commit message?
seeing "Revert $HASH" conveys zero information about the code change.
I'm sorry for bringing this up again, but following AMDGPU/Radeon driver 
development is an exercise in frustration for anyone who is not on AMD's 
payroll.
git commit logs like:
"revert XYZ" or "fix bug #123" make it really cumbersome to actually look at 
history and pick interesting/breaking commits.

thanks,
Jan
Just a polite agreement and seconding here.  The abundance of acronyms is 
confusing but understandable, and the weekly dumps of DC updates show not a bit 
of dialog about how or why the patches were written.  Although I read the rest 
of the emails to the list, I can usually just mark that set of 18 to 30 mails 
as read and send it straight to the trash.  It's too much work to glean useful 
information from them.

Regards,
Will


On Wed, Jun 13, 2018 at 8:46 AM, Christian König 
mailto:ckoenig.leichtzumer...@gmail.com>> 
wrote:
Am 13.06.2018 um 13:40 schrieb Rex Zhu:
Move the CG enablement out of delay worker thread.

1. CG/PG enablement are part of gpu hw ip initialize, we should
wait for them complete. otherwise, there are some potential conflicts,
for example, Suspend and CG enablement concurrently.
2. better run ib test after hw initialize completely. That is to say,
ib test should be after CG/PG enablement. otherwise, the test will
not cover the cg/pg/poweroff enable case.

Signed-off-by: Rex Zhu mailto:rex@amd.com>>

Yeah, that thought came to my mind as well.

Essentially the IB test should simulate a submission from userspace to make 
sure that the stack is working as expected. I think it was just moved before 
CG/PG to avoid issues with that, which is actually not very clever.

Patch is Reviewed-by: Christian König 
mailto:christian.koe...@amd.com>>, but there could be 
some fallout we could need to deal with.

Thanks,
Christian.


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 --
  1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9647f54..90b78c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1709,10 +1709,6 @@ static int amdgpu_device_ip_late_set_cg_state(struct 
amdgpu_device *adev)
if (amdgpu_emu_mode == 1)
return 0;
  - r = amdgpu_ib_ring_tests(adev);
-   if (r)
-   DRM_ERROR("ib ring test failed (%d).\n", r);
-
for (i = 0; i < adev->num_ip_blocks; i++) {
if 
(!adev->ip_blocks[i].status.valid)
continue;
@@ -1793,6 +1789,9 @@ static int amdgpu_device_ip_late_init(struct 
amdgpu_device *adev)
}
}
  + amdgpu_device_ip_late_set_cg_state(adev);
+   amdgpu_device_ip_late_set_pg_state(adev);
+
queue_delayed_work(system_wq, >late_init_work,
   msecs_to_jiffies(AMDGPU_RESUME_MS));
  @@ -1921,8 +1920,11 @@ static void 
amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
  {
struct amdgpu_device *adev =
container_of(work, struct amdgpu_device, 
late_init_work.work);
-   amdgpu_device_ip_late_set_cg_state(adev);
-   amdgpu_device_ip_late_set_pg_state(adev);
+   int r;
+
+   r = amdgpu_ib_ring_tests(adev);
+   if (r)
+   DRM_ERROR("ib ring test failed (%d).\n", r);
  }
/**

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx




___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx=02%7C01%7C%7C3869c12d0e1d489d0f1b08d5d131d2d5%7C84df9e7fe9f640afb435%7C1%7C0%7C636644934270387474=EllXqELZzZXDFafao7ingUyBAK4bl2T4Ja54uqdzR%2BE%3D=0


___
amd-gfx mailing list

Re: [PATCH] drm/amdgpu: Partially revert commit 2dc80b006

[Jan Vesely]

Hi,

can you please improve the commit message?
seeing "Revert $HASH" conveys zero information about the code change.
I'm sorry for bringing this up again, but following AMDGPU/Radeon driver
development is an exercise in frustration for anyone who is not on AMD's
payroll.
git commit logs like:
"revert XYZ" or "fix bug #123" make it really cumbersome to actually look
at history and pick interesting/breaking commits.

thanks,
Jan

On Wed, Jun 13, 2018 at 8:46 AM, Christian König <
ckoenig.leichtzumer...@gmail.com> wrote:

> Am 13.06.2018 um 13:40 schrieb Rex Zhu:
>
>> Move the CG enablement out of delay worker thread.
>>
>> 1. CG/PG enablement are part of gpu hw ip initialize, we should
>> wait for them complete. otherwise, there are some potential conflicts,
>> for example, Suspend and CG enablement concurrently.
>> 2. better run ib test after hw initialize completely. That is to say,
>> ib test should be after CG/PG enablement. otherwise, the test will
>> not cover the cg/pg/poweroff enable case.
>>
>> Signed-off-by: Rex Zhu 
>>
>
> Yeah, that thought came to my mind as well.
>
> Essentially the IB test should simulate a submission from userspace to
> make sure that the stack is working as expected. I think it was just moved
> before CG/PG to avoid issues with that, which is actually not very clever.
>
> Patch is Reviewed-by: Christian König , but
> there could be some fallout we could need to deal with.
>
> Thanks,
> Christian.
>
>
> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 --
>>   1 file changed, 8 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> index 9647f54..90b78c7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> @@ -1709,10 +1709,6 @@ static int amdgpu_device_ip_late_set_cg_state(struct
>> amdgpu_device *adev)
>> if (amdgpu_emu_mode == 1)
>> return 0;
>>   - r = amdgpu_ib_ring_tests(adev);
>> -   if (r)
>> -   DRM_ERROR("ib ring test failed (%d).\n", r);
>> -
>> for (i = 0; i < adev->num_ip_blocks; i++) {
>> if (!adev->ip_blocks[i].status.valid)
>> continue;
>> @@ -1793,6 +1789,9 @@ static int amdgpu_device_ip_late_init(struct
>> amdgpu_device *adev)
>> }
>> }
>>   + amdgpu_device_ip_late_set_cg_state(adev);
>> +   amdgpu_device_ip_late_set_pg_state(adev);
>> +
>> queue_delayed_work(system_wq, >late_init_work,
>>msecs_to_jiffies(AMDGPU_RESUME_MS));
>>   @@ -1921,8 +1920,11 @@ static void 
>> amdgpu_device_ip_late_init_func_handler(struct
>> work_struct *work)
>>   {
>> struct amdgpu_device *adev =
>> container_of(work, struct amdgpu_device,
>> late_init_work.work);
>> -   amdgpu_device_ip_late_set_cg_state(adev);
>> -   amdgpu_device_ip_late_set_pg_state(adev);
>> +   int r;
>> +
>> +   r = amdgpu_ib_ring_tests(adev);
>> +   if (r)
>> +   DRM_ERROR("ib ring test failed (%d).\n", r);
>>   }
>> /**
>>
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: Partially revert commit 2dc80b006

[Christian König]

Am 13.06.2018 um 13:40 schrieb Rex Zhu:

Move the CG enablement out of delay worker thread.

1. CG/PG enablement are part of gpu hw ip initialize, we should
wait for them complete. otherwise, there are some potential conflicts,
for example, Suspend and CG enablement concurrently.
2. better run ib test after hw initialize completely. That is to say,
ib test should be after CG/PG enablement. otherwise, the test will
not cover the cg/pg/poweroff enable case.

Signed-off-by: Rex Zhu 


Yeah, that thought came to my mind as well.

Essentially the IB test should simulate a submission from userspace to 
make sure that the stack is working as expected. I think it was just 
moved before CG/PG to avoid issues with that, which is actually not very 
clever.


Patch is Reviewed-by: Christian König , but 
there could be some fallout we could need to deal with.


Thanks,
Christian.


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 --
  1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9647f54..90b78c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1709,10 +1709,6 @@ static int amdgpu_device_ip_late_set_cg_state(struct 
amdgpu_device *adev)
if (amdgpu_emu_mode == 1)
return 0;
  
-	r = amdgpu_ib_ring_tests(adev);

-   if (r)
-   DRM_ERROR("ib ring test failed (%d).\n", r);
-
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.valid)
continue;
@@ -1793,6 +1789,9 @@ static int amdgpu_device_ip_late_init(struct 
amdgpu_device *adev)
}
}
  
+	amdgpu_device_ip_late_set_cg_state(adev);

+   amdgpu_device_ip_late_set_pg_state(adev);
+
queue_delayed_work(system_wq, >late_init_work,
   msecs_to_jiffies(AMDGPU_RESUME_MS));
  
@@ -1921,8 +1920,11 @@ static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work)

  {
struct amdgpu_device *adev =
container_of(work, struct amdgpu_device, late_init_work.work);
-   amdgpu_device_ip_late_set_cg_state(adev);
-   amdgpu_device_ip_late_set_pg_state(adev);
+   int r;
+
+   r = amdgpu_ib_ring_tests(adev);
+   if (r)
+   DRM_ERROR("ib ring test failed (%d).\n", r);
  }
  
  /**


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu: Partially revert commit 2dc80b006

[Rex Zhu]

Move the CG enablement out of delay worker thread.

1. CG/PG enablement are part of gpu hw ip initialize, we should
wait for them complete. otherwise, there are some potential conflicts,
for example, Suspend and CG enablement concurrently.
2. better run ib test after hw initialize completely. That is to say,
   ib test should be after CG/PG enablement. otherwise, the test will
   not cover the cg/pg/poweroff enable case.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9647f54..90b78c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1709,10 +1709,6 @@ static int amdgpu_device_ip_late_set_cg_state(struct 
amdgpu_device *adev)
if (amdgpu_emu_mode == 1)
return 0;
 
-   r = amdgpu_ib_ring_tests(adev);
-   if (r)
-   DRM_ERROR("ib ring test failed (%d).\n", r);
-
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.valid)
continue;
@@ -1793,6 +1789,9 @@ static int amdgpu_device_ip_late_init(struct 
amdgpu_device *adev)
}
}
 
+   amdgpu_device_ip_late_set_cg_state(adev);
+   amdgpu_device_ip_late_set_pg_state(adev);
+
queue_delayed_work(system_wq, >late_init_work,
   msecs_to_jiffies(AMDGPU_RESUME_MS));
 
@@ -1921,8 +1920,11 @@ static void 
amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
 {
struct amdgpu_device *adev =
container_of(work, struct amdgpu_device, late_init_work.work);
-   amdgpu_device_ip_late_set_cg_state(adev);
-   amdgpu_device_ip_late_set_pg_state(adev);
+   int r;
+
+   r = amdgpu_ib_ring_tests(adev);
+   if (r)
+   DRM_ERROR("ib ring test failed (%d).\n", r);
 }
 
 /**
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v2 7/7] drm/amdgpu: Change PG enable sequence

[Rex Zhu]

Enable PG state after CG enabled.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 33 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  |  4 
 2 files changed, 28 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index caf588d..9647f54 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1732,12 +1732,34 @@ static int amdgpu_device_ip_late_set_cg_state(struct 
amdgpu_device *adev)
}
}
 
-   if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
-   /* enable gfx powergating */
-   amdgpu_device_ip_set_powergating_state(adev,
-  AMD_IP_BLOCK_TYPE_GFX,
-  AMD_PG_STATE_GATE);
+   return 0;
+}
+
+static int amdgpu_device_ip_late_set_pg_state(struct amdgpu_device *adev)
+{
+   int i = 0, r;
 
+   if (amdgpu_emu_mode == 1)
+   return 0;
+
+   for (i = 0; i < adev->num_ip_blocks; i++) {
+   if (!adev->ip_blocks[i].status.valid)
+   continue;
+   /* skip CG for VCE/UVD, it's handled specially */
+   if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
+   adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
+   adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
+   adev->ip_blocks[i].version->funcs->set_powergating_state) {
+   /* enable powergating to save power */
+   r = 
adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
+   
 AMD_PG_STATE_GATE);
+   if (r) {
+   DRM_ERROR("set_powergating_state(gate) of IP 
block <%s> failed %d\n",
+ 
adev->ip_blocks[i].version->funcs->name, r);
+   return r;
+   }
+   }
+   }
return 0;
 }
 
@@ -1900,6 +1922,7 @@ static void 
amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
struct amdgpu_device *adev =
container_of(work, struct amdgpu_device, late_init_work.work);
amdgpu_device_ip_late_set_cg_state(adev);
+   amdgpu_device_ip_late_set_pg_state(adev);
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 916776a..2a860ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5581,10 +5581,6 @@ static int gfx_v8_0_late_init(void *handle)
return r;
}
 
-   amdgpu_device_ip_set_powergating_state(adev,
-  AMD_IP_BLOCK_TYPE_GFX,
-  AMD_PG_STATE_GATE);
-
return 0;
 }
 
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v2 6/7] drm/amdgpu: Make gfx_off control by GFX ip

[Rex Zhu]

gfx off should be controlled by GFX IP.
Powerplay only export interface to gfx ip.
This logic is same as uvd/vce cg/pg.

1. Delete the gfx pg/off ctrl code in pp_set_powergating_state
   this ip function is for smu pg enablement.
2. call set_powergating_by_smu to enable/disalbe power off feature.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 19 +++
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |  4 
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 25 +
 3 files changed, 12 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3adef57..caf588d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1732,16 +1732,11 @@ static int amdgpu_device_ip_late_set_cg_state(struct 
amdgpu_device *adev)
}
}
 
-   if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) {
+   if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
/* enable gfx powergating */
amdgpu_device_ip_set_powergating_state(adev,
   AMD_IP_BLOCK_TYPE_GFX,
   AMD_PG_STATE_GATE);
-   /* enable gfxoff */
-   amdgpu_device_ip_set_powergating_state(adev,
-  AMD_IP_BLOCK_TYPE_SMC,
-  AMD_PG_STATE_GATE);
-   }
 
return 0;
 }
@@ -1814,6 +1809,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
*adev)
  
adev->ip_blocks[i].version->funcs->name, r);
return r;
}
+   if (adev->powerplay.pp_funcs->set_powergating_by_smu)
+   amdgpu_dpm_set_powergating_by_smu(adev, 
AMD_IP_BLOCK_TYPE_GFX, false);
r = adev->ip_blocks[i].version->funcs->hw_fini((void 
*)adev);
/* XXX handle errors */
if (r) {
@@ -1923,12 +1920,6 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
if (amdgpu_sriov_vf(adev))
amdgpu_virt_request_full_gpu(adev, false);
 
-   /* ungate SMC block powergating */
-   if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
-   amdgpu_device_ip_set_powergating_state(adev,
-  AMD_IP_BLOCK_TYPE_SMC,
-  AMD_CG_STATE_UNGATE);
-
/* ungate SMC block first */
r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
   AMD_CG_STATE_UNGATE);
@@ -1936,6 +1927,10 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r);
}
 
+   /* call smu to disable gfx off feature first when suspend */
+   if (adev->powerplay.pp_funcs->set_powergating_by_smu)
+   amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, 
false);
+
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_blocks[i].status.valid)
continue;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ae35bbe..bec5592 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3715,6 +3715,10 @@ static int gfx_v9_0_set_powergating_state(void *handle,
 
/* update mgcg state */
gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
+
+   /* set gfx off through smu */
+   if (enable && adev->powerplay.pp_funcs->set_powergating_by_smu)
+   amdgpu_dpm_set_powergating_by_smu(adev, 
AMD_IP_BLOCK_TYPE_GFX, true);
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index cb2dd7c..387a1eb 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -221,30 +221,7 @@ static int pp_sw_reset(void *handle)
 static int pp_set_powergating_state(void *handle,
enum amd_powergating_state state)
 {
-   struct amdgpu_device *adev = handle;
-   struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
-   int ret;
-
-   if (!hwmgr || !hwmgr->pm_en)
-   return 0;
-
-   if (hwmgr->hwmgr_func->gfx_off_control) {
-   /* Enable/disable GFX off through SMU */
-   ret = hwmgr->hwmgr_func->gfx_off_control(hwmgr,
-state == 
AMD_PG_STATE_GATE);
-   if (ret)
-   

[PATCH 7/7] drm/amdgpu: Make gfx_off control by GFX ip

[Rex Zhu]

gfx off should be controlled by GFX IP.
Powerplay only export interface to gfx ip.
This logic is same as uvd/vce cg/pg.

1. Delete the gfx pg/off ctrl code in pp_set_powergating_state
   this ip function is for smu pg enablement.
2. call set_powergating_by_smu to enable/disalbe power off feature.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 12 ++--
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |  4 
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 25 +
 3 files changed, 11 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5086f9f..e50a053 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1842,6 +1842,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
*adev)
  
adev->ip_blocks[i].version->funcs->name, r);
return r;
}
+   if (adev->powerplay.pp_funcs->set_powergating_by_smu)
+   amdgpu_dpm_set_powergating_by_smu(adev, 
AMD_IP_BLOCK_TYPE_GFX, false);
r = adev->ip_blocks[i].version->funcs->hw_fini((void 
*)adev);
/* XXX handle errors */
if (r) {
@@ -1952,12 +1954,6 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
if (amdgpu_sriov_vf(adev))
amdgpu_virt_request_full_gpu(adev, false);
 
-   /* ungate SMC block powergating */
-   if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
-   amdgpu_device_ip_set_powergating_state(adev,
-  AMD_IP_BLOCK_TYPE_SMC,
-  AMD_CG_STATE_UNGATE);
-
/* ungate SMC block first */
r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
   AMD_CG_STATE_UNGATE);
@@ -1965,6 +1961,10 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r);
}
 
+   /* call smu to disable gfx off feature first when suspend */
+   if (adev->powerplay.pp_funcs->set_powergating_by_smu)
+   amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, 
false);
+
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_blocks[i].status.valid)
continue;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ae35bbe..bec5592 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3715,6 +3715,10 @@ static int gfx_v9_0_set_powergating_state(void *handle,
 
/* update mgcg state */
gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
+
+   /* set gfx off through smu */
+   if (enable && adev->powerplay.pp_funcs->set_powergating_by_smu)
+   amdgpu_dpm_set_powergating_by_smu(adev, 
AMD_IP_BLOCK_TYPE_GFX, true);
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index cb2dd7c..387a1eb 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -221,30 +221,7 @@ static int pp_sw_reset(void *handle)
 static int pp_set_powergating_state(void *handle,
enum amd_powergating_state state)
 {
-   struct amdgpu_device *adev = handle;
-   struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
-   int ret;
-
-   if (!hwmgr || !hwmgr->pm_en)
-   return 0;
-
-   if (hwmgr->hwmgr_func->gfx_off_control) {
-   /* Enable/disable GFX off through SMU */
-   ret = hwmgr->hwmgr_func->gfx_off_control(hwmgr,
-state == 
AMD_PG_STATE_GATE);
-   if (ret)
-   pr_err("gfx off control failed!\n");
-   }
-
-   if (hwmgr->hwmgr_func->powergate_gfx == NULL) {
-   pr_info("%s was not implemented.\n", __func__);
-   return 0;
-   }
-
-   /* Enable/disable GFX per cu powergating through SMU */
-   return hwmgr->hwmgr_func->powergate_gfx(hwmgr,
-   state == AMD_PG_STATE_GATE);
-
+   return 0;
 }
 
 static int pp_suspend(void *handle)
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 5/7] drm/amd/pp: Add powergate_gfx backend function on Raven

[Rex Zhu]

Raven support gfx off feature instand of gfx powergate,
so use smu10_gfx_off_control as the powergate_gfx backend function.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 0f8352c..0bbf11d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1186,6 +1186,7 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, 
bool bgate)
.smus_notify_pwe = smu10_smus_notify_pwe,
.gfx_off_control = smu10_gfx_off_control,
.display_clock_voltage_request = smu10_display_clock_voltage_request,
+   .powergate_gfx = smu10_gfx_off_control,
 };
 
 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/7] drm/amd/pp: Unify powergate_uvd/vce/mmhub to set_powergating_by_smu

[Rex Zhu]

Some HW ip blocks need call SMU to enter/leave power gate state.
So export common set_powergating_by_smu interface.

1. keep consistent with set_clockgating_by_smu
2. scales easily to powergate other ip(gfx) if necessary

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h| 14 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c |  8 +++
 drivers/gpu/drm/amd/amdgpu/ci_dpm.c| 15 -
 drivers/gpu/drm/amd/amdgpu/kv_dpm.c| 15 -
 drivers/gpu/drm/amd/include/kgd_pp_interface.h |  5 ++---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 29 +++---
 6 files changed, 64 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index c6d6926..ff24e1c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -287,12 +287,6 @@ enum amdgpu_pcie_gen {
 #define amdgpu_dpm_force_performance_level(adev, l) \

((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle,
 (l)))
 
-#define amdgpu_dpm_powergate_uvd(adev, g) \
-   
((adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)))
-
-#define amdgpu_dpm_powergate_vce(adev, g) \
-   
((adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)))
-
 #define amdgpu_dpm_get_current_power_state(adev) \

((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
 
@@ -347,6 +341,10 @@ enum amdgpu_pcie_gen {
((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
(adev)->powerplay.pp_handle, msg_id))
 
+#define amdgpu_dpm_set_powergating_by_smu(adev, block_type, gate) \
+   ((adev)->powerplay.pp_funcs->set_powergating_by_smu(\
+   (adev)->powerplay.pp_handle, block_type, gate))
+
 #define amdgpu_dpm_get_power_profile_mode(adev, buf) \
((adev)->powerplay.pp_funcs->get_power_profile_mode(\
(adev)->powerplay.pp_handle, buf))
@@ -359,10 +357,6 @@ enum amdgpu_pcie_gen {
((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
(adev)->powerplay.pp_handle, type, parameter, size))
 
-#define amdgpu_dpm_powergate_mmhub(adev) \
-   ((adev)->powerplay.pp_funcs->powergate_mmhub( \
-   (adev)->powerplay.pp_handle))
-
 struct amdgpu_dpm {
struct amdgpu_ps*ps;
/* number of valid power states */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 1c49103..90e84a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1668,10 +1668,10 @@ static void amdgpu_dpm_change_power_state_locked(struct 
amdgpu_device *adev)
 
 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
 {
-   if (adev->powerplay.pp_funcs->powergate_uvd) {
+   if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
/* enable/disable UVD */
mutex_lock(>pm.mutex);
-   amdgpu_dpm_powergate_uvd(adev, !enable);
+   amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, 
!enable);
mutex_unlock(>pm.mutex);
} else {
if (enable) {
@@ -1690,10 +1690,10 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, 
bool enable)
 
 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
 {
-   if (adev->powerplay.pp_funcs->powergate_vce) {
+   if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
/* enable/disable VCE */
mutex_lock(>pm.mutex);
-   amdgpu_dpm_powergate_vce(adev, !enable);
+   amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, 
!enable);
mutex_unlock(>pm.mutex);
} else {
if (enable) {
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index b6248c0..85b3f46 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -6764,6 +6764,19 @@ static int ci_dpm_read_sensor(void *handle, int idx,
}
 }
 
+static int ci_set_powergating_by_smu(void *handle,
+   uint32_t block_type, bool gate)
+{
+   switch (block_type) {
+   case AMD_IP_BLOCK_TYPE_UVD:
+   ci_dpm_powergate_uvd(handle, gate);
+   break;
+   default:
+   break;
+   }
+   return 0;
+}
+
 static const struct amd_ip_funcs ci_dpm_ip_funcs = {
.name = "ci_dpm",
.early_init = ci_dpm_early_init,
@@ -6801,7 +6814,7 @@ static int ci_dpm_read_sensor(void *handle, int idx,
.debugfs_print_current_performance_level = 
_dpm_debugfs_print_current_performance_level,
.force_performance_level = _dpm_force_performance_level,

[PATCH 2/7] drm/amd/pp: Rename enable_per_cu_power_gating to powergate_gfx

[Rex Zhu]

keep consistent with powergate_uvd/vce/mmhub

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c   | 6 +++---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c | 2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h | 2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c| 2 +-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h   | 2 +-
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index da98208..b69da11 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -236,13 +236,13 @@ static int pp_set_powergating_state(void *handle,
pr_err("gfx off control failed!\n");
}
 
-   if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
-   pr_debug("%s was not implemented.\n", __func__);
+   if (hwmgr->hwmgr_func->powergate_gfx == NULL) {
+   pr_info("%s was not implemented.\n", __func__);
return 0;
}
 
/* Enable/disable GFX per cu powergating through SMU */
-   return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr,
+   return hwmgr->hwmgr_func->powergate_gfx(hwmgr,
state == AMD_PG_STATE_GATE);
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
index 4149562..683b29a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
@@ -416,7 +416,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
  * Powerplay will only control the static per CU Power Gating.
  * Dynamic per CU Power Gating will be done in gfx.
  */
-int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable)
+int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable)
 {
struct amdgpu_device *adev = hwmgr->adev;
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
index be7f66d..fc8f8a6 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
@@ -33,6 +33,6 @@
 int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
 int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
const uint32_t *msg_id);
-int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable);
+int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable);
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index b73e200..b4c93a9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -5044,7 +5044,7 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr 
*hwmgr, long *input, uint
.get_fan_control_mode = smu7_get_fan_control_mode,
.force_clock_level = smu7_force_clock_level,
.print_clock_levels = smu7_print_clock_levels,
-   .enable_per_cu_power_gating = smu7_enable_per_cu_power_gating,
+   .powergate_gfx = smu7_powergate_gfx,
.get_sclk_od = smu7_get_sclk_od,
.set_sclk_od = smu7_set_sclk_od,
.get_mclk_od = smu7_get_mclk_od,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 9b07d6e..95e29a2 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -302,7 +302,7 @@ struct pp_hwmgr_func {
int (*power_off_asic)(struct pp_hwmgr *hwmgr);
int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type 
type, uint32_t mask);
int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type 
type, char *buf);
-   int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);
+   int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable);
int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/7] drm/amdgpu: Rename set_mmhub_powergating_by_smu to powergate_mmhub

[Rex Zhu]

In order to keep consistent with powergate_uvd/vce.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h   | 4 ++--
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c   | 4 ++--
 drivers/gpu/drm/amd/include/kgd_pp_interface.h| 2 +-
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 8 
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 4 ++--
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 +-
 6 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 9acfbee..c6d6926 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -359,8 +359,8 @@ enum amdgpu_pcie_gen {
((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
(adev)->powerplay.pp_handle, type, parameter, size))
 
-#define amdgpu_dpm_set_mmhub_powergating_by_smu(adev) \
-   ((adev)->powerplay.pp_funcs->set_mmhub_powergating_by_smu( \
+#define amdgpu_dpm_powergate_mmhub(adev) \
+   ((adev)->powerplay.pp_funcs->powergate_mmhub( \
(adev)->powerplay.pp_handle))
 
 struct amdgpu_dpm {
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 3d53c44..377f536 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -471,8 +471,8 @@ void mmhub_v1_0_update_power_gating(struct amdgpu_device 
*adev,
RENG_EXECUTE_ON_REG_UPDATE, 1);
WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, 
pctl1_reng_execute);
 
-   if (adev->powerplay.pp_funcs->set_mmhub_powergating_by_smu)
-   amdgpu_dpm_set_mmhub_powergating_by_smu(adev);
+   if (adev->powerplay.pp_funcs->powergate_mmhub)
+   amdgpu_dpm_powergate_mmhub(adev);
 
} else {
pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 06f08f3..0f98862 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -269,7 +269,7 @@ struct amd_pm_funcs {
int (*get_power_profile_mode)(void *handle, char *buf);
int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, 
uint32_t size);
-   int (*set_mmhub_powergating_by_smu)(void *handle);
+   int (*powergate_mmhub)(void *handle);
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index d567be4..da98208 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1168,19 +1168,19 @@ static int pp_get_display_mode_validation_clocks(void 
*handle,
return ret;
 }
 
-static int pp_set_mmhub_powergating_by_smu(void *handle)
+static int pp_dpm_powergate_mmhub(void *handle)
 {
struct pp_hwmgr *hwmgr = handle;
 
if (!hwmgr || !hwmgr->pm_en)
return -EINVAL;
 
-   if (hwmgr->hwmgr_func->set_mmhub_powergating_by_smu == NULL) {
+   if (hwmgr->hwmgr_func->powergate_mmhub == NULL) {
pr_info("%s was not implemented.\n", __func__);
return 0;
}
 
-   return hwmgr->hwmgr_func->set_mmhub_powergating_by_smu(hwmgr);
+   return hwmgr->hwmgr_func->powergate_mmhub(hwmgr);
 }
 
 static const struct amd_pm_funcs pp_dpm_funcs = {
@@ -1227,5 +1227,5 @@ static int pp_set_mmhub_powergating_by_smu(void *handle)
.set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges,
.display_clock_voltage_request = pp_display_clock_voltage_request,
.get_display_mode_validation_clocks = 
pp_get_display_mode_validation_clocks,
-   .set_mmhub_powergating_by_smu = pp_set_mmhub_powergating_by_smu,
+   .powergate_mmhub = pp_dpm_powergate_mmhub,
 };
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index d4bc83e..0f8352c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1126,7 +1126,7 @@ static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr)
return smum_send_msg_to_smc(hwmgr, 
PPSMC_MSG_SetRccPfcPmeRestoreRegister);
 }
 
-static int smu10_set_mmhub_powergating_by_smu(struct pp_hwmgr *hwmgr)
+static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr)
 {
return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub);
 }
@@ -1182,7 +1182,7 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, 
bool bgate)
.asic_setup = smu10_setup_asic_task,
.power_state_set = smu10_set_power_state_tasks,
.dynamic_state_management_disable = 

Re: KASAN: use-after-free in amdgpu_ttm_tt_pte_flags

[Michel Dänzer]

On 2018-06-13 12:55 PM, Huang Rui wrote:
> On Fri, Jun 08, 2018 at 08:15:26PM +0200, Christian König wrote:
>> Going to take a look on Monday.
>>
> 
> Christian, have you looked at this issue? If not, can I volunteer to look at
> it?
> 
> Michel, may I know which test of piglit trigger this issue? I tried to run
> with quick.py, but didn't reproduce it.

I'm using the gpu profile, which runs slightly fewer tests than quick.

It could be one of those issues which can only be reproduced when
running piglit after compiling LLVM etc., e.g. due to the pressure on
the kernel memory management subsystem created by the latter.

Also note that I've only ever seen this once so far.

In summary, it may be difficult to reproduce. :) Probably best to look
at the KASAN report for now.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: KASAN: use-after-free in amdgpu_ttm_tt_pte_flags

[Christian König]

Am 13.06.2018 um 12:55 schrieb Huang Rui:

On Fri, Jun 08, 2018 at 08:15:26PM +0200, Christian König wrote:

Going to take a look on Monday.


Christian, have you looked at this issue?


Not yet, I'm still busy figuring out why restoring the resize able BAR 
config doesn't work as it should.



If not, can I volunteer to look at it?


Sure.



Michel, may I know which test of piglit trigger this issue? I tried to run
with quick.py, but didn't reproduce it.


My guess is that it is a rare issue or otherwise I would see it on the 
sporadic piglit runs I do as well.


Christian.



Thanks,
Ray


Thanks,
Christian.

Am 08.06.2018 um 16:07 schrieb Michel Dänzer:

KASAN picked up something during today's piglit run on
amd-staging-drm-next, see attached. I've never seen this one before.




___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: KASAN: use-after-free in amdgpu_ttm_tt_pte_flags

[Huang Rui]

On Fri, Jun 08, 2018 at 08:15:26PM +0200, Christian König wrote:
> Going to take a look on Monday.
> 

Christian, have you looked at this issue? If not, can I volunteer to look at
it?

Michel, may I know which test of piglit trigger this issue? I tried to run
with quick.py, but didn't reproduce it.

Thanks,
Ray

> Thanks,
> Christian.
> 
> Am 08.06.2018 um 16:07 schrieb Michel Dänzer:
> >KASAN picked up something during today's piglit run on
> >amd-staging-drm-next, see attached. I've never seen this one before.
> >
> >
> >
> >
> >___
> >amd-gfx mailing list
> >amd-gfx@lists.freedesktop.org
> >https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> 

> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: Consolidate visible vs. real vram check.

[Christian König]

Am 12.06.2018 um 20:37 schrieb Andrey Grodzovsky:

Move all instnaces of this check into a function in amdgpu_gmc.h
Rename the original function to a more proper name.

Signed-off-by: Andrey Grodzovsky 


There seems to be two more candidates for that cleanup:

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:    if 
(adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:        } else if 
(adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&


With those two fixed as well the patch is Reviewed-by: Christian König 
.


Thanks,
Christian.


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 11 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 15 +++
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 20 
  3 files changed, 25 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 12f0d18..f98be69 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -31,6 +31,7 @@
  #include 
  #include "amdgpu.h"
  #include "amdgpu_trace.h"
+#include "amdgpu_gmc.h"
  
  static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,

  struct drm_amdgpu_cs_chunk_fence *data,
@@ -302,7 +303,7 @@ static void amdgpu_cs_get_threshold_for_moves(struct 
amdgpu_device *adev,
*max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
  
  	/* Do the same for visible VRAM if half of it is free */

-   if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size) {
+   if (!amdgpu_gmc_vram_full_visible(>gmc)) {
u64 total_vis_vram = adev->gmc.visible_vram_size;
u64 used_vis_vram =

amdgpu_vram_mgr_vis_usage(>mman.bdev.man[TTM_PL_VRAM]);
@@ -359,7 +360,7 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
 * to move it. Don't move anything if the threshold is zero.
 */
if (p->bytes_moved < p->bytes_moved_threshold) {
-   if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
+   if (!amdgpu_gmc_vram_full_visible(>gmc) &&
(bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
/* And don't move a CPU_ACCESS_REQUIRED BO to limited
 * visible VRAM if we've depleted our allowance to do
@@ -381,7 +382,7 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
r = ttm_bo_validate(>tbo, >placement, );
  
  	p->bytes_moved += ctx.bytes_moved;

-   if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
+   if (!amdgpu_gmc_vram_full_visible(>gmc) &&
amdgpu_bo_in_cpu_visible_vram(bo))
p->bytes_moved_vis += ctx.bytes_moved;
  
@@ -434,8 +435,8 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
  
  		/* Good we can try to move this BO somewhere else */

update_bytes_moved_vis =
-   adev->gmc.visible_vram_size < adev->gmc.real_vram_size 
&&
-   amdgpu_bo_in_cpu_visible_vram(bo);
+   !amdgpu_gmc_vram_full_visible(>gmc) &&
+   amdgpu_bo_in_cpu_visible_vram(bo);
amdgpu_ttm_placement_from_domain(bo, other);
r = ttm_bo_validate(>tbo, >placement, );
p->bytes_moved += ctx.bytes_moved;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 893c249..6cb4948 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -109,4 +109,19 @@ struct amdgpu_gmc {
const struct amdgpu_gmc_funcs   *gmc_funcs;
  };
  
+/**

+ * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Returns:
+ * True if full VRAM is visible through the BAR
+ */
+static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
+{
+   WARN_ON(gmc->real_vram_size < gmc->visible_vram_size);
+
+   return (gmc->real_vram_size == gmc->visible_vram_size);
+}
+
  #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 7f03f8c..6d22942 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -33,6 +33,7 @@
  #include "amdgpu.h"
  #include "amdgpu_trace.h"
  #include "amdgpu_amdkfd.h"
+#include "amdgpu_gmc.h"
  
  /**

   * DOC: GPUVM
@@ -669,19 +670,6 @@ bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
  }
  
  /**

- * amdgpu_vm_is_large_bar - Check if BAR is large enough
- *
- * @adev: amdgpu_device pointer
- *
- * Returns:
- * True if BAR is large enough.
- */
-static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev)
-{
-   return (adev->gmc.real_vram_size == adev->gmc.visible_vram_size);
-}
-
-/**
   * amdgpu_vm_flush - hardware flush the vm
   *
   * 

[PATCH] drm/amd/pp: Remove SAMU support in powerplay

[Rex Zhu]

As the SAMU ip was not supported in linux,
so delete the SAMU support in powerplay on
asics Bonarire/Hawwii/Tonga/Fiji/Polaris/vegam.

Signed-off-by: Rex Zhu 
---
 .../amd/powerplay/hwmgr/smu7_clockpowergating.c| 54 --
 .../amd/powerplay/hwmgr/smu7_clockpowergating.h|  1 -
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   |  1 -
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h   |  1 -
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h |  1 -
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h |  2 -
 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c   | 35 -
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 74 ---
 .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c  | 10 ---
 .../drm/amd/powerplay/smumgr/polaris10_smumgr.c| 86 --
 .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c| 80 
 .../gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c| 85 -
 12 files changed, 430 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
index 6d72a56..4149562 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
@@ -39,13 +39,6 @@ static int smu7_enable_disable_vce_dpm(struct pp_hwmgr 
*hwmgr, bool enable)
PPSMC_MSG_VCEDPM_Disable);
 }
 
-static int smu7_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
-{
-   return smum_send_msg_to_smc(hwmgr, enable ?
-   PPSMC_MSG_SAMUDPM_Enable :
-   PPSMC_MSG_SAMUDPM_Disable);
-}
-
 static int smu7_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
 {
if (!bgate)
@@ -60,13 +53,6 @@ static int smu7_update_vce_dpm(struct pp_hwmgr *hwmgr, bool 
bgate)
return smu7_enable_disable_vce_dpm(hwmgr, !bgate);
 }
 
-static int smu7_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
-{
-   if (!bgate)
-   smum_update_smc_table(hwmgr, SMU_SAMU_TABLE);
-   return smu7_enable_disable_samu_dpm(hwmgr, !bgate);
-}
-
 int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr)
 {
if (phm_cf_want_uvd_power_gating(hwmgr))
@@ -107,35 +93,15 @@ static int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
return 0;
 }
 
-static int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
-{
-   if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-   PHM_PlatformCaps_SamuPowerGating))
-   return smum_send_msg_to_smc(hwmgr,
-   PPSMC_MSG_SAMPowerOFF);
-   return 0;
-}
-
-static int smu7_powerup_samu(struct pp_hwmgr *hwmgr)
-{
-   if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-   PHM_PlatformCaps_SamuPowerGating))
-   return smum_send_msg_to_smc(hwmgr,
-   PPSMC_MSG_SAMPowerON);
-   return 0;
-}
-
 int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr)
 {
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 
data->uvd_power_gated = false;
data->vce_power_gated = false;
-   data->samu_power_gated = false;
 
smu7_powerup_uvd(hwmgr);
smu7_powerup_vce(hwmgr);
-   smu7_powerup_samu(hwmgr);
 
return 0;
 }
@@ -195,26 +161,6 @@ void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
}
 }
 
-int smu7_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate)
-{
-   struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-
-   if (data->samu_power_gated == bgate)
-   return 0;
-
-   data->samu_power_gated = bgate;
-
-   if (bgate) {
-   smu7_update_samu_dpm(hwmgr, true);
-   smu7_powerdown_samu(hwmgr);
-   } else {
-   smu7_powerup_samu(hwmgr);
-   smu7_update_samu_dpm(hwmgr, false);
-   }
-
-   return 0;
-}
-
 int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
const uint32_t *msg_id)
 {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
index 1ddce02..be7f66d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
@@ -29,7 +29,6 @@
 void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
 void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
 int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr);
-int smu7_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate);
 int smu7_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
 int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
 int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 11e1762..a338142 100644
---