On Mon, Jul 8, 2019 at 6:05 PM Arnd Bergmann wrote:
> On Mon, Jul 8, 2019 at 4:54 PM Nathan Chancellor
> wrote:
> > On Mon, Jul 08, 2019 at 03:57:06PM +0200, Arnd Bergmann wrote:
> > > A couple of calls to smu_get_current_clk_freq() and smu_force_clk_levels()
> > > pass constants of the wrong
On 2019/07/15, Fuqian Huang wrote:
> kzalloc has already zeroed the memory during the allocation.
> So memset is unneeded.
>
> Signed-off-by: Fuqian Huang
> ---
> Changes in v3:
> - Fix subject prefix: gpu/drm -> drm/amdgpu
>
Reviewed-by: Emil Velikov
-Emil
Since DP-specific information is stored in driver's structures, every
driver needs to implement subconnector property by itself.
Signed-off-by: Oleg Vasilev
Cc: amd-gfx@lists.freedesktop.org
---
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 12
Am 13.07.19 um 22:24 schrieb Felix Kuehling:
Am 2019-04-30 um 1:03 p.m. schrieb Koenig, Christian:
The only real solution I can see is to be able to reliable kill shaders
in an OOM situation.
Well, we can in fact preempt our compute shaders with low latency.
Killing a KFD process will do
Hi David,
You are right, it will copy per-vm resv.
But currently, it still has the delay free issue which non per vm bo
doesn't has. Maybe it already has new fences append to this resv object before
copy.
Hi Christian,
Do you have any suggestion about this? For per vm bo, it seems
Hi Christian,
As has this behavior, when test vulkan cts allocation test, it will
exhausting the memory, and cause out of memory. Do you think we don't need to
fix it?
Best wishes
Emily Deng
>-Original Message-
>From: Koenig, Christian
>Sent: Monday, July 15, 2019 5:31 PM
>To:
From 09c1952466752033722b02d9c7e5532e1982f6d9 Mon Sep 17 00:00:00 2001
From: Paul Menzel
Date: Sat, 13 Jul 2019 20:33:49 +0200
This basically reverts commit 00893681a0ff4 (drm/amd/display: Reject
PPLib clock values if they are invalid).
0 kHz values are a thing on at least the boards below.
Hi Emily,
no, we can only cleanup the current one because we don't have a
reference to the other ones.
At least that's how I understand you question,
Christian.
Am 15.07.19 um 12:47 schrieb Deng, Emily:
> Hi Christian,
> Do you think we could free all those bos those are in current
Hi guys,
> Do you have any suggestion about this? For per vm bo, it seems always delay
> to free the ttm bo.
Yeah, and that is correct behavior.
Since we don't know who is using a per-vm BO we need to wait for all
command submissions in flight when it is freed.
For this we copy the current
> Do you think we don't need to fix it?
No, when the application is exhausting memory then we can't expect
anything else here.
See memory freeing is always delayed until it isn't used any more or
when the process is killed after access is prevented (by clearing page
tables for example).
What
On Thu, Jul 4, 2019 at 7:52 AM Nathan Chancellor
wrote:
>
> clang warns:
>
> drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:995:39: warning:
> implicit conversion from enumeration type 'PPCLK_e' to different
> enumeration type 'enum smu_clk_type' [-Wenum-conversion]
> ret =
Hi Christian,
Do you think we could free all those bos those are in current destroy list
when the current resv is signal in ttm_bo_cleanup_refs?
Best wishes
Emily Deng
>-Original Message-
>From: Koenig, Christian
>Sent: Monday, July 15, 2019 5:41 PM
>To: Deng, Emily ; Zhou,
kzalloc has already zeroed the memory.
So the memset is unneeded.
Signed-off-by: Fuqian Huang
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index
On 7/15/19 6:34 AM, Paul Menzel wrote:
> From 09c1952466752033722b02d9c7e5532e1982f6d9 Mon Sep 17 00:00:00 2001
> From: Paul Menzel
> Date: Sat, 13 Jul 2019 20:33:49 +0200
>
> This basically reverts commit 00893681a0ff4 (drm/amd/display: Reject
> PPLib clock values if they are invalid).
>
> 0
Dear Nicholas,
On 7/15/19 2:57 PM, Kazlauskas, Nicholas wrote:
> On 7/15/19 6:34 AM, Paul Menzel wrote:
>> From 09c1952466752033722b02d9c7e5532e1982f6d9 Mon Sep 17 00:00:00 2001
>> From: Paul Menzel
>> Date: Sat, 13 Jul 2019 20:33:49 +0200
>>
>> This basically reverts commit 00893681a0ff4
Acked-by: Alex Deucher
From: amd-gfx on behalf of Russell,
Kent
Sent: Monday, July 15, 2019 8:54 AM
To: amd-gfx@lists.freedesktop.org
Cc: Russell, Kent
Subject: [PATCH] drm/amdgpu: Fix Vega20 Perf counter for pcie_bw
The perf counter for Vega20 is 108, instead
Am 02.07.19 um 19:15 schrieb Emil Velikov:
On Fri, 14 Jun 2019 at 19:02, Koenig, Christian
wrote:
Am 14.06.19 um 19:33 schrieb Emil Velikov:
From: Emil Velikov
Currently the AMDGPU_CTX_PRIORITY_* defines are used in both
drm_amdgpu_ctx_in::priority and drm_amdgpu_sched_in::priority.
Extend
> kzalloc has already zeroed the memory.
> So the memset is unneeded.
See also a previous patch:
drm/amd/powerplay: Delete a redundant memory setting in
vega20_set_default_od8_setttings()
https://lore.kernel.org/lkml/de3f6a5e-8ac4-bc8e-0d0c-3a4a5db28...@web.de/
The perf counter for Vega20 is 108, instead of 104 which it was on all
previous GPUs, so add a check to use the appropriate value.
Change-Id: Id5b5026a03b09d8b9d52dda85e17ed5acd818912
Signed-off-by: Kent Russell
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 10 --
1 file changed, 8
From: Wang Xiayang
The simple_strtol() function is deprecated. kstrto[l,u32]() is
the correct replacement as it can properly handle overflows.
This patch replaces the deprecated simple_strtol() use introduced recently.
As clk is of type uint32_t, we are safe to use kstrtou32().
It is also safe
On Mon, Jul 15, 2019 at 3:57 AM Fuqian Huang wrote:
>
> kzalloc has already zeroed the memory during the allocation.
> So memset is unneeded.
>
> Signed-off-by: Fuqian Huang
Applied. thanks!
Alex
> ---
> Changes in v3:
> - Fix subject prefix: gpu/drm -> drm/amdgpu
>
>
With a KASAN enabled kernel built from amd-staging-drm-next, the
attached use-after-free is pretty reliably detected during a piglit gpu run.
Any ideas?
P.S. With my standard kernels without KASAN (currently 5.2.y + drm-next
changes for 5.3), I'm having trouble lately completing a piglit run,
On Mon, Jul 15, 2019 at 11:25:29AM +0200, Arnd Bergmann wrote:
> On Thu, Jul 4, 2019 at 7:52 AM Nathan Chancellor
> wrote:
> >
> > clang warns:
> >
> > drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:995:39: warning:
> > implicit conversion from enumeration type 'PPCLK_e' to different
> >
On Mon, Jun 24, 2019 at 7:40 PM Catalin Marinas wrote:
>
> On Mon, Jun 24, 2019 at 04:32:56PM +0200, Andrey Konovalov wrote:
> > This patch is a part of a series that extends kernel ABI to allow to pass
> > tagged user pointers (with the top byte set to something else other than
> > 0x00) as
On Mon, Jul 15, 2019 at 10:57 AM wrote:
>
> From: Wang Xiayang
>
> The simple_strtol() function is deprecated. kstrto[l,u32]() is
> the correct replacement as it can properly handle overflows.
>
> This patch replaces the deprecated simple_strtol() use introduced recently.
> As clk is of type
On Mon, Jun 24, 2019 at 7:50 PM Catalin Marinas wrote:
>
> On Mon, Jun 24, 2019 at 04:32:52PM +0200, Andrey Konovalov wrote:
> > This patch is a part of a series that extends kernel ABI to allow to pass
> > tagged user pointers (with the top byte set to something else other than
> > 0x00) as
On Fri, Jul 12, 2019 at 5:41 AM Arnd Bergmann wrote:
>
> It is annoying to have #warnings that trigger in randconfig
> builds like
>
> drivers/gpu/drm/amd/amdgpu/soc15.c:653:3: error: "Enable CONFIG_DRM_AMD_DC
> for display support on SOC15."
> drivers/gpu/drm/amd/amdgpu/nv.c:400:3: error:
From: Aric Cyr
Signed-off-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index e513028faefa..2a7f25d372e1 100644
---
From: Dmytro Laktyushkin
A regression caused dsc to never get disabled in certain situations.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Nikola Cornij
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff
From: David Galiffi
[WHY]
To add support for OS requirement to set preferred link training
parameters.
[HOW]
Create new structure of dp link training overrides. During link training
processes, these values should be used instead of the default training
parameters.
Signed-off-by: David Galiffi
From: Su Sung Chung
[why]
for 2 purposes:
1. get raw register value dumped on the log, which will make it easier
to talk to other team who only knows about the register
2. enable other HW to be able to use the same interface as raven to log
clock register data
Signed-off-by: Su Sung Chung
From: Dmytro Laktyushkin
We're not expected to enter the default case, but not returning a
default value here is incorrect.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c | 1 +
From: Eric Yang
[Why]
Unintentionally introduced behaviour change from previous refactor,
which causes clks to be 0 in no stream cases, which will cause
divide by 0.
[How]
Skip calculation of clocks when no stream. Which is the same as old
behaviour.
Signed-off-by: Eric Yang
Reviewed-by: Tony
From: Samson Tam
[Why]
Fixes issue when we have a display connected using a passive
dongle and then emulate over it using a DP connection at 1 x 1.62 Ghz.
System hangs because register bus returns back 0x for all
register reads after setting register DIG_BE_CNTL in
From: Dmytro Laktyushkin
This change adds EMP packet programming for enabling dsc with
hdmi. The packets are structured according to VESA HDMI 2.1x
r2 spec, section 10.10.2.2.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Leo Li
---
From: David Galiffi
[WHY]
TRAINING_AUX_RD_INTERVAL (DPCD 000Eh) modifies the read interval
for the EQ training sequence. CR read interval should remain 100 us.
Currently, the CR interval is also being modified.
[HOW]
lt_settings->cr_pattern_time should always be 100 us.
Signed-off-by: David
From: Chiawen Huang
[Why]
dce was re-arch'd, therefore adding aux tracing log into new dce
[How]
The porting from submit_channel_request/process_channel_reply of
aux_engine_dce110.c
Signed-off-by: Chiawen Huang
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
From: Nikola Cornij
[why]
DSC should be powered-on only on as-needed basis, i.e. if the mode
requires it
[how]
Loop over all the DSCs at driver init time and power-gate each
Signed-off-by: Nikola Cornij
Reviewed-by: Nevenko Stupar
Acked-by: Leo Li
---
From: Joshua Aberback
[Why]
We want a debug option to disable timing sync for testing.
[How]
New dc debug option that must be false to call program_timing_sync
Signed-off-by: Joshua Aberback
Reviewed-by: Jun Lei
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
From: Dingchen Zhang
[Why]
We need to check the pipe crc source through debugfs for bypass mode test.
[How]
add implementation of amdgpu_dm_crtc_get_crc_sources and hook into drm_crtc
callback get_crc_sources.
Signed-off-by: Dingchen Zhang
Reviewed-by: Nicholas Kazlauskas
Acked-by: Leo Li
From: SivapiriyanKumarasamy
[WHY]
Currently we don't wait for blacklight programming completion in DMCU
when setting backlight level. Some sequences such as PSR static screen
event trigger reprogramming requires it to be complete.
[How]
Add generic wait for dmcu command completion in set
From: Jun Lei
[why]
Some values were not being converted or bit-shifted properly for
HW registers, causing black screen
[how]
Fix up the values before programming HW
Signed-off-by: Jun Lei
Reviewed-by: Anthony Koo
Acked-by: Leo Li
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c | 17
From: Jun Lei
[why]
On some modes SMU will be in infinite loop state at boot, this is
because driver assumes p_state_support is false, but this is the
opposite of the assumed boot state by SMU. we optimize away
notifying SMU about no pstate, and so they will get stuck
[how]
when we init clk
From: Eric Bernstein
Use helper to determine if HDMI signal when processing avmute.
Signed-off-by: Eric Bernstein
Reviewed-by: Charlene Liu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Harmanprit Tatla
[Why]
There are certain MST displays (i.e. Dell P2715Q)
that although have the MST feature set to off may still
report it is a branch device and a non-zero
value for downstream port present.
This can lead to us incorrectly classifying a
dp dongle connection as being active
From: Alvin Lee
[Why]
When we recover from hang, we do not want to skip the audio enable call.
[How]
Disable audio in dc_reinitialize_hardware
Signed-off-by: Alvin Lee
Reviewed-by: Jun Lei
Acked-by: Leo Li
---
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 1 +
From: Charlene Liu
There are shared regs and code across DCN generations. Pull them out
into a shared common location.
Also, expose some dcn20 init functions.
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
---
.../gpu/drm/amd/display/dc/dce/dce_hwseq.h| 3
From: Nevenko Stupar
[Why]
-Pass and use pixel clock in 100 Hz to Audio for HDMI
audio DTO for Audio wall clock programming so audio DTO gets
increased precision for timings with /1001 factor.
-For HDMI TMDS for N and CTS ACR tables are based on 10 KHz
units, these does not need to be modified
From: Su Sung Chung
[why]
dcn20_clk_mgr_construct was not initializing pp_smu, and PME call gets
filtered out by the null check
[how]
initialize pp_smu dcn20_clk_mgr_construct
Signed-off-by: Su Sung Chung
Reviewed-by: Eric Yang
Acked-by: Leo Li
---
From: Nicholas Kazlauskas
[Why]
For DCE110, DCE112 and DCE120 the max_clks_by_state for the clk_mgr are
copied from their respective table before the call to
dce_clk_mgr_construct, but then dce_clk_mgr_construct overwrites
these with the dce80_max_clks_by_state.
[How]
Copy these after we call
From: Murton Liu
[why]
We reset the optimized_required in atomic_plane_disable
flag immediately after it is set in atomic_plane_disconnect, causing us to
never have flag set during next flip in UpdatePlanes.
[how]
Optimize directly after each time plane is removed.
Signed-off-by: Murton Liu
From: Tai Man
[Why]
On some platforms, the encoder id 3 is not populated. So the encoders
are not stored in right order as index (id: 0, 1, 2, 4, 5) at pool. This
would cause encoders id 4 & id 5 to fail when finding corresponding
audio device, defaulting to the first available audio device. As
From: Harry Wentland
[Why]
link_stream is never NULL here as we've dereferenced it a couple lines before
and have done so for a couple months now.
[How]
- Drop the NULL check.
- Initialize where we know link_stream is non-NULL
Signed-off-by: Harry Wentland
Reviewed-by: Nicholas Kazlauskas
From: Eric Yang
[Why]
Seamless boot optimization removed proper front end power off sequence.
In driver disable enable case, this causes driver to power gate hubp
and dpp while there is still memory fetching going on, this can cause
invalid memory requests to be generated which will hang data
From: Jun Lei
[why]
Due to limitation in SMU/PPLIB, it is not possible to know Fmax @ Vmin for
DCFCLK.
This causes issues at high display configurations where extra headroom of DCFCLK
can enable P-state switching
[how]
Use existing override logic. If override not defined, then force
min = 507
From: Aric Cyr
Signed-off-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index a307a3a1cde4..0aad22b1ef36 100644
---
From: Anthony Koo
[Why]
Specifically to one panel,
TCON is able to accept active video signal quickly, but
the Source Driver requires 2-3 frames of extra time.
It is a Panel issue since TCON needs to take care of
all Sink requirements including Source Driver. But in
this case it does not.
From: Wenjing Liu
[why]
The current code will not wait for the entire frame
after global unlock.
This causes dsc dynamic target bpp update corruption when
there is a surface update immediately happens after this.
[how]
Wait for the entire whole frame after unlock before continuing
the rest of
From: Nikola Cornij
[why]
'second_line_offset_adj' was mistakenly left at zero, even though DSC spec
v1.2a recommends setting this field to 512 for 4:2:0.
[how]
Set 'second_line_offset_adj' to 512 for 4:2:0 and leave at zero otherwise
Signed-off-by: Nikola Cornij
Reviewed-by: Eric Bernstein
From: Aric Cyr
Signed-off-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 2a7f25d372e1..c0ebb77fab70 100644
---
From: Alvin Lee
[why]
In pipe split issue occurs when we program immediate flip while vsync flip is
pending
[how]
Don't program immediate flip until flip is no longer pending
Signed-off-by: Alvin Lee
Reviewed-by: Jaehyun Chung
Acked-by: Leo Li
---
From: David Francis
[Why]
Some parts of the DSC spec relating to 4.2.0 were not reflected in
drm_dsc_compute_rc_parameters, causing unexpected config failures
[How]
Add nsl_bpg_offset and rbs_min computation
Signed-off-by: David Francis
Reviewed-by: Nikola Cornij
Acked-by: Leo Li
---
From: Eric Yang
[Why]
For better readability and reusability
[How]
Move snippets of BW calculation code into helpers.
Signed-off-by: Eric Yang
Reviewed-by: Fatemeh Darbehani
Acked-by: Leo Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 1 +
From: Julian Parkin
[Why]
Hardware docs state that we must wait until the GPUVM context is ready
after programming it.
[How]
Poll until the valid bit of PAGE_TABLE_BASE_ADDR_LO32 is set to 1 after
programming it.
Signed-off-by: Julian Parkin
Reviewed-by: Charlene Liu
Acked-by: Leo Li
---
From: Fatemeh Darbehani
[Why]
Some display's hsync width is lower than the minimum dcn20 is set
to support right now. This will cause optc1_validate_timing to fail which
eventually will result in wrong set mode. This was set to 8 as per
HW team's request for no valid reason.
[How]
Changing
From: Jun Lei
[why]
Currently logical values are swapped in HW, causing
system aperture to be undefined, so VA and PA cannot co-exist
[how]
program values correctly
Signed-off-by: Jun Lei
Reviewed-by: Yongqiang Sun
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4
From: Ilya Bakoulin
[Why]
Need to implement register programming for HDR dynamic
metadata transmission and tests.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Eric Bernstein
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 2 +-
From: Zi Yu Liao
[why]
When the system is going into suspend, set_backlight gets called
after the eDP got blanked. Since smooth brightness is enabled,
the driver will make a call into the DMCU to ramp the brightness.
The DMCU would try to enable ABM to do so. But since the display is
blanked,
From: Aric Cyr
Signed-off-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index c0ebb77fab70..a307a3a1cde4 100644
---
From: Murton Liu
[Why]
Logic & structures for generic regs does not exist in DC currently.
[How]
Implement register masks/shifts and relevant functions for generic mux,
similar to existing HPD and DDC objects.
Signed-off-by: Murton Liu
Reviewed-by: Aric Cyr
Acked-by: Joshua Aberback
From: Leo Li
Lots of patches this time, sorry for the volume! Regular DC promotions
were put on hold while Navi was being reviewed and upstreamed. These
patches were what accumulated during that period.
Summary of change:
* Implement DPRX CRC source capture
* Implement CRC source readback
*
From: Charlene Liu
add dc_set_clock
add dc_get_clock
this is for testing and diagnostics to get/set DPPCLK and DISPCLK.
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
---
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 23 +++-
From: hersen wu
[WHY] dc sw clock implementation of navi10 and raven are not exact the
same. dcccg, dchub reference clock initialization is done after dc calls
vbios dispcontroller_init table. for raven family, before
dispcontroller_init is called by dc, the ref clk values are referred
by sw
From: Ilya Bakoulin
[Why]
Alpha could be improperly applied (only affecting half the
frame) for some source pixel formats.
[How]
Change how alpha is enabled in MPC/DPP LB and change the
bottom plane blend mode in MPC.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo
From: Dmytro Laktyushkin
Current default is sufficient for a flag that does not change.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 8 +---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h | 4 ++--
From: Ilya Bakoulin
Before accessing it's vtable, check that stream_encoder is non-null.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Eric Bernstein
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Nikola Cornij
[why]
As a fail-safe, in case 'set FEC_READY' DPCD write fails, a HW shadow
register should be cleared and the internal FEC stat should be set to
'not ready'. This is to make sure HW settings will be consistent with
FEC_READY state on the RX.
Signed-off-by: Nikola Cornij
From: Derek Lai
[Why]
Driver will create 0, 1, and 2 ddc engines for RV2,
but some platforms used 0, 1, and 3.
[How]
Still allocate 4 ddc engines for RV2.
Signed-off-by: Derek Lai
Reviewed-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +-
1
From: Aric Cyr
Signed-off-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 0aad22b1ef36..14664bed8c84 100644
---
From: Dale Zhao
[Why]:
Some active dongles have DP++ port and DP port at the same time. Current
code doesn't cover DP++ case and processes as default DVI case, in which
audio is disabled. Because of dual mode, DP case is also treat as DVI case
for the other port.
[How]:
According DP 1.4 spec,
From: Alvin Lee
[why]
We initialize pp_smu twice
[how]
Remove second initialization of pp_smu
Signed-off-by: Alvin Lee
Reviewed-by: Jaehyun Chung
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 --
1 file changed, 2 deletions(-)
diff --git
From: Ilya Bakoulin
For clarity, save the use_pitch_c logic to a bool
Signed-off-by: Ilya Bakoulin
Reviewed-by: Eric Bernstein
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git
From: Nikola Cornij
[why]
Right now we FEC_READY is set only before the final link training,
i.e. at mode set time. This means FEC_READY won't be set when doing
link training as a response to HPD. It also fails UCD400 FEC test in
DP compliance.
[how]
Move FEC_READY setup to link training.
From: Eric Yang
[Why]
Previously assume eDP sink present if connector present. Do not
need to enforce this restriction. Fix issue where driver attempt
to read link setting even though no edp connected.
{How]
Only read link setting after reading connection status.
Signed-off-by: Eric Yang
From: Charlene Liu
[Description]
Do not fill Null packet in the blank period for new packet gen
This is based on HW IP team recommended default setting change.
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
---
From: Derek Lai
[Why]
When launch D10.2, driver will write DPCD 0x107 with 0x00
[How]
Read MAX_DOWNSPREAD (0x0003h) then keep in current
link settings
Signed-off-by: Derek Lai
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 7 +++
1 file
From: Julian Parkin
[Why]
It is possible (but very unlikely) that constructing dc fails
before current_state is created.
We support 666 color depth in some scenarios, but this
isn't handled in get_norm_pix_clk. It uses exactly the
same pixel clock as the 888 case.
[How]
Check for non null
From: Krunoslav Kovac
[Why]
1. Stack usage is pretty high as fixed31_32 struct is 8 bytes and we
have functions with >30 vars on the stack.
2. Optimize gamma calculation by reducing number of calls to
dc_fixpt_pow Our X points are divided into 32 regions wth 16 pts each.
Each region is 2x the
From: Fatemeh Darbehani
For some platforms, we need to know SMU version for driver/SMU
compatibility. This change adds that field.
Change-Id: I2586161fb645bf0d16d30c91954a871f83e87edf
Signed-off-by: Fatemeh Darbehani
Reviewed-by: Yongqiang Sun
Acked-by: Leo Li
---
From: Qingqing Zhuo
[Why]
bypass CM block and MPC ogam for debug or triage use.
[How]
create a new flag cm_bypass_mode, which will set both CM_CONTROL
and MPCC_OGAM_MODE to bypass when set to 1.
Signed-off-by: Qingqing Zhuo
Reviewed-by: Charlene Liu
Acked-by: Leo Li
---
From: Aric Cyr
Signed-off-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 27900297bdcf..abc039b836d4 100644
---
From: Charlene Liu
[Description]
This is for HW negative stress testing use.
force reset the dispclk and dppclk even the same clock already set in HW.
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c |
From: Nicholas Kazlauskas
Workaround for now to avoid underflow.
The uclk switch time should really be bumped up to 404, but doing so
would expose p-state hang issues for higher bandwidth display
configurations.
Change-Id: I98060fc9c4eeece07ef54e13a144def88a3c3d21
Signed-off-by: Nicholas
From: Reza Amini
[WHY]
Users want to not have filtering when scaling by integer
multiples to native timing.
[HOW]
If timing is a multiple integer of view, we set number of taps
to 1 (effectivly closest neighbour).
Signed-off-by: Reza Amini
Reviewed-by: Aric Cyr
Acked-by: Leo Li
Acked-by:
From: Ilya Bakoulin
[Why]
A hubp pointer was being passed to DCN1 functions, which
expect the enclosing structure (for the purpose of container_of macros)
to be dcn10_hubp, but the actual type was dcn20_hubp.
[How]
Copy existing DCN1 functions and alter them slightly for use with
dcn20_hubp.
From: Murton Liu
id_to_offset does not point to the same reg offset that offset_to_id checks for,
causing unintended asserts
Signed-off-by: Murton Liu
Reviewed-by: Aric Cyr
Acked-by: Leo Li
---
.../drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c | 2 +-
From: Zhan Liu
[Why]
For boards that support eDP but do not have a physical eDP
display connected an ASSERT will be thrown. This is not a
critical failure and shouldn't be treated as such.
[How]
Drop the assertion.
Signed-off-by: Zhan Liu
Reviewed-by: Nicholas Kazlauskas
Acked-by: Leo Li
From: Nevenko Stupar
Add this register for future use
Signed-off-by: Nevenko Stupar
Reviewed-by: Vitaly Prosyak
Acked-by: Leo Li
---
.../drm/amd/display/dc/dcn10/dcn10_stream_encoder.h| 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git
From: Dingchen Zhang
[Why]
We need to compare DPRX CRCs with framebuffer CRCs for digital bypass mode.
[How]
Hook into DRM to grab DP receiver CRCs through drm_dp_start_crc.
Signed-off-by: Dingchen Zhang
Reviewed-by: Harry Wentland
Acked-by: Leo Li
---
From: Tai Man
[Why]
The audios array defined in "struct resource_pool" is only 6 (MAX_PIPES)
but the max number of audio devices (num_audio) is 7. In some projects,
it will run out of audios array.
[How]
Incraese the audios array size to 7.
Signed-off-by: Tai Man Wong
Reviewed-by: Joshua
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