From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Aric Cyr
[Why]
DC is very fast at link training and stream enablement
which causes issues such as blackscreens for non-compliant
monitors.
[How]
After debugging with scaler vendors we implement the
minimum delays at the necessary locations to ensure
the monitor does not hang. Delays are
From: Nicholas Kazlauskas
[Why]
DML failures occur for 420 modes with dynamic pipe
splitting enabled because the ChromaViewport exceeds
the ChromaSurfaceWidth.
This is caused by adding the viewport_width instead
of the viewport_width_c.
This similarly occurs for rotated modes due to the
use of
From: po-tchen
[Why]
The SDP deadline indicate the vertical time to send CRC
infopacket in PSR.
Signed-off-by: po-tchen
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Martin Tsai
[Why]
Some sprcified monitor scalar cannot recognize timing
change on demand. Once the link phy disable and enable
during a short period then the Sink protection mechanism
could keep the screen in blank and cannot be recoverred.
[How]
To add 100ms delay between enable link phy
From: Wesley Chalmers
[WHY]
Disabling DPG should happen after setting watermarks and clocks
Signed-off-by: Wesley Chalmers
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Rodrigo Siqueira
When we want to use float point operation on Linux
we need to use within special kernel protection
(`kernel_fpu_{begin,end}()`.), otherwise the kernel
can clobber userspace FPU register state. For detecting
these issues we use a tool named objtool (with -Ffa
flags) to
From: Lewis Huang
[Why]
Multi-adapter calculate regamma table at the same time.
Two thread used the same global variable cause race
condition.
[How]
Change global buffer to local buffer
Signed-off-by: Lewis Huang
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
From: Jun Lei
[why]
Dummy pstate latency actually varies between different
UCLK frequencies, when calculating watermark C, if DAL
always assumes worst case, then it can lead to dummy
pstate not supported scenarios.
[how]
Rather than statically calculating dummy pstate using
worst case, we store
From: Dmytro Laktyushkin
To allow code reuse with minimal duplication watermark
calculation needs to be function pointer.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 6 +-
1 file changed, 5
From: Charlene Liu
[why]
for following new format, no alpha
SURFACE_PIXEL_FORMAT_GRPH_RGB10_FLOAT/_FIX:
SURFACE_PIXEL_FORMAT_GRPH_BGR10_FLOAT/_FIX
same as case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
Signed-off-by: Charlene Liu
Reviewed-by: Chris Park
Acked-by:
From: Dale Zhao
[Why]
For some special timing with border, like DMT 640*480 72Hz,
pipe split can't handle well. Thus, it will be black screen
for these special timing.
[How]
Disable pipe split for these timing with borders as W/A.
Signed-off-by: Dale Zhao
Reviewed-by: Tony Cheng
Acked-by:
From: Wenjing Liu
[why]
The change causes some regression in a common use case.
Will need more investigation before fixing the original issue.
[how]
This reverts commit ad418864c63a1718f9e283207b3fac96fbc148c2.
Signed-off-by: Wenjing Liu
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
---
From: Hugo Hu
revert commit 77dcea7a0b133b362b2ebbf494eb13ee3e946836.
Signed-off-by: Hugo Hu
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git
From: Michael Strauss
[WHY]
Typos cause bandwidth calculation errors, one
of which can cause infinite loop on dcn1 with eDP
Signed-off-by: Michael Strauss
Reviewed-by: Dmytro Laktyushkin
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c | 6 +++---
1 file
From: Yongqiang Sun
[Why & How]
Add emul specific hw function to dmub, in case of
emulator is created, we can runtime switch between
dmub emulator or dmub uC via is_virtual flag in dmub.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
From: Rodrigo Siqueira
During the debugging process related to a hot-plug
problem with 4k display, we realized that we had
some issues related to the global state validation.
This problem was not explicitly highlighted in the
dmesg log, for this reason, this commit adds a function
that converts
From: Roman Li
[Why]
SOC_BOUNDING_BOX_VALID is unused and not required for dcn21.
[How]
Remove it.
Signed-off-by: Roman Li
Reviewed-by: Bhawanpreet Lakha
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 1 -
1 file changed, 1 deletion(-)
diff --git
From: Anthony Koo
[Header Changes]
- Add SDP transmission deadline for PSR config cmd
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff
From: Yongqiang Sun
[Why]
during S0i3, set power state is toggled a few times,
and dmub uC will restart with current reset/hw_init.
[How]
Remove reset in set power state, and before doing hw_init,
check if dmub is enabled, and doing FW autoload check only
if dmub is already enabled.
From: Aurabindo Pillai
[Why & How]
DMUB command table should be allowed to be used
only if dmcu is explicitly disabled.
Signed-off-by: Aurabindo Pillai
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 ++
1 file changed,
From: Yongqiang Sun
[Why]
dmub FW running abnormal after resume from S0i3 due
to data aliagnment issue.
[How]
Before having a solution for this issue, temparory
not doing data pack.
Signed-off-by: Yongqiang Sun
Reviewed-by: Sung Lee
Acked-by: Qingqing Zhuo
---
From: Charlene Liu
[why]
for audio on real TV issue.
[how]
-add wall clock programming for DPREF based when
Pixel clock is done by DP DTO.
Signed-off-by: Charlene Liu
Reviewed-by: Chris Park
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 4 +++-
This DC patchset brings changes in multiple areas. In summary, we highlight:
* Bug fixes in bandwidth calculation, DSC calculation, etc.
* Improvements in DP
* Code refactoring and cleanup
* FW promotion
Anthony Koo (3):
drm/amd/display: [FW Promotion] Release 1.0.13
drm/amd/display: [FW
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Anthony Koo
[Header Changes]
- Add new initialization bits for driver to check
firmware status
- Add command for HW locking via DMUB
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 68 ++-
From: Nicholas Kazlauskas
[Why]
DSC calculations fail because the u16 bits_per_pixel from
the DRM struct is being casted to the u8 drm_bpp parameters
and locals. Integer wraparound is happening because this
value is greater than 255.
[How]
Use u16 to match what's in the structure instead of u8.
From: Dmytro Laktyushkin
We were updating mpcc if there were tree changes which
is unnecessary since any mpcc being added or removed
will automatically update the tree.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Qingqing Zhuo
---
From: Anthony Koo
[Header Changes]
- Version bump to 1.0.13
Signed-off-by: Anthony Koo
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Friday, June 5, 2020 11:40 PM
To: amd-gfx@lists.freedesktop.org; Liang, Prike
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/soc15: fix using
30 matches
Mail list logo