[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Kevin Wang
Notes:
we'd better to avoid adding ASIC type check in common file...
Best Regards,
Kevin
From: Du, Xiaojian
Sent: Monday, February 1, 2021 4:45 PM
To: amd-gfx@lists.freedesktop.org
On Mon, Feb 01, 2021 at 04:33:40PM +0800, Du, Xiaojian wrote:
> This patch is to fill in the data member of v2 gpu metrics
> table for vangogh.
>
> Signed-off-by: Xiaojian Du
> ---
Reviewed-by: Huang Rui
> drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 +++
> 1 file changed, 3
This patch is to remove some useless code for vangogh.
In the earlier code, vangogh can't finish all the sequence of
smu late init. But now vangogh has one stable work state,so
remove the useless code.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ---
1 file
Signed-off-by: chen gong
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 56 +-
1 file changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 024460b..d7e9a18 100644
---
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Evan Quan
-Original Message-
From: Du, Xiaojian
Sent: Monday, February 1, 2021 4:34 PM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Quan, Evan ; Wang,
Kevin(Yang) ; Du, Xiaojian
Subject: [PATCH] drm/amd/pm: fill
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Evan Quan
-Original Message-
From: Du, Xiaojian
Sent: Monday, February 1, 2021 4:46 PM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Quan, Evan ; Wang,
Kevin(Yang) ; Du, Xiaojian
Subject: [PATCH] drm/amd/pm:
This patch is to fill in the data member of v2 gpu metrics
table for vangogh.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Kevin Wang
Best Regards,
Kevin
From: Du, Xiaojian
Sent: Monday, February 1, 2021 4:33 PM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Quan, Evan ; Wang,
Kevin(Yang) ; Du, Xiaojian
On Mon, Feb 01, 2021 at 04:45:58PM +0800, Du, Xiaojian wrote:
> This patch is to remove some useless code for vangogh.
> In the earlier code, vangogh can't finish all the sequence of
> smu late init. But now vangogh has one stable work state,so
> remove the useless code.
>
> Signed-off-by:
Wave limiting can be use to load balance high priority
compute jobs along with gfx jobs. When enabled, this will reserve
~75% of waves for compute jobs.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 18
For high priority compute to work properly we need to enable
wave limiting on gfx pipe. Wave limiting is done through writing
into mmSPI_WCL_PIPE_PERCENT_GFX register. Enable only one high
priority compute queue to avoid race condition between multiple
high priority compute queues writing that
Enable gfx wave limiting for gfx jobs before pushing high priority
compute jobs so that high priority compute jobs gets more resources
to finish early.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9 +
1 file changed, 9 insertions(+)
diff --git
Am 01.02.21 um 13:07 schrieb Nirmoy Das:
Enable gfx wave limiting for gfx jobs before pushing high priority
compute jobs so that high priority compute jobs gets more resources
to finish early.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9 +
1 file
Adding gpu folks.
On Tue, Nov 03, 2020 at 03:28:05PM -0800, Alexei Starovoitov wrote:
> On Tue, Nov 03, 2020 at 05:57:47PM -0500, Kenny Ho wrote:
> > On Tue, Nov 3, 2020 at 4:04 PM Alexei Starovoitov
> > wrote:
> > >
> > > On Tue, Nov 03, 2020 at 02:19:22PM -0500, Kenny Ho wrote:
> > > > On Tue,
On 2/1/21 1:19 PM, Christian König wrote:
Am 01.02.21 um 13:07 schrieb Nirmoy Das:
Enable gfx wave limiting for gfx jobs before pushing high priority
compute jobs so that high priority compute jobs gets more resources
to finish early.
Signed-off-by: Nirmoy Das
---
Am 01.02.21 um 14:56 schrieb Nirmoy:
On 2/1/21 1:19 PM, Christian König wrote:
Am 01.02.21 um 13:07 schrieb Nirmoy Das:
Enable gfx wave limiting for gfx jobs before pushing high priority
compute jobs so that high priority compute jobs gets more resources
to finish early.
Signed-off-by:
Some newer APUs can scanout directly from GTT, that saves us from
allocating another bounce buffer in VRAM and enables freesync in such
configurations.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 8 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +-
For high priority compute to work properly we need to enable
wave limiting on gfx pipe. Wave limiting is done through writing
into mmSPI_WCL_PIPE_PERCENT_GFX register. Enable only one high
priority compute queue to avoid race condition between multiple
high priority compute queues writing that
Assign correct ring priority.
Fixes: 33abcb1f5a17 ("drm/amdgpu: set compute queue priority at mqd_init")
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
Wave limiting can be use to load balance high priority
compute jobs along with gfx jobs. When enabled, this will reserve
~75% of waves for compute jobs.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 18
Enable gfx wave limiting for gfx jobs before pushing high priority
compute jobs so that high priority compute jobs gets more resources
to finish early.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9 +
1 file changed, 9 insertions(+)
diff --git
Fix the following coccicheck warning:
./drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1591:0-23: WARNING:
fops_sclk_set should be defined with DEFINE_DEBUGFS_ATTRIBUTE.
./drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1588:0-23: WARNING:
fops_ib_preempt should be defined with
Thank you for catching this. I haven't had a chance to try out Alex's
rebased branch myself yet. I think this needs a
Fixes: 246cb7e49a70 ("drm/amdgpu: Introduce GEM object functions")
With that fixed, the patch is
Reviewed-by: Felix Kuehling
The fix also needs to go upstream as KFD seems
Hello Christian,
On 01/02/21 8:04 pm, Christian König wrote:
> Some newer APUs can scanout directly from GTT, that saves us from
> allocating another bounce buffer in VRAM and enables freesync in such
> configurations.
Shall we add some more details about how this patch helps with VRR, like
Am 01.02.21 um 16:13 schrieb Shashank Sharma:
On 01/02/21 8:39 pm, Christian König wrote:
Am 01.02.21 um 16:06 schrieb Shashank Sharma:
Hello Christian,
On 01/02/21 8:04 pm, Christian König wrote:
Some newer APUs can scanout directly from GTT, that saves us from
allocating another bounce
This patch consist of below related changes:
1 Rename ring->priority to ring->hw_prio.
2 Assign correct hardware ring priority.
3 Remove ring->priority_mutex as ring priority remains unchanged
after initialization.
4 Remove unused ring->num_jobs.
v3: remove ring->num_jobs.
v2: remove
For high priority compute to work properly we need to enable
wave limiting on gfx pipe. Wave limiting is done through writing
into mmSPI_WCL_PIPE_PERCENT_GFX register. Enable only one high
priority compute queue to avoid race condition between multiple
high priority compute queues writing that
Wave limiting can be use to load balance high priority
compute jobs along with gfx jobs. When enabled, this will reserve
~75% of waves for compute jobs.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 18
Enable gfx wave limiting for gfx jobs before pushing high priority
compute jobs so that high priority compute jobs gets more resources
to finish early.
v2: use ring priority instead of job priority.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9 +
1 file
On Mon, Feb 1, 2021 at 9:49 AM Daniel Vetter wrote:
>
> - there's been a pile of cgroups proposal to manage gpus at the drm
> subsystem level, some by Kenny, and frankly this at least looks a bit
> like a quick hack to sidestep the consensus process for that.
>
No Daniel, this is quick
On Mon, Feb 1, 2021 at 4:07 AM chen gong wrote:
>
Missing patch description.
Also, nothing wrong with the change per se, but
gfx_v10_0_check_grbm_cam_remapping() returns true for vangogh, so
gfx_v10_0_setup_grbm_cam_remapping() is never called for vangogh.
Alex
> Signed-off-by: chen gong
>
On 01/02/21 8:53 pm, Christian König wrote:
> Am 01.02.21 um 16:13 schrieb Shashank Sharma:
>> On 01/02/21 8:39 pm, Christian König wrote:
>>> Am 01.02.21 um 16:06 schrieb Shashank Sharma:
Hello Christian,
On 01/02/21 8:04 pm, Christian König wrote:
> Some newer APUs can
[Resent in plain text.]
On Mon, Feb 1, 2021 at 9:49 AM Daniel Vetter wrote:
> - there's been a pile of cgroups proposal to manage gpus at the drm
> subsystem level, some by Kenny, and frankly this at least looks a bit
> like a quick hack to sidestep the consensus process for that.
No Daniel,
On 2/1/21 4:00 PM, Christian König wrote:
Am 01.02.21 um 15:37 schrieb Nirmoy Das:
Assign correct ring priority.
Fixes: 33abcb1f5a17 ("drm/amdgpu: set compute queue priority at
mqd_init")
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 3 ++-
1 file changed, 2
Am 01.02.21 um 16:06 schrieb Shashank Sharma:
Hello Christian,
On 01/02/21 8:04 pm, Christian König wrote:
Some newer APUs can scanout directly from GTT, that saves us from
allocating another bounce buffer in VRAM and enables freesync in such
configurations.
Shall we add some more details
Wave limiting can be use to load balance high priority
compute jobs along with gfx jobs. When enabled, this will reserve
~75% of waves for compute jobs.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 18
For high priority compute to work properly we need to enable
wave limiting on gfx pipe. Wave limiting is done through writing
into mmSPI_WCL_PIPE_PERCENT_GFX register. Enable only one high
priority compute queue to avoid race condition between multiple
high priority compute queues writing that
Assign correct hw priority for compute ring. Also we assign
ring priority at ring initialization and it remains unchanged,
so we don't need ring->priority_mutex anymore.
v2: remove ring->priority_mutex.
Fixes: 33abcb1f5a17 ("drm/amdgpu: set compute queue priority at mqd_init")
Signed-off-by:
For each asic family. Will be used to populate tables
for the new INFO ioctl query.
v2: add max_pixels_per_frame to handle the portrait case
Reviewed-by: Leo Liu (v1)
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/cik.c | 75 ++
drivers/gpu/drm/amd/amdgpu/nv.c| 179
We currently hardcode these in mesa, but querying them from
the kernel makes more sense since there may be board specific
limitations that the kernel driver is better suited to
determining.
Userpace patches that use this interface:
This will be used by a new INFO ioctl query to fetch the decode
and encode capabilities from the kernel driver rather than
hardcoding them in mesa. This gives us more fine grained control
of capabilities using information that is only availabl in the
kernel (e.g., platform limitations or
So mesa can check when to query the kernel vs use hardcoded
codec bandwidth data.
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
Am 01.02.21 um 15:37 schrieb Nirmoy Das:
Assign correct ring priority.
Fixes: 33abcb1f5a17 ("drm/amdgpu: set compute queue priority at mqd_init")
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
On 01/02/21 8:39 pm, Christian König wrote:
> Am 01.02.21 um 16:06 schrieb Shashank Sharma:
>> Hello Christian,
>>
>> On 01/02/21 8:04 pm, Christian König wrote:
>>> Some newer APUs can scanout directly from GTT, that saves us from
>>> allocating another bounce buffer in VRAM and enables freesync
Am 01.02.21 um 16:33 schrieb Nirmoy Das:
Assign correct hw priority for compute ring. Also we assign
ring priority at ring initialization and it remains unchanged,
so we don't need ring->priority_mutex anymore.
v2: remove ring->priority_mutex.
Fixes: 33abcb1f5a17 ("drm/amdgpu: set compute
Enable gfx wave limiting for gfx jobs before pushing high priority
compute jobs so that high priority compute jobs gets more resources
to finish early.
v2: use ring priority instead of job priority.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9 +
1 file
Am 01.02.21 um 16:51 schrieb Nirmoy Das:
This patch consist of below related changes:
1 Rename ring->priority to ring->hw_prio.
2 Assign correct hardware ring priority.
3 Remove ring->priority_mutex as ring priority remains unchanged
after initialization.
4 Remove unused ring->num_jobs.
v3:
In drm_gem_object_free, it will call funcs of drm buffer obj. So
kfd_alloc should use amdgpu_gem_object_create instead of
amdgpu_bo_create to initialize the funcs as amdgpu_gem_object_funcs.
[ 396.231390] amdgpu: Release VA 0x7f76b4ada000 - 0x7f76b4add000
[ 396.231394] amdgpu: remove VA
Am 01.02.21 um 13:07 schrieb Nirmoy Das:
For high priority compute to work properly we need to enable
wave limiting on gfx pipe. Wave limiting is done through writing
into mmSPI_WCL_PIPE_PERCENT_GFX register. Enable only one high
priority compute queue to avoid race condition between multiple
If the user passes a "level" value which is higher than 31 then that
leads to shift wrapping. The undefined behavior will lead to a
syzkaller stack dump.
Fixes: 5632708f4452 ("drm/amd/powerplay: add dpm force multiple levels on
cz/tonga/fiji/polaris (v2)")
Signed-off-by: Dan Carpenter
---
[AMD Public Use]
+ case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
+ r = amdgpu_asic_query_video_codecs(adev, true, );
+ if (r)
+ return -EINVAL;
+ break;
+ break;
One
[Why & How]
On DCN1.0, need otg vertical line interrupt to get appropriate timing
to achieve specific feature request.
Add otg vertical interrupt0 support for registers which operation is
vertical sensitive.
Signed-off-by: Wayne Lin
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 22
[Why & How]
In order to get appropriate timing for registers which
read/write is vertical line sensitive, add new IRQ source variable.
This interrupt is triggered by specific vertical line,
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
1 file changed, 1 insertion(+)
On Mon, Feb 01, 2021 at 10:25:36PM +0800, Kuehling, Felix wrote:
> Thank you for catching this. I haven't had a chance to try out Alex's
> rebased branch myself yet. I think this needs a
>
> Fixes: 246cb7e49a70 ("drm/amdgpu: Introduce GEM object functions")
>
> With that fixed, the patch is
[AMD Official Use Only - Internal Distribution Only]
Tested-by: Changfeng
BR,
Changfeng.
-Original Message-
From: Huang, Ray
Sent: Monday, February 1, 2021 6:39 PM
To: amd-gfx@lists.freedesktop.org
Cc: Kuehling, Felix ; Deucher, Alexander
; Koenig, Christian ; Zhu,
Changfeng ;
On Mon, Feb 1, 2021 at 11:13 AM Christian König
wrote:
>
> Am 01.02.21 um 16:51 schrieb Nirmoy Das:
> > This patch consist of below related changes:
> >
> > 1 Rename ring->priority to ring->hw_prio.
> > 2 Assign correct hardware ring priority.
> > 3 Remove ring->priority_mutex as ring priority
On 1/28/2021 7:00 PM, Xingyou Chen wrote:
> On 2021/1/27 上午5:46, Brian Welty wrote:
>
>> We'd like to revisit the proposal of a GPU cgroup controller for managing
>> GPU devices but with just a basic set of controls. This series is based on
>> the prior patch series from Kenny Ho [1]. We take
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