Add video_codecs query support for aldebaran.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 080e715..75008cc 100644
---
When this is not compliant with RFC4122 then why do we try to expose a
UUID which seems to be compliant?
And emulating it for older hardware doesn't sounds like something I
would want in the kernel driver. That can perfectly be handled in
userspace as far as I can see.
Christian.
Am
Well not an expert on that stuff, but looks like that should work for me.
Question is can you provide a patch to use that information in Mesa as
well? Umr might be sufficient as well as justification for upstreaming,
but I want to be better save than sorry.
Unless Marek has a better idea
[AMD Official Use Only - Internal Distribution Only]
If changing the ioctl is an issue why not just use sysfs? umr already makes
uses of all three for it's purposes so it's fine by me for either.
Tom
From: amd-gfx on behalf of Christian
König
Sent:
Add AMDGPU_INFO_VBIOS_INFO subquery id for detailed vbios info.
Provides a way for the user application to get the VBIOS
information without having to parse the binary.
It is useful for the user to be able to display in a simple way the VBIOS
version in their system if they happen to encounter an
WIth Kevin's comments addressed, the patch is:
Reviewed-by: Alex Deucher
On Tue, May 18, 2021 at 5:36 AM Wang, Kevin(Yang) wrote:
>
> [AMD Official Use Only]
>
>
>
>
>
> From: amd-gfx on behalf of Aaron Liu
>
> Sent: Tuesday, May 18, 2021 2:26 PM
> To:
Am 18.05.21 um 05:00 schrieb xinhui pan:
looks like we forget to set ttm->sg to NULL.
Hit panic below
[ 1235.844104] general protection fault, probably for non-canonical address
0x6b6b6b6b6b6b7b4b: [#1] SMP DEBUG_PAGEALLOC NOPTI
[ 1235.862186] CPU: 5 PID: 25180 Comm: kfdtest Tainted: G
Am 17.05.21 um 22:42 schrieb James Zhu:
Add cancel_delayed_work_sync before set power gating state
to avoid race condition issue when power gating.
Sounds logical to me, but Leo needs to take a look as well.
Acked-by: Christian König
Signed-off-by: James Zhu
---
[Public]
Not sure about this one - vbios version : 285409288
Windows driver reports VBIOS version from atom_firmware_info_v3_1 /
firmware_revision.
Thanks,
Lijo
From: amd-gfx On Behalf Of Gu, JiaWei
(Will)
Sent: Tuesday, May 18, 2021 11:28 AM
To: Nieto, David M ; Koenig, Christian
;
The function kfd_lookup_process_by_pasid will increase the reference
count of kfd_process object, its caller should call kfd_unref_process to
decrease the reference count. Otherwise resource leakage will happen.
Signed-off-by: Dennis Li
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
[AMD Official Use Only]
From: amd-gfx on behalf of Aaron Liu
Sent: Tuesday, May 18, 2021 2:26 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Liu, Aaron
Subject: [PATCH] drm/amdgpu: modify system reference clock source for navi+
[AMD Official Use Only - Internal Distribution Only]
Hi all,
Please help confirm that we're all fine with this new struct in uapi in this V3
patch:
+struct drm_amdgpu_info_vbios {
+ __u8 name[64];
+ __u8 vbios_pn[64];
+ __u32 version;
+ __u8 vbios_ver_str[32];
+
[AMD Official Use Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Dennis Li
Sent: Tuesday, May 18, 2021 19:59
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Kuehling, Felix ; Zhang,
Hawking ; Koenig, Christian
Cc: Li, Dennis
Subject: [PATCH]
In a separate discussion with Daniel we once more iterated over the
dma_resv requirements and I came to the conclusion that this approach
here won't work reliable.
The problem is as following:
1. device A schedules some rendering with into a buffer and exports it
as DMA-buf.
2. device B
On Tue, May 18, 2021 at 10:16 AM Aaron Liu wrote:
>
> Starting from Navi+, the rlc reference clock is used for system clock
> from vbios gfx_info table. It is incorrect to use core_refclk_10khz of
> vbios smu_info table as system clock.
>
> Signed-off-by: Aaron Liu
Reviewed-by: Alex Deucher
>
Am 18.05.21 um 17:45 schrieb James Zhu:
On 2021-05-18 11:23 a.m., Christian König wrote:
Am 18.05.21 um 17:11 schrieb James Zhu:
Add cancel_delayed_work_sync before set power gating state
to avoid race condition issue when power gating.
Signed-off-by: James Zhu
---
Ping
Andrey
On 2021-05-17 3:31 p.m., Andrey Grodzovsky wrote:
Access to those must be prevented post pci_remove
v6: Drop BOs list, unampping VRAM BAR is enough.
v8:
Add condition of xgmi.connected_to_cpu to MTTR
handling and remove MTTR handling from the old place.
Signed-off-by: Andrey
[Public]
Reviewed-by: Alex Deucher
From: Grodzovsky, Andrey
Sent: Tuesday, May 18, 2021 10:01 AM
To: dri-de...@lists.freedesktop.org ;
amd-gfx@lists.freedesktop.org ;
linux-...@vger.kernel.org ;
ckoenig.leichtzumer...@gmail.com ;
daniel.vet...@ffwll.ch ;
Starting from Navi+, the rlc reference clock is used for system clock
from vbios gfx_info table. It is incorrect to use core_refclk_10khz of
vbios smu_info table as system clock.
Signed-off-by: Aaron Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 15 +++
1 file changed,
On 2021-05-17 4:34 a.m., Pekka Paalanen wrote:
> On Fri, 14 May 2021 17:04:51 -0400
> Harry Wentland wrote:
>
>> On 2021-04-30 8:53 p.m., Sebastian Wick wrote:
>>> On 2021-04-26 20:56, Harry Wentland wrote:
>
> ...
>
Another reason I'm proposing to define the color space (and gamma) of
Am 18.05.21 um 17:03 schrieb Andrey Grodzovsky:
On 2021-05-18 10:07 a.m., Christian König wrote:
In a separate discussion with Daniel we once more iterated over the
dma_resv requirements and I came to the conclusion that this approach
here won't work reliable.
The problem is as following:
On 2021-05-17 3:08 p.m., Alex Deucher wrote:
> Unused so remove them.
>
> Fixes: 5791d219561cb6 ("drm/amd/display: Refactor and add visual confirm for
> HW Flip Queue")
> Signed-off-by: Alex Deucher
> Cc: Wyatt Wood
Series is
Reviewed-by: Harry Wentland
Harry
> ---
>
On 2021-05-18 11:23 a.m., Christian König wrote:
Am 18.05.21 um 17:11 schrieb James Zhu:
Add cancel_delayed_work_sync before set power gating state
to avoid race condition issue when power gating.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 19 ++-
On 2021-05-11 11:44 a.m., Alex Deucher wrote:
> To stay consistent with the user's setting.
>
> v2: rebase on multi-eDP support
>
Series is
Reviewed-by: Harry Wentland
Harry
> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1337>> Signed-off-by:
> Alex Deucher
> ---
>
On 2021-05-18 11:54 a.m., Christian König wrote:
Am 18.05.21 um 17:45 schrieb James Zhu:
On 2021-05-18 11:23 a.m., Christian König wrote:
Am 18.05.21 um 17:11 schrieb James Zhu:
Add cancel_delayed_work_sync before set power gating state
to avoid race condition issue when power gating.
On 2021-05-18 11:15 a.m., Christian König wrote:
Am 18.05.21 um 17:03 schrieb Andrey Grodzovsky:
On 2021-05-18 10:07 a.m., Christian König wrote:
In a separate discussion with Daniel we once more iterated over the
dma_resv requirements and I came to the conclusion that this approach
here
On 2021-05-17 11:33 a.m., xgqt wrote:
> Hello!
>
> I run a AMD laptop "81NC Lenovo IdeaPad S340-15API" - AMD Ryzen 5 3500U with
> Radeon Vega 8 Graphics.
> Recently some breakages started happening for me. In about 1h after boot-up
> while using a KDE desktop machine GUI would freeze. Sometimes
Add cancel_delayed_work_sync before set power gating state
to avoid race condition issue when power gating.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git
Am 18.05.21 um 18:17 schrieb Andrey Grodzovsky:
On 2021-05-18 11:15 a.m., Christian König wrote:
Am 18.05.21 um 17:03 schrieb Andrey Grodzovsky:
On 2021-05-18 10:07 a.m., Christian König wrote:
In a separate discussion with Daniel we once more iterated over the
dma_resv requirements and I
On Mon, May 17, 2021 at 1:54 AM Jiawei Gu wrote:
>
> Introduce an RFC 4122 compliant UUID for the GPUs derived
> from the unique GPU serial number (from Vega10) on gpus.
> Where this serial number is not available, use a compliant
> random UUID.
>
> For virtualization, the unique ID is passed by
On 2021-05-18 3:56 a.m., Pekka Paalanen wrote:
> On Mon, 17 May 2021 15:39:03 -0400
> Vitaly Prosyak wrote:
>
>> On 2021-05-17 12:48 p.m., Sebastian Wick wrote:
>>> On 2021-05-17 10:57, Pekka Paalanen wrote:
On Fri, 14 May 2021 17:05:11 -0400
Harry Wentland wrote:
> On
Reviewed-by: Leo Liu
On 2021-05-17 4:42 p.m., James Zhu wrote:
Add cancel_delayed_work_sync before set power gating state
to avoid race condition issue when power gating.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 19 +--
1 file changed, 13
Reviewed-by: Leo Liu
On 2021-05-18 8:47 a.m., James Zhu wrote:
Add video_codecs query support for aldebaran.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
This unfortunately comes up in regular intervals and breaks
GPU reset for the engine in question.
The sched.ready flag controls if an engine can't get working
during hw_init, but should never be set to false during hw_fini.
Signed-off-by: Christian König
---
On 2021-05-18 10:07 a.m., Christian König wrote:
In a separate discussion with Daniel we once more iterated over the
dma_resv requirements and I came to the conclusion that this approach
here won't work reliable.
The problem is as following:
1. device A schedules some rendering with into a
Am 18.05.21 um 17:11 schrieb James Zhu:
Add cancel_delayed_work_sync before set power gating state
to avoid race condition issue when power gating.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
Am 18.05.21 um 17:59 schrieb James Zhu:
On 2021-05-18 11:54 a.m., Christian König wrote:
Am 18.05.21 um 17:45 schrieb James Zhu:
On 2021-05-18 11:23 a.m., Christian König wrote:
Am 18.05.21 um 17:11 schrieb James Zhu:
Add cancel_delayed_work_sync before set power gating state
to avoid
On 2021-05-18 2:02 p.m., Christian König wrote:
Am 18.05.21 um 19:43 schrieb Andrey Grodzovsky:
On 2021-05-18 12:33 p.m., Christian König wrote:
Am 18.05.21 um 18:17 schrieb Andrey Grodzovsky:
On 2021-05-18 11:15 a.m., Christian König wrote:
Am 18.05.21 um 17:03 schrieb Andrey
On 2021-05-18 2:06 p.m., Christian König wrote:
Am 18.05.21 um 19:04 schrieb James Zhu:
On 2021-05-18 12:36 p.m., Christian König wrote:
Am 18.05.21 um 17:59 schrieb James Zhu:
On 2021-05-18 11:54 a.m., Christian König wrote:
Am 18.05.21 um 17:45 schrieb James Zhu:
On 2021-05-18 11:23
On 05/14, Mark Yacoub wrote:
> On Fri, May 14, 2021 at 12:31 PM Mark Yacoub wrote:
> >
> > On Fri, May 14, 2021 at 11:28 AM Harry Wentland
> > wrote:
> > >
> > > On 2021-05-14 7:47 a.m., Rodrigo Siqueira wrote:
> > > > A few weeks ago, we saw a two cursor issue in a ChromeOS system. We
> > > >
On 2021-05-18 2:13 p.m., Christian König wrote:
Am 18.05.21 um 20:09 schrieb Andrey Grodzovsky:
On 2021-05-18 2:02 p.m., Christian König wrote:
Am 18.05.21 um 19:43 schrieb Andrey Grodzovsky:
On 2021-05-18 12:33 p.m., Christian König wrote:
Am 18.05.21 um 18:17 schrieb Andrey Grodzovsky:
On 2021-05-18 12:36 p.m., Christian König wrote:
Am 18.05.21 um 17:59 schrieb James Zhu:
On 2021-05-18 11:54 a.m., Christian König wrote:
Am 18.05.21 um 17:45 schrieb James Zhu:
On 2021-05-18 11:23 a.m., Christian König wrote:
Am 18.05.21 um 17:11 schrieb James Zhu:
Add
[Public]
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Christian
König
Sent: Tuesday, May 18, 2021 11:50 AM
To: Zhu, James
Cc: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: stop touching sched.ready in the backend
This unfortunately
Am 18.05.21 um 19:04 schrieb James Zhu:
On 2021-05-18 12:36 p.m., Christian König wrote:
Am 18.05.21 um 17:59 schrieb James Zhu:
On 2021-05-18 11:54 a.m., Christian König wrote:
Am 18.05.21 um 17:45 schrieb James Zhu:
On 2021-05-18 11:23 a.m., Christian König wrote:
Am 18.05.21 um
Am 18.05.21 um 19:43 schrieb Andrey Grodzovsky:
On 2021-05-18 12:33 p.m., Christian König wrote:
Am 18.05.21 um 18:17 schrieb Andrey Grodzovsky:
On 2021-05-18 11:15 a.m., Christian König wrote:
Am 18.05.21 um 17:03 schrieb Andrey Grodzovsky:
On 2021-05-18 10:07 a.m., Christian König
Am 18.05.21 um 20:09 schrieb Andrey Grodzovsky:
On 2021-05-18 2:02 p.m., Christian König wrote:
Am 18.05.21 um 19:43 schrieb Andrey Grodzovsky:
On 2021-05-18 12:33 p.m., Christian König wrote:
Am 18.05.21 um 18:17 schrieb Andrey Grodzovsky:
On 2021-05-18 11:15 a.m., Christian König wrote:
On 2021-05-18 12:33 p.m., Christian König wrote:
Am 18.05.21 um 18:17 schrieb Andrey Grodzovsky:
On 2021-05-18 11:15 a.m., Christian König wrote:
Am 18.05.21 um 17:03 schrieb Andrey Grodzovsky:
On 2021-05-18 10:07 a.m., Christian König wrote:
In a separate discussion with Daniel we once
On Tue, May 18, 2021 at 10:11 AM Michel Dänzer wrote:
>
> On 2021-05-17 11:33 a.m., xgqt wrote:
> > Hello!
> >
> > I run a AMD laptop "81NC Lenovo IdeaPad S340-15API" - AMD Ryzen 5 3500U
> > with Radeon Vega 8 Graphics.
> > Recently some breakages started happening for me. In about 1h after
For Aldebaran, driver needs to query DramMegaBaseAddress to
check if DF hashing is enabled.
Signed-off-by: Mukul Joshi
Acked-by: Alex Deucher
Reviewed-by: Harish Kasiviswanathan
---
drivers/gpu/drm/amd/amdgpu/df_v3_6.c| 9 +
[AMD Official Use Only]
I think the sysfs node should be moved into amdgpu_pm instead of the
amdgpu_device.c and generation of the unique_id should be moved to
navi10_ppt.c, similarly to other chips.
Thinking it better, generating a random UUID makes no sense in the driver
level, any
On 2021-05-18 2:48 p.m., Andrey Grodzovsky wrote:
On 2021-05-18 2:13 p.m., Christian König wrote:
Am 18.05.21 um 20:09 schrieb Andrey Grodzovsky:
On 2021-05-18 2:02 p.m., Christian König wrote:
Am 18.05.21 um 19:43 schrieb Andrey Grodzovsky:
On 2021-05-18 12:33 p.m., Christian König
Do we need a similar check in the vega powerplay code?
Alex
On Mon, May 17, 2021 at 10:59 PM Feng, Kenneth wrote:
>
> [AMD Official Use Only]
>
> Reviewed-by: Kenneth Feng
>
> -Original Message-
> From: Quan, Evan
> Sent: Tuesday, May 18, 2021 10:05 AM
> To:
Can also add:
Fixes: https://gitlab.freedesktop.org/drm/amd/-/issues/1580
Reviewed-by: Alex Deucher
Alex
On Tue, May 18, 2021 at 10:12 PM Alex Deucher wrote:
>
> Do we need a similar check in the vega powerplay code?
>
> Alex
>
>
> On Mon, May 17, 2021 at 10:59 PM Feng, Kenneth wrote:
> >
>
cpu 1 cpu 2
kfd alloc BO A(userptr) alloc BO B(GTT)
->init -> validate -> init -> validate -> populate
init_user_pages -> swapout BO A //hit ttm
pages limit
->
Signed-off-by: xinhui pan
---
drivers/gpu/drm/ttm/ttm_device.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c
index 510e3e001dab..a9772fcc8f9c 100644
--- a/drivers/gpu/drm/ttm/ttm_device.c
+++
On 2021-05-18 16:19, Harry Wentland wrote:
On 2021-05-18 3:56 a.m., Pekka Paalanen wrote:
On Mon, 17 May 2021 15:39:03 -0400
Vitaly Prosyak wrote:
On 2021-05-17 12:48 p.m., Sebastian Wick wrote:
On 2021-05-17 10:57, Pekka Paalanen wrote:
On Fri, 14 May 2021 17:05:11 -0400
Harry Wentland
On Tue, May 18, 2021 at 10:13 PM Alex Deucher wrote:
>
> Can also add:
> Fixes: https://gitlab.freedesktop.org/drm/amd/-/issues/1580
er,
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1580
>
> Reviewed-by: Alex Deucher
>
> Alex
>
> On Tue, May 18, 2021 at 10:12 PM Alex Deucher wrote:
>
Care to submit a patch to re-enable the extra compute queues?
Alex
On Mon, May 17, 2021 at 4:09 AM Zhu, Changfeng wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Ray and Alex,
>
> I have confirmed it can enable the additional compute queues with this patch:
>
> [
[AMD Official Use Only - Internal Distribution Only]
Hi Alex.
I have submitted the patch: drm/amdgpu: disable 3DCGCG on picasso/raven1 to
avoid compute hang
Do you mean we have something else to do for re-enabling the extra compute
queues?
BR,
Changfeng.
-Original Message-
From:
[Public]
+ Nirmoy
I thought we disabled all but one of the compute queues on raven due to this
issue. Maybe that patch never landed? Wasn't this the same issue that was
exposed by Nirmoy's patch that provided better load balancing across queues?
Alex
From:
[Public]
Nirmoy's patch landed already if I understand correctly.
d41a39dda140 drm/scheduler: improve job distribution with multiple queues
Regards,
Guchun
From: amd-gfx On Behalf Of Zhu,
Changfeng
Sent: Wednesday, May 19, 2021 10:56 AM
To: Deucher, Alexander ; Alex Deucher
; Das, Nirmoy
Mesa doesn't have any use for this. It should be ok to expose just the
ioctl without userspace because it's just vbios info.
Marek
On Tue., May 18, 2021, 22:41 Gu, JiaWei (Will), wrote:
> [AMD Official Use Only - Internal Distribution Only]
>
> Thanks Tom's suggestion.
> I'm fine to replace
[Public]
I check the patch (below) to disable compute queues for raven is not landed
into drm-next. So actually all queues are enabled at this moment. Nirmoy, can
we get your confirmation?
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index
[Public]
That is correct, it is 0x11030008, that matches the FW information.
From: Lazar, Lijo
Sent: Tuesday, May 18, 2021 3:50 AM
To: Gu, JiaWei (Will) ; Nieto, David M
; Koenig, Christian ;
amd-gfx@lists.freedesktop.org ; mar...@gmail.com
; Deucher,
[AMD Official Use Only]
yes, we really dont swapout SG BOs.
The problems is that before we validate a userptr BO, we create this BO in CPU
domain by default. So this BO has chance to swapout.
we set flag TTM_PAGE_FLAG_SG on userptr BO in popluate() which is too late.
I have not try to revert
[AMD Official Use Only]
I have reverted Chris' patch, still hit this failure.
Just see two lines in Chris' patch. Any BO in cpu domian would be swapout
first. That is why we hit this issue frequently now. But the bug is there long
time ago.
- for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) {
[AMD Official Use Only - Internal Distribution Only]
Thanks Tom's suggestion.
I'm fine to replace ioctl with sysfs.
Hi all, how about this sysfs alternative?
And if it's a must to insist on ioctl, is there any Mesa expert to help provide
the patch?
Best regards,
Jiawei
-Original
[Public]
Hi Alex,
This is the issue exposed by Nirmoy's patch that provided better load balancing
across queues.
BR,
Changfeng.
From: Deucher, Alexander
Sent: Wednesday, May 19, 2021 10:53 AM
To: Zhu, Changfeng ; Alex Deucher
; Das, Nirmoy
Cc: Huang, Ray ; amd-gfx list
Subject: Re:
[Public]
I thought we had disabled all but one of the compute queues on raven due to
this issue or at least disabled the schedulers for the additional queues, but
maybe I'm misremembering.
Alex
From: Chen, Guchun
Sent: Tuesday, May 18, 2021 11:00 PM
To: Zhu,
1.correct KFD SDMA RLC queue register offset error.
(all sdma rlc register offset is base on SDMA0.RLC0_RLC0_RB_CNTL)
2.HQD_N_REGS (19+6+7+12)
12: the 2 more resgisters than navi1x (SDMAx_RLCy_MIDCMD_DATA{9,10})
the patch also can be fixed NULL pointer issue when read
/sys/kernel/debug/kfd/hqds
[AMD Official Use Only]
To observe the issue. I made one kfdtest case for debug.
It just alloc a userptr memory and detect if memory is corrupted.
I can hit this failure in 2 minutes. :(
diff --git a/tests/kfdtest/src/KFDMemoryTest.cpp
b/tests/kfdtest/src/KFDMemoryTest.cpp
index
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Likun Gao
Regards,
Likun
-Original Message-
From: Wang, Kevin(Yang)
Sent: Wednesday, May 19, 2021 11:22 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Kuehling, Felix
; Min, Frank ; Gao, Likun
; Wang,
Swapping SG BOs makes no sense, because TTM doesn't own the pages of
this type of BO.
Last I checked, userptr BOs (and other SG BOs) were protected from
swapout by the fact that they would not be added to the swap-LRU. But it
looks like Christian just removed the swap-LRU. I guess this broke
On Mon, 17 May 2021 15:39:03 -0400
Vitaly Prosyak wrote:
> On 2021-05-17 12:48 p.m., Sebastian Wick wrote:
> > On 2021-05-17 10:57, Pekka Paalanen wrote:
> >> On Fri, 14 May 2021 17:05:11 -0400
> >> Harry Wentland wrote:
> >>
> >>> On 2021-04-27 10:50 a.m., Pekka Paalanen wrote:
> >>> >
On Fri, 14 May 2021 17:07:14 -0400
Harry Wentland wrote:
> We are looking to enable HDR support for a couple of single-plane and
> multi-plane scenarios. To do this effectively we recommend new interfaces
> to drm_plane. The first patch gives a bit of background on HDR and why we
> propose these
On Tue, May 18, 2021 at 02:26:03PM +0800, Liu, Aaron wrote:
> Starting from Navi+, the rlc reference clock is used for system clock
> from vbios gfx_info table. It is incorrect to use core_refclk_10khz of
> vbios smu_info table as system clock.
>
> Signed-off-by: Aaron Liu
Acked-by: Huang Rui
On 5/18/2021 9:39 AM, David M Nieto wrote:
Fill voltage fields in metrics table
Signed-off-by: David M Nieto
---
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 62 ++-
1 file changed, 45 insertions(+), 17 deletions(-)
diff --git
On 5/18/2021 9:39 AM, David M Nieto wrote:
Enable displaying DPM levels for VCN clocks
in swsmu supported ASICs
Signed-off-by: David M Nieto
---
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 46 ++
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 4 ++
SG BOs such as dmabuf imports and userptr BOs do not consume system
resources directly. Instead they point to resources owned elsewhere.
They typically get evicted by DMABuf move notifiers of MMU notifiers.
If those notifiers don't need to wait for hardware fences (i.e. the SG
BOs are used in a
KFD userptr BOs and SG BOs used for DMA mappings can be preempted with
CWSR. Therefore we can place them in the preemptible domain and avoid
unwanted evictions.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 6 +++---
1 file changed, 3 insertions(+), 3
The intel IOMMU driver causes kernel oopses or internal errors flooding
kernel log when mapping larger SG tables. Limiting the size of userptr BOs
to 6GB seems to avoid this.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 +++
1 file changed, 3
Hi Xinhui,
This should be another way to fix the userptr swapout problem you found.
This is meant to address a long-stadinp problem with userptr BOs getting
evicted (not swapped), which broke DMA mappings. This patch series is
meant to completely avoid evictions of userptrs and dma mappings
Starting from Navi+, the rlc reference clock is used for system clock
from vbios gfx_info table. It is incorrect to use core_refclk_10khz of
vbios smu_info table as system clock.
Signed-off-by: Aaron Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 15 +++
1 file changed,
[Public]
That looks like the right output to me.
From: Gu, JiaWei (Will)
Sent: Monday, May 17, 2021 10:58 PM
To: Nieto, David M ; Koenig, Christian
; amd-gfx@lists.freedesktop.org
; mar...@gmail.com ; Deucher,
Alexander
Cc: Deng, Emily
Subject: RE: [PATCH]
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