tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 71941773e143369a73c9c4a3b62fbb60736a1182 Add linux-next specific
files for 20220310
Error/Warning reports:
https://lore.kernel.org/linux-doc/202202240704.pqd40a9l-...@intel.com
https
In https://lore.kernel.org/lkml/20211209150910.ga23...@axis.com/
Vincent's patch commented on, and worked around, a bug toggling
static_branch's, when a 2nd PRINTK-ish flag was added. The bug
results in a premature static_branch_disable when the 1st of 2 flags
was disabled.
The cited commit
DRM defines/uses 10 enum drm_debug_category's to create exclusive
classes of debug messages. To support this directly in dynamic-debug,
add the following:
- struct _ddebug.class_id:4 - 4 bits is enough
- define _DPRINTK_SITE_UNCLASSED 15 - see below
and the query support:
- struct
DEFINE_DYNAMIC_DEBUG_CLASSBITS(fsname, var, bitmap_desc, classes..)
allows users to create a drm.debug style (bitmap) sysfs interface, to
control sets of pr_debug's according to their .class_id's
This wraps existing "class" keyword and behavior:
bash-5.1# echo < /proc/dynamic_debug/control
This exported fn is effectively obsoleted by Commit:HEAD~2, so remove it.
Its intent was to allow drm.debug to use the exported function to
implement its drm.debug bitmap api using dynamic_debug. Instead,
HEAD~2 implements the bitmap inside dyndbg, using the internal fn that
the export wraps.
print old -> new flag values in the info("change") message.
Signed-off-by: Jim Cromie
---
lib/dynamic_debug.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/lib/dynamic_debug.c b/lib/dynamic_debug.c
index b15a9c715e5b..cceac8ebbacd 100644
---
Hi Greg, Jason,
Please consider these for char/misc or linux-next/soon/mumble.
This patchset adds exclusive class support to dyndbg, allowing it to
directly represent drm's debug_category.
It is the dyndbg half of:
https://lore.kernel.org/lkml/20220217034829.64395-1-jim.cro...@gmail.com/
The
Am 09.03.22 um 19:12 schrieb Rob Clark:
On Tue, Mar 8, 2022 at 11:40 PM Shashank Sharma
wrote:
From: Shashank Sharma
This patch adds a new sysfs event, which will indicate
the userland about a GPU reset, and can also provide
some information like:
- process ID of the process involved with
Am 10.03.22 um 07:11 schrieb Victor Zhao:
add parameter soft_reset_enable to control the enablement of
soft reset
NAK, proper working soft recovery is something mandatory and shouldn't
be controlled by the end user.
Marek and I have also decided to completely disable job re-submission on
Am 10.03.22 um 07:11 schrieb Victor Zhao:
In order to get more accurate engine hang detection, pass the hang
job to check_soft_reset to find the hang engine instead of check
register status.
NAK, the amdgpu_ring_soft_recovery() function already gets the hardware
fence as parameter.
That
[AMD Official Use Only]
The asic structure has a function callback "errmsg" which should be used for
this.
Tom
From: Tuikov, Luben
Sent: Wednesday, March 9, 2022 19:42
To: amd-gfx@lists.freedesktop.org
Cc: Tuikov, Luben; Deucher, Alexander; StDenis,
[AMD Official Use Only]
This will fail to create the sysfs attributes for SS1.0.
Regards,
Sathish
-Original Message-
From: amd-gfx On Behalf Of Lazar, Lijo
Sent: Thursday, March 10, 2022 10:58 AM
To: Limonciello, Mario ;
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] amdgpu/pm:
Leo you didn't answered the question if we need TMZ for encode as well.
Regards,
Christian.
Am 10.03.22 um 09:45 schrieb Lang Yu:
Ping.
On 03/08/ , Leo Liu wrote:
On 2022-03-08 11:18, Leo Liu wrote:
On 2022-03-08 04:16, Christian König wrote:
Am 08.03.22 um 09:06 schrieb Lang Yu:
On
Am 10.03.22 um 07:11 schrieb Victor Zhao:
enable sdma v5_2 soft reset
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 79 +-
1 file changed, 78 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
xgmi_ras is only initialized when host to GPU interface
is PCIE. in such case, xgmi23 is disabled and protected
by security firmware. Host access will results to
security violation
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 22 --
1 file
Reviewed-by: Tao Zhou
> -Original Message-
> From: Hawking Zhang
> Sent: Thursday, March 10, 2022 4:14 PM
> To: amd-gfx@lists.freedesktop.org; Zhou1, Tao
> Cc: Zhang, Hawking
> Subject: [PATCH] drm/amdgpu: drop xmgi23 error query/reset support
>
> xgmi_ras is only initialized when
Schedule work function with valid PID, process name and
vram lost status during a GPU reset/recovery.
Signed-off-by: Somalapuram Amaranath
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
[AMD Official Use Only]
Reviewed-by: Evan Quan
> -Original Message-
> From: Stanley.Yang
> Sent: Thursday, March 10, 2022 10:02 PM
> To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
> ; Zhou1, Tao ; Li,
> Candice ; Quan, Evan
> Cc: Yang, Stanley
> Subject: [PATCH Review 1/1]
Ok, thanks.
Lang is that case your patch should work fine.
Just add another patch with a check for the encode case to reject any CS
with TMZ buffers in it.
Thanks,
Christian.
Am 10.03.22 um 15:17 schrieb Leo Liu:
No need for encode. Encrypting uses TEE/TA to convert clear bitstream
to
Change-Id: I6afe0332cbb20528648c38665264930d6b091c2f
Signed-off-by: Stanley.Yang
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index
[AMD Official Use Only]
Patches 2-4 look great. With #1 swapped out to use asic->errmsg() you can
throw my Rb on them.
Tom
From: Tuikov, Luben
Sent: Wednesday, March 9, 2022 19:42
To: amd-gfx@lists.freedesktop.org
Cc: Tuikov, Luben; Deucher,
On Thu, Mar 10, 2022 at 1:55 AM Christian König
wrote:
>
>
>
> Am 09.03.22 um 19:12 schrieb Rob Clark:
> > On Tue, Mar 8, 2022 at 11:40 PM Shashank Sharma
> > wrote:
> >> From: Shashank Sharma
> >>
> >> This patch adds a new sysfs event, which will indicate
> >> the userland about a GPU reset,
Reviewed-by: Andrey Grodzovsky
Andrey
On 2022-03-10 04:07, Somalapuram Amaranath wrote:
Schedule work function with valid PID, process name and
vram lost status during a GPU reset/recovery.
Signed-off-by: Somalapuram Amaranath
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13
On 08/03/22 10:31 pm, Matthew Auld wrote:
> On 08/03/2022 13:59, Arunpravin wrote:
>>
>>
>> On 07/03/22 10:11 pm, Matthew Auld wrote:
>>> On 07/03/2022 14:37, Arunpravin wrote:
place BUG_ON(order < min_order) outside do..while
loop as it fails Unigine Heaven benchmark.
On 2022-03-10 00:17, Lazar, Lijo wrote:
On 3/10/2022 2:33 AM, Andrey Grodzovsky wrote:
It will be used during GPU reset.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 10 +++
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 3 +++
On 10/03/2022 14:47, Arunpravin wrote:
On 08/03/22 10:31 pm, Matthew Auld wrote:
On 08/03/2022 13:59, Arunpravin wrote:
On 07/03/22 10:11 pm, Matthew Auld wrote:
On 07/03/2022 14:37, Arunpravin wrote:
place BUG_ON(order < min_order) outside do..while
loop as it fails Unigine Heaven
From: "Tianci.Yin"
[why]
CP hangs in igt reloading test on renoir, more precisely, hangs on the
second time insmod.
[how]
mode2 reset can make it recover, and mode2 reset only effects gfx core,
dcn and the screen will not be impacted.
Signed-off-by: Tianci.Yin
---
No need for encode. Encrypting uses TEE/TA to convert clear bitstream to
encrypted bitstream, and has nothing to do with VCN encode and tmz.
Regards,
Leo
On 2022-03-10 04:53, Christian König wrote:
Leo you didn't answered the question if we need TMZ for encode as well.
Regards,
Christian.
On 2022-03-10 05:06, Christian König wrote:
Am 10.03.22 um 07:11 schrieb Victor Zhao:
enable sdma v5_2 soft reset
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 79 +-
1 file changed, 78 insertions(+), 1 deletion(-)
diff --git
On 3/10/2022 6:10 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 8:21 AM Sharma, Shashank
wrote:
On 3/10/2022 4:24 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 1:55 AM Christian König
wrote:
Am 09.03.22 um 19:12 schrieb Rob Clark:
On Tue, Mar 8, 2022 at 11:40 PM Shashank Sharma
DEVICE_COHERENT pages introduce a subtle distinction in the way
"normal" pages can be used by various callers throughout the kernel.
They behave like normal pages for purposes of mapping in CPU page
tables, and for COW. But they do not support LRU lists, NUMA
migration or THP. Therefore we split
Test device pages with get_user_pages and get_user_pages_fast.
The motivation is to test device coherent type pages in the gup and
gup fast paths, after vm_normal_pages was split into LRU and non-LRU
handled.
Signed-off-by: Alex Sierra
Acked-by: Felix Kuehling
---
The objective is to test device migration mechanism in pages marked
as COW, for private and coherent device type. In case of writing to
COW private page(s), a page fault will migrate pages back to system
memory first. Then, these pages will be duplicated. In case of COW
device coherent type, pages
DEVICE_COHERENT pages introduce a subtle distinction in the way
"normal" pages can be used by various callers throughout the kernel.
They behave like normal pages for purposes of mapping in CPU page
tables, and for COW. But they do not support LRU lists, NUMA
migration or THP. Therefore we split
On Thu, Mar 10, 2022 at 8:27 AM Andrey Grodzovsky
wrote:
>
>
> On 2022-03-10 11:21, Sharma, Shashank wrote:
> >
> >
> > On 3/10/2022 4:24 PM, Rob Clark wrote:
> >> On Thu, Mar 10, 2022 at 1:55 AM Christian König
> >> wrote:
> >>>
> >>>
> >>>
> >>> Am 09.03.22 um 19:12 schrieb Rob Clark:
>
On 2022-03-10 11:21, Sharma, Shashank wrote:
On 3/10/2022 4:24 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 1:55 AM Christian König
wrote:
Am 09.03.22 um 19:12 schrieb Rob Clark:
On Tue, Mar 8, 2022 at 11:40 PM Shashank Sharma
wrote:
From: Shashank Sharma
This patch adds a new
On Thu, Mar 10, 2022 at 9:04 AM Tianci Yin wrote:
>
> From: "Tianci.Yin"
>
> [why]
> CP hangs in igt reloading test on renoir, more precisely, hangs on the
> second time insmod.
>
> [how]
> mode2 reset can make it recover, and mode2 reset only effects gfx core,
> dcn and the screen will not be
On Thu, Mar 10, 2022 at 8:21 AM Sharma, Shashank
wrote:
>
>
>
> On 3/10/2022 4:24 PM, Rob Clark wrote:
> > On Thu, Mar 10, 2022 at 1:55 AM Christian König
> > wrote:
> >>
> >>
> >>
> >> Am 09.03.22 um 19:12 schrieb Rob Clark:
> >>> On Tue, Mar 8, 2022 at 11:40 PM Shashank Sharma
> >>> wrote:
>
On 3/10/2022 9:11 PM, Andrey Grodzovsky wrote:
On 2022-03-10 05:06, Christian König wrote:
Am 10.03.22 um 07:11 schrieb Victor Zhao:
enable sdma v5_2 soft reset
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 79 +-
1 file changed, 78
On 3/10/2022 4:24 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 1:55 AM Christian König
wrote:
Am 09.03.22 um 19:12 schrieb Rob Clark:
On Tue, Mar 8, 2022 at 11:40 PM Shashank Sharma
wrote:
From: Shashank Sharma
This patch adds a new sysfs event, which will indicate
the userland
Okay, I'll rework them and resubmit.
Regards,
Luben
On 2022-03-10 09:22, StDenis, Tom wrote:
> [AMD Official Use Only]
>
> Patches 2-4 look great. With #1 swapped out to use asic->errmsg() you can
> throw my Rb on them.
>
> Tom
>
>
> From: Tuikov,
On Thu, Mar 10, 2022 at 9:19 AM Sharma, Shashank
wrote:
>
>
>
> On 3/10/2022 6:10 PM, Rob Clark wrote:
> > On Thu, Mar 10, 2022 at 8:21 AM Sharma, Shashank
> > wrote:
> >>
> >>
> >>
> >> On 3/10/2022 4:24 PM, Rob Clark wrote:
> >>> On Thu, Mar 10, 2022 at 1:55 AM Christian König
> >>> wrote:
>
On Thu, Mar 10, 2022 at 11:44 AM Sharma, Shashank
wrote:
>
>
>
> On 3/10/2022 8:35 PM, Rob Clark wrote:
> > On Thu, Mar 10, 2022 at 11:14 AM Sharma, Shashank
> > wrote:
> >>
> >>
> >>
> >> On 3/10/2022 7:33 PM, Abhinav Kumar wrote:
> >>>
> >>>
> >>> On 3/10/2022 9:40 AM, Rob Clark wrote:
>
On 3/10/2022 8:56 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 11:44 AM Sharma, Shashank
wrote:
On 3/10/2022 8:35 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 11:14 AM Sharma, Shashank
wrote:
On 3/10/2022 7:33 PM, Abhinav Kumar wrote:
On 3/10/2022 9:40 AM, Rob Clark wrote:
On
[AMD Official Use Only]
Thank you very much Alex!
Regards,
Rico
From: Alex Deucher
Sent: Friday, March 11, 2022 0:52
To: Yin, Tianci (Rico)
Cc: amd-gfx list ; Chen, Guchun
; Zhuo, Qingqing (Lillian) ; Liu,
Wenjing ; Wang, Yu (Charlie) ; Deucher,
Alexander ;
If the GPU is passed through to a guest VM, use the PCI
BAR for CPU FB access rather than the physical address of
carve out. The physical address is not valid in a guest.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 5
On Thu, Mar 10, 2022 at 11:14 AM Sharma, Shashank
wrote:
>
>
>
> On 3/10/2022 7:33 PM, Abhinav Kumar wrote:
> >
> >
> > On 3/10/2022 9:40 AM, Rob Clark wrote:
> >> On Thu, Mar 10, 2022 at 9:19 AM Sharma, Shashank
> >> wrote:
> >>>
> >>>
> >>>
> >>> On 3/10/2022 6:10 PM, Rob Clark wrote:
>
[AMD Official Use Only]
I'm not familiar with SS 1.0 in this regard, can you explain why it would fail
to make the attributes?
I would think the attributes should show up because of
amdgpu_device_supports_smart_shift?
Or are the checks done in that function not sufficient for SS 1.0?
>
On 3/10/2022 7:33 PM, Abhinav Kumar wrote:
On 3/10/2022 9:40 AM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 9:19 AM Sharma, Shashank
wrote:
On 3/10/2022 6:10 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 8:21 AM Sharma, Shashank
wrote:
On 3/10/2022 4:24 PM, Rob Clark wrote:
On
On 3/10/2022 8:35 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 11:14 AM Sharma, Shashank
wrote:
On 3/10/2022 7:33 PM, Abhinav Kumar wrote:
On 3/10/2022 9:40 AM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 9:19 AM Sharma, Shashank
wrote:
On 3/10/2022 6:10 PM, Rob Clark wrote:
On
On 3/10/2022 9:40 AM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 9:19 AM Sharma, Shashank
wrote:
On 3/10/2022 6:10 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 8:21 AM Sharma, Shashank
wrote:
On 3/10/2022 4:24 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 1:55 AM Christian König
Am 2022-03-10 um 14:25 schrieb Matthew Wilcox:
On Thu, Mar 10, 2022 at 11:26:31AM -0600, Alex Sierra wrote:
@@ -606,7 +606,7 @@ static void print_bad_pte(struct vm_area_struct *vma,
unsigned long addr,
* PFNMAP mappings in order to support COWable mappings.
*
*/
-struct page
From: Jing Zhou
[Why & How]
Add null pointer filter for logical integrity.
Reviewed-by: Charlene Liu
Acked-by: Agustin Gutierrez
Signed-off-by: Jing Zhou
---
drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
From: Becle Lee
[Why]
Underflow occurred while hubp ret pipe read is idle and the
second pipe is powered up and added. Flickering and underflow
are only observed on Pollock.
[How]
Check the hubp ret pipe read prior to unlock pipes.
Reviewed-by: Hersen Wu
Reviewed-by: Aric Cyr
Acked-by:
From: Charlene Liu
[why]
DCN31 has this in zstate save/restore sequence.
need for non_zstate supported ASIC
[how]
add this PANEL_PWRSEQ_REF_DIV2 to existing panel_cntl_hw_init structure.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Agustin Gutierrez
Signed-off-by: Charlene Liu
---
From: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Agustin Gutierrez
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
From: Eric Yang
[Why]
Currently Z10 save/restore only covers 1 plane case. If we enter
Z10 with 2 planes enabled, 1 of the 2 planes will not be restored.
causing black screen.
[How]
Disable Zstate when more than 1 plane is enabled. Right now Z9 enable
but Z10 disable is not a supported config,
From: Dale Zhao
[Why]
We must support a new type of partial edid return in the future
[How]
Add interface and case hander for partial edid
Reviewed-by: Charlene Liu
Acked-by: Agustin Gutierrez
Signed-off-by: Dale Zhao
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +++
From: Wayne Lin
[Why]
In dp_get_lane_status_and_lane_adjust(), we call core_link_read_dpcd()
to get lane status but we ignore the return value of the function. If
there is problem with AUX and we eventually can only get partial data
from monitor, we might misuse the data to jude the link
From: "JinZe.Xu"
[How]
1. Search OEM I2C info from BIOS and compare with input parameter.
2. If BIOS doesn't record it, just try to read one byte.
Reviewed-by: Aric Cyr
Acked-by: Agustin Gutierrez
Signed-off-by: JinZe.Xu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 13 ++
From: "Leo (Hanghong) Ma"
[Why]
We need a helper function in dc to grab the pipe from the stream
context.
[How]
Add it.
Reviewed-by: Martin Leung
Acked-by: Agustin Gutierrez
Signed-off-by: Leo (Hanghong) Ma
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 14 ++
From: Wayne Lin
[Why & How]
1. To leverage and simplify the igt tool. Change the value of
retrain when calling preferred training settings.
Now, writing value to link settings triggers link training immediately.
2. Add dc lock when triggering link training in edp_ilr_write()
Reviewed-by:
This DC patchset brings improvements in multiple areas. In summary:
* Fixes on lane status, zstate, engine ddc, debugfx entry.
* Enhancements for Pollock, EDID status.
* Amongst other.
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.108.0
Aric Cyr (1):
drm/amd/display:
From: Aric Cyr
This version brings along following fixes:
- Added I2C escape to support query exist
- Functionality to get pipe from stream context
- debugfs entry fixes
- Block zstate when more than one plane enabled
- Update to engine ddc
- Reading lante status
From: Jing Zhou
[Why]
Crash caused by a ddc update failure
[How]
Update engine ddc before release engine.
Reviewed-by: Wyatt Wood
Reviewed-by: Aric Cyr
Acked-by: Agustin Gutierrez
Signed-off-by: Jing Zhou
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 1 +
1 file changed, 1
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