Am 18.04.24 um 04:58 schrieb YiPeng Chai:
Add interface to reserve bad page.
Signed-off-by: YiPeng Chai
Yeah, that approach looks valid to me. Just keep in mind that
amdgpu_vram_mgr_query_page_status() is not the fastest function cause it
does a linear search.
Apart from that
[AMD Official Use Only - General]
> -Original Message-
> From: Chai, Thomas
> Sent: Thursday, April 18, 2024 10:59 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Chai, Thomas ; Zhang, Hawking
> ; Zhou1, Tao ; Li, Candice
> ; Wang, Yang(Kevin) ; Yang,
> Stanley ; Chai, Thomas
> Subject:
Observed on gfx8 ASIC when KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM is used.
Two attachments use the same VM, root PD would be locked twice.
[ 57.910418] Call Trace:
[ 57.793726] ? reserve_bo_and_cond_vms+0x111/0x1c0 [amdgpu]
[ 57.793820] amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu+0x6c/0x1c0
v1:
because SMU CE valid mca bank will be cleared after reading,
this patch adds mca cache at the driver level to ensure that the mca bank is
not lost.
v2:
refine amdgpu_mca_init/fini/reset() function name.
v3:
add mca_cache.lock support
only add CE bank to mca bank cache.
Signed-off-by: Yang
- Refine mca driver code.
- Centralize mca bank dispatch code logic.
Signed-off-by: Yang Wang
Reviewed-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c | 96 ++---
1 file changed, 53 insertions(+), 43 deletions(-)
diff --git
- remove unused callback functions.
- make part of mca functions static and refine the function order.
Signed-off-by: Yang Wang
Reviewed-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c | 199 --
drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h | 16 --
On 4/22/2024 11:23 AM, Le Ma wrote:
> To adapt to different gc versions in gfx_v9_4_3.c file.
>
> Change-Id: Ib4465aade0dcbbcc43318c6dc865f813c5411097
> Signed-off-by: Le Ma
> Reviewed-by: Hawking Zhang
Reviewed-by: Lijo Lazar
Thanks,
Lijo
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
[AMD Official Use Only - General]
-
Best Regards,
Thomas
-Original Message-
From: Zhou1, Tao
Sent: Monday, April 22, 2024 4:14 PM
To: Chai, Thomas ; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Li, Candice ;
Wang, Yang(Kevin) ; Yang, Stanley
Subject: RE: [PATCH
Some boards(like Oland PRO: 0x1002:0x6613) seem to have
garbage in the upper 16 bits of the vram size register,
kern log as follows:
[6.00] [drm] Detected VRAM RAM=2256537600M, BAR=256M
[6.007812] [drm] RAM width 64bits GDDR5
[6.031250] [drm] amdgpu: 2256537600M of VRAM memory
[AMD Official Use Only - General]
update
-
Best Regards,
Thomas
-Original Message-
From: amd-gfx On Behalf Of Chai, Thomas
Sent: Monday, April 22, 2024 5:21 PM
To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Li, Candice ;
Wang, Yang(Kevin) ; Yang,
Am 22.04.24 um 07:26 schrieb Qiang Ma:
Some boards(like Oland PRO: 0x1002:0x6613) seem to have
garbage in the upper 16 bits of the vram size register,
kern log as follows:
[6.00] [drm] Detected VRAM RAM=2256537600M, BAR=256M
[6.007812] [drm] RAM width 64bits GDDR5
[6.031250]
Use '<' instead of '<=' to fix the out-of-bounds
read error
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index
Initialize the variables which were not initialized
to fix the coverity issue "Uninitialized scalar variable"
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 2 +-
3 files
return 0 to avoid returning an uninitialized variable r
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/amdgpu/aldebaran.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c
Delete fence fallback timer to fix the ramdom
use-after-free issue.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index
Am 22.04.24 um 10:47 schrieb Jack Xiao:
Delete fence fallback timer to fix the ramdom
use-after-free issue.
That's already done in amdgpu_fence_driver_hw_fini() and absolutely
shouldn't be in amdgpu_ring_fini().
And the kfree(ring->fence_drv.fences); shouldn't be there either since
that is
On 4/22/2024 2:59 PM, Christian König wrote:
> Am 22.04.24 um 10:47 schrieb Jack Xiao:
>> Delete fence fallback timer to fix the ramdom
>> use-after-free issue.
>
> That's already done in amdgpu_fence_driver_hw_fini() and absolutely
> shouldn't be in amdgpu_ring_fini().
>
> And the
[AMD Official Use Only - General]
With my concern fixed, the series is:
Reviewed-by: Tao Zhou
> -Original Message-
> From: Chai, Thomas
> Sent: Thursday, April 18, 2024 5:35 PM
> To: Christian König ; amd-
> g...@lists.freedesktop.org
> Cc: Zhang, Hawking ; Zhou1, Tao
> ; Li, Candice
Delete fence fallback timer to fix the ramdom
use-after-free issue.
v2: move to amdgpu_mes.c
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
On Mon, Apr 22, 2024 at 03:10:10PM +0300, Jani Nikula wrote:
> Surprisingly many places depend on debugfs.h to be included via
> drm_print.h. Fix them.
>
> v3: Also fix armada, ite-it6505, imagination, msm, sti, vc4, and xe
>
> v2: Also fix ivpu and vmwgfx
>
> Reviewed-by: Andrzej Hajda
>
On Mon, Apr 22, 2024 at 10:12 AM Sathishkumar S
wrote:
>
> jpeg ip version v2.1 and higher supports 16kx16k resolution decode
>
> Signed-off-by: Sathishkumar S
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c| 6 +++---
> drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++--
>
Am 18.04.24 um 18:10 schrieb Alex Deucher:
On Thu, Mar 21, 2024 at 10:37 AM Christian König
wrote:
Am 21.03.24 um 15:12 schrieb Tvrtko Ursulin:
On 21/03/2024 12:43, Christian König wrote:
This reverts drm/amdgpu: fix ftrace event amdgpu_bo_move always move
on same heap. The basic problem
Am 22.04.24 um 11:49 schrieb Ma Jun:
Initialize the variables which were not initialized
to fix the coverity issue "Uninitialized scalar variable"
Feel free to add my Acked-by to the first two patches, but this here
clearly doesn't looks like a good idea to me.
Signed-off-by: Ma Jun
---
On 4/19/2024 9:14 PM, Srinivasan Shanmugam wrote:
> This commit addresses buffer overflow in the smu_v14_0_init_microcode
> function. The issue was about the snprintf function writing more bytes
> into the fw_name buffer than it can hold.
>
> The line of code is:
>
> snprintf(fw_name,
jpeg ip version v2.1 and higher supports 16kx16k resolution decode
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/nv.c| 6 +++---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/soc21.c | 4 ++--
3 files changed, 7 insertions(+), 7 deletions(-)
diff
This reverts commit 5ea4581611d14a6a0e8df40965802ec7bee9c671.
This change must be reverted since it caused soft hangs when changing
the refresh rate to 122 & 144Hz when using a 7000 series GPU.
Reported-by: Mark Broadworth
Cc: Daniel Wheeler
Cc: Harry Wentland
Signed-off-by: Rodrigo Siqueira
On Mon, Apr 22, 2024 at 10:02 AM Rodrigo Siqueira
wrote:
>
> This reverts commit 5ea4581611d14a6a0e8df40965802ec7bee9c671.
>
> This change must be reverted since it caused soft hangs when changing
> the refresh rate to 122 & 144Hz when using a 7000 series GPU.
>
> Reported-by: Mark Broadworth
>
As we use wb slots more dynamically, we need to lock
access to avoid racing on allocation or free.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 11 ++-
2 files changed, 11 insertions(+), 1 deletion(-)
We can't use a shared fence location because each transaction
should be considered independently.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 12
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 4
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 21
On Mon, Apr 22, 2024 at 9:00 AM Christian König
wrote:
>
> Am 22.04.24 um 14:33 schrieb Qiang Ma:
> > On Mon, 22 Apr 2024 11:40:26 +0200
> > Christian König wrote:
> >
> >> Am 22.04.24 um 07:26 schrieb Qiang Ma:
> >>> Some boards(like Oland PRO: 0x1002:0x6613) seem to have
> >>> garbage in the
Am 22.04.24 um 15:57 schrieb Philip Yang:
Define macro MAX_SG_SEGMENT_SIZE 2GB, because struct scatterlist length
is unsigned int, and some users of it cast to a signed int, so every
segment of sg table is limited to size 2GB maximum.
For contiguous VRAM allocation, don't limit the max buddy
[AMD Official Use Only - General]
Soft ping for the series.
Thanks,
Prike
> -Original Message-
> From: Liang, Prike
> Sent: Tuesday, April 16, 2024 4:52 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Liang, Prike
>
> Subject: [PATCH 3/3] drm/amdgpu: add the amdgpu
Am 16.04.24 um 10:51 schrieb Prike Liang:
Add the amdgpu buffer object move speed metrics.
What should that be good for? It adds quite a bunch of complexity for a
feature we actually want to deprecate.
Regards,
Christian.
Signed-off-by: Prike Liang
---
If the BO pages pinned for RDMA is not contiguous on VRAM, evict it to
system memory first to free the VRAM space, then allocate contiguous
VRAM space, and then move it from system memory back to VRAM.
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 16
Define macro MAX_SG_SEGMENT_SIZE 2GB, because struct scatterlist length
is unsigned int, and some users of it cast to a signed int, so every
segment of sg table is limited to size 2GB maximum.
For contiguous VRAM allocation, don't limit the max buddy block size in
order to get contiguous VRAM
When TTM failed to alloc VRAM, TTM try evict BOs from VRAM to system
memory then retry the allocation, this skips the KFD BOs from the same
process because KFD require all BOs are resident for user queues.
If TTM with TTM_PL_FLAG_CONTIGUOUS flag to alloc contiguous VRAM, allow
TTM evict KFD BOs
Bump the kfd ioctl minor version to delcare the contiguous VRAM
allocation flag support.
Signed-off-by: Philip Yang
---
include/uapi/linux/kfd_ioctl.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index
TTM allocate contiguous VRAM may takes more than 1 second to evict BOs
for larger size RDMA buffer. Because KFD restore bo worker reserves all
KFD BOs, then TTM cannot hold the remainning KFD BOs lock to evict them,
this causes TTM failed to alloc contiguous VRAM.
Increase the KFD restore BO wait
This patch series implement new KFD memory alloc flag for best effort contiguous
VRAM allocation, to support peer direct access RDMA device with limited
scatter-gather
dma capability.
v2: rebase on patch ("drm/amdgpu: Modify the contiguous flags behaviour")
to avoid adding the new GEM flag
RDMA device with limited scatter-gather ability requires contiguous VRAM
buffer allocation for RDMA peer direct support.
Add a new KFD alloc memory flag and store as bo alloc flag
AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS. When pin this bo to export for RDMA
peerdirect access, this will set
To test RDMA using dummy driver on the system without NIC/RDMA
device, the get/put dma pages pass in null device pointer, skip the
dma map/unmap resource and sg table to avoid null pointer access.
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 33
On 4/22/2024 3:09 PM, Jack Xiao wrote:
> Delete fence fallback timer to fix the ramdom
> use-after-free issue.
>
> v2: move to amdgpu_mes.c
>
> Signed-off-by: Jack Xiao
Acked-by: Lijo Lazar
Thanks,
Lijo
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 1 +
> 1 file changed, 1
Am 22.04.24 um 11:37 schrieb Lazar, Lijo:
On 4/22/2024 2:59 PM, Christian König wrote:
Am 22.04.24 um 10:47 schrieb Jack Xiao:
Delete fence fallback timer to fix the ramdom
use-after-free issue.
That's already done in amdgpu_fence_driver_hw_fini() and absolutely
shouldn't be in
Am 20.04.24 um 21:02 schrieb Alex Deucher:
This avoids a potential conflict with firmwares with the newer
HDP flush mechanism.
The patch is fine, but I'm starting to wonder why we are using the newer
HDP flush mechanism in the first place?
Closes:
Am 22.04.24 um 13:29 schrieb Lazar, Lijo:
On 4/22/2024 4:52 PM, Christian König wrote:
Am 22.04.24 um 11:37 schrieb Lazar, Lijo:
On 4/22/2024 2:59 PM, Christian König wrote:
Am 22.04.24 um 10:47 schrieb Jack Xiao:
Delete fence fallback timer to fix the ramdom
use-after-free issue.
That's
Am 22.04.24 um 13:12 schrieb Lazar, Lijo:
On 4/22/2024 3:09 PM, Jack Xiao wrote:
Delete fence fallback timer to fix the ramdom
use-after-free issue.
v2: move to amdgpu_mes.c
Signed-off-by: Jack Xiao
Acked-by: Lijo Lazar
Acked-by: Christian König
Thanks,
Lijo
---
On 4/22/2024 4:52 PM, Christian König wrote:
> Am 22.04.24 um 11:37 schrieb Lazar, Lijo:
>>
>> On 4/22/2024 2:59 PM, Christian König wrote:
>>> Am 22.04.24 um 10:47 schrieb Jack Xiao:
Delete fence fallback timer to fix the ramdom
use-after-free issue.
>>> That's already done in
Am 22.04.24 um 14:33 schrieb Qiang Ma:
On Mon, 22 Apr 2024 11:40:26 +0200
Christian König wrote:
Am 22.04.24 um 07:26 schrieb Qiang Ma:
Some boards(like Oland PRO: 0x1002:0x6613) seem to have
garbage in the upper 16 bits of the vram size register,
kern log as follows:
[6.00] [drm]
On Thu, 18 Apr 2024, Jani Nikula wrote:
> On Thu, 18 Apr 2024, Robert Foss wrote:
>> I'm seeing build errors for drivers/gpu/drm/bridge/ite-it6505.c, is
>> this expected?
>
> No, but it's possible my configs didn't catch all configs. :(
Okay, enabled a bunch more arm/arm64 stuff, and hit some
Surprisingly many places depend on debugfs.h to be included via
drm_print.h. Fix them.
v3: Also fix armada, ite-it6505, imagination, msm, sti, vc4, and xe
v2: Also fix ivpu and vmwgfx
Reviewed-by: Andrzej Hajda
Acked-by: Maxime Ripard
Link:
On Mon, 22 Apr 2024 11:40:26 +0200
Christian König wrote:
> Am 22.04.24 um 07:26 schrieb Qiang Ma:
> > Some boards(like Oland PRO: 0x1002:0x6613) seem to have
> > garbage in the upper 16 bits of the vram size register,
> > kern log as follows:
> >
> > [6.00] [drm] Detected VRAM
On 2024-04-22 09:51, Rodrigo Siqueira wrote:
> This reverts commit 5ea4581611d14a6a0e8df40965802ec7bee9c671.
>
> This change must be reverted since it caused soft hangs when changing
> the refresh rate to 122 & 144Hz when using a 7000 series GPU.
>
> Reported-by: Mark Broadworth
> Cc: Daniel
Am 22.04.24 um 16:40 schrieb Alex Deucher:
On Mon, Apr 22, 2024 at 9:00 AM Christian König
wrote:
Am 22.04.24 um 14:33 schrieb Qiang Ma:
On Mon, 22 Apr 2024 11:40:26 +0200
Christian König wrote:
Am 22.04.24 um 07:26 schrieb Qiang Ma:
Some boards(like Oland PRO: 0x1002:0x6613) seem to have
Am 22.04.24 um 15:57 schrieb Philip Yang:
To test RDMA using dummy driver on the system without NIC/RDMA
device, the get/put dma pages pass in null device pointer, skip the
dma map/unmap resource and sg table to avoid null pointer access.
Well that is completely illegal and would break IOMMU.
On 2024-04-22 10:56, Christian König
wrote:
Am
22.04.24 um 15:57 schrieb Philip Yang:
To test RDMA using dummy driver on the
system without NIC/RDMA
device, the get/put dma pages pass in null device pointer, skip
From: Sung Joon Kim
[why & how]
Need to update the function pointers that
perform the power up and down sequence
to reuse the modified sequence as a requirement.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Aurabindo Pillai
Signed-off-by: Sung Joon Kim
Tested-by: Daniel Wheeler
---
From: Sung-huai Wang
[Why]
TCON data is corrupted after electro static discharge test.
Once the TCON data get corrupted, they will get themselves
reset and send HPD_IRQ to source side.
[How]
Support HPD_IRQ for internal link, and restore the PSR/Replay setup.
Reviewed-by: Robin Chen
Acked-by:
From: Rodrigo Siqueira
Add some missing HDCP registers to be used in DCN35.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
.../amd/display/dc/dcn35/dcn35_dio_link_encoder.h| 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff
From: Rodrigo Siqueira
In the DCN20 resource initialization, ensure that DMCUB support starts
configured as true.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c | 1 +
1 file changed, 1
From: Rodrigo Siqueira
This commit adds, updates, and removes some of the comments used in the
DC code.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.h| 2 +-
From: Rodrigo Siqueira
This commit add some DPCX IRQ types.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/irq_types.h | 8
1 file changed, 8 insertions(+)
diff --git
From: Dennis Chan
When PHY power off, the DP_SEC_CNTL cannot be configured and cause
disable Adaptive sync SDP failed. Regarding the issue, the driver will
disabled AS-SDP in replay state machine.
Reviewed-by: ChunTao Tso
Acked-by: Aurabindo Pillai
Signed-off-by: Dennis Chan
Tested-by:
From: Natanel Roizenman
[WHY]
When switching from "Extend" to "Second Display Only" we sometimes
call resource_get_otg_master_for_stream on a stream for the eDP,
which is disconnected. This leads to a null pointer dereference.
[HOW]
Added a null check in
From: Swapnil Patel
[Why & How]
Currently DCN315 clk manager is missing code to enable/disable dtbclk.
Because of this, "optimized_required" flag is constantly set
and this prevents FreeSync from engaging for certain high bandwidth
display Modes which require DTBCLK.
Reviewed-by: Dmytro
From: Rodrigo Siqueira
Drop unnecessary semicolon that can create a problem of double semicolon
in some compilers.
Reviewed-by: Martin Leung
Acked-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.h | 3 +--
From: Cruise
[Why]
Error correction was enabled in a monitor which doesn't support.
[How]
Disable error correction if it's not supported
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Cruise
Tested-by: Daniel Wheeler
---
.../display/dc/link/protocols/link_dp_phy.c |
From: Sung Joon Kim
[why & how]
There are potential issues with Z8 and IPS
that need to be addressed and need to add
in missing function pointers.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Aurabindo Pillai
Signed-off-by: Sung Joon Kim
Tested-by: Daniel Wheeler
---
From: yi-lchen
[why]
VBios & Driver may have differnet pixel rate div policy.
If the policy is not same and fast boot is enabled,
it would cause the pixel rate is too high
after driver only performs stream blank & unblank.
[how]
We would keep pixel rate div setting by VBios until next mode set.
From: Joshua Aberback
This reverts commit 44739205e867
[Why]
The change being reverted incorrectly assumes that a pointer type was
intended, however copying to a new structure is correct. As well, there
is no compiler error, it was instead an error in the testing framework
being used.
From: Harry Wentland
We're seeing issues when user-space tries to do an atomic update of
the primary surface, as well as the cursor. These two updates are
separate calls into DC and don't currently act as an atomic update.
This might lead to cursor updates being locked out and cursors
From: Harry Wentland
HWSS set_cursor_attributes copies the stream's cursor attributes
to the hubp cursor attributes. set_cursor_position might attempt
to program the cursor attributes but will program them wrong if
they're not set correctly. We need to call HWSS set_cursor_attributes
first to
From: Aric Cyr
Summary:
* Changes across DSC, MST, DMCUB, Panel Replay and misc fixes.
* Fixes to cursor programming sequence
* Add some missing register defs
* Formatting/Sytle fixes
Acked-by: Aurabindo Pillai
Signed-off-by: Aric Cyr
Tested-by: Daniel Wheeler
---
From: Rodrigo Siqueira
The string dp_hdmi_dongle_signature_str already uses u8 but the string
dp_hdmi_dongle_signature_str does not. Just replace uint8_t with u8 for
dp_hdmi_dongle_signature_str.
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
Tested-by:
From: Anthony Koo
- Adjust the dmub_fw_boot_options reserved bits to be correct
Acked-by: Aurabindo Pillai
Signed-off-by: Anthony Koo
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Sung Joon Kim
[why & how]
The recout x offset was incorrect which led to
wrong viewport calculation. For stereo
side-by-side case, the slice index should be
0 for both split pipes.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Aurabindo Pillai
Signed-off-by: Sung Joon Kim
Tested-by: Daniel
On 2024-04-22 10:40, Christian König
wrote:
Am
22.04.24 um 15:57 schrieb Philip Yang:
Define macro MAX_SG_SEGMENT_SIZE 2GB,
because struct scatterlist length
is unsigned int, and some users of it cast to a signed int, so
From: Ethan Bitnun
[Description]
- Block FPO if the max stretch refresh rate is low enough
to cause a flicker by storing the maximum safe refresh
decrease from nominal in stream.
- Brought over various Freesync Luminance functions to dc. Use these
new functions to block fpo if we will
From: Michael Strauss
[WHY]
Avoid race condition which puts LTTPR into bad state during UHBR LT.
[HOW]
Delay 30ms between starting UHBR TPS1 PHY output and sending TPS1 via DPCD.
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Michael Strauss
Tested-by: Daniel Wheeler
From: George Shen
[Why]
Upon disconnecting a UHBR SST display, the disconnection and the
SetTimings to disable the display can occur such that link_set_dpms_off
occurs after the disconnection has already processed
(link->type is dc_connection_none). Thus, the AUX related
operations should be
From: Gabe Teeger
New request from KMD/VBIOS in order to support new UMA carveout
model. This fixes a null dereference from accessing
Ctx->dc_bios->integrated_info while it was NULL.
DAL parses through the BIOS and extracts the necessary
integrated_info but was missing a case for the new BIOS
From: Hersen Wu
[Why] DSC debugfs, such as dp_dsc_clock_en_read,
use aconnector->dc_link to find pipe_ctx for display.
Displays connected to MST hub share the same dc_link.
DSC instance is from pipe_ctx. This causes incorrect
DSC instance for display connected to MST hub.
[How] Add
From: Meenakshikumar Somasundaram
[Why]
During DP tunnel creation, CM preallocates BW and reduces
estimated BW of other DPIA. CM release preallocation only
when allocation is complete. Display mode validation logic
validates timings based on bw available per host router.
In multi display setup,
From: Ilya Bakoulin
Not every ASIC implements dp_set_dsc_config. Add condition to prevent
calls to unimplemented function.
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Ilya Bakoulin
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 16
From: Nicholas Kazlauskas
[Why]
It's possible that the write hasn't fully completed by the time we
send (and flush) a command to DMCUB to notify idle to request IPS2
exit.
[How]
Perform a readback of the volatile structure into dc_dmub_srv state.
Reviewed-by: Charlene Liu
Acked-by: Aurabindo
From: Rodrigo Siqueira
This commit reorganizes the order in which some control registers are
presented to make it easier to identify the operations based on the
hardware doc.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
From: Rodrigo Siqueira
This commit address some small code style issues in DC.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c| 3 +--
drivers/gpu/drm/amd/display/dc/dm_helpers.h
Summary:
* Changes across DSC, MST, DMCUB, Panel Replay and misc fixes.
* Fixes to cursor programming sequence
* Add some missing register defs
* Formatting/Sytle fixes
==
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.214.0
Aric Cyr (1):
From: Rodrigo Siqueira
This commit add some missing debug registers for DPCS and RDPC debug.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
.../amd/display/dc/dcn20/dcn20_link_encoder.h | 5 +++-
.../display/dc/dcn31/dcn31_dio_link_encoder.h | 2
From: Dmytro Laktyushkin
Headless dp 2.0 will take longer to update.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Dmytro Laktyushkin
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.c| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Rodrigo Siqueira
This commit removes some unnecessary code and makes the required
adjustments to replace other parts of the code with a short option.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
From: George Shen
Theoretically rare corner case where ceil(Y) results in rounding up to
an integer. If this happens, the 1 should be carried over to the X
value.
CC: sta...@vger.kernel.org
Reviewed-by: Rodrigo Siqueira
Signed-off-by: George Shen
Tested-by: Daniel Wheeler
---
From: Rodrigo Siqueira
This commit add some missing HDMI control registers to DCN3x.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h | 3 +++
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
From: Rodrigo Siqueira
DCN3.0 supports some specific DWB debug registers that are not exposed
yet. This commit just adds the missing registers.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h | 14
From: Rodrigo Siqueira
Add TMDS balancer control to the list of available encoder registers for
DCN 30.
Signed-off-by: Rodrigo Siqueira
Acked-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.h | 3 ++-
1 file changed, 2
[Public]
Hi all,
This week this patchset was tested on the following systems:
* Lenovo ThinkBook T13s Gen4 with AMD Ryzen 5 6600U
* MSI Gaming X Trio RX 6800
* Gigabyte Gaming OC RX 7900 XTX
These systems were tested on the following display/connection types:
*
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: f529a6d274b3b8c75899e949649d231298f30a32 Add linux-next specific
files for 20240422
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202404221830.cjqlhldl-...@intel.com
Error
[AMD Official Use Only - General]
These two patches Looks good to me .
Reviewed by Shaoyun.liu
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Monday, April 22, 2024 10:38 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 1/2] drm/amdgpu:
From: Lijo Lazar
[ Upstream commit f7e232de51bb1b45646e5b7dc4ebcf13510f2630 ]
VCN need not be shared in CPX mode always for all GFX 9.4.3 SOC SKUs. In
certain configs, VCN instance can be exclusively allocated to a
partition even under CPX mode.
Signed-off-by: Lijo Lazar
Reviewed-by: James
From: Zhigang Luo
[ Upstream commit d06af584be5a769d124b7302b32a033e9559761d ]
If there are more than one device doing reset in parallel, the first
device will call kfd_suspend_all_processes() to evict all processes
on all devices, this call takes time to finish. other device will
start reset
From: Alex Hung
[ Upstream commit ecedd99a9369fb5cde601ae9abd58bca2739f1ae ]
[WHY]
dynamic memory safety error detector (KASAN) catches and generates error
messages "BUG: KASAN: slab-out-of-bounds" as writeback connector does not
support certain features which are not initialized.
[HOW]
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