[PATCH 1/2] drm/amdkfd: initialize mqd_manager_init function for navi10
Change-Id: I43c50769557a9be932891e923f669f7993eeedf9
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c
index adb3885..72e4d61a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c
@@ -36,6 +36,7 @@ void device_queue_manager_init_v10_navi10(
{
asic_ops->update_qpd = update_qpd_v10;
asic_ops->init_sdma_vm = init_sdma_vm_v10;
+ asic_ops->mqd_manager_init = mqd_manager_init_v10;
}
static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
--
2.7.4
___
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[PATCH] drm/amdgpu: Fix the null pointer about get vbios
Move the get vbios only before SDMA block early init to fix null pointer
about get vbios.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 4a836db..830c4b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1534,18 +1534,19 @@ static int amdgpu_device_ip_early_init(struct
amdgpu_device *adev)
if (amdgpu_sriov_vf(adev))
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
- /* Read BIOS */
- if (!amdgpu_get_bios(adev))
- return -EINVAL;
-
- r = amdgpu_atombios_init(adev);
- if (r) {
- dev_err(adev->dev, "amdgpu_atombios_init failed\n");
- amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL,
0, 0);
- return r;
- }
-
for (i = 0; i < adev->num_ip_blocks; i++) {
+ if ( adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA
) {
+ /* Read BIOS */
+ if (!amdgpu_get_bios(adev))
+ return -EINVAL;
+
+ r = amdgpu_atombios_init(adev);
+ if (r) {
+ dev_err(adev->dev, "amdgpu_atombios_init
failed\n");
+ amdgpu_vf_error_put(adev,
AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
+ return r;
+ }
+ }
if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
DRM_ERROR("disabled ip block: %d <%s>\n",
i, adev->ip_blocks[i].version->funcs->name);
--
2.7.4
___
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RE: [PATCH] drm/amd/powerplay: detect version of smu backend
> -Original Message-
> From: amd-gfx On Behalf Of
> Prike Liang
> Sent: Friday, June 14, 2019 3:01 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liang, Prike ; Huang, Ray
> ; Feng, Kenneth ; Quan,
> Evan
> Subject: [PATCH] drm/amd/powerplay: detect version of smu backend
>
> Change-Id: Ib050c8cf0c2c5af4c1f747cf596860f9be01a2d3
> Signed-off-by: Prike Liang
Acked-by: Huang Rui
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 1 +
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
> drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c| 1 +
> drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 1 +
> drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 1 +
> drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 1 +
> drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c | 1 +
> drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 1 +
> drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 1 +
> drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c| 1 +
> drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c| 1 +
> drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c| 1 +
> drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c | 1 +
> 13 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index f1d326c..b996819 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -194,6 +194,7 @@ int hwmgr_sw_init(struct pp_hwmgr *hwmgr)
> return -EINVAL;
>
> phm_register_irq_handlers(hwmgr);
> + pr_info("hwmgr_sw_init smu backed is %s\n",hwmgr-
> >smumgr_funcs->name);
>
> return hwmgr->smumgr_funcs->smu_init(hwmgr);
> }
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index c92999a..47dbecc 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -190,6 +190,7 @@ struct phm_vce_clock_voltage_dependency_table { };
>
> struct pp_smumgr_func {
> + char *name;
> int (*smu_init)(struct pp_hwmgr *hwmgr);
> int (*smu_fini)(struct pp_hwmgr *hwmgr);
> int (*start_smu)(struct pp_hwmgr *hwmgr); diff --git
> a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> index 9ef57fc..022f3c8 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> @@ -2935,6 +2935,7 @@ static int ci_update_smc_table(struct pp_hwmgr
> *hwmgr, uint32_t type) }
>
> const struct pp_smumgr_func ci_smu_funcs = {
> + .name = "ci_smu",
> .smu_init = ci_smu_init,
> .smu_fini = ci_smu_fini,
> .start_smu = ci_start_smu,
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> index 0ce85b7..da025b1 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> @@ -2643,6 +2643,7 @@ static int fiji_update_dpm_settings(struct
> pp_hwmgr *hwmgr, }
>
> const struct pp_smumgr_func fiji_smu_funcs = {
> + .name = "fiji_smu",
> .smu_init = _smu_init,
> .smu_fini = _smu_fini,
> .start_smu = _start_smu,
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> index f24f13d..f414f22 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> @@ -2661,6 +2661,7 @@ static bool iceland_is_dpm_running(struct
> pp_hwmgr *hwmgr) }
>
> const struct pp_smumgr_func iceland_smu_funcs = {
> + .name = "iceland_smu",
> .smu_init = _smu_init,
> .smu_fini = _smu_fini,
> .start_smu = _start_smu,
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> index 0d8958e..fbac2d3 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> @@ -2550,6 +2550,7 @@ static int polaris10_update_dpm_settings(struct
> pp_hwmgr *hwmgr, }
>
> const struct pp_smumgr_func polaris10_smu_funcs = {
> + .name = "polaris10_smu",
> .smu_init = polaris10_smu_init,
> .smu_fini = smu7_smu_fini,
> .start_smu = polaris10_start_smu,
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
> b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
> index 6d11076a..ca66035 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
> @@ -291,6 +291,7 @@ static int smu10_smc_table_manager(struct
> pp_hwmgr *hwmgr, uint8_t *table, uint1
>
>
> const struct pp_smumgr_func smu10_smu_funcs = {
> + .name =
arm32 build failure after abe882a39a9c ("drm/amd/display: fix issue with eDP not detected on driver load")
Hi all,
After commit abe882a39a9c ("drm/amd/display: fix issue with eDP not
detected on driver load") in -next, arm32 allyesconfig builds start
failing at link time:
arm-linux-gnueabi-ld: drivers/gpu/drm/amd/display/dc/core/dc_link.o: in
function `dc_link_detect':
dc_link.c:(.text+0x260c): undefined reference to `__bad_udelay'
arm32 only allows a udelay value of up to 2000, see
arch/arm/include/asm/delay.h for more info.
Please look into this when you have a chance!
Nathan
[PATCH v2] drm/amd/amdgpu: Tabs instead of spaces in gfx_v10_0.c
Done automatically with unexpand, plus some extra 7-space lines.
Signed-off-by: Ernst Sjöstrand
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 168 -
1 file changed, 84 insertions(+), 84 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 0090cba2d24d..266287d2eebc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -114,7 +114,7 @@ static void gfx_v10_0_set_irq_funcs(struct amdgpu_device
*adev);
static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
- struct amdgpu_cu_info *cu_info);
+struct amdgpu_cu_info *cu_info);
static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
u32 sh_num, u32 instance);
@@ -345,63 +345,63 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring
*ring)
static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
-struct amdgpu_device *adev = ring->adev;
-struct amdgpu_ib ib;
-struct dma_fence *f = NULL;
-uint32_t scratch;
-uint32_t tmp = 0;
-long r;
-
-r = amdgpu_gfx_scratch_get(adev, );
-if (r) {
-DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
-return r;
-}
-
-WREG32(scratch, 0xCAFEDEAD);
-
-memset(, 0, sizeof(ib));
-r = amdgpu_ib_get(adev, NULL, 256, );
-if (r) {
-DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
-goto err1;
-}
-
-ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
-ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
-ib.ptr[2] = 0xDEADBEEF;
-ib.length_dw = 3;
-
-r = amdgpu_ib_schedule(ring, 1, , NULL, );
-if (r)
-goto err2;
-
-r = dma_fence_wait_timeout(f, false, timeout);
-if (r == 0) {
-DRM_ERROR("amdgpu: IB test timed out.\n");
-r = -ETIMEDOUT;
-goto err2;
-} else if (r < 0) {
-DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
-goto err2;
-}
-
-tmp = RREG32(scratch);
-if (tmp == 0xDEADBEEF) {
-DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
-r = 0;
-} else {
-DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
- scratch, tmp);
-r = -EINVAL;
-}
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_ib ib;
+ struct dma_fence *f = NULL;
+ uint32_t scratch;
+ uint32_t tmp = 0;
+ long r;
+
+ r = amdgpu_gfx_scratch_get(adev, );
+ if (r) {
+ DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
+ return r;
+ }
+
+ WREG32(scratch, 0xCAFEDEAD);
+
+ memset(, 0, sizeof(ib));
+ r = amdgpu_ib_get(adev, NULL, 256, );
+ if (r) {
+ DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
+ goto err1;
+ }
+
+ ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
+ ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
+ ib.ptr[2] = 0xDEADBEEF;
+ ib.length_dw = 3;
+
+ r = amdgpu_ib_schedule(ring, 1, , NULL, );
+ if (r)
+ goto err2;
+
+ r = dma_fence_wait_timeout(f, false, timeout);
+ if (r == 0) {
+ DRM_ERROR("amdgpu: IB test timed out.\n");
+ r = -ETIMEDOUT;
+ goto err2;
+ } else if (r < 0) {
+ DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
+ goto err2;
+ }
+
+ tmp = RREG32(scratch);
+ if (tmp == 0xDEADBEEF) {
+ DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
+ r = 0;
+ } else {
+ DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
+ scratch, tmp);
+ r = -EINVAL;
+ }
err2:
-amdgpu_ib_free(adev, , NULL);
-dma_fence_put(f);
+ amdgpu_ib_free(adev, , NULL);
+ dma_fence_put(f);
err1:
-amdgpu_gfx_scratch_free(adev, scratch);
+ amdgpu_gfx_scratch_free(adev, scratch);
-return r;
+ return r;
}
static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
@@ -1153,10 +1153,10 @@ static int gfx_v10_0_sw_init(void *handle)
return r;
/* Privileged reg */
-r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
+ r = amdgpu_irq_add_id(adev,
Re: [PATCH v17 03/15] arm64: Introduce prctl() options to control the tagged user addresses ABI
On Mon, Jun 17, 2019 at 10:18 AM Catalin Marinas wrote: > > On Mon, Jun 17, 2019 at 09:57:36AM -0700, Evgenii Stepanov wrote: > > On Mon, Jun 17, 2019 at 6:56 AM Catalin Marinas > > wrote: > > > On Wed, Jun 12, 2019 at 01:43:20PM +0200, Andrey Konovalov wrote: > > > > From: Catalin Marinas > > > > > > > > It is not desirable to relax the ABI to allow tagged user addresses into > > > > the kernel indiscriminately. This patch introduces a prctl() interface > > > > for enabling or disabling the tagged ABI with a global sysctl control > > > > for preventing applications from enabling the relaxed ABI (meant for > > > > testing user-space prctl() return error checking without reconfiguring > > > > the kernel). The ABI properties are inherited by threads of the same > > > > application and fork()'ed children but cleared on execve(). > > > > > > > > The PR_SET_TAGGED_ADDR_CTRL will be expanded in the future to handle > > > > MTE-specific settings like imprecise vs precise exceptions. > > > > > > > > Signed-off-by: Catalin Marinas > > > > > > A question for the user-space folk: if an application opts in to this > > > ABI, would you want the sigcontext.fault_address and/or siginfo.si_addr > > > to contain the tag? We currently clear it early in the arm64 entry.S but > > > we could find a way to pass it down if needed. > > > > For HWASan this would not be useful because we instrument memory > > accesses with explicit checks anyway. For MTE, on the other hand, it > > would be very convenient to know the fault address tag without > > disassembling the code. > > I could as this differently: does anything break if, once the user > opts in to TBI, fault_address and/or si_addr have non-zero top byte? I think it would be fine. > Alternatively, we could present the original FAR_EL1 register as a > separate field as we do with ESR_EL1, independently of whether the user > opted in to TBI or not. > > -- > Catalin
[PATCH 2/2] drm/amd/amdgpu: Indent AMD_IS_APU properly
Reported by smatch: drivers/gpu/drm/amd/amdgpu/soc15.c:715 soc15_get_pcie_usage() warn: inconsistent indenting And a similar one in si.c. Signed-off-by: Ernst Sjöstrand --- drivers/gpu/drm/amd/amdgpu/si.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 4ff930a47e10..4b1e0c16ac41 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1339,8 +1339,8 @@ static void si_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, /* This reports 0 on APUs, so return to avoid writing/reading registers * that may or may not be different from their GPU counterparts */ -if (adev->flags & AMD_IS_APU) -return; + if (adev->flags & AMD_IS_APU) + return; /* Set the 2 events that we wish to watch, defined above */ /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */ diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 9dfbbc65ea67..812a6c198cfe 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -712,8 +712,8 @@ static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, /* This reports 0 on APUs, so return to avoid writing/reading registers * that may or may not be different from their GPU counterparts */ -if (adev->flags & AMD_IS_APU) -return; + if (adev->flags & AMD_IS_APU) + return; /* Set the 2 events that we wish to watch, defined above */ /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */ -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2] drm/amd/amdgpu: Tabs instead of spaces in gfx_v10_0.c
Done automatically with unexpand.
Signed-off-by: Ernst Sjöstrand
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 158 -
1 file changed, 79 insertions(+), 79 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 0090cba2d24d..d04f95ec4471 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -114,7 +114,7 @@ static void gfx_v10_0_set_irq_funcs(struct amdgpu_device
*adev);
static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
- struct amdgpu_cu_info *cu_info);
+struct amdgpu_cu_info *cu_info);
static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
u32 sh_num, u32 instance);
@@ -345,63 +345,63 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring
*ring)
static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
-struct amdgpu_device *adev = ring->adev;
-struct amdgpu_ib ib;
-struct dma_fence *f = NULL;
-uint32_t scratch;
-uint32_t tmp = 0;
-long r;
-
-r = amdgpu_gfx_scratch_get(adev, );
-if (r) {
-DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
-return r;
-}
-
-WREG32(scratch, 0xCAFEDEAD);
-
-memset(, 0, sizeof(ib));
-r = amdgpu_ib_get(adev, NULL, 256, );
-if (r) {
-DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
-goto err1;
-}
-
-ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
-ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
-ib.ptr[2] = 0xDEADBEEF;
-ib.length_dw = 3;
-
-r = amdgpu_ib_schedule(ring, 1, , NULL, );
-if (r)
-goto err2;
-
-r = dma_fence_wait_timeout(f, false, timeout);
-if (r == 0) {
-DRM_ERROR("amdgpu: IB test timed out.\n");
-r = -ETIMEDOUT;
-goto err2;
-} else if (r < 0) {
-DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
-goto err2;
-}
-
-tmp = RREG32(scratch);
-if (tmp == 0xDEADBEEF) {
-DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
-r = 0;
-} else {
-DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
- scratch, tmp);
-r = -EINVAL;
-}
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_ib ib;
+ struct dma_fence *f = NULL;
+ uint32_t scratch;
+ uint32_t tmp = 0;
+ long r;
+
+ r = amdgpu_gfx_scratch_get(adev, );
+ if (r) {
+ DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
+ return r;
+ }
+
+ WREG32(scratch, 0xCAFEDEAD);
+
+ memset(, 0, sizeof(ib));
+ r = amdgpu_ib_get(adev, NULL, 256, );
+ if (r) {
+ DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
+ goto err1;
+ }
+
+ ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
+ ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
+ ib.ptr[2] = 0xDEADBEEF;
+ ib.length_dw = 3;
+
+ r = amdgpu_ib_schedule(ring, 1, , NULL, );
+ if (r)
+ goto err2;
+
+ r = dma_fence_wait_timeout(f, false, timeout);
+ if (r == 0) {
+ DRM_ERROR("amdgpu: IB test timed out.\n");
+ r = -ETIMEDOUT;
+ goto err2;
+ } else if (r < 0) {
+ DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
+ goto err2;
+ }
+
+ tmp = RREG32(scratch);
+ if (tmp == 0xDEADBEEF) {
+ DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
+ r = 0;
+ } else {
+ DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
+ scratch, tmp);
+ r = -EINVAL;
+ }
err2:
-amdgpu_ib_free(adev, , NULL);
-dma_fence_put(f);
+ amdgpu_ib_free(adev, , NULL);
+ dma_fence_put(f);
err1:
-amdgpu_gfx_scratch_free(adev, scratch);
+ amdgpu_gfx_scratch_free(adev, scratch);
-return r;
+ return r;
}
static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
@@ -1153,10 +1153,10 @@ static int gfx_v10_0_sw_init(void *handle)
return r;
/* Privileged reg */
-r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
+ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
Re: [PATCH] drm/amdgpu: improve HMM error -ENOMEM and -EBUSY handling
On 2019-06-14 9:52 p.m., Yang, Philip wrote:
> Under memory pressure, hmm_range_fault may return error code -ENOMEM
> or -EBUSY, change pr_info to pr_debug to remove unnecessary kernel log
> message because we will retry restore again.
>
> Call get_user_pages_done if TTM get user pages failed will have
> WARN_ONCE kernel calling stack dump log.
>
> Change-Id: I086f92944630f9d1a70365c00417cb9440662464
> Signed-off-by: Philip Yang
Reviewed-by: Felix Kuehling
> ---
> .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 38 +++
> 1 file changed, 6 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index 74e86952553f..10abae398e51 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -1731,35 +1731,17 @@ static int update_invalid_user_pages(struct
> amdkfd_process_info *process_info,
> ret = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
> bo->tbo.ttm->pages);
> if (ret) {
> - bo->tbo.ttm->pages[0] = NULL;
> - pr_info("%s: Failed to get user pages: %d\n",
> + pr_debug("%s: Failed to get user pages: %d\n",
> __func__, ret);
> - /* Pretend it succeeded. It will fail later
> - * with a VM fault if the GPU tries to access
> - * it. Better than hanging indefinitely with
> - * stalled user mode queues.
> - */
> - }
> - }
> -
> - return 0;
> -}
>
> -/* Remove invalid userptr BOs from hmm track list
> - *
> - * Stop HMM track the userptr update
> - */
> -static void untrack_invalid_user_pages(struct amdkfd_process_info
> *process_info)
> -{
> - struct kgd_mem *mem, *tmp_mem;
> - struct amdgpu_bo *bo;
> + /* Return error -EBUSY or -ENOMEM, retry restore */
> + return ret;
> + }
>
> - list_for_each_entry_safe(mem, tmp_mem,
> - _info->userptr_inval_list,
> - validate_list.head) {
> - bo = mem->bo;
> amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
> }
> +
> + return 0;
> }
>
> /* Validate invalid userptr BOs
> @@ -1841,13 +1823,6 @@ static int validate_invalid_user_pages(struct
> amdkfd_process_info *process_info)
> list_move_tail(>validate_list.head,
> _info->userptr_valid_list);
>
> - /* Stop HMM track the userptr update. We dont check the return
> - * value for concurrent CPU page table update because we will
> - * reschedule the restore worker if process_info->evicted_bos
> - * is updated.
> - */
> - amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
> -
> /* Update mapping. If the BO was not validated
>* (because we couldn't get user pages), this will
>* clear the page table entries, which will result in
> @@ -1946,7 +1921,6 @@ static void amdgpu_amdkfd_restore_userptr_worker(struct
> work_struct *work)
> }
>
> unlock_out:
> - untrack_invalid_user_pages(process_info);
> mutex_unlock(_info->lock);
> mmput(mm);
> put_task_struct(usertask);
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Re: [PATCH] drm/amd/amdgpu: cast mem->num_pages to 64-bits when shifting
Ok no worries I'll fix it up and push it later today.
Btw I didn't use an inline cast because the macro kept breaking. I tried
variants of parentheses and nothing worked Odd...
Thanks,
Tom
On June 17, 2019 3:32:03 PM EDT, "Kuehling, Felix"
wrote:
On 2019-06-17 3:28 p.m., Christian König wrote:
Am 17.06.19 um 21:15 schrieb Kuehling, Felix:
Looks good to me. One cosmetic comment inline. With that fixed this
patch is Reviewed-by: Felix Kuehling
On 2019-06-14 12:51 p.m., StDenis, Tom wrote:
On 32-bit hosts mem->num_pages is 32-bits and can overflow
when shifted. Add a cast to avoid this.
Signed-off-by: Tom St Denis
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index c963ad86072e..31895d3c33de 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -279,14 +279,16 @@ static int amdgpu_vram_mgr_new(struct
ttm_mem_type_manager *man,
uint64_t vis_usage = 0;
unsigned i;
int r;
+uint64_t mem_bytes;
Christian likes the "upside-down christmas tree" to help readability of
local variable declarations.
Ah, yeah. Thanks for the note.
I actually don't care about that much, but I always get rejects from
upstream subsystem maintainers if I don't do this.
It's most likely not even documented somewhere,
Right. The fact that I even noticed it probably means that I have a mild
case of OCD myself. If it was a strict requirement, it should be caught
by checkpatch.pl.
Cheers,
Felix
Christian.
lpfn = place->lpfn;
if (!lpfn)
lpfn = man->size;
/* bail out quickly if there's likely not enough VRAM for
this BO */
-if (atomic64_add_return(mem->num_pages << PAGE_SHIFT,
>usage) > adev->gmc.mc_vram_size) {
-atomic64_sub(mem->num_pages << PAGE_SHIFT, >usage);
+mem_bytes = (u64)mem->num_pages << PAGE_SHIFT;
+if (atomic64_add_return(mem_bytes, >usage) >
adev->gmc.mc_vram_size) {
+atomic64_sub(mem_bytes, >usage);
mem->mm_node = NULL;
return 0;
}
@@ -308,7 +310,7 @@ static int amdgpu_vram_mgr_new(struct
ttm_mem_type_manager *man,
nodes = kvmalloc_array((uint32_t)num_nodes, sizeof(*nodes),
GFP_KERNEL | __GFP_ZERO);
if (!nodes) {
-atomic64_sub(mem->num_pages << PAGE_SHIFT, >usage);
+atomic64_sub(mem_bytes, >usage);
return -ENOMEM;
}
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[PATCH 453/459] drm/amd/display: dcn2 use fixed clocks.
From: Charlene Liu
[Description]
dcn2 use fixed clocks and not program DPP CLK or Disp_CLK.
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 22 +--
drivers/gpu/drm/amd/display/dc/dc.h | 2 ++
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 9 +++-
3 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 6f01830fc020..445bbc3bea0e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -225,19 +225,19 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
update_dispclk = true;
}
-
- if (dpp_clock_lowered) {
- // if clock is being lowered, increase DTO before lowering
refclk
- dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
- dcn20_update_clocks_update_dentist(clk_mgr);
- } else {
- // if clock is being raised, increase refclk before lowering DTO
- if (update_dppclk || update_dispclk)
- dcn20_update_clocks_update_dentist(clk_mgr);
- if (update_dppclk)
+ if (dc->config.forced_clocks == false) {
+ if (dpp_clock_lowered) {
+ // if clock is being lowered, increase DTO before
lowering refclk
dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
+ dcn20_update_clocks_update_dentist(clk_mgr);
+ } else {
+ // if clock is being raised, increase refclk before
lowering DTO
+ if (update_dppclk || update_dispclk)
+ dcn20_update_clocks_update_dentist(clk_mgr);
+ if (update_dppclk)
+ dcn20_update_clocks_update_dpp_dto(clk_mgr,
context);
+ }
}
-
if (update_dispclk &&
dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
/*update dmcu for wait_loop count*/
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 499544359faf..07a264fdce4e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -218,6 +218,8 @@ struct dc_config {
bool allow_seamless_boot_optimization;
bool power_down_display_on_boot;
bool edp_not_connected;
+ bool forced_clocks;
+
};
enum visual_confirm {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 36bf14332bf5..26af860df7d4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2156,7 +2156,10 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct
dc_state *context,
}
if (force_split &&
context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]
== 1)
context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]
/= 2;
-
+ if (dc->config.forced_clocks == true) {
+
context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]
=
+
context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
+ }
if (!pipe->top_pipe && !pipe->plane_state &&
context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
hsplit_pipe =
find_idle_secondary_pipe(>res_ctx, dc->res_pool, pipe);
ASSERT(hsplit_pipe);
@@ -2258,6 +2261,10 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct
dc_state *context,
else
pipes[pipe_cnt].pipe.dest.odm_combine = 0;
}
+ if (dc->config.forced_clocks) {
+ pipes[pipe_cnt].clks_cfg.dispclk_mhz =
context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
+ pipes[pipe_cnt].clks_cfg.dppclk_mhz =
context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
+ }
pipe_cnt++;
}
--
2.20.1
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[PATCH 459/459] drm/amd/display/dc: set num-dwb = 1 as navi10 asic cap
From: hersen wu
during navi10 bring up, dwb causes system hang.
to continue debug major issue, disable dwb by
set num-dwb = 0. the hang issue is not reproduced now
by enable num-dwb =1. dc source is shared by all os.
win needs num-dwb = 1.
Signed-off-by: hersen wu
Acked-by: Alex Deucher
Reviewed-by: Roman Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 6d9fd93ece85..c5ac25980f19 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -661,7 +661,7 @@ static const struct resource_caps res_cap_nv10 = {
.num_audio = 7,
.num_stream_encoder = 6,
.num_pll = 6,
- .num_dwb = 0,
+ .num_dwb = 1,
.num_ddc = 6,
.num_vmid = 16,
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
--
2.20.1
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[PATCH 452/459] drm/amd/display: add p010 and ayuv plane caps
From: Charlene Liu
for future use
Signed-off-by: Charlene Liu
Reviewed-by: Chris Park
Acked-by: Bhawanpreet Lakha
Acked-by: Krunoslav Kovac
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 252eba2ee116..499544359faf 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -70,6 +70,8 @@ struct dc_plane_cap {
uint32_t argb : 1;
uint32_t nv12 : 1;
uint32_t fp16 : 1;
+ uint32_t p010 : 1;
+ uint32_t ayuv : 1;
} pixel_format_support;
// max upscaling factor x1000
// upscaling factors are always >= 1
--
2.20.1
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[PATCH 457/459] drm/amd/display: expose dentist_get_did_from_divider
From: Charlene Liu
for future use
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 445bbc3bea0e..df59cb7597a5 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -70,7 +70,7 @@ static const struct clk_mgr_mask clk_mgr_mask = {
CLK_MASK_SH_LIST_NV10(_MASK)
};
-static uint32_t dentist_get_did_from_divider(int divider)
+uint32_t dentist_get_did_from_divider(int divider)
{
uint32_t divider_id;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
index a44afc0625c5..5661a5a89847 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
@@ -43,4 +43,6 @@ void dcn20_clk_mgr_construct(struct dc_context *ctx,
struct pp_smu_funcs *pp_smu,
struct dccg *dccg);
+uint32_t dentist_get_did_from_divider(int divider);
+
#endif //__DCN20_CLK_MGR_H__
--
2.20.1
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[PATCH 455/459] drm/amd/display: Add Underflow Asserts to dc
From: Thomas Lim
[Why]
For debugging underflow issues it can be useful to have asserts when the
underflow initially occurs.
[How]
Read the underflow status registers after actions that have a high risk
of causing underflow and assert that no underflow occurred. If underflow
occurred, clear the bit.
Signed-off-by: Thomas Lim
Reviewed-by: Eric Yang
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 32 ++-
.../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 2 ++
.../drm/amd/display/dc/dcn10/dcn10_resource.c | 4 ++-
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 1 +
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 2 ++
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 1 +
7 files changed, 41 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 5ebfeee9d08e..e513028faefa 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -346,6 +346,7 @@ struct dc_debug_options {
int sr_exit_time_ns;
int sr_enter_plus_exit_time_ns;
int urgent_latency_ns;
+ uint32_t underflow_assert_delay_us;
int percent_of_ideal_drambw;
int dram_clock_change_latency_ns;
bool optimized_watermark;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index e6b7e10c612f..3834979e61d0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -420,6 +420,23 @@ void dcn10_log_hw_state(struct dc *dc,
DTN_INFO_END();
}
+bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)
+{
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ struct timing_generator *tg = pipe_ctx->stream_res.tg;
+
+ if (tg->funcs->is_optc_underflow_occurred(tg)) {
+ tg->funcs->clear_optc_underflow(tg);
+ return true;
+ }
+
+ if (hubp->funcs->hubp_get_underflow_status(hubp)) {
+ hubp->funcs->hubp_clear_underflow(hubp);
+ return true;
+ }
+ return false;
+}
+
static void enable_power_gating_plane(
struct dce_hwseq *hws,
bool enable)
@@ -2397,6 +2414,7 @@ static void dcn10_apply_ctx_for_surface(
{
int i;
struct timing_generator *tg;
+ uint32_t underflow_check_delay_us;
bool removed_pipe[4] = { false };
bool interdependent_update = false;
struct pipe_ctx *top_pipe_to_program =
@@ -2411,11 +2429,22 @@ static void dcn10_apply_ctx_for_surface(
interdependent_update = top_pipe_to_program->plane_state &&
top_pipe_to_program->plane_state->update_flags.bits.full_update;
+ underflow_check_delay_us = dc->debug.underflow_assert_delay_us;
+
+ if (underflow_check_delay_us != 0x &&
dc->hwss.did_underflow_occur)
+ ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
+
if (interdependent_update)
lock_all_pipes(dc, context, true);
else
dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
+ if (underflow_check_delay_us != 0x)
+ udelay(underflow_check_delay_us);
+
+ if (underflow_check_delay_us != 0x &&
dc->hwss.did_underflow_occur)
+ ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
+
if (num_planes == 0) {
/* OTG blank before remove all front end */
dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
@@ -3092,7 +3121,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
.disable_stream_gating = NULL,
.enable_stream_gating = NULL,
.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
- .setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt
+ .setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
+ .did_underflow_occur = dcn10_did_underflow_occur
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index ef94d6b15843..d3616b1948cc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -71,6 +71,8 @@ void dcn10_get_hdr_visual_confirm_color(
struct pipe_ctx *pipe_ctx,
struct tg_color *color);
+bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);
+
void update_dchubp_dpp(
struct dc *dc,
struct pipe_ctx *pipe_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index f6004bc53dce..29fd3cb9422b 100644
---
[PATCH 458/459] drm/amd/display: make clk_mgr call enable_pme_wa
From: Su Sung Chung
[why]
Before for raven and navi we are calling pp_smu functions for pme
[how]
refactor a code so we will call clk_mgr's enable_pme_wa function so we
can use pme_wa for future asics. This way we don't need to worry about
different ASIC since clk_mgr already have that information
Signed-off-by: Su Sung Chung
Reviewed-by: Eric Yang
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c| 14 +
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 16 +-
.../display/dc/dce110/dce110_hw_sequencer.c | 29 ---
3 files changed, 35 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
index 31db9b55e11a..183ca39ce5a1 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
@@ -215,9 +215,23 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
}
}
+static void rv1_enable_pme_wa(struct clk_mgr *clk_mgr_base)
+{
+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+ struct pp_smu_funcs_rv *pp_smu = NULL;
+
+ if (clk_mgr->pp_smu) {
+ pp_smu = _mgr->pp_smu->rv_funcs;
+
+ if (pp_smu->set_pme_wa_enable)
+ pp_smu->set_pme_wa_enable(_smu->pp_smu);
+ }
+}
+
static struct clk_mgr_funcs rv1_clk_funcs = {
.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
.update_clocks = rv1_update_clocks,
+ .enable_pme_wa = rv1_enable_pme_wa,
};
static struct clk_mgr_internal_funcs rv1_clk_internal_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index df59cb7597a5..08a774fc7b67 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -303,10 +303,24 @@ void dcn2_init_clocks(struct clk_mgr *clk_mgr)
memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
}
+void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)
+{
+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+ struct pp_smu_funcs_nv *pp_smu = NULL;
+
+ if (clk_mgr->pp_smu) {
+ pp_smu = _mgr->pp_smu->nv_funcs;
+
+ if (pp_smu->set_pme_wa_enable)
+ pp_smu->set_pme_wa_enable(_smu->pp_smu);
+ }
+}
+
static struct clk_mgr_funcs dcn2_funcs = {
.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
.update_clocks = dcn2_update_clocks,
- .init_clocks = dcn2_init_clocks
+ .init_clocks = dcn2_init_clocks,
+ .enable_pme_wa = dcn2_enable_pme_wa
};
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index edda426e32b4..940e74b7d2c6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -958,30 +958,12 @@ void hwss_edp_backlight_control(
edp_receiver_ready_T9(link);
}
-// Static helper function which calls the correct function
-// based on pp_smu version
-static void set_pme_wa_enable_by_version(struct dc *dc)
-{
- struct pp_smu_funcs *pp_smu = NULL;
-
- if (dc->res_pool->pp_smu)
- pp_smu = dc->res_pool->pp_smu;
-
- if (pp_smu) {
- if (pp_smu->ctx.ver == PP_SMU_VER_RV &&
pp_smu->rv_funcs.set_pme_wa_enable)
-
pp_smu->rv_funcs.set_pme_wa_enable(&(pp_smu->rv_funcs.pp_smu));
-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
- else if (pp_smu->ctx.ver == PP_SMU_VER_NV &&
pp_smu->nv_funcs.set_pme_wa_enable)
-
pp_smu->nv_funcs.set_pme_wa_enable(&(pp_smu->nv_funcs.pp_smu));
-#endif
- }
-}
-
void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
{
/* notify audio driver for audio modes of monitor */
struct dc *core_dc = pipe_ctx->stream->ctx->dc;
struct pp_smu_funcs *pp_smu = NULL;
+ struct clk_mgr *clk_mgr = core_dc->clk_mgr;
unsigned int i, num_audio = 1;
if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled
== true)
@@ -999,9 +981,9 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
- if (num_audio >= 1 && pp_smu != NULL)
+ if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa)
/*this is the first audio. apply the PME w/a in order
to wake AZ from D3*/
- set_pme_wa_enable_by_version(core_dc);
+ clk_mgr->funcs->enable_pme_wa(clk_mgr);
/* un-mute audio */
/* TODO: audio
[PATCH 456/459] drm/amd/display: add missing mod_vmid destructor
From: Dmytro Laktyushkin
mod_vmid is missing a destructor.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h | 2 ++
drivers/gpu/drm/amd/display/modules/vmid/vmid.c| 9 +
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h
b/drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h
index c7672f3b837f..a3787fdf0c08 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h
@@ -41,4 +41,6 @@ struct mod_vmid *mod_vmid_create(
unsigned int num_vmid,
struct dc_virtual_addr_space_config *va_config);
+void mod_vmid_destroy(struct mod_vmid *mod_vmid);
+
#endif /* MOD_VMID_H_ */
diff --git a/drivers/gpu/drm/amd/display/modules/vmid/vmid.c
b/drivers/gpu/drm/amd/display/modules/vmid/vmid.c
index 431052626d93..f0a153704f6e 100644
--- a/drivers/gpu/drm/amd/display/modules/vmid/vmid.c
+++ b/drivers/gpu/drm/amd/display/modules/vmid/vmid.c
@@ -156,3 +156,12 @@ struct mod_vmid *mod_vmid_create(
fail_dc_null:
return NULL;
}
+
+void mod_vmid_destroy(struct mod_vmid *mod_vmid)
+{
+ if (mod_vmid != NULL) {
+ struct core_vmid *core_vmid = MOD_VMID_TO_CORE(mod_vmid);
+
+ kfree(core_vmid);
+ }
+}
--
2.20.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 448/459] drm/amd/display: expose enable dp output functions
From: Eric Bernstein expose this function for future use Implementation of DCN3 DIO Link Encoder including dpcs register headers. Signed-off-by: Eric Bernstein Reviewed-by: Charlene Liu Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h | 5 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c index b04ef576ec5a..f495582e9e87 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c @@ -240,7 +240,7 @@ static bool update_cfg_data( return true; } -static void dcn20_link_encoder_enable_dp_output( +void dcn20_link_encoder_enable_dp_output( struct link_encoder *enc, const struct dc_link_settings *link_settings, enum clock_source_id clock_source) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h index 401fdea77262..3736b5548a25 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h @@ -155,6 +155,11 @@ void enc2_hw_init(struct link_encoder *enc); void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s); #endif +void dcn20_link_encoder_enable_dp_output( + struct link_encoder *enc, + const struct dc_link_settings *link_settings, + enum clock_source_id clock_source); + void dcn20_link_encoder_construct( struct dcn20_link_encoder *enc20, const struct encoder_init_data *init_data, -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 450/459] drm/amd/display: Rework CRTC color management
From: Nicholas Kazlauskas
[Why]
To prepare for the upcoming DRM plane color management properties
we need to correct a lot of wrong behavior and assumptions made for
CRTC color management.
The documentation added by this commit in amdgpu_dm_color explains
how the HW color pipeline works and its limitations with the DRM
interface.
The current implementation does the following wrong:
- Implicit sRGB DGM when no CRTC DGM is set
- Implicit sRGB RGM when no CRTC RGM is set
- No way to specify a non-linear DGM matrix that produces correct output
- No way to specify a correct RGM when a linear DGM is used
We had workarounds for passing kms_color tests but not all of the
behavior we had wrong was covered by these tests (especially when
it comes to non-linear DGM). Testing both DGM and RGM at the same time
isn't something kms_color tests well either.
[How]
The specifics for how color management works in AMDGPU and the new
behavior can be found by reading the documentation added to
amdgpu_dm_color.c from this patch.
All of the incorrect cases from the old implementation have been
addressed for the atomic interface, but there still a few TODOs for
the legacy one.
Note: this does cause regressions for kms_color@pipe-a-ctm-* over HDMI.
The result looks correct from visual inspection but the CRC no longer
matches. For reference, the test was previously doing the following:
linear degamma -> CTM -> sRGB regamma -> RGB to YUV (709) -> ...
Now the test is doing:
linear degamma -> CTM -> linear regamma -> RGB to YUV (709) -> ...
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Sun peng Li
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 10 +-
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 473 --
3 files changed, 356 insertions(+), 159 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0be6363c66e4..e8f2e0804bdb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2951,6 +2951,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device
*adev,
struct drm_plane_state *plane_state,
struct drm_crtc_state *crtc_state)
{
+ struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
const struct amdgpu_framebuffer *amdgpu_fb =
to_amdgpu_framebuffer(plane_state->fb);
struct dc_scaling_info scaling_info;
@@ -2995,13 +2996,11 @@ static int fill_dc_plane_attributes(struct
amdgpu_device *adev,
* Always set input transfer function, since plane state is refreshed
* every time.
*/
- ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
- if (ret) {
- dc_transfer_func_release(dc_plane_state->in_transfer_func);
- dc_plane_state->in_transfer_func = NULL;
- }
+ ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
+ if (ret)
+ return ret;
- return ret;
+ return 0;
}
static void update_stream_scaling_settings(const struct drm_display_mode *mode,
@@ -3590,6 +3589,8 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
state->vrr_supported = cur->vrr_supported;
state->freesync_config = cur->freesync_config;
state->crc_enabled = cur->crc_enabled;
+ state->cm_has_degamma = cur->cm_has_degamma;
+ state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
/* TODO Duplicate dc_stream after objects are stream object is
flattened */
@@ -5637,8 +5638,18 @@ static void amdgpu_dm_commit_planes(struct
drm_atomic_state *state,
bundle->stream_update.dst = acrtc_state->stream->dst;
}
- if (new_pcrtc_state->color_mgmt_changed)
- bundle->stream_update.out_transfer_func =
acrtc_state->stream->out_transfer_func;
+ if (new_pcrtc_state->color_mgmt_changed) {
+ /*
+* TODO: This isn't fully correct since we've actually
+* already modified the stream in place.
+*/
+ bundle->stream_update.gamut_remap =
+ _state->stream->gamut_remap_matrix;
+ bundle->stream_update.output_csc_transform =
+ _state->stream->csc_color_matrix;
+ bundle->stream_update.out_transfer_func =
+ acrtc_state->stream->out_transfer_func;
+ }
acrtc_state->stream->abm_level = acrtc_state->abm_level;
if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
@@ -6468,10 +6479,9 @@ static int dm_update_crtc_state(struct
[PATCH 454/459] drm/amd/display: move vmid determination logic to a module
From: Dmytro Laktyushkin
Currently vmid is decided internally inside dc. With the introduction
of new asics we are required to coordinate vmid use with external
components.
This change converts vmid logic to a DAL module allowing vmid to be
passed in as a parameter to DC.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/Makefile | 7 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 20 ---
.../drm/amd/display/dc/core/dc_vm_helper.c| 93 +++
drivers/gpu/drm/amd/display/dc/dc.h | 17 +-
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 3 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 3 +-
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 +-
.../drm/amd/display/dc/dcn20/dcn20_hubbub.c | 72
.../drm/amd/display/dc/dcn20/dcn20_hubbub.h | 12 +-
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 5 +-
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 3 +-
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 83 -
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
.../gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c | 7 +-
.../gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h | 1 -
.../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 16 +-
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 3 +-
drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h | 1 +
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 17 +-
.../gpu/drm/amd/display/dc/inc/vm_helper.h| 16 +-
.../drm/amd/display/modules/inc/mod_vmid.h| 44 +
.../gpu/drm/amd/display/modules/vmid/vmid.c | 158 ++
23 files changed, 357 insertions(+), 231 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h
create mode 100644 drivers/gpu/drm/amd/display/modules/vmid/vmid.c
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
b/drivers/gpu/drm/amd/display/dc/Makefile
index 00eaa69ba53d..55ce5b657390 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -50,8 +50,11 @@ AMD_DC = $(addsuffix /Makefile, $(addprefix
$(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LI
include $(AMD_DC)
DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \
-dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o \
-dc_vm_helper.o
+dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o
+
+ifdef CONFIG_DRM_AMD_DC_DCN2_0
+DISPLAY_CORE += dc_vm_helper.o
+endif
AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 8bc8ac3a7718..a29bb9bf3f9c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -808,26 +808,6 @@ void dc_destroy(struct dc **dc)
*dc = NULL;
}
-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
-bool dc_init_memory_hub(struct dc *dc, struct dc_addr_space_config *config)
-{
- // Memory hub init isn't done as part of dc_create because in windows,
dal/dc is
- // constructed before the vm config is setup in kmd so there's no way
- // they can give it to us at boot/dc_create
- bool vmSupported;
-
- // Call HWSS to setup HUBBUB for address config
- dc->hwss.init_dchub(dc->hwseq, dc, config);
-
- // Pre-init system aperture start/end for all HUBP instances (if not
gating?)
- // or cache system aperture if using power gating
- memcpy(>vm_config, config, sizeof(struct dc_addr_space_config));
-
- vmSupported = (dc->ctx->asic_id.chip_family == FAMILY_NV) ? true :
false;
- return vmSupported;
-}
-
-#endif
static void enable_timing_multisync(
struct dc *dc,
struct dc_state *ctx)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
index 6ce87b682a32..a96d8de9380e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
@@ -24,8 +24,9 @@
*/
#include "vm_helper.h"
+#include "dc.h"
-static void mark_vmid_used(struct vm_helper *vm_helper, unsigned int pos,
uint8_t hubp_idx)
+void vm_helper_mark_vmid_used(struct vm_helper *vm_helper, unsigned int pos,
uint8_t hubp_idx)
{
struct vmid_usage vmids = vm_helper->hubp_vmid_usage[hubp_idx];
@@ -33,91 +34,43 @@ static void mark_vmid_used(struct vm_helper *vm_helper,
unsigned int pos, uint8_
vmids.vmid_usage[1] = 1 << pos;
}
-static void add_ptb_to_table(struct vm_helper *vm_helper, unsigned int vmid,
uint64_t ptb)
+int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config
*pa_config)
{
- vm_helper->ptb_assigned_to_vmid[vmid] = ptb;
- vm_helper->num_vmids_available--;
-}
-
-static void clear_entry_from_vmid_table(struct
[PATCH 441/459] drm/amd/display: add support for forcing DCFCLK without affecting watermarks
From: Jun Lei
[why]
useful for debugging
[how]
plumb a debug option in dc
Signed-off-by: Jun Lei
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 4
drivers/gpu/drm/amd/display/dc/dc.h | 8
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index de471ca87ed7..e3c1debf2597 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -172,6 +172,10 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
pp_smu->set_voltage_by_freq(_smu->pp_smu,
PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
}
+ if (dc->debug.force_min_dcfclk_mhz > 0)
+ new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz >
(dc->debug.force_min_dcfclk_mhz * 1000)) ?
+ new_clocks->dcfclk_khz :
(dc->debug.force_min_dcfclk_mhz * 1000);
+
if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz,
clk_mgr_base->clks.dcfclk_khz)) {
clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 53a3876841cc..80c118f0d6da 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -369,6 +369,10 @@ struct dc_debug_options {
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
bool disable_fec;
#endif
+ /* This forces a hard min on the DCFCLK requested to SMU/PP
+* watermarks are not affected.
+*/
+ unsigned int force_min_dcfclk_mhz;
};
struct dc_debug_data {
@@ -418,6 +422,10 @@ struct dc_bounding_box_overrides {
int urgent_latency_ns;
int percent_of_ideal_drambw;
int dram_clock_change_latency_ns;
+ /* This forces a hard min on the DCFCLK we use
+* for DML. Unlike the debug option for forcing
+* DCFCLK, this override affects watermark calculations
+*/
int min_dcfclk_mhz;
};
--
2.20.1
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[PATCH 449/459] drm/amd/display: Use macro for invalid OPP ID
From: Wesley Chalmers
[WHY]
This is meant to make it clearer that 0xf is not a valid OPP ID, and
that code making use of OPP IDs should not accept this value.
Signed-off-by: Wesley Chalmers
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c| 4 ++--
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 2 ++
5 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 3f9ad09769b1..a48d314011a9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -63,7 +63,7 @@ void hubp1_set_blank(struct hubp *hubp, bool blank)
}
hubp->mpcc_id = 0xf;
- hubp->opp_id = 0xf;
+ hubp->opp_id = OPP_ID_INVALID;
}
}
@@ -1253,7 +1253,7 @@ void dcn10_hubp_construct(
hubp1->hubp_shift = hubp_shift;
hubp1->hubp_mask = hubp_mask;
hubp1->base.inst = inst;
- hubp1->base.opp_id = 0xf;
+ hubp1->base.opp_id = OPP_ID_INVALID;
hubp1->base.mpcc_id = 0xf;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index a2d3c4fdc805..0b1503de0f7a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1085,7 +1085,7 @@ static void dcn10_init_pipes(struct dc *dc, struct
dc_state *context)
pipe_ctx->plane_res.dpp = dpp;
pipe_ctx->plane_res.mpcc_inst = dpp->inst;
hubp->mpcc_id = dpp->inst;
- hubp->opp_id = 0xf;
+ hubp->opp_id = OPP_ID_INVALID;
hubp->power_gated = false;
dc->res_pool->opps[i]->mpc_tree_params.opp_id =
dc->res_pool->opps[i]->inst;
@@ -2436,7 +2436,7 @@ static void dcn10_apply_ctx_for_surface(
if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
if (old_pipe_ctx->stream_res.tg == tg &&
old_pipe_ctx->plane_res.hubp &&
- old_pipe_ctx->plane_res.hubp->opp_id != 0xf)
+ old_pipe_ctx->plane_res.hubp->opp_id !=
OPP_ID_INVALID)
dcn10_disable_plane(dc, old_pipe_ctx);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
index 82738f126517..dcba2c5326b2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
@@ -694,7 +694,7 @@ bool hubp2_construct(
hubp2->hubp_shift = hubp_shift;
hubp2->hubp_mask = hubp_mask;
hubp2->base.inst = inst;
- hubp2->base.opp_id = 0xf;
+ hubp2->base.opp_id = OPP_ID_INVALID;
hubp2->base.mpcc_id = 0xf;
return true;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 2cbffe2809b6..d55b15fbfe99 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -605,7 +605,7 @@ static void dcn20_init_hw(struct dc *dc)
pipe_ctx->plane_res.dpp = dpp;
pipe_ctx->plane_res.mpcc_inst = dpp->inst;
hubp->mpcc_id = dpp->inst;
- hubp->opp_id = 0xf;
+ hubp->opp_id = OPP_ID_INVALID;
hubp->power_gated = false;
pipe_ctx->stream_res.opp = NULL;
@@ -1307,7 +1307,7 @@ static void dcn20_apply_ctx_for_surface(
if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
if (old_pipe_ctx->stream_res.tg == tg &&
old_pipe_ctx->plane_res.hubp &&
- old_pipe_ctx->plane_res.hubp->opp_id != 0xf)
+ old_pipe_ctx->plane_res.hubp->opp_id !=
OPP_ID_INVALID)
dcn20_disable_plane(dc, old_pipe_ctx);
}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index fa98c96d0046..342477822dc0 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -28,6 +28,8 @@
#include "mem_input.h"
+#define OPP_ID_INVALID 0xf
+
enum cursor_pitch {
CURSOR_PITCH_64_PIXELS = 0,
--
2.20.1
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[PATCH 451/459] drm/amd/display: update DCN2 uclk switch time
From: Jun Lei
[why]
value commited to by HW team is going to be higher
than pre-silicon, and will cause underflow if driver not
updated
[how]
update hardcoded value, update pstate switching logic
to fix case where with long uclk time we won't allow switch
even when we should
Signed-off-by: Jun Lei
Reviewed-by: Eric Yang
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 8 +++-
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 6 ++
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index e3c1debf2597..6f01830fc020 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -195,12 +195,10 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
pp_smu->set_hard_min_socclk_by_freq(_smu->pp_smu,
clk_mgr_base->clks.socclk_khz / 1000);
}
- if (!safe_to_lower && pp_smu && pp_smu->set_pstate_handshake_support) {
- clk_mgr_base->clks.p_state_change_support = false;
- pp_smu->set_pstate_handshake_support(_smu->pp_smu, false);
- } else if (safe_to_lower && pp_smu &&
pp_smu->set_pstate_handshake_support) {
+ if (should_update_pstate_support(safe_to_lower,
new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support))
{
clk_mgr_base->clks.p_state_change_support =
new_clocks->p_state_change_support;
- pp_smu->set_pstate_handshake_support(_smu->pp_smu,
clk_mgr_base->clks.p_state_change_support);
+ if (pp_smu && pp_smu->set_pstate_handshake_support)
+ pp_smu->set_pstate_handshake_support(_smu->pp_smu,
clk_mgr_base->clks.p_state_change_support);
}
if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz,
clk_mgr_base->clks.dramclk_khz)) {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index c322e4697242..0835ac041acf 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -274,6 +274,12 @@ static inline bool should_set_clock(bool safe_to_lower,
int calc_clk, int cur_cl
return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk);
}
+static inline bool should_update_pstate_support(bool safe_to_lower, bool
calc_support, bool cur_support)
+{
+ // Whenever we are transitioning pstate support, we always want to
notify prior to committing state
+ return (calc_support != cur_support) ? !safe_to_lower : false;
+}
+
int clk_mgr_helper_get_active_display_cnt(
struct dc *dc,
struct dc_state *context);
--
2.20.1
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[PATCH 440/459] drm/amd/display: Copy stream updates onto streams
From: Nicholas Kazlauskas
[Why]
Almost every function in DC that works with stream state expects that
the current state on the stream is the one that it should be writing
out. These functions are typically triggered by specifying a particular
stream update - but the actual contents of the stream update itself
are ignored, leaving it to the DM to actually update the stream state
itself.
The problem with doing this in DM is a matter of timing. On Linux
most of this is incorrectly done in atomic check, when we actually want
it to be done during atomic commit tail while access to DC is locked.
To give an example, a commit requesting to modify color management
state for DM could come in, be rejected, but still have modified
the actual system state for the stream since it's shared memory. The
next time color management gets programmed it'll use the rejected
color management info - which might not even still be around if it's
a custom transfer function.
So a reasonable place to perform this is within DC itself and this is
the model that's currently in use for surface updates. DC can even
compare the current system state to the incoming surface update to
determine update level, something that can't currnetly be done with the
framework for stream updates.
[How]
Duplicate the framework used for surface updates for stream updates
as well. Copy all the updates after checking the update type.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Harry Wentland
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 97
1 file changed, 97 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 8cecd58653cf..8bc8ac3a7718 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1694,6 +1694,101 @@ static void copy_surface_update_to_plane(
*srf_update->coeff_reduction_factor;
}
+static void copy_stream_update_to_stream(struct dc *dc,
+struct dc_state *context,
+struct dc_stream_state *stream,
+const struct dc_stream_update *update)
+{
+ if (update == NULL || stream == NULL)
+ return;
+
+ if (update->src.height && update->src.width)
+ stream->src = update->src;
+
+ if (update->dst.height && update->dst.width)
+ stream->dst = update->dst;
+
+ if (update->out_transfer_func &&
+ stream->out_transfer_func != update->out_transfer_func) {
+ stream->out_transfer_func->sdr_ref_white_level =
+ update->out_transfer_func->sdr_ref_white_level;
+ stream->out_transfer_func->tf = update->out_transfer_func->tf;
+ stream->out_transfer_func->type =
+ update->out_transfer_func->type;
+ memcpy(>out_transfer_func->tf_pts,
+ >out_transfer_func->tf_pts,
+ sizeof(struct dc_transfer_func_distributed_points));
+ }
+
+ if (update->hdr_static_metadata)
+ stream->hdr_static_metadata = *update->hdr_static_metadata;
+
+ if (update->abm_level)
+ stream->abm_level = *update->abm_level;
+
+ if (update->periodic_interrupt0)
+ stream->periodic_interrupt0 = *update->periodic_interrupt0;
+
+ if (update->periodic_interrupt1)
+ stream->periodic_interrupt1 = *update->periodic_interrupt1;
+
+ if (update->gamut_remap)
+ stream->gamut_remap_matrix = *update->gamut_remap;
+
+ /* Note: this being updated after mode set is currently not a use case
+* however if it arises OCSC would need to be reprogrammed at the
+* minimum
+*/
+ if (update->output_color_space)
+ stream->output_color_space = *update->output_color_space;
+
+ if (update->output_csc_transform)
+ stream->csc_color_matrix = *update->output_csc_transform;
+
+ if (update->vrr_infopacket)
+ stream->vrr_infopacket = *update->vrr_infopacket;
+
+ if (update->dpms_off)
+ stream->dpms_off = *update->dpms_off;
+
+ if (update->vsc_infopacket)
+ stream->vsc_infopacket = *update->vsc_infopacket;
+
+ if (update->vsp_infopacket)
+ stream->vsp_infopacket = *update->vsp_infopacket;
+
+ if (update->dither_option)
+ stream->dither_option = *update->dither_option;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /* update current stream with writeback info */
+ if (update->wb_update) {
+ int i;
+
+ stream->num_wb_info = update->wb_update->num_wb_info;
+ ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
+ for (i = 0; i < stream->num_wb_info; i++)
+
[PATCH 410/459] drm/amd/display: add flags for gamut map library
From: Vitaly Prosyak
[Why & How]
Gamut map lib provides a wider gamut mapping options
vs BT2390
Signed-off-by: Vitaly Prosyak
Reviewed-by: Krunoslav Kovac
Acked-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
Acked-by: Vitaly Prosyak
Signed-off-by: Alex Deucher
---
.../drm/amd/display/modules/inc/mod_shared.h | 24 ++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
b/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
index 9406d0a167ee..6c877eeba429 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
@@ -61,7 +61,10 @@ union lut3d_control_flags {
unsigned int use_3dlut :1;
unsigned int less_than_dcip3:1;
unsigned int override_lum :1;
- unsigned int reseved:8;
+ unsigned int use_gamut_map_lib
:1;
+ unsigned int chromatic_adaptation_src
:1;
+ unsigned int chromatic_adaptation_dst
:1;
+ unsigned int reseved:5;
} bits;
};
@@ -71,6 +74,21 @@ enum tm_show_option_internal {
tm_show_option_internal_duplicate_sidebyside/*use flags2*/
};
+enum lut3d_control_gamut_map {
+ lut3d_control_gamut_map_none = 0,
+ lut3d_control_gamut_map_tonemap,
+ lut3d_control_gamut_map_chto,
+ lut3d_control_gamut_map_chto_chso,
+ lut3d_control_gamut_map_chto_chci
+};
+
+enum lut3d_control_rotation_mode {
+ lut3d_control_rotation_mode_none = 0,
+ lut3d_control_rotation_mode_hue,
+ lut3d_control_rotation_mode_cc,
+ lut3d_control_rotation_mode_hue_cc
+};
+
struct lut3d_settings {
unsigned char version;
union lut3d_control_flags flags;
@@ -80,6 +98,10 @@ struct lut3d_settings {
unsigned int max_lum;
unsigned int min_lum2;
unsigned int max_lum2;
+ enum lut3d_control_gamut_map map;
+ enum lut3d_control_rotation_mode rotation;
+ enum lut3d_control_gamut_map map2;
+ enum lut3d_control_rotation_mode rotation2;
};
#endif
--
2.20.1
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[PATCH 435/459] drm/amd/display: Drive-by fixes for display_mode_vba
From: Ilya Bakoulin
Fixes for the following:
- Incorrect pointer type (unsigned int instead of double)
- Incorrect DSC number of slices setting
Signed-off-by: Ilya Bakoulin
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 3 ---
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 4 ++--
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 4df885d17e69..a21608cd67ef 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -564,7 +564,6 @@ static void fetch_pipe_params(struct display_mode_lib
*mode_lib)
if (src->is_hsplit) {
for (k = j + 1; k < mode_lib->vba.cache_num_pipes; ++k)
{
display_pipe_source_params_st *src_k =
[k].pipe.src;
- display_output_params_st *dout_k =
[k].dout;
if (src_k->is_hsplit && !visited[k]
&& src->hsplit_grp ==
src_k->hsplit_grp) {
@@ -579,8 +578,6 @@ static void fetch_pipe_params(struct display_mode_lib
*mode_lib)
mode_lib->vba.ViewportHeight[mode_lib->vba.NumberOfActivePlanes] +=
src_k->viewport_height;
-
mode_lib->vba.NumberOfDSCSlices[mode_lib->vba.NumberOfActivePlanes] +=
- dout_k->dsc_slices;
visited[k] = true;
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 75028007095c..faf33e77e8d4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -455,7 +455,7 @@ struct vba_vars_st {
double TotalNumberOfActiveOTG;
double FECOverhead;
double EffectiveFECOverhead;
- unsigned int Outbpp;
+ double Outbpp;
unsigned int OutbppDSC;
double TotalDSCUnitsRequired;
double bpp;
@@ -538,7 +538,7 @@ struct vba_vars_st {
bool RequiresDSC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
unsigned int NumberOfDSCSlice[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
double RequiresFEC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
- unsigned int OutputBppPerState[DC__VOLTAGE_STATES +
1][DC__NUM_DPP__MAX];
+ double OutputBppPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
double DSCDelayPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
bool ViewportSizeSupport[DC__VOLTAGE_STATES + 1];
unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX];
--
2.20.1
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[PATCH 427/459] drm/amd/display: Set test pattern on blank when using Visual Confirm
From: Joshua Aberback
[Why]
We want a test pattern to show up on screen when we're blanked and have
visual confirm enabled, for debugging. Raven does this, it's a mistake that
Navi does not.
[How]
- in "blank_pixel_data", set appropriate DPG pattern for visual confirm
- refactor DPG calls out of "enable_stream_timing"
Signed-off-by: Joshua Aberback
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 53 ---
1 file changed, 11 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index f9b0ea75eeb4..f788a39a1df1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -679,13 +679,8 @@ enum dc_status dcn20_enable_stream_timing(
struct dc *dc)
{
struct dc_stream_state *stream = pipe_ctx->stream;
- enum dc_color_space color_space;
- struct tg_color black_color = {0};
struct drr_params params = {0};
unsigned int event_triggers = 0;
- int width = stream->timing.h_addressable + stream->timing.h_border_left
+ stream->timing.h_border_right;
- int height = stream->timing.v_addressable +
stream->timing.v_border_bottom + stream->timing.v_border_top;
- enum controller_dp_test_pattern dpg_pattern =
CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
@@ -734,44 +729,16 @@ enum dc_status dcn20_enable_stream_timing(
pipe_ctx->stream_res.tg->funcs->setup_global_lock(
pipe_ctx->stream_res.tg);
- /* program otg blank color */
- color_space = stream->output_color_space;
- color_space_to_black_color(dc, color_space, _color);
-
- if (odm_pipe) {
-
- if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
- dpg_pattern = CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
-
- width /= 2;
-
+ if (odm_pipe)
odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
odm_pipe->stream_res.opp,
true);
- odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
- odm_pipe->stream_res.opp,
- dpg_pattern,
- stream->timing.display_color_depth,
- _color,
- width,
- height);
- }
-
- if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
- dpg_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
-
pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
pipe_ctx->stream_res.opp,
true);
- pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(
- pipe_ctx->stream_res.opp,
- dpg_pattern,
- stream->timing.display_color_depth,
- _color,
- width,
- height);
+ dc->hwss.blank_pixel_data(dc, pipe_ctx, true);
/* VTG is within DCHUB command block. DCFCLK is always on */
if (false ==
pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
@@ -1022,19 +989,17 @@ void dcn20_blank_pixel_data(
struct pipe_ctx *pipe_ctx,
bool blank)
{
- enum dc_color_space color_space;
struct tg_color black_color = {0};
struct stream_resource *stream_res = _ctx->stream_res;
struct dc_stream_state *stream = pipe_ctx->stream;
+ enum dc_color_space color_space = stream->output_color_space;
enum controller_dp_test_pattern test_pattern =
CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
-
int width = stream->timing.h_addressable + stream->timing.h_border_left
+ stream->timing.h_border_right;
int height = stream->timing.v_addressable +
stream->timing.v_border_bottom + stream->timing.v_border_top;
- /* program opp dpg blank color */
- color_space = stream->output_color_space;
+ /* get opp dpg blank color */
color_space_to_black_color(dc, color_space, _color);
if (bot_odm_pipe)
@@ -1043,9 +1008,12 @@ void dcn20_blank_pixel_data(
if (blank) {
if (stream_res->abm)
stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
- } else
- test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
+ if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
+ test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
+ } else {
+ test_pattern =
[PATCH 408/459] drm/amd/display: DCHUB requestors numbers for Navi.
From: Yongqiang Sun
[Why]
The DCHub arbiter has a mechanism to dynamically rate limit the DCHub
request stream to the fabric. If the memory controller is fully utilized
and the DCHub requestors are well ahead of their amortized schedule,
then it is safe to prevent the next winner from being committed and sent
to the fabric. The utilization of the memory controller is approximated
by ensuring that the number of outstanding requests is greater than a
threshold specified by the ARB_MIN_REQ_OUTSTANDING. To determine that
the DCHub requestors are well ahead of the amortized schedule, the slack
of the next winner is compared with the ARB_SAT_LEVEL in DLG RefClk
cycles.
[How]
The recommended settings to enable thise dynamic limiting for Navi is
180 requests.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../drm/amd/display/dc/dcn20/dcn20_hubbub.c | 24 ++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
index d6705b40a57c..a851574f118a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
@@ -493,6 +493,28 @@ void hubbub2_get_dchub_ref_freq(struct hubbub *hubbub,
}
}
+static void hubbub2_program_watermarks(
+ struct hubbub *hubbub,
+ struct dcn_watermark_set *watermarks,
+ unsigned int refclk_mhz,
+ bool safe_to_lower)
+{
+ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
+ /*
+* Need to clamp to max of the register values (i.e. no wrap)
+* for dcn1, all wm registers are 21-bit wide
+*/
+ hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz,
safe_to_lower);
+ hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz,
safe_to_lower);
+ hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz,
safe_to_lower);
+
+ REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,
+ DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
+ REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND,
180);
+
+ hubbub1_allow_self_refresh_control(hubbub,
!hubbub->ctx->dc->debug.disable_stutter);
+}
+
static const struct hubbub_funcs hubbub2_funcs = {
.update_dchub = hubbub2_update_dchub,
.init_dchub = hubbub2_init_dchub,
@@ -502,7 +524,7 @@ static const struct hubbub_funcs hubbub2_funcs = {
.get_dcc_compression_cap = hubbub2_get_dcc_compression_cap,
.wm_read_state = hubbub2_wm_read_state,
.get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
- .program_watermarks = hubbub1_program_watermarks,
+ .program_watermarks = hubbub2_program_watermarks,
};
void hubbub2_construct(struct dcn20_hubbub *hubbub,
--
2.20.1
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[PATCH 433/459] drm/amd/display: Return UPDATE_TYPE_FULL on writeback update
From: Charlene Liu
Should do full update when display writeback is updated.
Signed-off-by: Charlene Liu
Reviewed-by: Duke Du
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 5 +
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 +++-
drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 1 +
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index fd955151132f..8cecd58653cf 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1516,6 +1516,11 @@ static enum surface_update_type
check_update_surfaces_for_stream(
if (stream_update->dpms_off)
return UPDATE_TYPE_FULL;
+
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (stream_update->wb_update)
+ return UPDATE_TYPE_FULL;
+#endif
}
for (i = 0 ; i < surface_count; i++) {
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 3787398f6d80..30a25e694da0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -373,6 +373,7 @@ bool dc_stream_add_writeback(struct dc *dc,
{
bool isDrc = false;
int i = 0;
+ struct dwbc *dwb;
if (stream == NULL) {
dm_error("DC: dc_stream is NULL!\n");
@@ -391,7 +392,8 @@ bool dc_stream_add_writeback(struct dc *dc,
wb_info->dwb_params.out_transfer_func = stream->out_transfer_func;
-
+ dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
+ dwb->dwb_is_drc = false;
/* recalculate and apply DML parameters */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
index d4ae6eaaeb57..0ac21fa231c7 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
@@ -127,6 +127,7 @@ struct dwbc {
enum dc_transfer_func_predefined tf;
enum dc_color_space output_color_space;
bool dwb_is_efc_transition;
+ bool dwb_is_drc;
int wb_src_plane_inst;/*hubp, mpcc, inst*/
bool update_privacymask;
uint32_t mask_id;
--
2.20.1
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[PATCH 417/459] drm/amd/display: Remove OPP clock programming on plane disable
From: Joshua Aberback
[Why]
Plane disable gets calls when we enable blank. On DCN2, we blank by using
DPG to display a black colour instead of using OTG blank. DPG runs off the
OPP clock, therefore we shouldn't disable the OPP clock when disabling the
plane. We do need to disable the OPP clock when disabling the entire pipe,
that will be addressed in a separate commit.
Signed-off-by: Joshua Aberback
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index c7ae538611f7..ea56f15a51fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -463,7 +463,6 @@ static void dcn20_plane_atomic_disable(struct dc *dc,
struct pipe_ctx *pipe_ctx)
{
struct hubp *hubp = pipe_ctx->plane_res.hubp;
struct dpp *dpp = pipe_ctx->plane_res.dpp;
- int opp_id = hubp->opp_id;
dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
@@ -479,11 +478,6 @@ static void dcn20_plane_atomic_disable(struct dc *dc,
struct pipe_ctx *pipe_ctx)
dpp->funcs->dpp_dppclk_control(dpp, false, false);
- if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list
== NULL)
- pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
- pipe_ctx->stream_res.opp,
- false);
-
hubp->power_gated = true;
dc->optimized_required = false; /* We're powering off, no need to
optimize */
--
2.20.1
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[PATCH 420/459] drm/amd/display: Expose send immediate sdp message interface
From: "Leo (Hanghong) Ma"
[Why]
To send sdp message immediately from a single slot.
[How]
Modify the generic SDP message interface, and use GSP4 to send immediate
sdp message.
Signed-off-by: Leo (Hanghong) Ma
Reviewed-by: Harry Wentland
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dc_stream.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 0a83cd36d506..e253a5c591f6 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -126,7 +126,6 @@ struct dc_stream_state {
struct dc_info_packet vrr_infopacket;
struct dc_info_packet vsc_infopacket;
struct dc_info_packet vsp_infopacket;
- struct dc_info_packet dpsdp_infopacket;
struct rect src; /* composition area */
struct rect dst; /* stream addressable area */
--
2.20.1
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[PATCH 422/459] drm/amd/display: add dsc_passthrough_support bit in dpcd struct
From: Wenjing Liu
Signed-off-by: Wenjing Liu
Reviewed-by: Nikola Cornij
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/include/dpcd_structs.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/include/dpcd_structs.h
b/drivers/gpu/drm/amd/display/include/dpcd_structs.h
index 6f417e0480e6..ca9c5e0c062f 100644
--- a/drivers/gpu/drm/amd/display/include/dpcd_structs.h
+++ b/drivers/gpu/drm/amd/display/include/dpcd_structs.h
@@ -34,9 +34,9 @@ struct dpcd_dsc_basic_capabilities {
struct {
// Byte 0
struct {
-
- unsigned char dsc_support
:1; // Bit0
- unsigned char reserved
:7;
+ unsigned char dsc_support :1; //
Bit0
+ unsigned char dsc_passthrough_support :1; //
Bit1
+ unsigned char reserved :6;
} dsc_support;
// Byte 1
--
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[PATCH 446/459] drm/amd/display: Alpha plane type
From: Eric Bernstein Add Alpha surface type for future use Signed-off-by: Eric Bernstein Reviewed-by: Dmytro Laktyushkin Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h index b8a4bfcdbeb2..91dc42e580ec 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h @@ -459,6 +459,7 @@ type ROTATION_ANGLE;\ type H_MIRROR_EN;\ type SURFACE_PIXEL_FORMAT;\ + type ALPHA_PLANE_EN;\ type SURFACE_FLIP_TYPE;\ type SURFACE_FLIP_MODE_FOR_STEREOSYNC;\ type SURFACE_FLIP_IN_STEREOSYNC;\ -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 442/459] drm/amd/display: update DSC MST DP virtual DPCD peer device enumeration policy
From: Wenjing Liu
[why]
Current policy assumes virtual DPCD peer device as
an individual MST branch device with 1 input and 1 output.
However this is only true for virtual DP-to-DP peer device.
In general there are three types of virtual DP peer devices.
1. Sink peer device with virtual DPCD.
2. Virtual DP-to-DP Peer device with virtual DPCD.
3. Virtual DP-to-HDMI Protocol Converter Peer Device with
Virtual DPCD.
So we should break the assumption and handle all three types.
[how]
DP-to-DP peer device will have virtual DPCD cap upstream.
Sink peer device will have virtual DPCD on the logical port.
Dp to HDMI protocol converter peer device will have virtual DPCD
on its converter port.
For DSC capable Synaptics non VGA port we workaround by enumerating
a virutal DPCD peer device on its upstream
even if it doesn't have one.
Signed-off-by: Wenjing Liu
Reviewed-by: Jun Lei
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 ++
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 95 ++
drivers/gpu/drm/amd/display/dc/dc.h | 19 +-
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 115 +++-
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 6 +
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 5 +-
.../drm/amd/display/include/dpcd_structs.h| 168 --
7 files changed, 161 insertions(+), 261 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/display/include/dpcd_structs.h
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8f206a7ddb8c..0be6363c66e4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3494,6 +3494,20 @@ create_stream_for_sink(struct amdgpu_dm_connector
*aconnector,
fill_stream_properties_from_drm_display_mode(stream,
, >base, con_state, old_stream);
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* stream->timing.flags.DSC = 0; */
+/* */
+ /* if (aconnector->dc_link && */
+ /* aconnector->dc_link->connector_signal ==
SIGNAL_TYPE_DISPLAY_PORT #<{(|&& */
+ /*
aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.is_dsc_supported|)}>#) */
+ /* if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc, */
+ /* >dc_link->dpcd_caps.dsc_caps, */
+ /* dc_link_bandwidth_kbps(aconnector->dc_link,
dc_link_get_link_cap(aconnector->dc_link)), */
+ /* >timing, */
+ /* >timing.dsc_cfg)) */
+ /* stream->timing.flags.DSC = 1; */
+#endif
+
update_stream_scaling_settings(, dm_state, stream);
fill_audio_info(
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 017f88c9f2e4..056be4c34a98 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2382,10 +2382,6 @@ static bool retrieve_link_cap(struct dc_link *link)
uint32_t read_dpcd_retry_cnt = 3;
int i;
struct dp_sink_hw_fw_revision dp_hw_fw_revision;
-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
- uint8_t dsc_data[16]; /* DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1
== 16 */
- struct dsc_dec_dpcd_caps *dsc_dec_caps;
-#endif
memset(dpcd_data, '\0', sizeof(dpcd_data));
memset(_strm_port_count,
@@ -2558,93 +2554,26 @@ static bool retrieve_link_cap(struct dc_link *link)
sizeof(dp_hw_fw_revision.ieee_fw_rev));
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
- dsc_dec_caps = >dpcd_caps.dsc_sink_caps;
- memset(dsc_dec_caps, '\0', sizeof(*dsc_dec_caps));
- memset(>dpcd_caps.dsc_sink_caps, '\0',
- sizeof(link->dpcd_caps.dsc_sink_caps));
+ memset(>dpcd_caps.dsc_caps, '\0',
+ sizeof(link->dpcd_caps.dsc_caps));
memset(>dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
/* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
- status = core_link_read_dpcd(
- link,
- DP_DSC_SUPPORT,
- dsc_data,
- sizeof(dsc_data));
- if (status == DC_OK) {
- DC_LOG_DSC("DSC DPCD capability read at link %d:",
- link->link_index);
- DC_LOG_DSC("\t%02x %02x %02x %02x",
- dsc_data[0], dsc_data[1],
- dsc_data[2], dsc_data[3]);
- DC_LOG_DSC("\t%02x %02x %02x %02x",
- dsc_data[4], dsc_data[5],
-
[PATCH 444/459] drm/amd/display: update dsc max_target_bpp to 16 bpp
From: Wenjing Liu
[why]
According to the latest specs, the max_target bpp sink
can support is 16 bpp.
[how]
update dsc max_target_bpp to 16
Signed-off-by: Wenjing Liu
Reviewed-by: Jun Lei
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 96b18bb3b1cc..77e7a0f8a527 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -242,9 +242,6 @@ static bool intersect_dsc_caps(
}
struct dc_dsc_policy {
- float max_compression_ratio_legacy;
- float sst_compression_legacy; // Maximum quality if 0.0
- float mst_compression_legacy;
bool use_min_slices_h;
int max_slices_h; // Maximum available if 0
int num_slices_v;
@@ -274,18 +271,14 @@ static inline uint32_t calc_dsc_bpp_x16(uint32_t
stream_bandwidth_kbps, uint32_t
}
const struct dc_dsc_policy dsc_policy = {
- .max_compression_ratio_legacy = 3.0f, // DSC Policy: Limit compression
to 3:1 at most in all cases
- .sst_compression_legacy = 0.0f, // DSC Policy: SST - Maximum quality
(0.0)
- .mst_compression_legacy = 3.0f, // DSC Policy: MST - always 3:1
compression
.use_min_slices_h = true, // DSC Policy: Use minimum number of slices
that fits the pixel clock
.max_slices_h = 0, // DSC Policy: Use max available slices (in our case
4 for or 8, depending on the mode)
-
/* DSC Policy: Number of vertical slices set to 2 for no particular
reason.
* Seems small enough to not affect the quality too much, while still
providing some error
* propagation control (which may also help debugging).
*/
.num_slices_v = 16,
- .max_target_bpp = 24,
+ .max_target_bpp = 16,
.min_target_bpp = 8,
};
--
2.20.1
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[PATCH 439/459] drm/amd/display: Fix incorrect vba type
From: Ilya Bakoulin
SwathWidthCThisState is expected to be an unsigned int array.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Charlene Liu
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index faf33e77e8d4..0347f74cda3a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -633,7 +633,7 @@ struct vba_vars_st {
bool LinkDSCEnable;
bool ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES + 1];
bool ODMCombineEnableThisState[DC__NUM_DPP__MAX];
- double SwathWidthCThisState[DC__NUM_DPP__MAX];
+ unsigned int SwathWidthCThisState[DC__NUM_DPP__MAX];
bool ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
double AlignedDCCMetaPitchY[DC__NUM_DPP__MAX];
double AlignedDCCMetaPitchC[DC__NUM_DPP__MAX];
--
2.20.1
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[PATCH 423/459] drm/amd/display: used optimum VSTARTUP instead of MaxVStartup
From: Charlene Liu
[Description]
Features that are desirable for minimizing the Global Sync Period:
DRR and lateflip
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4
.../drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c| 8 ++--
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 2 ++
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 9243f275d265..ca5a7791d080 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1671,6 +1671,8 @@ int dcn20_populate_dml_pipes_from_context(
/* Unknown link capabilities, so assume max */
pipes[pipe_cnt].dout.dp_lanes = 4;
}
+ pipes[pipe_cnt].pipe.dest.vtotal_min =
res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
+ pipes[pipe_cnt].pipe.dest.vtotal_max =
res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
pipes[pipe_cnt].dout.output_bpp =
res_ctx->pipe_ctx[i].stream->timing.display_color_depth;
switch (res_ctx->pipe_ctx[i].stream->signal) {
@@ -1749,6 +1751,8 @@ int dcn20_populate_dml_pipes_from_context(
pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
pipes[pipe_cnt].pipe.src.is_hsplit = 0;
pipes[pipe_cnt].pipe.dest.odm_combine = 0;
+ pipes[pipe_cnt].pipe.dest.vtotal_min = timing->v_total;
+ pipes[pipe_cnt].pipe.dest.vtotal_max = timing->v_total;
} else {
struct dc_plane_state *pln =
res_ctx->pipe_ctx[i].plane_state;
struct scaler_data *scl =
_ctx->pipe_ctx[i].plane_res.scl_data;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index 21d90c6f3c88..649883777f62 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -2698,8 +2698,12 @@ static void
dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
VStartupMargin =
dml_min(VStartupMargin, Margin);
}
- if (mode_lib->vba.UseMaximumVStartup)
- mode_lib->vba.VStartup[k] =
mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]];
+ if (mode_lib->vba.UseMaximumVStartup) {
+ if (mode_lib->vba.VTotal_Max[k] ==
mode_lib->vba.VTotal[k]) {
+ //only use max vstart if it is not drr or
lateflip.
+ mode_lib->vba.VStartup[k] =
mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]];
+ }
+ }
}
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 4e0183dd634a..75028007095c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -284,6 +284,8 @@ struct vba_vars_st {
unsigned int VTAPsChroma[DC__NUM_DPP__MAX];
unsigned int HTotal[DC__NUM_DPP__MAX];
unsigned int VTotal[DC__NUM_DPP__MAX];
+ unsigned int VTotal_Max[DC__NUM_DPP__MAX];
+ unsigned int VTotal_Min[DC__NUM_DPP__MAX];
int DPPPerPlane[DC__NUM_DPP__MAX];
double PixelClock[DC__NUM_DPP__MAX];
double PixelClockBackEnd[DC__NUM_DPP__MAX];
--
2.20.1
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[PATCH 443/459] drm/amd/display: add some parameters to validate bandwidth functions
From: Charlene Liu
Signed-off-by: Charlene Liu
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dc_types.h| 8
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c| 3 ++-
.../gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 9 +
.../amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c| 5 -
.../amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h| 5 -
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h| 5 -
6 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 7ce8d62ce5ae..a06429ca0019 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -574,6 +574,14 @@ struct dc_info_packet {
uint8_t sb[32];
};
+struct dc_info_packet_128 {
+ bool valid;
+ uint8_t hb0;
+ uint8_t hb1;
+ uint8_t hb2;
+ uint8_t hb3;
+ uint8_t sb[128];
+};
#define DC_PLANE_UPDATE_TIMES_MAX 10
struct dc_plane_flip_time {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index d71a0dcf652a..310687ec166e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2364,7 +2364,8 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct
dc_state *context,
pipe_cnt,
pipe_idx,
cstate_en,
-
context->bw_ctx.bw.dcn.clk.p_state_change_support);
+
context->bw_ctx.bw.dcn.clk.p_state_change_support,
+ false, false, false);
context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(>bw_ctx.dml,
>res_ctx.pipe_ctx[i].rq_regs,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
index 130b01801a26..791aa745efd2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
@@ -204,14 +204,7 @@ static void enc2_stream_encoder_stop_hdmi_info_packets(
}
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-struct dc_info_packet_128 {
- bool valid;
- uint8_t hb0;
- uint8_t hb1;
- uint8_t hb2;
- uint8_t hb3;
- uint8_t sb[128];
-};
+
/* Update GSP7 SDP 128 byte long */
static void enc2_send_gsp7_128_info_packet(
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
index ec518ab0f694..878bf4782ce6 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
@@ -1567,7 +1567,10 @@ void dml20_rq_dlg_get_dlg_reg(struct display_mode_lib
*mode_lib,
const unsigned int num_pipes,
const unsigned int pipe_idx,
const bool cstate_en,
- const bool pstate_en)
+ const bool pstate_en,
+ const bool vm_en,
+ const bool ignore_viewport_pos,
+ const bool immediate_flip_support)
{
display_rq_params_st rq_param = {0};
display_dlg_sys_params_st dlg_sys_param = {0};
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
index ebb26105cf59..8c86b63ddf07 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
@@ -66,6 +66,9 @@ void dml20_rq_dlg_get_dlg_reg(
const unsigned int num_pipes,
const unsigned int pipe_idx,
const bool cstate_en,
- const bool pstate_en);
+ const bool pstate_en,
+ const bool vm_en,
+ const bool ignore_viewport_pos,
+ const bool immediate_flip_support);
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
index 61541c431110..5bf13d67f289 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
@@ -50,7 +50,10 @@ struct dml_funcs {
const unsigned int num_pipes,
const unsigned int pipe_idx,
const bool cstate_en,
- const bool pstate_en);
+ const bool pstate_en,
+ const bool vm_en,
+ const bool ignore_viewport_pos,
+ const bool
[PATCH 447/459] drm/amd/display: add dwb stere caps and version
From: Charlene Liu
add dwb stereo caps and ver for future use
Signed-off-by: Charlene Liu
Reviewed-by: Charlene Liu
Reviewed-by: Krunoslav Kovac
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 1 +
drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index a06429ca0019..6eabb6491a3d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -582,6 +582,7 @@ struct dc_info_packet_128 {
uint8_t hb3;
uint8_t sb[128];
};
+
#define DC_PLANE_UPDATE_TIMES_MAX 10
struct dc_plane_flip_time {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
index 0ac21fa231c7..a3409294ae0c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
@@ -38,6 +38,7 @@ enum dce_version;
enum dwb_sw_version {
dwb_ver_1_0 = 1,
+ dwb_ver_2_0 = 2,
};
enum dwb_source {
@@ -112,8 +113,9 @@ struct dwb_caps {
unsigned int support_ogam :1;
unsigned int support_wbscl :1;
unsigned int support_ocsc :1;
+ unsigned int support_stereo :1;
} caps;
- unsigned int reserved2[10]; /* Reserved for future use, MUST BE 0.
*/
+ unsigned int reserved2[9]; /* Reserved for future use, MUST BE 0.
*/
};
struct dwbc {
--
2.20.1
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[PATCH 419/459] drm/amd/display: Fix LB BPP and Cursor width
From: Ilya Bakoulin
DCN2.0 LB BPP should be 48 or 16BPC and max cursor width should be 256.
Also use populate_dml_pipes as functions pointer instead of using it directly
Signed-off-by: Ilya Bakoulin
Reviewed-by: Eric Bernstein
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 27 +--
.../amd/display/dc/dml/display_mode_enums.h | 3 ++-
.../drm/amd/display/dc/dml/display_mode_vba.c | 3 +++
.../gpu/drm/amd/display/dc/inc/core_types.h | 5
4 files changed, 29 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 0bd0b5279c18..9243f275d265 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1720,10 +1720,10 @@ int dcn20_populate_dml_pipes_from_context(
* bw calculations due to cursor on/off
*/
pipes[pipe_cnt].pipe.src.num_cursors = 2;
- pipes[pipe_cnt].pipe.src.cur0_src_width = 128;
- pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_64bit;
- pipes[pipe_cnt].pipe.src.cur1_src_width = 128;
- pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_64bit;
+ pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
+ pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
+ pipes[pipe_cnt].pipe.src.cur1_src_width = 256;
+ pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit;
if (!res_ctx->pipe_ctx[i].plane_state) {
pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
@@ -1800,7 +1800,7 @@ int dcn20_populate_dml_pipes_from_context(
res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height;
}
- pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth =
dm_lb_10;
+ pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth =
dm_lb_16;
pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio =
(double) scl->ratios.horz.value / (1ULL<<32);
pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c =
(double) scl->ratios.horz_c.value / (1ULL<<32);
pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio =
(double) scl->ratios.vert.value / (1ULL<<32);
@@ -2022,7 +2022,12 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct
dc_state *context,
resource_build_scaling_params(pipe);
}
- pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, >res_ctx,
pipes);
+ if (dc->res_pool->funcs->populate_dml_pipes)
+ pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
+ >res_ctx, pipes);
+ else
+ pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
+ >res_ctx, pipes);
if (!pipe_cnt) {
BW_VAL_TRACE_SKIP(pass);
@@ -2223,8 +2228,14 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct
dc_state *context,
pipe_cnt++;
}
- if (pipe_cnt != pipe_idx)
- pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
>res_ctx, pipes);
+ if (pipe_cnt != pipe_idx) {
+ if (dc->res_pool->funcs->populate_dml_pipes)
+ pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
+ >res_ctx, pipes);
+ else
+ pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
+ >res_ctx, pipes);
+ }
pipes[0].clks_cfg.voltage = vlevel;
pipes[0].clks_cfg.dcfclk_mhz =
context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
index 2a65af31eaa9..0c2fab1e93b6 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
@@ -86,7 +86,8 @@ enum dm_swizzle_mode {
dm_sw_gfx7_2d_thin_gl
};
enum lb_depth {
- dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16
+ dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16 = 4,
+ dm_lb_19 = 5
};
enum voltage_state {
dm_vmin = 0, dm_vmid = 1, dm_vnom = 2, dm_vmax = 3
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 7f3ea740bfe8..4df885d17e69 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -510,6 +510,9 @@ static void fetch_pipe_params(struct display_mode_lib
*mode_lib)
case dm_lb_16:
lb_depth = 48;
break;
+
[PATCH 414/459] drm/amd/display: Create DWB resource for DCN2
From: Charlene Liu
[Description]
dcn20 has num_dwb =1 in the res cap, but not created.
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Reviewed-by: Duke Du
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 1 -
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 111 ++
.../drm/amd/display/include/logger_types.h| 3 +
.../include/asic_reg/dcn/dcn_2_0_0_offset.h | 4 +
.../include/asic_reg/dcn/dcn_2_0_0_sh_mask.h | 16 +++
5 files changed, 134 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
index a6299f0d6b22..1b68de27ba74 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
@@ -10,7 +10,6 @@ ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
DCN20 += dcn20_dsc.o
endif
-
CFLAGS_dcn20_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20))
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index ceee0d6b3c26..46e7f76a6553 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -64,6 +64,9 @@
#include "nbio/nbio_2_3_offset.h"
+#include "dcn20/dcn20_dwb.h"
+#include "dcn20/dcn20_mmhubbub.h"
+
#include "mmhub/mmhub_2_0_0_offset.h"
#include "mmhub/mmhub_2_0_0_sh_mask.h"
@@ -470,6 +473,40 @@ static const struct dcn2_dpp_mask tf_mask = {
TF_REG_LIST_SH_MASK_DCN20(_MASK)
};
+#define dwbc_regs_dcn2(id)\
+[id] = {\
+ DWBC_COMMON_REG_LIST_DCN2_0(id),\
+ }
+
+static const struct dcn20_dwbc_registers dwbc20_regs[] = {
+ dwbc_regs_dcn2(0),
+};
+
+static const struct dcn20_dwbc_shift dwbc20_shift = {
+ DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
+};
+
+static const struct dcn20_dwbc_mask dwbc20_mask = {
+ DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
+};
+
+#define mcif_wb_regs_dcn2(id)\
+[id] = {\
+ MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
+ }
+
+static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
+ mcif_wb_regs_dcn2(0),
+};
+
+static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
+ MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
+};
+
+static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
+ MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
+};
+
static const struct dcn20_mpc_registers mpc_regs = {
MPC_REG_LIST_DCN2_0(0),
MPC_REG_LIST_DCN2_0(1),
@@ -1088,6 +1125,17 @@ static void destruct(struct dcn20_resource_pool *pool)
}
}
+ for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ if (pool->base.dwbc[i] != NULL) {
+ kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
+ pool->base.dwbc[i] = NULL;
+ }
+ if (pool->base.mcif_wb[i] != NULL) {
+ kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
+ pool->base.mcif_wb[i] = NULL;
+ }
+ }
+
for (i = 0; i < pool->base.audio_count; i++) {
if (pool->base.audios[i])
dce_aud_destroy(>base.audios[i]);
@@ -2384,6 +2432,58 @@ static struct resource_funcs dcn20_res_pool_funcs = {
#endif
};
+bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+ int i;
+ uint32_t pipe_count = pool->res_cap->num_dwb;
+
+ ASSERT(pipe_count > 0);
+
+ for (i = 0; i < pipe_count; i++) {
+ struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
+ GFP_KERNEL);
+
+ if (!dwbc20) {
+ dm_error("DC: failed to create dwbc20!\n");
+ return false;
+ }
+ dcn20_dwbc_construct(dwbc20, ctx,
+ _regs[i],
+ _shift,
+ _mask,
+ i);
+ pool->dwbc[i] = >base;
+ }
+ return true;
+}
+
+bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+ int i;
+ uint32_t pipe_count = pool->res_cap->num_dwb;
+
+ ASSERT(pipe_count > 0);
+
+ for (i = 0; i < pipe_count; i++) {
+ struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct
dcn20_mmhubbub),
+ GFP_KERNEL);
+
+ if (!mcif_wb20) {
+ dm_error("DC: failed to create mcif_wb20!\n");
+ return false;
+ }
+
+ dcn20_mmhubbub_construct(mcif_wb20, ctx,
+ _wb20_regs[i],
+ _wb20_shift,
+
[PATCH 406/459] drm/amd/display: add SW_USE_I2C_REG request.
From: Charlene Liu [Description] This is for DC_I2c arbitration use between HW use/SW use and DMCU use. Signed-off-by: Charlene Liu Reviewed-by: Krunoslav Kovac Reviewed-by: Tony Cheng Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c index d658b862430a..b2786a704708 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c @@ -306,6 +306,8 @@ static bool setup_engine( #if defined(CONFIG_DRM_AMD_DC_DCN2_0) uint32_t reset_length = 0; #endif + /* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/ + REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1); /* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/ REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1); -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 418/459] drm/amd/display: fix macro_tile_size for tiling
From: Dmytro Laktyushkin A regression was introduced when we set correct tile size for the gfx9 swizzle mode. This resulted in incorrect macro tile size. Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index 1daf4029b566..0bd0b5279c18 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -1753,8 +1753,6 @@ int dcn20_populate_dml_pipes_from_context( struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state; struct scaler_data *scl = _ctx->pipe_ctx[i].plane_res.scl_data; - pipes[pipe_cnt].pipe.src.macro_tile_size = - swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate; pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) @@ -1818,6 +1816,8 @@ int dcn20_populate_dml_pipes_from_context( pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps; pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c; + pipes[pipe_cnt].pipe.src.macro_tile_size = + swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, [pipe_cnt].pipe.src.sw_mode); -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 438/459] drm/amd/display: removing MODULO change for dcn2
From: Martin Leung
[why]
when resetting pipes from 480p to dual-pipe 8k, modulo reg write for
video optimized rate updated one pipe without changing the other, causing
sync error
[how]
removed code from dcn2
Signed-off-by: Martin Leung
Reviewed-by: Jun Lei
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
.../drm/amd/display/dc/dce/dce_clock_source.c | 28 ---
1 file changed, 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index bf8cfd9b3e8f..c72aed35f4db 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -1046,41 +1046,13 @@ static const struct pixel_rate_range_table_entry
video_optimized_pixel_rates[] =
{108100, 108110, 108000, 1001, 1000},//108Mhz
};
-static const struct pixel_rate_range_table_entry
*look_up_in_video_optimized_rate_tlb(
- unsigned int pixel_rate_khz)
-{
- int i;
-
- for (i = 0; i < NUM_ELEMENTS(video_optimized_pixel_rates); i++) {
- const struct pixel_rate_range_table_entry *e =
_optimized_pixel_rates[i];
-
- if (e->range_min_khz <= pixel_rate_khz && pixel_rate_khz <=
e->range_max_khz) {
- return e;
- }
- }
-
- return NULL;
-}
-
static bool dcn20_program_pix_clk(
struct clock_source *clock_source,
struct pixel_clk_params *pix_clk_params,
struct pll_settings *pll_settings)
{
- struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
- unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
- unsigned int dp_dto_ref_khz =
clock_source->ctx->dc->clk_mgr->dprefclk_khz;
- const struct pixel_rate_range_table_entry *e =
-
look_up_in_video_optimized_rate_tlb(pll_settings->actual_pix_clk_100hz / 10);
-
dce112_program_pix_clk(clock_source, pix_clk_params, pll_settings);
- if (e) {
- /* Set DTO values: phase = target clock, modulo = reference
clock */
- REG_WRITE(PHASE[inst], e->target_pixel_rate_khz *
e->mult_factor);
- REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
- }
-
return true;
}
--
2.20.1
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[PATCH 400/459] drm/amd/display: Fix ODM combine data format
From: Ilya Bakoulin
[Why]
OPTC data format was left at its default value (444) when enabling
ODM combine. This caused issues with FPGA capture.
[How]
Write the OPTC_DATA_FORMAT field when enabling ODM combine.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Eric Bernstein
Acked-by: Leo Li
Acked-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c| 6 --
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 11 ++-
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h | 4 +++-
.../gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 3 ++-
5 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index cd9b662fbea9..02599eb92ca6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -463,6 +463,7 @@ struct dcn_optc_registers {
type OPTC_SEG0_SRC_SEL;\
type OPTC_SEG1_SRC_SEL;\
type OPTC_MEM_SEL;\
+ type OPTC_DATA_FORMAT;\
type OPTC_DSC_MODE;\
type OPTC_DSC_BYTES_PER_PIXEL;\
type OPTC_DSC_SLICE_WIDTH;\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index fbcb4d860e7a..2ea72e965c1b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -703,7 +703,8 @@ enum dc_status dcn20_enable_stream_timing(
pipe_ctx->stream_res.tg->funcs->set_odm_combine(
pipe_ctx->stream_res.tg,
odm_pipe->stream_res.opp->inst,
- pipe_ctx->stream->timing.h_addressable/2);
+ pipe_ctx->stream->timing.h_addressable/2,
+ pipe_ctx->stream->timing.pixel_encoding);
/* HW program guide assume display already disable
* by unplug sequence. OTG assume stop.
*/
@@ -1007,7 +1008,8 @@ static void dcn20_update_odm(struct dc *dc, struct
dc_state *context, struct pip
pipe_ctx->stream_res.tg->funcs->set_odm_combine(
pipe_ctx->stream_res.tg,
combine_pipe->stream_res.opp->inst,
- pipe_ctx->plane_res.scl_data.h_active);
+ pipe_ctx->plane_res.scl_data.h_active,
+ pipe_ctx->stream->timing.pixel_encoding);
else
pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
pipe_ctx->stream_res.tg,
_ctx->stream->timing);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index ea6a19063b22..d0b317ea3a7c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -238,11 +238,13 @@ void optc2_set_odm_bypass(struct timing_generator *optc,
OPTC_MEM_SEL, 0);
}
-void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id,
int mpcc_hactive)
+void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id,
+ int mpcc_hactive, enum dc_pixel_encoding pixel_encoding)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
/* 2 pieces of memory required for up to 5120 displays, 4 for up to
8192 */
int memory_mask = mpcc_hactive <= 2560 ? 0x3 : 0xf;
+ uint32_t data_fmt = 0;
/* TODO: In pseudocode but does not affect maximus, delete comment if
we dont need on asic
* REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
@@ -255,6 +257,13 @@ void optc2_set_odm_combine(struct timing_generator *optc,
int combine_opp_id, in
REG_SET(OPTC_MEMORY_CONFIG, 0,
OPTC_MEM_SEL, memory_mask << (optc->inst * 4));
+ if (pixel_encoding == PIXEL_ENCODING_YCBCR422)
+ data_fmt = 1;
+ else if (pixel_encoding == PIXEL_ENCODING_YCBCR420)
+ data_fmt = 2;
+
+ REG_SET(OPTC_DATA_FORMAT_CONTROL, 0, OPTC_DATA_FORMAT, data_fmt);
+
REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
OPTC_NUM_OF_INPUT_SEGMENT, 1,
OPTC_SEG0_SRC_SEL, optc->inst,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
index a21781332a06..ebf07c582da2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
@@ -66,6 +66,7 @@
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
+
[PATCH 409/459] drm/amd/display: block passive dongle EDID Emulation for USB-C ports
From: Samson Tam
[Why]
Emulating passive dongle on USB-C port causes issue on some asics.
[How]
Check for DP_IS_USB_C flag in bios parser and propagate it to
encoder features flags. If DP_IS_USB_C flag is set and it is trying to
emulate passive dongle, then return fail.
Signed-off-by: Samson Tam
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
index 6f7af235dd79..b04ef576ec5a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
@@ -447,6 +447,8 @@ void dcn20_link_encoder_construct(
enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
bp_cap_info.DP_HBR3_EN;
enc10->base.features.flags.bits.HDMI_6GB_EN =
bp_cap_info.HDMI_6GB_EN;
+ enc10->base.features.flags.bits.DP_IS_USB_C =
+ bp_cap_info.DP_IS_USB_C;
} else {
DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS
with error code %d!\n",
__func__,
--
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[PATCH 412/459] drm/amd/display: Add support for extended DSC DPCD caps
From: Nikola Cornij
[why]
A few of the new DSC DPCD caps were introduced by a DP 1.4a SCR in order
to give DSC branch decoders a chance to expose their maximum throughput
and maximum line width limitations.
Signed-off-by: Nikola Cornij
Reviewed-by: Wenjing Liu
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 50 +++---
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 3 +-
drivers/gpu/drm/amd/display/dc/dc_types.h | 5 +
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 118
.../drm/amd/display/include/dpcd_structs.h| 168 ++
include/drm/drm_dp_helper.h | 5 +
6 files changed, 289 insertions(+), 60 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/include/dpcd_structs.h
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index effc36745671..017f88c9f2e4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2383,8 +2383,8 @@ static bool retrieve_link_cap(struct dc_link *link)
int i;
struct dp_sink_hw_fw_revision dp_hw_fw_revision;
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
- uint8_t dsc_data[16];
- struct dsc_dec_dpcd_caps *dsc_caps;
+ uint8_t dsc_data[16]; /* DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1
== 16 */
+ struct dsc_dec_dpcd_caps *dsc_dec_caps;
#endif
memset(dpcd_data, '\0', sizeof(dpcd_data));
@@ -2558,8 +2558,8 @@ static bool retrieve_link_cap(struct dc_link *link)
sizeof(dp_hw_fw_revision.ieee_fw_rev));
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
- dsc_caps = >dpcd_caps.dsc_sink_caps;
- memset(dsc_caps, '\0', sizeof(*dsc_caps));
+ dsc_dec_caps = >dpcd_caps.dsc_sink_caps;
+ memset(dsc_dec_caps, '\0', sizeof(*dsc_dec_caps));
memset(>dpcd_caps.dsc_sink_caps, '\0',
sizeof(link->dpcd_caps.dsc_sink_caps));
memset(>dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
@@ -2571,7 +2571,7 @@ static bool retrieve_link_cap(struct dc_link *link)
dsc_data,
sizeof(dsc_data));
if (status == DC_OK) {
- DC_LOG_DSC("DSC capability read at link %d:",
+ DC_LOG_DSC("DSC DPCD capability read at link %d:",
link->link_index);
DC_LOG_DSC("\t%02x %02x %02x %02x",
dsc_data[0], dsc_data[1],
@@ -2590,37 +2590,43 @@ static bool retrieve_link_cap(struct dc_link *link)
return false;
}
- if (dc_dsc_parse_dsc_dpcd(dsc_data,
- dsc_caps)) {
- DC_LOG_DSC("DSC capability parsed at link %d:",
+ if (dc_dsc_parse_dsc_dpcd(dsc_data, NULL,
+ dsc_dec_caps)) {
+ DC_LOG_DSC("DSC DPCD capabilities parsed at link %d:",
link->link_index);
DC_LOG_DSC("\tis_dsc_supported:\t%d",
- dsc_caps->is_dsc_supported);
- DC_LOG_DSC("\tdsc_version:\t%d", dsc_caps->dsc_version);
+ dsc_dec_caps->is_dsc_supported);
+ DC_LOG_DSC("\tdsc_version:\t%d",
dsc_dec_caps->dsc_version);
DC_LOG_DSC("\trc_buffer_size:\t%d",
- dsc_caps->rc_buffer_size);
+ dsc_dec_caps->rc_buffer_size);
DC_LOG_DSC("\tslice_caps1:\t0x%x20",
- dsc_caps->slice_caps1.raw);
+ dsc_dec_caps->slice_caps1.raw);
DC_LOG_DSC("\tslice_caps2:\t0x%x20",
- dsc_caps->slice_caps2.raw);
+ dsc_dec_caps->slice_caps2.raw);
DC_LOG_DSC("\tlb_bit_depth:\t%d",
- dsc_caps->lb_bit_depth);
+ dsc_dec_caps->lb_bit_depth);
DC_LOG_DSC("\tis_block_pred_supported:\t%d",
- dsc_caps->is_block_pred_supported);
+ dsc_dec_caps->is_block_pred_supported);
DC_LOG_DSC("\tedp_max_bits_per_pixel:\t%d",
- dsc_caps->edp_max_bits_per_pixel);
+ dsc_dec_caps->edp_max_bits_per_pixel);
DC_LOG_DSC("\tcolor_formats:\t%d",
- dsc_caps->color_formats.raw);
+ dsc_dec_caps->color_formats.raw);
[PATCH 404/459] drm/amd/display: Change DCN2 vupdate start programming
From: Eryk Brol
[Why]
In order to ensure that incoming flips are latched and
complete immediately, we need to program the vupdate
interrupt to come during the back porch of each frame.
[How]
Program the vupdate start_line to be in the back porch
like it's done for DCN1.
Signed-off-by: Eryk Brol
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index e7580e6e0fb6..f9eae47f7be3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1704,13 +1704,10 @@ void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
void dcn20_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx)
{
struct timing_generator *tg = pipe_ctx->stream_res.tg;
- int start_position = get_vupdate_offset_from_vsync(pipe_ctx);
- uint32_t start_line;
+ int start_line = get_vupdate_offset_from_vsync(pipe_ctx);
- if (start_position < 0)
- start_line = pipe_ctx->stream->timing.v_total + start_position
- 1;
- else
- start_line = start_position;
+ if (start_line < 0)
+ start_line = 0;
if (tg->funcs->setup_vertical_interrupt2)
tg->funcs->setup_vertical_interrupt2(tg, start_line);
--
2.20.1
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[PATCH 426/459] drm/amd/display: add null checks and set update flags for DCN2
From: Dmytro Laktyushkin
* add plane state null checks
* add and set update surface flags
*
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 8 +++-
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h | 14 +++---
.../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 1 -
4 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 867a84c2bfbf..8bf3433af3f8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1427,6 +1427,9 @@ static enum surface_update_type det_surface_update(const
struct dc *dc,
update_flags->raw = 0; // Reset all flags
+ if (u->flip_addr)
+ update_flags->bits.addr_update = 1;
+
if (!is_surface_in_context(context, u->surface)) {
update_flags->bits.new_plane = 1;
return UPDATE_TYPE_FULL;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index ea56f15a51fb..f9b0ea75eeb4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -492,7 +492,7 @@ static void dcn20_plane_atomic_disable(struct dc *dc,
struct pipe_ctx *pipe_ctx)
}
-static void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
+void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
{
DC_LOGGER_INIT(dc->ctx->logger);
@@ -501,8 +501,6 @@ static void dcn20_disable_plane(struct dc *dc, struct
pipe_ctx *pipe_ctx)
dcn20_plane_atomic_disable(dc, pipe_ctx);
- //apply_DEGVIDCN10_253_wa(dc);
-
DC_LOG_DC("Power down front end %d\n",
pipe_ctx->pipe_idx);
}
@@ -1092,7 +1090,7 @@ static void dcn20_power_on_plane(
}
}
-static void dcn20_enable_plane(
+void dcn20_enable_plane(
struct dc *dc,
struct pipe_ctx *pipe_ctx,
struct dc_state *context)
@@ -1167,7 +1165,7 @@ static void dcn20_enable_plane(
}
-void dcn20_program_pipe(
+static void dcn20_program_pipe(
struct dc *dc,
struct pipe_ctx *pipe_ctx,
struct dc_state *context)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
index 78a6477deffb..2b0409454073 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
@@ -89,7 +89,15 @@ void dcn20_pipe_control_lock_global(
struct pipe_ctx *pipe,
bool lock);
void dcn20_setup_gsl_group_as_lock(const struct dc *dc,
- struct pipe_ctx *pipe_ctx,
- bool enable);
-
+ struct pipe_ctx *pipe_ctx,
+ bool enable);
+void dcn20_pipe_control_lock(
+ struct dc *dc,
+ struct pipe_ctx *pipe,
+ bool lock);
+void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
+void dcn20_enable_plane(
+ struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ struct dc_state *context);
#endif /* __DC_HWSS_DCN20_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index ca5a7791d080..e7a8a13a9d33 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2340,7 +2340,6 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct
dc_state *context,
context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(>bw_ctx.dml,
>res_ctx.pipe_ctx[i].rq_regs,
pipes[pipe_idx].pipe);
-
pipe_idx++;
}
--
2.20.1
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[PATCH 415/459] drm/amd/display: [backport] dwb dm + efc support
From: Charlene Liu
Signed-off-by: Charlene Liu
Reviewed-by: Duke Du
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c | 25 ---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.h| 4 +++
drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 7 ++
.../drm/amd/display/include/logger_types.h| 1 +
4 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
index 14bdb63950af..8d3884b306dd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
@@ -36,6 +36,8 @@
#define CTX \
dwbc20->base.ctx
+#define DC_LOGGER \
+ dwbc20->base.ctx->logger
#undef FN
#define FN(reg_name, field_name) \
dwbc20->dwbc_shift->field_name, dwbc20->dwbc_mask->field_name
@@ -47,6 +49,7 @@ enum dwb_outside_pix_strategy {
static bool dwb2_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
{
+ struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
if (caps) {
caps->adapter_id = 0; /* we only support 1 adapter currently
*/
caps->hw_version = DCN_VERSION_2_0;
@@ -58,8 +61,10 @@ static bool dwb2_get_caps(struct dwbc *dwbc, struct dwb_caps
*caps)
caps->caps.support_ogam = false;
caps->caps.support_wbscl = false;
caps->caps.support_ocsc = false;
+ DC_LOG_DWB("%s SUPPORTED! inst = %d", __func__,
dwbc20->base.inst);
return true;
} else {
+ DC_LOG_DWB("%s NOT SUPPORTED! inst = %d", __func__,
dwbc20->base.inst);
return false;
}
}
@@ -67,6 +72,7 @@ static bool dwb2_get_caps(struct dwbc *dwbc, struct dwb_caps
*caps)
void dwb2_config_dwb_cnv(struct dwbc *dwbc, struct dc_dwb_params *params)
{
struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+ DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst);
/* Set DWB source size */
REG_UPDATE_2(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH,
params->cnv_params.src_width,
@@ -95,10 +101,13 @@ static bool dwb2_enable(struct dwbc *dwbc, struct
dc_dwb_params *params)
struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
/* Only chroma scaling (sub-sampling) is supported in DCN2 */
- if ((params->cnv_params.src_width != params->dest_width)
-|| (params->cnv_params.src_height != params->dest_height)) {
+if ((params->cnv_params.src_width != params->dest_width) ||
+ (params->cnv_params.src_height != params->dest_height)) {
+
+ DC_LOG_DWB("%s inst = %d, FAILED!LUMA SCALING NOT SUPPORTED",
__func__, dwbc20->base.inst);
return false;
}
+ DC_LOG_DWB("%s inst = %d, ENABLED", __func__, dwbc20->base.inst);
/* disable power gating */
//REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 1,
@@ -126,6 +135,7 @@ static bool dwb2_enable(struct dwbc *dwbc, struct
dc_dwb_params *params)
bool dwb2_disable(struct dwbc *dwbc)
{
struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+ DC_LOG_DWB("%s inst = %d, Disabled", __func__, dwbc20->base.inst);
/* disable CNV */
REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_DISABLE);
@@ -151,10 +161,12 @@ static bool dwb2_update(struct dwbc *dwbc, struct
dc_dwb_params *params)
unsigned int pre_locked;
/* Only chroma scaling (sub-sampling) is supported in DCN2 */
- if ((params->cnv_params.src_width != params->dest_width)
- || (params->cnv_params.src_height !=
params->dest_height)) {
+ if ((params->cnv_params.src_width != params->dest_width) ||
+ (params->cnv_params.src_height != params->dest_height))
{
+ DC_LOG_DWB("%s inst = %d, FAILED!LUMA SCALING NOT SUPPORTED",
__func__, dwbc20->base.inst);
return false;
}
+ DC_LOG_DWB("%s inst = %d, scaling", __func__, dwbc20->base.inst);
/*
* Check if the caller has already locked CNV registers.
@@ -199,6 +211,8 @@ void dwb2_set_stereo(struct dwbc *dwbc,
struct dwb_stereo_params *stereo_params)
{
struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+ DC_LOG_DWB("%s inst = %d, enabled =%d", __func__,\
+ dwbc20->base.inst, stereo_params->stereo_enabled);
if (stereo_params->stereo_enabled) {
REG_UPDATE(CNV_MODE, CNV_STEREO_TYPE,
stereo_params->stereo_type);
@@ -213,6 +227,7 @@ void dwb2_set_new_content(struct dwbc *dwbc,
bool is_new_content)
{
struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
+ DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst);
REG_UPDATE(CNV_MODE, CNV_NEW_CONTENT, is_new_content);
}
@@ -221,6 +236,7 @@ static void dwb2_set_warmup(struct dwbc *dwbc,
[PATCH 445/459] drm/amd/display: making DCN20 WM table non-overlapping
From: Jun Lei
[why]
Existing behavior has overlapping ranges resulting in path
dependent SMU selection
[how]
Make ranges non-overlapping, resulting in non-path dependent
selection
Signed-off-by: Jun Lei
Reviewed-by: Eric Yang
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 310687ec166e..36bf14332bf5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2635,7 +2635,8 @@ static void update_bounding_box(struct dc *dc, struct
_vcs_dpi_soc_bounding_box_
calculated_states[i].state = i;
calculated_states[i].dram_speed_mts = uclk_states[i] * 16 /
1000;
- min_fclk_required_by_uclk = ((unsigned long
long)uclk_states[i]) * 1008 / 100;
+ // FCLK:UCLK ratio is 1.08
+ min_fclk_required_by_uclk = ((unsigned long
long)uclk_states[i]) * 1080 / 100;
calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk
< min_dcfclk) ?
min_dcfclk : min_fclk_required_by_uclk;
@@ -2989,21 +2990,19 @@ static bool construct(
ranges.num_reader_wm_sets = 1;
} else if (dcn2_0_soc.num_states > 1) {
- for (i = 0; i < 4 && i < dcn2_0_soc.num_states - 1;
i++) {
+ for (i = 0; i < 4 && i < dcn2_0_soc.num_states; i++) {
ranges.reader_wm_sets[i].wm_inst = i;
ranges.reader_wm_sets[i].min_drain_clk_mhz =
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
ranges.reader_wm_sets[i].max_drain_clk_mhz =
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
- ranges.reader_wm_sets[i].min_fill_clk_mhz =
dcn2_0_soc.clock_limits[i].dram_speed_mts / 16;
- ranges.reader_wm_sets[i].max_fill_clk_mhz =
dcn2_0_soc.clock_limits[i + 1].dram_speed_mts / 16;
+ ranges.reader_wm_sets[i].min_fill_clk_mhz = (i
> 0) ? (dcn2_0_soc.clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
+ ranges.reader_wm_sets[i].max_fill_clk_mhz =
dcn2_0_soc.clock_limits[i].dram_speed_mts / 16;
ranges.num_reader_wm_sets = i + 1;
}
- }
- ranges.reader_wm_sets[0].min_drain_clk_mhz =
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
- ranges.reader_wm_sets[0].min_fill_clk_mhz =
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
- ranges.reader_wm_sets[ranges.num_reader_wm_sets -
1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
- ranges.reader_wm_sets[ranges.num_reader_wm_sets -
1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+ ranges.reader_wm_sets[0].min_fill_clk_mhz =
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+ ranges.reader_wm_sets[ranges.num_reader_wm_sets -
1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+ }
ranges.num_writer_wm_sets = 1;
--
2.20.1
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[PATCH 431/459] drm/amd/display: always use 4 dp lanes for dml
From: Jun Lei
[why]
current DML logic uses currently trained setting for number
of dp lanes in DML calculations. this is obviously flawed since
just because 1 lane is in use doesn't mean only 1 lane can be used
this causes mode validation to fail depending on current state,
which is incorrect
[how]
DML should always assume 4 lanes are available. validation of
bandwidth is not supposed to be handled by DML, since we do
link validation without DML already
also, DML is expecting there to be a copy of the max state, this
state is removed when update_bounding_box is called to update
actual SKU clocks. fix this as well by duping last state.
Signed-off-by: Jun Lei
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
Acked-by: Eric Yang
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c| 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index caebf4746475..266d2ea50882 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1619,7 +1619,6 @@ int dcn20_populate_dml_pipes_from_context(
for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
struct dc_crtc_timing *timing =
_ctx->pipe_ctx[i].stream->timing;
- struct dc_link *link;
if (!res_ctx->pipe_ctx[i].stream)
continue;
@@ -1665,16 +1664,7 @@ int dcn20_populate_dml_pipes_from_context(
if (timing->timing_3d_format ==
TIMING_3D_FORMAT_HW_FRAME_PACKING)
pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
pipes[pipe_cnt].pipe.dest.otg_inst =
res_ctx->pipe_ctx[i].stream_res.tg->inst;
-
- link = res_ctx->pipe_ctx[i].stream->link;
- if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) {
- pipes[pipe_cnt].dout.dp_lanes =
link->cur_link_settings.lane_count;
- } else if (link->verified_link_cap.lane_count !=
LANE_COUNT_UNKNOWN) {
- pipes[pipe_cnt].dout.dp_lanes =
link->verified_link_cap.lane_count;
- } else {
- /* Unknown link capabilities, so assume max */
- pipes[pipe_cnt].dout.dp_lanes = 4;
- }
+ pipes[pipe_cnt].dout.dp_lanes = 4;
pipes[pipe_cnt].pipe.dest.vtotal_min =
res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
pipes[pipe_cnt].pipe.dest.vtotal_max =
res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
--
2.20.1
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[PATCH 428/459] drm/amd/display: Disable DSC power gating in Diags
From: Nikola Cornij
[why]
With DSC power gating enabled, one of the register reads times out occasionally,
causing a DSC test to fail.
[how]
Disable DSC power gating in Diags.
NOTE: This has to be reverted once the problems with DSC power gating are
resolved.
Signed-off-by: Nikola Cornij
Reviewed-by: Nevenko Stupar
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index e7a8a13a9d33..ac65794c7fa6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -723,6 +723,9 @@ static const struct dc_debug_options debug_defaults_diags =
{
.disable_pplib_wm_range = true,
.disable_stutter = true,
.scl_reset_length10 = true,
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ .disable_dsc_power_gate = true,
+#endif
};
void dcn20_dpp_destroy(struct dpp **dpp)
--
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[PATCH 402/459] drm/amd/display: fix dcn2 mpc split decision
From: Dmytro Laktyushkin
The split condition is broken and will always activate
at the moment.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Jun Lei
Acked-by: Leo Li
Acked-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 0a11d1098a7e..ceee0d6b3c26 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2103,7 +2103,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct
dc_state *context,
vlevel = vlevel_unsplit;
context->bw_ctx.dml.vba.maxMpcComb = 0;
} else
- need_split =
context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
+ need_split =
context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]
== 2;
if (need_split3d || need_split || force_split) {
if (!hsplit_pipe || hsplit_pipe->plane_state !=
pipe->plane_state) {
--
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[PATCH 407/459] drm/amd/display: Add 170Mpix/sec DSC throughput support
From: Nikola Cornij
[why]
It was missing, although defined in DP spec
[how]
- Add handling of this value to DSC code
- Also remove unused file dsc_helpers.c
Signed-off-by: Nikola Cornij
Reviewed-by: Joshua Aberback
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 10 +-
.../gpu/drm/amd/display/dc/dsc/dsc_helpers.c | 243 --
include/drm/drm_dp_helper.h | 4 +
3 files changed, 12 insertions(+), 245 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/display/dc/dsc/dsc_helpers.c
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index d58d718171b5..f09f23707a94 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -74,6 +74,12 @@ static bool dsc_line_buff_depth_from_dpcd(int
dpcd_line_buff_bit_depth, int *lin
static bool dsc_throughput_from_dpcd(int dpcd_throughput, int *throughput)
{
switch (dpcd_throughput) {
+ case DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED:
+ *throughput = 0;
+ break;
+ case DP_DSC_THROUGHPUT_MODE_0_170:
+ *throughput = 170;
+ break;
case DP_DSC_THROUGHPUT_MODE_0_340:
*throughput = 340;
break;
@@ -170,7 +176,7 @@ static void get_dsc_enc_caps(
/* Returns 'false' if no intersection was found for at least one capablity.
* It also implicitly validates some sink caps against invalid value of zero.
*/
-static bool dc_intersect_dsc_caps(
+static bool intersect_dsc_caps(
const struct dsc_dec_dpcd_caps *dsc_sink_caps,
const struct dsc_enc_caps *dsc_enc_caps,
enum dc_pixel_encoding pixel_encoding,
@@ -537,7 +543,7 @@ static bool setup_dsc_config(
goto done;
// Intersect decoder with encoder DSC caps and validate DSC settings
- is_dsc_possible = dc_intersect_dsc_caps(dsc_sink_caps, dsc_enc_caps,
timing->pixel_encoding, _common_caps);
+ is_dsc_possible = intersect_dsc_caps(dsc_sink_caps, dsc_enc_caps,
timing->pixel_encoding, _common_caps);
if (!is_dsc_possible)
goto done;
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dsc_helpers.c
b/drivers/gpu/drm/amd/display/dc/dsc/dsc_helpers.c
deleted file mode 100644
index 0ecd5065d120..
--- a/drivers/gpu/drm/amd/display/dc/dsc/dsc_helpers.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * Copyright 2018 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-
-#include "dc.h"
-#include "dsc.h"
-#include "dc_hw_types.h"
-#include
-
-#define DC_LOGGER \
- dsc->ctx->logger
-
-static bool dsc_buff_block_size_from_dpcd(int dpcd_buff_block_size, int
*buff_block_size);
-static bool dsc_line_buff_depth_from_dpcd(int dpcd_line_buff_bit_depth, int
*line_buff_bit_depth);
-static bool dsc_throughput_from_dpcd(int dpcd_throughput, int *throughput);
-static bool dsc_bpp_increment_div_from_dpcd(int bpp_increment_dpcd, uint32_t
*bpp_increment_div);
-
-void dsc_optc_config_log(struct display_stream_compressor *dsc,
- struct dsc_optc_config *config)
-{
- DC_LOG_DSC("Setting optc DSC config at DSC inst %d", dsc->inst);
- DC_LOG_DSC("\n\tbytes_per_pixel %d\n\tis_pixel_format_444
%d\n\tslice_width %d",
- config->bytes_per_pixel,
- config->is_pixel_format_444, config->slice_width);
-}
-
-void dsc_config_log(struct display_stream_compressor *dsc,
- const struct dsc_config *config)
-{
- DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
- DC_LOG_DSC("\n\tnum_slices_h %d\n\tnum_slices_v %d\n\tbits_per_pixel
%d\n\tcolor_depth %d",
- config->dc_dsc_cfg.num_slices_h,
- config->dc_dsc_cfg.num_slices_v,
-
[PATCH 401/459] drm/amd/display: Add hubp_init entry to hubp vtable
From: Charlene Liu
Different HW will need to init HUBP differently. For now, add a vtable
entry, and hook a NO-OP for DCN1 and DCN2.
In addition, future HW will need to access the HUBPREQ_DEBUG and
CUR_TTU_CNTL0 register for hubp_init. Add that here.
Signed-off-by: Charlene Liu
Reviewed-by: Jun Lei
Acked-by: Leo Li
Acked-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 4 +++-
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 2 ++
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 --
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 4 ++--
4 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
index 529bdc2f2975..82738f126517 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
@@ -675,9 +675,11 @@ static struct hubp_funcs dcn20_hubp_funcs = {
.dmdata_status_done = hubp2_dmdata_status_done,
.hubp_read_state = hubp1_read_state,
.hubp_clear_underflow = hubp1_clear_underflow,
- .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl
+ .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
+ .hubp_init = hubp1_init,
};
+
bool hubp2_construct(
struct dcn20_hubp *hubp2,
struct dc_context *ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
index 9f56c1d2d188..f790ab9db6eb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
@@ -62,6 +62,7 @@
SRI(FLIP_PARAMETERS_0, HUBPREQ, id),\
SRI(FLIP_PARAMETERS_1, HUBPREQ, id),\
SRI(FLIP_PARAMETERS_2, HUBPREQ, id),\
+ SRI(DCN_CUR1_TTU_CNTL0, HUBPREQ, id),\
SRI(DCN_CUR1_TTU_CNTL1, HUBPREQ, id),\
SRI(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \
SRI(VMID_SETTINGS_0, HUBPREQ, id)
@@ -146,6 +147,7 @@
uint32_t FLIP_PARAMETERS_0;\
uint32_t FLIP_PARAMETERS_1;\
uint32_t FLIP_PARAMETERS_2;\
+ uint32_t DCN_CUR1_TTU_CNTL0;\
uint32_t DCN_CUR1_TTU_CNTL1;\
uint32_t VMID_SETTINGS_0;\
uint32_t FLIP_PARAMETERS_3;\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 2ea72e965c1b..e7580e6e0fb6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -601,6 +601,8 @@ static void dcn20_init_hw(struct dc *dc)
hubp->power_gated = false;
pipe_ctx->stream_res.opp = NULL;
+ hubp->funcs->hubp_init(hubp);
+
//dc->res_pool->opps[i]->mpc_tree_params.opp_id =
dc->res_pool->opps[i]->inst;
//dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] =
true;
@@ -1224,7 +1226,7 @@ static void dcn20_program_all_pipe_in_tree(
dcn20_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe,
context);
}
-static void dcn20_pipe_control_lock_global(
+void dcn20_pipe_control_lock_global(
struct dc *dc,
struct pipe_ctx *pipe,
bool lock)
@@ -1244,7 +1246,7 @@ static void dcn20_pipe_control_lock_global(
}
}
-static void dcn20_pipe_control_lock(
+void dcn20_pipe_control_lock(
struct dc *dc,
struct pipe_ctx *pipe,
bool lock)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index e7a21fc9845b..fa98c96d0046 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -145,11 +145,11 @@ struct hubp_funcs {
uint32_t dmdata_sw_size,
const uint32_t *dmdata_sw_data);
bool (*dmdata_status_done)(struct hubp *hubp);
- void(*hubp_enable_tripleBuffer)(
+ void (*hubp_enable_tripleBuffer)(
struct hubp *hubp,
bool enable);
- bool(*hubp_is_triplebuffer_enabled)(
+ bool (*hubp_is_triplebuffer_enabled)(
struct hubp *hubp);
void (*hubp_set_flip_control_surface_gsl)(
--
2.20.1
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[PATCH 403/459] drm/amd/display: Refactor program watermark.
From: Yongqiang Sun
Refactor programming watermark function:
Divided into urgent watermark, stutter watermark and pstate watermark.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h | 4
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
index b3a99b10cfbd..d6705b40a57c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
@@ -294,7 +294,7 @@ bool hubbub2_get_dcc_compression_cap(struct hubbub *hubbub,
return true;
}
-static void hubbub2_setup_vmid_ptb(struct hubbub *hubbub,
+void hubbub2_setup_vmid_ptb(struct hubbub *hubbub,
uint64_t ptb,
uint8_t vmid)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
index cdd19f5887d7..6ca4a5a9f8c7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
@@ -102,4 +102,8 @@ void hubbub2_get_dchub_ref_freq(struct hubbub *hubbub,
void hubbub2_wm_read_state(struct hubbub *hubbub,
struct dcn_hubbub_wm *wm);
+void hubbub2_setup_vmid_ptb(struct hubbub *hubbub,
+ uint64_t ptb,
+ uint8_t vmid);
+
#endif
--
2.20.1
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[PATCH 430/459] drm/amd/display: Use DCN2 functions instead of DCE
From: Wesley Chalmers
[WHY]
DCN code should make as few references to DCE as possible
[HOW]
Copy DCE110 implementation of find_first_free_match_stream_enc_for_link
into DCN10
Signed-off-by: Wesley Chalmers
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 8b4853dd4fd4..caebf4746475 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -40,6 +40,7 @@
#include "dcn20_optc.h"
#include "dcn20_hwseq.h"
#include "dce110/dce110_hw_sequencer.h"
+#include "dcn10/dcn10_resource.h"
#include "dcn20_opp.h"
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
@@ -2448,7 +2449,7 @@ static struct resource_funcs dcn20_res_pool_funcs = {
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
.remove_dsc_from_stream_resource =
dcn20_remove_dsc_from_stream_resource,
#endif
- .find_first_free_match_stream_enc_for_link =
dce110_find_first_free_match_stream_enc_for_link
+ .find_first_free_match_stream_enc_for_link =
dcn10_find_first_free_match_stream_enc_for_link
};
bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
--
2.20.1
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[PATCH 405/459] drm/amd/display: Make sure line size is not zero in DCN2 line buffer size calculations
From: Nikola Cornij
[why]
'Divide by zero' error happens when line size happens to be zero.
[how]
The code that makes sure line size minimum value can be 1 was already
present in DCN1 part of the driver, this is mearly a port to DCN2.
Signed-off-by: Nikola Cornij
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c| 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
index b706190e16c1..9bc5dd23d297 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
@@ -251,14 +251,23 @@ void dscl2_calc_lb_num_partitions(
int *num_part_y,
int *num_part_c)
{
+ int memory_line_size_y, memory_line_size_c, memory_line_size_a,
+ lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a;
+
int line_size = scl_data->viewport.width < scl_data->recout.width ?
scl_data->viewport.width : scl_data->recout.width;
int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
scl_data->viewport_c.width : scl_data->recout.width;
- int memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */
- int memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */
- int memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
- int lb_memory_size, lb_memory_size_c, lb_memory_size_a,
num_partitions_a;
+
+ if (line_size == 0)
+ line_size = 1;
+
+ if (line_size_c == 0)
+ line_size_c = 1;
+
+ memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */
+ memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */
+ memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
if (lb_config == LB_MEMORY_CONFIG_1) {
lb_memory_size = 970;
--
2.20.1
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[PATCH 434/459] drm/amd/display: Enable DSC power-gating for DSC streams
From: Nikola Cornij
[why]
Currently DSC power gating is disabled by default because the power
transition doesn't happen, causing a crash on some systems
[how]
Fix the lack of power state transition and enable DSC power gating
by default.
Signed-off-by: Nikola Cornij
Reviewed-by: Martin Leung
Reviewed-by: Nevenko Stupar
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c| 8
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 3 ---
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index f788a39a1df1..914071393d1c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -222,6 +222,7 @@ static void dcn20_dsc_pg_control(
{
uint32_t power_gate = power_on ? 0 : 1;
uint32_t pwr_status = power_on ? 0 : 2;
+ uint32_t org_ip_request_cntl = 0;
if (hws->ctx->dc->debug.disable_dsc_power_gate)
return;
@@ -229,6 +230,10 @@ static void dcn20_dsc_pg_control(
if (REG(DOMAIN16_PG_CONFIG) == 0)
return;
+ REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, _ip_request_cntl);
+ if (org_ip_request_cntl == 0)
+ REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
+
switch (dsc_inst) {
case 0: /* DSC0 */
REG_UPDATE(DOMAIN16_PG_CONFIG,
@@ -282,6 +287,9 @@ static void dcn20_dsc_pg_control(
BREAK_TO_DEBUGGER();
break;
}
+
+ if (org_ip_request_cntl == 0)
+ REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
}
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index f2c2cbf4114b..d726f36c5e38 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -724,9 +724,6 @@ static const struct dc_debug_options debug_defaults_diags =
{
.disable_pplib_wm_range = true,
.disable_stutter = true,
.scl_reset_length10 = true,
-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
- .disable_dsc_power_gate = true,
-#endif
};
void dcn20_dpp_destroy(struct dpp **dpp)
--
2.20.1
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[PATCH 421/459] drm/amd/display: fix a potential issue in DSC logic
From: Wenjing Liu [why] In compute dsc bandwidth range there is an uninitialized variable [how] Initialize the variable to the correct value. Signed-off-by: Wenjing Liu Reviewed-by: Nikola Cornij Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 94a623dc37f4..252c3d0a2555 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -826,10 +826,16 @@ bool dc_dsc_compute_bandwidth_range( struct dc_dsc_config config; get_dsc_enc_caps(dc, _enc_caps, timing->pix_clk_100hz); - is_dsc_possible = setup_dsc_config(dsc_sink_caps, - _enc_caps, - 0, - timing, ); + + is_dsc_possible = intersect_dsc_caps(dsc_sink_caps, _enc_caps, + timing->pixel_encoding, _common_caps); + + if (is_dsc_possible) + is_dsc_possible = setup_dsc_config(dsc_sink_caps, + _enc_caps, + 0, + timing, ); + if (is_dsc_possible) get_dsc_bandwidth_range(min_bpp, max_bpp, _common_caps, timing, range); -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 436/459] drm/amd/display: Add missing VM conversion from hw values
From: Jun Lei
[why]
VM implemenation is missing conversion from HW values in hubbub
DM not passing actual PTB during flip
[how]
add proper HW conversion from logical values
fix cases where we programmed VA even though we are in PA
plumb in PTB from DM
Signed-off-by: Jun Lei
Reviewed-by: Tony Cheng
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
.../drm/amd/display/dc/dcn20/dcn20_hubbub.c | 77 +++
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 5 +-
2 files changed, 65 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
index a851574f118a..724f1c5ef614 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
@@ -303,6 +303,49 @@ void hubbub2_setup_vmid_ptb(struct hubbub *hubbub,
dcn20_vmid_set_ptb(>vmid[vmid], ptb);
}
+static enum dcn_hubbub_page_table_depth page_table_depth_to_hw(unsigned int
page_table_depth)
+{
+ enum dcn_hubbub_page_table_depth depth = 0;
+
+ switch (page_table_depth) {
+ case 1:
+ depth = DCN_PAGE_TABLE_DEPTH_1_LEVEL;
+ break;
+ case 2:
+ depth = DCN_PAGE_TABLE_DEPTH_2_LEVEL;
+ break;
+ case 3:
+ depth = DCN_PAGE_TABLE_DEPTH_3_LEVEL;
+ break;
+ case 4:
+ depth = DCN_PAGE_TABLE_DEPTH_4_LEVEL;
+ break;
+ default:
+ ASSERT(false);
+ break;
+ }
+
+ return depth;
+}
+
+static enum dcn_hubbub_page_table_block_size
page_table_block_size_to_hw(unsigned int page_table_block_size)
+{
+ enum dcn_hubbub_page_table_block_size block_size = 0;
+
+ switch (page_table_block_size) {
+ case 4096:
+ block_size = DCN_PAGE_TABLE_BLOCK_SIZE_4KB;
+ break;
+ case 65536:
+ block_size = DCN_PAGE_TABLE_BLOCK_SIZE_64KB;
+ break;
+ default:
+ ASSERT(false);
+ break;
+ }
+
+ return block_size;
+}
void hubbub2_init_dchub(struct hubbub *hubbub,
struct hubbub_addr_config *config)
@@ -312,11 +355,6 @@ void hubbub2_init_dchub(struct hubbub *hubbub,
struct dcn_vmid_page_table_config phys_config;
struct dcn_vmid_page_table_config virt_config;
- phys_config.depth = 0; // Depth 1
- phys_config.block_size = 0; // Block size 4KB
- phys_config.page_table_start_addr =
config->pa_config.gart_config.page_table_start_addr;
- phys_config.page_table_end_addr =
config->pa_config.gart_config.page_table_end_addr;
-
REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
FB_BASE, config->pa_config.system_aperture.fb_base);
REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
@@ -330,18 +368,27 @@ void hubbub2_init_dchub(struct hubbub *hubbub,
REG_SET(DCN_VM_AGP_BASE, 0,
AGP_BASE, config->pa_config.system_aperture.agp_base);
- // Init VMID 0 based on PA config
- dcn20_vmid_setup(>vmid[0], _config);
- dcn20_vmid_set_ptb(>vmid[0],
config->pa_config.gart_config.page_table_base_addr);
+ if (config->pa_config.gart_config.page_table_start_addr !=
config->pa_config.gart_config.page_table_end_addr) {
+ phys_config.depth = 1;
+ phys_config.block_size = 4096;
+ phys_config.page_table_start_addr =
config->pa_config.gart_config.page_table_start_addr >> 12;
+ phys_config.page_table_end_addr =
config->pa_config.gart_config.page_table_end_addr >> 12;
- // Init VMID 1-15 based on VA config
- for (i = 1; i < 16; i++) {
- virt_config.page_table_start_addr =
config->va_config.page_table_start_addr;
- virt_config.page_table_end_addr =
config->va_config.page_table_end_addr;
- virt_config.depth = config->va_config.page_table_depth;
- virt_config.block_size =
config->va_config.page_table_block_size;
+ // Init VMID 0 based on PA config
+ dcn20_vmid_setup(>vmid[0], _config);
+ dcn20_vmid_set_ptb(>vmid[0],
config->pa_config.gart_config.page_table_base_addr);
+ }
+
+ if (config->va_config.page_table_start_addr !=
config->va_config.page_table_end_addr) {
+ // Init VMID 1-15 based on VA config
+ for (i = 1; i < 16; i++) {
+ virt_config.page_table_start_addr =
config->va_config.page_table_start_addr >> 12;
+ virt_config.page_table_end_addr =
config->va_config.page_table_end_addr >> 12;
+ virt_config.depth =
page_table_depth_to_hw(config->va_config.page_table_depth);
+ virt_config.block_size =
page_table_block_size_to_hw(config->va_config.page_table_block_size);
- dcn20_vmid_setup(>vmid[i], _config);
+
[PATCH 432/459] drm/amd/display: decouple dsc adjustment out of enablement
From: Wenjing Liu
[why]
dsc adjustment is allowed via stream update sequence.
dsc enablement is only allowed via commit stream sequence.
with the current unified dsc set function, it is hard
to determine which sequence it is called by.
The solution is to decouple dsc adjustment out of enablement
sequence so we can handle them separately.
[how]
decouple dsc adjustment out of enablement.
Signed-off-by: Wenjing Liu
Reviewed-by: Nikola Cornij
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 7 +---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
.../drm/amd/display/dc/core/dc_link_hwss.c| 35 +--
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 12 +++
.../drm/amd/display/dc/dcn20/dcn20_resource.h | 2 --
.../gpu/drm/amd/display/dc/inc/core_types.h | 9 -
.../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 1 +
7 files changed, 24 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 8bf3433af3f8..fd955151132f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1746,14 +1746,9 @@ static void commit_planes_do_stream_update(struct dc *dc,
#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
if (stream_update->dsc_config &&
dc->hwss.pipe_control_lock_global) {
- bool enable_dsc =
(stream_update->dsc_config->num_slices_h &&
stream_update->dsc_config->num_slices_v);
-
dc->hwss.pipe_control_lock_global(dc, pipe_ctx,
true);
- dp_set_dsc_enable(pipe_ctx, enable_dsc);
+ dp_update_dsc_config(pipe_ctx);
dc->hwss.pipe_control_lock_global(dc, pipe_ctx,
false);
-
- if (!stream->is_dsc_enabled)
-
dc->res_pool->funcs->remove_dsc_from_stream_resource(dc, context, stream);
}
#endif
/* Full fe update*/
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 511877974315..4c31930f1cdf 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2817,7 +2817,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx,
int option)
disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
- if (pipe_ctx->stream->is_dsc_enabled &&
+ if (pipe_ctx->stream->timing.flags.DSC &&
dc_is_dp_signal(pipe_ctx->stream->signal)) {
dp_set_dsc_enable(pipe_ctx, false);
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 8b22af9085e4..2d019e1f6135 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -467,41 +467,40 @@ static void dp_set_dsc_on_stream(struct pipe_ctx
*pipe_ctx, bool enable)
bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable)
{
- struct dc_stream_state *stream = pipe_ctx->stream;
struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
bool result = false;
+ if (!pipe_ctx->stream->timing.flags.DSC)
+ goto out;
if (!dsc)
goto out;
- if (enable && stream->is_dsc_enabled) {
- /* update dsc stream */
- dp_set_dsc_on_stream(pipe_ctx, true);
- stream->is_dsc_enabled = true;
- result = true;
- } else if (enable && !stream->is_dsc_enabled) {
- /* enable dsc on non dsc stream */
+ if (enable) {
if (dp_set_dsc_on_rx(pipe_ctx, true)) {
dp_set_dsc_on_stream(pipe_ctx, true);
- stream->is_dsc_enabled = true;
result = true;
- } else {
- stream->is_dsc_enabled = false;
- result = false;
}
- } else if (!enable && stream->is_dsc_enabled) {
- /* disable dsc on dsc stream */
+ } else {
dp_set_dsc_on_rx(pipe_ctx, false);
dp_set_dsc_on_stream(pipe_ctx, false);
- stream->is_dsc_enabled = false;
- result = true;
- } else {
- /* disable dsc on non dsc stream */
result = true;
}
out:
return result;
}
+bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx)
+{
+ struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
+
+ if (!pipe_ctx->stream->timing.flags.DSC)
+ return false;
+ if (!dsc)
+ return false;
+
+ dp_set_dsc_on_stream(pipe_ctx, true);
+
[PATCH 416/459] drm/amd/display: fix odm mpo disable
From: Dmytro Laktyushkin
It looks like mpo isn't properly disabled during odm, this change is
meant to fix that.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Nikola Cornij
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 46e7f76a6553..1daf4029b566 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2153,6 +2153,11 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct
dc_state *context,
} else
need_split =
context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]
== 2;
+ /* We do not support mpo + odm at the moment */
+ if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
+ &&
context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
+ goto validate_fail;
+
if (need_split3d || need_split || force_split) {
if (!hsplit_pipe || hsplit_pipe->plane_state !=
pipe->plane_state) {
/* pipe not split previously needs split */
@@ -2168,11 +2173,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct
dc_state *context,
goto validate_fail;
pipe_split_from[hsplit_pipe->pipe_idx] =
pipe_idx;
}
- } else if (hsplit_pipe && hsplit_pipe->plane_state !=
pipe->plane_state) {
- /* We do not support mpo + odm at the moment */
- if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
- goto validate_fail;
- } else if (hsplit_pipe) {
+ } else if (hsplit_pipe && hsplit_pipe->plane_state ==
pipe->plane_state) {
/* merge should already have been done */
ASSERT(0);
}
--
2.20.1
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[PATCH 437/459] drm/amd/display: Fix incorrect DML output_bpp value
From: Ilya Bakoulin
[Why]
The output_bpp pipe parameter was assigned an incorrect value
(color depth enum), and subsequently used to overwrite
the OutputBpp parameter calculated by DML. Seems like this had no
effect except with DSC enabled, which would make DML produce
bad outputs.
[How]
Removed assignment to OutputBpp, fixed output_bpp assignment,
and properly set ForcedOutputLinkBPP instead of OutputBpp.
Also removed condition in DML that prevented forcing of
Output BPP with DSC enabled.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 40 ++-
.../drm/amd/display/dc/dml/display_mode_vba.c | 8 +++-
2 files changed, 45 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index d726f36c5e38..d71a0dcf652a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1616,6 +1616,7 @@ int dcn20_populate_dml_pipes_from_context(
for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
struct dc_crtc_timing *timing =
_ctx->pipe_ctx[i].stream->timing;
+ int output_bpc;
if (!res_ctx->pipe_ctx[i].stream)
continue;
@@ -1665,7 +1666,6 @@ int dcn20_populate_dml_pipes_from_context(
pipes[pipe_cnt].pipe.dest.vtotal_min =
res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
pipes[pipe_cnt].pipe.dest.vtotal_max =
res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
- pipes[pipe_cnt].dout.output_bpp =
res_ctx->pipe_ctx[i].stream->timing.display_color_depth;
switch (res_ctx->pipe_ctx[i].stream->signal) {
case SIGNAL_TYPE_DISPLAY_PORT_MST:
case SIGNAL_TYPE_DISPLAY_PORT:
@@ -1684,22 +1684,60 @@ int dcn20_populate_dml_pipes_from_context(
pipes[pipe_cnt].dout.output_type = dm_dp;
pipes[pipe_cnt].dout.dp_lanes = 4;
}
+
+ switch
(res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
+ case COLOR_DEPTH_666:
+ output_bpc = 6;
+ break;
+ case COLOR_DEPTH_888:
+ output_bpc = 8;
+ break;
+ case COLOR_DEPTH_101010:
+ output_bpc = 10;
+ break;
+ case COLOR_DEPTH_121212:
+ output_bpc = 12;
+ break;
+ case COLOR_DEPTH_141414:
+ output_bpc = 14;
+ break;
+ case COLOR_DEPTH_161616:
+ output_bpc = 16;
+ break;
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ case COLOR_DEPTH_999:
+ output_bpc = 9;
+ break;
+ case COLOR_DEPTH_11:
+ output_bpc = 11;
+ break;
+#endif
+ default:
+ output_bpc = 8;
+ break;
+ }
+
+
switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
case PIXEL_ENCODING_RGB:
case PIXEL_ENCODING_YCBCR444:
pipes[pipe_cnt].dout.output_format = dm_444;
+ pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
break;
case PIXEL_ENCODING_YCBCR420:
pipes[pipe_cnt].dout.output_format = dm_420;
+ pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3) / 2;
break;
case PIXEL_ENCODING_YCBCR422:
if (true) /* todo */
pipes[pipe_cnt].dout.output_format = dm_s422;
else
pipes[pipe_cnt].dout.output_format = dm_n422;
+ pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
break;
default:
pipes[pipe_cnt].dout.output_format = dm_444;
+ pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
}
pipes[pipe_cnt].pipe.src.hsplit_grp =
res_ctx->pipe_ctx[i].pipe_idx;
if (res_ctx->pipe_ctx[i].top_pipe &&
res_ctx->pipe_ctx[i].top_pipe->plane_state
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index a21608cd67ef..4d2a1262d9db 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -427,7 +427,12 @@ static void fetch_pipe_params(struct display_mode_lib
*mode_lib)
[PATCH 429/459] drm/amd/display: DCN2 Engine-specifc encoder allocation
From: Wesley Chalmers
[WHY]
From DCE110 onward, we have the ability to assign DIG BE and FE
separately for any display connector type; before, we could only do this
for DP.
Signed-off-by: Wesley Chalmers
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index ac65794c7fa6..8b4853dd4fd4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2446,8 +2446,9 @@ static struct resource_funcs dcn20_res_pool_funcs = {
.set_mcif_arb_params = dcn20_set_mcif_arb_params,
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
- .remove_dsc_from_stream_resource = dcn20_remove_dsc_from_stream_resource
+ .remove_dsc_from_stream_resource =
dcn20_remove_dsc_from_stream_resource,
#endif
+ .find_first_free_match_stream_enc_for_link =
dce110_find_first_free_match_stream_enc_for_link
};
bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
--
2.20.1
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[PATCH 425/459] drm/amd/display: move DWB structs and enums to dc_hw_types
From: Tyler DiBattista
[Why]
these enums/structs will be used more generically in the future
so moving it to dc_hw_types and dc_types
Signed-off-by: Tyler DiBattista
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 10 ++
drivers/gpu/drm/amd/display/dc/dc_types.h| 7 +++
drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 17 -
3 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index ea7a1c9efca8..6b1431d63dab 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -840,6 +840,16 @@ enum dwb_subsample_position {
DWB_COSITED_SUBSAMPLING = 1
};
+enum dwb_stereo_eye_select {
+ DWB_STEREO_EYE_LEFT = 1, /* Capture left eye only */
+ DWB_STEREO_EYE_RIGHT = 2, /* Capture right eye only */
+};
+
+enum dwb_stereo_type {
+ DWB_STEREO_TYPE_FRAME_PACKING = 0, /* Frame packing */
+ DWB_STEREO_TYPE_FRAME_SEQUENTIAL = 3, /* Frame sequential */
+};
+
#define MCIF_BUF_COUNT 4
struct mcif_buf_params {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 5984be3cdf0c..7ce8d62ce5ae 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -423,6 +423,13 @@ enum display_content_type {
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
/* writeback */
+struct dwb_stereo_params {
+ boolstereo_enabled; /* false:
normal mode, true: 3D stereo */
+ enum dwb_stereo_typestereo_type;/* indicates
stereo format */
+ boolstereo_polarity;/* indicates
left eye or right eye comes first in stereo mode */
+ enum dwb_stereo_eye_select stereo_eye_select; /* indicate
which eye should be captured */
+};
+
struct dc_dwb_cnv_params {
unsigned intsrc_width; /* input active width */
unsigned intsrc_height; /* input active height
(half-active height in interlaced mode) */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
index c3c7a34b0ab0..d4ae6eaaeb57 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
@@ -81,16 +81,6 @@ enum dwb_frame_capture_enable {
DWB_FRAME_CAPTURE_ENABLE = 1,
};
-enum dwb_stereo_eye_select {
- DWB_STEREO_EYE_LEFT = 1, /* Capture left eye only */
- DWB_STEREO_EYE_RIGHT = 2, /* Capture right eye only */
-};
-
-enum dwb_stereo_type {
- DWB_STEREO_TYPE_FRAME_PACKING = 0, /* Frame packing */
- DWB_STEREO_TYPE_FRAME_SEQUENTIAL = 3, /* Frame sequential */
-};
-
enum wbscl_coef_filter_type_sel {
WBSCL_COEF_LUMA_VERT_FILTER = 0,
WBSCL_COEF_CHROMA_VERT_FILTER = 1,
@@ -101,13 +91,6 @@ enum wbscl_coef_filter_type_sel {
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
-struct dwb_stereo_params {
- boolstereo_enabled; /* false:
normal mode, true: 3D stereo */
- enum dwb_stereo_typestereo_type;/* indicates
stereo format */
- boolstereo_polarity;/* indicates
left eye or right eye comes first in stereo mode */
- enum dwb_stereo_eye_select stereo_eye_select; /* indicate
which eye should be captured */
-};
-
struct dwb_warmup_params {
boolwarmup_en; /* false: normal mode, true: enable pattern
generator */
boolwarmup_mode;/* false: 420, true: 444 */
--
2.20.1
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[PATCH 411/459] drm/amd/display: Do a reg update instead of set when writing ODM color format
From: Nikola Cornij [why] If a set is done, DSC settings are zeroed out, leading to no DSC for the modes that require ODM, such as 8k60. This was a regression introduced by 5a4f26295176bbfc776c75aaf0f6dd8ccf806958. Signed-off-by: Nikola Cornij Reviewed-by: Eric Bernstein Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c index d0b317ea3a7c..26a66ccf6e72 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c @@ -262,7 +262,7 @@ void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id, else if (pixel_encoding == PIXEL_ENCODING_YCBCR420) data_fmt = 2; - REG_SET(OPTC_DATA_FORMAT_CONTROL, 0, OPTC_DATA_FORMAT, data_fmt); + REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt); REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, OPTC_NUM_OF_INPUT_SEGMENT, 1, -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 424/459] drm/amd/display: Integrate color transform3x4 with 3dlut tm
From: Vitaly Prosyak
[Why & How]
Reuse existent code path (dcn1+) and in order to do that apply de gamma
in 1D blender LUT and re use MPC OGAM.
Follow up is required.
Signed-off-by: Vitaly Prosyak
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
Acked-by: Krunoslav Kovac
Acked-by: Vitaly Prosyak
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 7 +++
drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 10 ++
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/modules/inc/mod_shared.h | 7 ---
4 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 6abf22aaf571..867a84c2bfbf 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1669,6 +1669,13 @@ static void copy_surface_update_to_plane(
srf_update->lut3d_func))
memcpy(surface->lut3d_func, srf_update->lut3d_func,
sizeof(*surface->lut3d_func));
+
+ if (srf_update->blend_tf &&
+ (surface->blend_tf !=
+ srf_update->blend_tf))
+ memcpy(surface->blend_tf, srf_update->blend_tf,
+ sizeof(*surface->blend_tf));
+
#endif
if (srf_update->input_csc_color_matrix)
surface->input_csc_color_matrix =
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
index 60f20d96f9e0..394a87981614 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
@@ -60,6 +60,11 @@ static void construct(struct dc_context *ctx, struct
dc_plane_state *plane_state
plane_state->lut3d_func->ctx = ctx;
plane_state->lut3d_func->initialized = false;
}
+ plane_state->blend_tf = dc_create_transfer_func();
+ if (plane_state->blend_tf != NULL) {
+ plane_state->blend_tf->type = TF_TYPE_BYPASS;
+ plane_state->blend_tf->ctx = ctx;
+ }
#endif
}
@@ -85,6 +90,11 @@ static void destruct(struct dc_plane_state *plane_state)
plane_state->lut3d_func);
plane_state->lut3d_func = NULL;
}
+ if (plane_state->blend_tf != NULL) {
+ dc_transfer_func_release(
+ plane_state->blend_tf);
+ plane_state->blend_tf = NULL;
+ }
#endif
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 139ea7354910..53a3876841cc 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -761,6 +761,7 @@ struct dc_surface_update {
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
const struct dc_transfer_func *func_shaper;
const struct dc_3dlut *lut3d_func;
+ const struct dc_transfer_func *blend_tf;
#endif
};
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
b/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
index 6c877eeba429..b45f7d65e76a 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
@@ -64,7 +64,8 @@ union lut3d_control_flags {
unsigned int use_gamut_map_lib
:1;
unsigned int chromatic_adaptation_src
:1;
unsigned int chromatic_adaptation_dst
:1;
- unsigned int reseved:5;
+ unsigned int do_blender_lut_degamma :1;
+ unsigned int reseved:4;
} bits;
};
@@ -78,8 +79,8 @@ enum lut3d_control_gamut_map {
lut3d_control_gamut_map_none = 0,
lut3d_control_gamut_map_tonemap,
lut3d_control_gamut_map_chto,
- lut3d_control_gamut_map_chto_chso,
- lut3d_control_gamut_map_chto_chci
+ lut3d_control_gamut_map_chso,
+ lut3d_control_gamut_map_chci
};
enum lut3d_control_rotation_mode {
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 413/459] drm/amd/display: Intermittent DCN2 pipe hang on mode change
From: Aric Cyr
[Why]
GSL is being used to synchronize pipes when vsync is off but
on transition to vsync on during a mode change GSL is not
being reset correctly.
[How]
Disable GSL on any plane that is disabled.
Signed-off-by: Aric Cyr
Reviewed-by: Krunoslav Kovac
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c| 15 +++
.../gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h| 2 +-
2 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index f9eae47f7be3..c7ae538611f7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -467,6 +467,14 @@ static void dcn20_plane_atomic_disable(struct dc *dc,
struct pipe_ctx *pipe_ctx)
dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
+ /* In flip immediate with pipe splitting case GSL is used for
+* synchronization so we must disable it when the plane is disabled.
+*/
+ if (pipe_ctx->stream_res.gsl_group != 0)
+ dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
+
+ dc->hwss.set_flip_control_gsl(pipe_ctx, false);
+
hubp->funcs->hubp_clk_cntl(hubp, false);
dpp->funcs->dpp_dppclk_control(dpp, false, false);
@@ -1900,14 +1908,14 @@ static int find_free_gsl_group(const struct dc *dc)
void dcn20_setup_gsl_group_as_lock(
const struct dc *dc,
struct pipe_ctx *pipe_ctx,
- bool flip_immediate)
+ bool enable)
{
struct gsl_params gsl;
int group_idx;
memset(, 0, sizeof(struct gsl_params));
- if (flip_immediate) {
+ if (enable) {
/* return if group already assigned since GSL was set up
* for vsync flip, we would unassign so it can't be "left over"
*/
@@ -1973,8 +1981,7 @@ void dcn20_setup_gsl_group_as_lock(
);
pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
- pipe_ctx->stream_res.tg, group_idx,
- flip_immediate ? 4 : 0);
+ pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0);
} else
BREAK_TO_DEBUGGER();
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
index 37699df685ee..b7892e8f4518 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
@@ -86,6 +86,6 @@ void dcn20_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx);
void dcn20_setup_gsl_group_as_lock(const struct dc *dc,
struct pipe_ctx *pipe_ctx,
- bool flip_immediate);
+ bool enable);
#endif /* __DC_HWSS_DCN20_H__ */
--
2.20.1
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[PATCH 399/459] drm/amd/display: Remove duplicate define of TO_DCN20_HUBBUB
From: Yongqiang Sun Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Leo Li Acked-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h index 63d51ab57103..cdd19f5887d7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h @@ -29,9 +29,6 @@ #include "dcn10/dcn10_hubbub.h" #include "dcn20_vmid.h" -#define TO_DCN20_HUBBUB(hubbub)\ - container_of(hubbub, struct dcn20_hubbub, base) - #define TO_DCN20_HUBBUB(hubbub)\ container_of(hubbub, struct dcn20_hubbub, base) -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 394/459] drm/amd/display: Acquire DSC HW resource only if required by stream
From: Nikola Cornij
[why]
There are ASICs that have fewer DSC engines than pipes, which makes
DSC a resource that should be used only if required.
[how]
Acquire DSC HW resource if required by stream and release when not
required anymore.
Signed-off-by: Nikola Cornij
Reviewed-by: Wenjing Liu
Acked-by: Leo Li
Acked-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 19 +--
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 139 ++
.../drm/amd/display/dc/dcn20/dcn20_resource.h | 2 +
.../gpu/drm/amd/display/dc/inc/core_types.h | 10 ++
4 files changed, 97 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 68eddcc0fbcc..6abf22aaf571 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1736,19 +1736,14 @@ static void commit_planes_do_stream_update(struct dc
*dc,
#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
if (stream_update->dsc_config &&
dc->hwss.pipe_control_lock_global) {
- if (stream_update->dsc_config->num_slices_h &&
-
stream_update->dsc_config->num_slices_v) {
- /* dsc enable */
- dc->hwss.pipe_control_lock_global(dc,
pipe_ctx, true);
- dp_set_dsc_enable(pipe_ctx, true);
- dc->hwss.pipe_control_lock_global(dc,
pipe_ctx, false);
- } else {
- /* dsc disable */
- dc->hwss.pipe_control_lock_global(dc,
pipe_ctx, true);
- dp_set_dsc_enable(pipe_ctx, false);
- dc->hwss.pipe_control_lock_global(dc,
pipe_ctx, false);
- }
+ bool enable_dsc =
(stream_update->dsc_config->num_slices_h &&
stream_update->dsc_config->num_slices_v);
+
+ dc->hwss.pipe_control_lock_global(dc, pipe_ctx,
true);
+ dp_set_dsc_enable(pipe_ctx, enable_dsc);
+ dc->hwss.pipe_control_lock_global(dc, pipe_ctx,
false);
+ if (!stream->is_dsc_enabled)
+
dc->res_pool->funcs->remove_dsc_from_stream_resource(dc, context, stream);
}
#endif
/* Full fe update*/
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index d2642cc52c85..2d6f9c4de893 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1230,94 +1230,79 @@ enum dc_status dcn20_build_mapped_resource(const struct
dc *dc, struct dc_state
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-static struct display_stream_compressor *acquire_dsc(struct resource_context
*res_ctx,
- const struct resource_pool
*pool)
+static void acquire_dsc(struct resource_context *res_ctx,
+ const struct resource_pool *pool,
+ struct display_stream_compressor **dsc)
{
int i;
- struct display_stream_compressor *dsc = NULL;
+
+ ASSERT(*dsc == NULL);
+ *dsc = NULL;
/* Find first free DSC */
for (i = 0; i < pool->res_cap->num_dsc; i++)
if (!res_ctx->is_dsc_acquired[i]) {
- dsc = pool->dscs[i];
+ *dsc = pool->dscs[i];
res_ctx->is_dsc_acquired[i] = true;
break;
}
-
- return dsc;
}
static void release_dsc(struct resource_context *res_ctx,
const struct resource_pool *pool,
- const struct display_stream_compressor *dsc)
+ struct display_stream_compressor **dsc)
{
int i;
for (i = 0; i < pool->res_cap->num_dsc; i++)
- if (pool->dscs[i] == dsc) {
+ if (pool->dscs[i] == *dsc) {
res_ctx->is_dsc_acquired[i] = false;
+ *dsc = NULL;
break;
}
}
#endif
-enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state
*new_ctx, struct dc_stream_state *dc_stream)
-{
- enum dc_status result = DC_ERROR_UNEXPECTED;
-
- result = resource_map_pool_resources(dc, new_ctx, dc_stream);
-
- if (result == DC_OK)
- result = resource_map_phy_clock_resources(dc, new_ctx,
dc_stream);
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
- /* Get a DSC if required and available */
- if (result == DC_OK)
[PATCH 398/459] drm/amd/display: Add power down display on boot flag
From: Thomas Lim [Why] Due to the generic introduction of seamless boot, the display is no longer blanked upon boot. However, this causes corruption on some systems that does not lock the memory in the non-secure boot case, resulting in brief corruption on boot due to garbage being written into the frame buffer. [How] Add a flag, read during DC init, to determine whether display should be blanked on boot. Default to true. Signed-off-by: Thomas Lim Reviewed-by: Aric Cyr Acked-by: Anthony Koo Acked-by: Leo Li Acked-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d20250b181b7..8f206a7ddb8c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -557,6 +557,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) init_data.flags.fbc_support = true; init_data.flags.power_down_display_on_boot = true; + #ifdef CONFIG_DRM_AMD_DC_DCN2_0 init_data.soc_bounding_box = adev->dm.soc_bounding_box; #endif -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 395/459] drm/amd/display: Implement DSC MST fair share algorithm
From: Wenjing Liu
[why]
The current policy will always enable DSC to 12 bpp
regardless of if the current bandwidth is enough for MST displays.
This logic is not optimal because user will get lower quality output
if DSC compression is enabled.
This change to is to implement a DSC MST bandwidth fair share
algorithm so we will dynamically decide if DSC is needed and what
quality (target bpp) is needed to fairly destribute the MST bandwidth
in one MST topology. This will allow user to see the most optimal
image quality with the given bandwidth.
[how]
We will start with lowest bandwidth possible and run a
Max-Min fairness algorithm to fairly distribute the available
bandwidth. If there is still remaining bandwidth, we will try to fit
the timing without DSC compression.
Signed-off-by: Wenjing Liu
Reviewed-by: Jun Lei
Acked-by: Leo Li
Acked-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 2 ++
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 26 +--
3 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 4c31930f1cdf..511877974315 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2817,7 +2817,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx,
int option)
disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
- if (pipe_ctx->stream->timing.flags.DSC &&
+ if (pipe_ctx->stream->is_dsc_enabled &&
dc_is_dp_signal(pipe_ctx->stream->signal)) {
dp_set_dsc_enable(pipe_ctx, false);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index 2cba6bd7937a..ddaf7532bb59 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -38,6 +38,8 @@ bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_data,
bool dc_dsc_compute_bandwidth_range(
const struct dc *dc,
+ const uint32_t min_kbps,
+ const uint32_t max_kbps,
const struct dsc_dec_dpcd_caps *dsc_sink_caps,
const struct dc_crtc_timing *timing,
struct dc_dsc_bw_range *range);
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 6357325d3c90..d15da6f906e8 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -284,7 +284,8 @@ const struct dc_dsc_policy dsc_policy = {
};
static void get_dsc_bandwidth_range(
- const struct dc_dsc_policy *policy,
+ const uint32_t min_bpp,
+ const uint32_t max_bpp,
const struct dsc_enc_caps *dsc_caps,
const struct dc_crtc_timing *timing,
struct dc_dsc_bw_range *range)
@@ -293,8 +294,8 @@ static void get_dsc_bandwidth_range(
range->stream_kbps = dc_bandwidth_in_kbps_from_timing(timing);
/* max dsc target bpp */
- range->max_kbps = dsc_round_up(policy->max_target_bpp *
timing->pix_clk_100hz);
- range->max_target_bpp_x16 = policy->max_target_bpp * 16;
+ range->max_kbps = dsc_round_up(max_bpp * timing->pix_clk_100hz);
+ range->max_target_bpp_x16 = max_bpp * 16;
if (range->max_kbps > range->stream_kbps) {
/* max dsc target bpp is capped to native bandwidth */
range->max_kbps = range->stream_kbps;
@@ -302,8 +303,8 @@ static void get_dsc_bandwidth_range(
}
/* min dsc target bpp */
- range->min_kbps = dsc_round_up(policy->min_target_bpp *
timing->pix_clk_100hz);
- range->min_target_bpp_x16 = policy->min_target_bpp * 16;
+ range->min_kbps = dsc_round_up(min_bpp * timing->pix_clk_100hz);
+ range->min_target_bpp_x16 = min_bpp * 16;
if (range->min_kbps > range->max_kbps) {
/* min dsc target bpp is capped to max dsc bandwidth*/
range->min_kbps = range->max_kbps;
@@ -330,7 +331,8 @@ static bool decide_dsc_target_bpp_x16(
memset(, 0, sizeof(range));
- get_dsc_bandwidth_range(policy, dsc_common_caps, timing, );
+ get_dsc_bandwidth_range(policy->min_target_bpp, policy->max_target_bpp,
+ dsc_common_caps, timing, );
if (target_bandwidth_kbps >= range.stream_kbps) {
/* enough bandwidth without dsc */
*target_bpp_x16 = 0;
@@ -753,6 +755,8 @@ bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_data,
struct dsc_dec_dpcd_cap
bool dc_dsc_compute_bandwidth_range(
const struct dc *dc,
+ const uint32_t min_bpp,
+ const uint32_t max_bpp,
const struct
[PATCH 396/459] drm/amd/display: enable abm on dcn2
From: Josip Pavic
[Why]
ABM is currently not enabled on DCN2.
[How]
Update the register name list for DCN2 and un-comment the code that
creates the abm object.
Signed-off-by: Josip Pavic
Reviewed-by: Anthony Koo
Acked-by: Leo Li
Acked-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 20 +++
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 14 ++---
2 files changed, 27 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
index ff9436966041..7ba7e6f722f6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
@@ -67,6 +67,22 @@
SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
NBIO_SR(BIOS_SCRATCH_2)
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+#define ABM_DCN20_REG_LIST() \
+ ABM_COMMON_REG_LIST_DCE_BASE(), \
+ SR(DC_ABM1_HG_SAMPLE_RATE), \
+ SR(DC_ABM1_LS_SAMPLE_RATE), \
+ SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
+ SR(DC_ABM1_HG_MISC_CTRL), \
+ SR(DC_ABM1_IPCSC_COEFF_SEL), \
+ SR(BL1_PWM_CURRENT_ABM_LEVEL), \
+ SR(BL1_PWM_TARGET_ABM_LEVEL), \
+ SR(BL1_PWM_USER_LEVEL), \
+ SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
+ SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
+ NBIO_SR(BIOS_SCRATCH_2)
+#endif
+
#define ABM_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
@@ -147,6 +163,10 @@
ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
+#endif
+
#define ABM_REG_FIELD_LIST(type) \
type ABM1_HG_NUM_OF_BINS_SEL; \
type ABM1_HG_VMAX_SEL; \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 2d6f9c4de893..0a11d1098a7e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -271,19 +271,19 @@ static const struct dce_dmcu_shift dmcu_shift = {
static const struct dce_dmcu_mask dmcu_mask = {
DMCU_MASK_SH_LIST_DCN10(_MASK)
};
-/*
+
static const struct dce_abm_registers abm_regs = {
- ABM_DCN10_REG_LIST(0)
+ ABM_DCN20_REG_LIST()
};
static const struct dce_abm_shift abm_shift = {
- ABM_MASK_SH_LIST_DCN10(__SHIFT)
+ ABM_MASK_SH_LIST_DCN20(__SHIFT)
};
static const struct dce_abm_mask abm_mask = {
- ABM_MASK_SH_LIST_DCN10(_MASK)
+ ABM_MASK_SH_LIST_DCN20(_MASK)
};
-*/
+
#define audio_regs(id)\
[id] = {\
AUD_COMMON_REG_LIST(id)\
@@ -2811,7 +2811,7 @@ static bool construct(
goto create_fail;
}
- /*pool->base.abm = dce_abm_create(ctx,
+ pool->base.abm = dce_abm_create(ctx,
_regs,
_shift,
_mask);
@@ -2819,7 +2819,7 @@ static bool construct(
dm_error("DC: failed to create abm!\n");
BREAK_TO_DEBUGGER();
goto create_fail;
- }*/
+ }
pool->base.pp_smu = dcn20_pp_smu_create(ctx);
--
2.20.1
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[PATCH 397/459] drm/amd/display: Consider DSC target bpp precision when calculating DSC target bpp
From: Nikola Cornij
[why]
DSC target bpp precision is a decoder DPCD and an AMD encoder capability.
It must be taken into account when calculating target bitrate.
[how]
Add a DC DSC function that does this calculation.
Signed-off-by: Nikola Cornij
Reviewed-by: Wenjing Liu
Acked-by: Leo Li
Acked-by: Hawking Zhang
Acked-by: Tony Cheng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 10 +
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 25 ++---
2 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index ddaf7532bb59..be0f7b09086a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -24,12 +24,13 @@
*
* Author: AMD
*/
+
struct dc_dsc_bw_range {
- uint32_t min_kbps;
+ uint32_t min_kbps; /* Bandwidth if min_target_bpp_x16 is used */
uint32_t min_target_bpp_x16;
- uint32_t max_kbps;
+ uint32_t max_kbps; /* Bandwidth if max_target_bpp_x16 is used */
uint32_t max_target_bpp_x16;
- uint32_t stream_kbps;
+ uint32_t stream_kbps; /* Uncompressed stream bandwidth */
};
@@ -43,10 +44,11 @@ bool dc_dsc_compute_bandwidth_range(
const struct dsc_dec_dpcd_caps *dsc_sink_caps,
const struct dc_crtc_timing *timing,
struct dc_dsc_bw_range *range);
+
bool dc_dsc_compute_config(
const struct dc *dc,
const struct dsc_dec_dpcd_caps *dsc_sink_caps,
- int target_bandwidth,
+ uint32_t target_bandwidth_kbps,
const struct dc_crtc_timing *timing,
struct dc_dsc_config *dsc_cfg);
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index d15da6f906e8..d58d718171b5 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -283,6 +283,10 @@ const struct dc_dsc_policy dsc_policy = {
.min_target_bpp = 8,
};
+
+/* Get DSC bandwidth range based on [min_bpp, max_bpp] target bitrate range,
and timing's pixel clock
+ * and uncompressed bandwidth.
+ */
static void get_dsc_bandwidth_range(
const uint32_t min_bpp,
const uint32_t max_bpp,
@@ -312,6 +316,7 @@ static void get_dsc_bandwidth_range(
}
}
+
/* Decides if DSC should be used and calculates target bpp if it should,
applying DSC policy.
*
* Returns:
@@ -494,10 +499,10 @@ static int fit_num_slices_up(union dsc_enc_slice_caps
slice_caps, int num_slices
*
* dsc_enc_caps- DSC encoder capabilities
*
- * target_bandwidth- Target bandwidth to fit the stream into.
- * If 0, do not calculate target bpp.
+ * target_bandwidth_kbps - Target bandwidth to fit the stream into.
+ * If 0, do not calculate target bpp.
*
- * timing - The stream timing to fit into 'target_bandwidth' or
apply
+ * timing - The stream timing to fit into 'target_bandwidth_kbps'
or apply
* maximum compression to, if 'target_badwidth == 0'
*
* dsc_cfg - DSC configuration to use if it was possible to come
up with
@@ -510,7 +515,7 @@ static int fit_num_slices_up(union dsc_enc_slice_caps
slice_caps, int num_slices
static bool setup_dsc_config(
const struct dsc_dec_dpcd_caps *dsc_sink_caps,
const struct dsc_enc_caps *dsc_enc_caps,
- int target_bandwidth,
+ int target_bandwidth_kbps,
const struct dc_crtc_timing *timing,
struct dc_dsc_config *dsc_cfg)
{
@@ -536,8 +541,8 @@ static bool setup_dsc_config(
if (!is_dsc_possible)
goto done;
- if (target_bandwidth > 0) {
- is_dsc_possible = decide_dsc_target_bpp_x16(_policy,
_common_caps, target_bandwidth, timing, _bpp);
+ if (target_bandwidth_kbps > 0) {
+ is_dsc_possible = decide_dsc_target_bpp_x16(_policy,
_common_caps, target_bandwidth_kbps, timing, _bpp);
dsc_cfg->bits_per_pixel = target_bpp;
}
if (!is_dsc_possible)
@@ -753,6 +758,10 @@ bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_data,
struct dsc_dec_dpcd_cap
}
+/* If DSC is possbile, get DSC bandwidth range based on [min_bpp, max_bpp]
target bitrate range and
+ * timing's pixel clock and uncompressed bandwidth.
+ * If DSC is not possible, leave '*range' untouched.
+ */
bool dc_dsc_compute_bandwidth_range(
const struct dc *dc,
const uint32_t min_bpp,
@@ -780,7 +789,7 @@ bool dc_dsc_compute_bandwidth_range(
bool dc_dsc_compute_config(
const struct dc *dc,
const struct dsc_dec_dpcd_caps *dsc_sink_caps,
- int target_bandwidth,
+ uint32_t
[PATCH 393/459] drm/amd/display: Disable display writeback on Linux for NV10
From: hersen wu
[WHY] system crash when initialize dwb
current linux driver does not support dwb.
disable this feature for now.
[HOW] set num_dwb = 0 to disable dwb for now
Signed-off-by: hersen wu
Reviewed-by: Leo Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index b2b74f5d..d2642cc52c85 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -623,7 +623,7 @@ static const struct resource_caps res_cap_nv10 = {
.num_audio = 7,
.num_stream_encoder = 6,
.num_pll = 6,
- .num_dwb = 1,
+ .num_dwb = 0,
.num_ddc = 6,
.num_vmid = 16,
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
--
2.20.1
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[PATCH 391/459] drm/amd/display: Mark DSC resource as unused after copying to the secondary ODM pipe
From: Nikola Cornij
[why]
DSC resource has to be acquired before it can be used and simply copying
a reference to it is very likely to cause problems when accessing DSC.
[how]
Set DSC resource pointer to NULL to mark it as unused after primary pipe
resources were copied to the secondary ODM pipe.
Signed-off-by: Nikola Cornij
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index c9b7340c9601..b2b74f5d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1427,6 +1427,9 @@ static bool dcn20_split_stream_for_combine(
secondary_pipe->plane_res.xfm =
pool->transforms[secondary_pipe->pipe_idx];
secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
secondary_pipe->plane_res.mpcc_inst =
pool->dpps[secondary_pipe->pipe_idx]->inst;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ secondary_pipe->stream_res.dsc = NULL;
+#endif
if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe !=
secondary_pipe) {
ASSERT(!secondary_pipe->bottom_pipe);
secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
--
2.20.1
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[PATCH 392/459] drm/amd/display: Add vupdate interrupt sources to NV10
From: hersen wu [WHY] linux upstream already has interrupt vupdate for freesync in dcn10. dcn20 interrupt shares the same source code as dcn10. but dcn20 interrupt translator does not add vupdate interrupt. this cause index of vupdate aarray be negative which causes crash. [HOW] add vupdate into dc interrupt transltor Signed-off-by: hersen wu Reviewed-by: Leo Li Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c index da70cc7b24b5..65866d620759 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c @@ -68,6 +68,18 @@ enum dc_irq_source to_dal_irq_source_dcn20( return DC_IRQ_SOURCE_PFLIP5; case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT: return DC_IRQ_SOURCE_PFLIP6; + case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE1; + case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE2; + case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE3; + case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE4; + case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE5; + case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE6; case DCN_1_0__SRCID__DC_HPD1_INT: /* generic src_id for all HPD and HPDRX interrupts */ -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 390/459] drm/amd/display: Change Min fclk to 1.2Ghz
From: Tyler DiBattista
[Why]
Some nightly tests are failing since the new value for fclk is a
bit too low. Also, a new test for the maximum downscale case was
needed.
[How]
Updated the default value for fclk to be 1.2GHz.
Signed-off-by: Tyler DiBattista
Reviewed-by: Eric Bernstein
Acked-by: Bhawanpreet Lakha
Acked-by: Tony Cheng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index c1511c9edd48..de471ca87ed7 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -249,8 +249,8 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
bool safe_to_lower)
{
struct dc_clocks *new_clocks = >bw_ctx.bw.dcn.clk;
- /* Min fclk = 1GHz since all the extra scemi logic seems to run off of
it */
- int fclk_adj = new_clocks->fclk_khz > 100 ? new_clocks->fclk_khz :
100;
+ /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off
of it */
+ int fclk_adj = new_clocks->fclk_khz > 120 ? new_clocks->fclk_khz :
120;
if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz,
clk_mgr->clks.phyclk_khz)) {
clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
--
2.20.1
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[PATCH 393/459] drm/amd/display: Disable display writeback on Linux for NV10
From: hersen wu
[WHY] system crash when initialize dwb
current linux driver does not support dwb.
disable this feature for now.
[HOW] set num_dwb = 0 to disable dwb for now
Signed-off-by: hersen wu
Reviewed-by: Leo Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index b2b74f5d..d2642cc52c85 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -623,7 +623,7 @@ static const struct resource_caps res_cap_nv10 = {
.num_audio = 7,
.num_stream_encoder = 6,
.num_pll = 6,
- .num_dwb = 1,
+ .num_dwb = 0,
.num_ddc = 6,
.num_vmid = 16,
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
--
2.20.1
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[PATCH 386/459] drm/amd/display: Optimize bandwidth validation by adding early return
From: Joshua Aberback
We can split validation into three parts: getting voltage level, getting
watermarks, and rq/dlg calculations. The voltage level is enough to answer
the question "do we support this state", and the rest of it is to determine
what hardware programming is needed to support the state. Most of the calls
to validate_bandwidth only care about the first part, so we added an early
return in that case
Signed-off-by: Joshua Aberback
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 11 +++---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 3 +-
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 35 ++-
3 files changed, 31 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index ef804948694e..38365dd911a3 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1116,9 +1116,8 @@ bool dcn_validate_bandwidth(
context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed *
100 /
(ddr4_dram_factor_single_Channel *
v->number_of_channels));
- if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65) {
+ if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65)
context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed
* 100 / 32);
- }
context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz =
(int)(v->dcf_clk_deep_sleep * 1000);
context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000);
@@ -1133,7 +1132,8 @@ bool dcn_validate_bandwidth(
dc->debug.min_disp_clk_khz;
}
- context->bw_ctx.bw.dcn.clk.dppclk_khz =
context->bw_ctx.bw.dcn.clk.dispclk_khz / v->dispclk_dppclk_ratio;
+ context->bw_ctx.bw.dcn.clk.dppclk_khz =
context->bw_ctx.bw.dcn.clk.dispclk_khz /
+ v->dispclk_dppclk_ratio;
context->bw_ctx.bw.dcn.clk.phyclk_khz =
v->phyclk_per_state[v->voltage_level];
switch (v->voltage_level) {
case 0:
@@ -1220,9 +1220,7 @@ bool dcn_validate_bandwidth(
/* pipe not split previously
needs split */
hsplit_pipe =
find_idle_secondary_pipe(>res_ctx, pool, pipe);
ASSERT(hsplit_pipe);
- split_stream_across_pipes(
- >res_ctx, pool,
- pipe, hsplit_pipe);
+
split_stream_across_pipes(>res_ctx, pool, pipe, hsplit_pipe);
}
dcn_bw_calc_rq_dlg_ttu(dc, v,
hsplit_pipe, input_idx);
@@ -1253,7 +1251,6 @@ bool dcn_validate_bandwidth(
}
if (v->voltage_level == 0) {
-
context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =
dc->dcn_soc->sr_enter_plus_exit_time;
context->bw_ctx.dml.soc.sr_exit_time_us =
dc->dcn_soc->sr_exit_time;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 542f144f807f..dc34ce28505c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1415,9 +1415,8 @@ bool dcn20_update_bandwidth(
int i;
/* recalculate DML parameters */
- if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
+ if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
return false;
- }
/* apply updated bandwidth parameters */
dc->hwss.prepare_bandwidth(dc, context);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index e3cd3e3db2c4..371d96290d86 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1907,10 +1907,11 @@ static bool dcn20_validate_dsc(struct dc *dc, struct
dc_state *new_ctx)
}
#endif
-bool dcn20_validate_bandwidth(struct dc *dc,
- struct dc_state *context,
- bool fast_validate)
+bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
+ bool fast_validate)
{
+ bool out = false;
+
int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
int pipe_split_from[MAX_PIPES];
bool odm_capable = context->bw_ctx.dml.ip.odm_capable;
@@ -1954,11 +1955,16 @@ bool
[PATCH 383/459] drm/amd/display: Add 3dlut control flags
From: Vitaly Prosyak
[Why & How]
The follow up change
Improve some naming for fields and structs
Signed-off-by: Vitaly Prosyak
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
Acked-by: Vitaly Prosyak
Signed-off-by: Alex Deucher
---
.../drm/amd/display/modules/inc/mod_shared.h | 36 +--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
b/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
index 5a631854efda..9406d0a167ee 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
@@ -46,35 +46,35 @@ enum vrr_packet_type {
};
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
-union tm3dlut_internal_flags {
+union lut3d_control_flags {
unsigned int raw;
struct {
- unsigned int dochroma_scale :1;
- unsigned int spec_version :3;
- unsigned int use_zero_display_black :1;
- unsigned int use_zero_source_black :1;
- unsigned int force_display_black:6;
- unsigned int apply_display_gamma:1;
- unsigned int exp_shaper_max :6;
- unsigned int unity3dlut :1;
- unsigned int bypass3dlut:1;
- unsigned int use3dlut :1;
- unsigned int less_than_dcip3:1;
- unsigned int override_lum :1;
- unsigned int reseved:8;
+ unsigned int do_chroma_scale:1;
+ unsigned int spec_version :3;
+ unsigned int use_zero_display_black :1;
+ unsigned int use_zero_source_black :1;
+ unsigned int force_display_black:6;
+ unsigned int apply_display_gamma:1;
+ unsigned int exp_shaper_max :6;
+ unsigned int unity_3dlut:1;
+ unsigned int bypass_3dlut :1;
+ unsigned int use_3dlut :1;
+ unsigned int less_than_dcip3:1;
+ unsigned int override_lum :1;
+ unsigned int reseved:8;
} bits;
};
enum tm_show_option_internal {
tm_show_option_internal_single_file = 0,/*flags2 not in
use*/
- tm_show_option_internal_duplicate_file,/*use flags2*/
+ tm_show_option_internal_duplicate_file, /*use flags2*/
tm_show_option_internal_duplicate_sidebyside/*use flags2*/
};
-struct tm3dlut_settings {
+struct lut3d_settings {
unsigned char version;
- union tm3dlut_internal_flags flags;
- union tm3dlut_internal_flags flags2;
+ union lut3d_control_flags flags;
+ union lut3d_control_flags flags2;
enum tm_show_option_internal option;
unsigned int min_lum;/*multiplied by 100*/
unsigned int max_lum;
--
2.20.1
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[PATCH 387/459] drm/amd/display: Add profiling tools for bandwidth validation
From: Joshua Aberback
[Why]
We used this change to investigate the performance of bandwidth validation,
it will be useful to have if we need to investigate further.
[How]
We use performance counter tick numbers to profile performance, they live
at dc->debug.bw_val_profile (set .enable in debugger to turn on measuring).
Signed-off-by: Joshua Aberback
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 371d96290d86..c9b7340c9601 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1912,6 +1912,8 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct
dc_state *context,
{
bool out = false;
+ BW_VAL_TRACE_SETUP();
+
int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
int pipe_split_from[MAX_PIPES];
bool odm_capable = context->bw_ctx.dml.ip.odm_capable;
@@ -1924,6 +1926,8 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct
dc_state *context,
display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count *
sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
DC_LOGGER_INIT(dc->ctx->logger);
+ BW_VAL_TRACE_COUNT();
+
ASSERT(pipes);
if (!pipes)
return false;
@@ -1957,6 +1961,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct
dc_state *context,
pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, >res_ctx,
pipes);
if (!pipe_cnt) {
+ BW_VAL_TRACE_SKIP(pass);
out = true;
goto validate_out;
}
@@ -2117,7 +2122,10 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct
dc_state *context,
}
#endif
+ BW_VAL_TRACE_END_VOLTAGE_LEVEL();
+
if (fast_validate) {
+ BW_VAL_TRACE_SKIP(fast);
out = true;
goto validate_out;
}
@@ -2213,6 +2221,8 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct
dc_state *context,
!=
dm_dram_clock_change_unsupported;
context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
+ BW_VAL_TRACE_END_WATERMARKS();
+
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
if (!context->res_ctx.pipe_ctx[i].stream)
continue;
@@ -2261,11 +2271,14 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct
dc_state *context,
DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
+ BW_VAL_TRACE_SKIP(fail);
out = false;
validate_out:
kfree(pipes);
+ BW_VAL_TRACE_FINISH();
+
return out;
}
--
2.20.1
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[PATCH 389/459] drm/amd/display: add global master update lock for DCN2
From: Wenjing Liu
[why]
when an update programming sequence requires both
front end and back end pipe to be updated synchronously,
a global update lock needs to be set to ensure that
we don't get a frame with only front end update but
not the back end update.
[how]
setup global lock parameters on enable_stream_timing.
enable global lock when pipe_control_lock_global is called.
disable global lock when pipe_control_lock is called.
Signed-off-by: Wenjing Liu
Reviewed-by: Tony Cheng
Signed-off-by: Alex Deucher
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 4 ++
.../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 63 ++-
.../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h | 3 +
.../amd/display/dc/inc/hw/timing_generator.h | 2 +
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 1 +
5 files changed, 72 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index dc34ce28505c..fbcb4d860e7a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -727,6 +727,10 @@ enum dc_status dcn20_enable_stream_timing(
pipe_ctx->stream->signal,
true);
+ if (pipe_ctx->stream_res.tg->funcs->setup_global_lock)
+ pipe_ctx->stream_res.tg->funcs->setup_global_lock(
+ pipe_ctx->stream_res.tg);
+
/* program otg blank color */
color_space = stream->output_color_space;
color_space_to_black_color(dc, color_space, _color);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index 43e71b4ab5e8..ea6a19063b22 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -330,6 +330,65 @@ void optc2_triplebuffer_unlock(struct timing_generator
*optc)
}
+
+void optc2_setup_global_lock(struct timing_generator *optc)
+{
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
+ uint32_t v_blank_start = 0;
+ uint32_t h_blank_start = 0, h_total = 0;
+
+ REG_SET(OTG_GLOBAL_CONTROL1, 0, MASTER_UPDATE_LOCK_DB_EN, 1);
+
+ REG_SET(OTG_GLOBAL_CONTROL2, 0, DIG_UPDATE_LOCATION, 20);
+
+ REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, _blank_start);
+
+ REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, _blank_start);
+
+ REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, _total);
+ REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
+ MASTER_UPDATE_LOCK_DB_X,
+ h_blank_start - 200 - 1,
+ MASTER_UPDATE_LOCK_DB_Y,
+ v_blank_start - 1);
+}
+
+void optc2_lock_global(struct timing_generator *optc)
+{
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+ REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1);
+
+ REG_SET(OTG_GLOBAL_CONTROL0, 0,
+ OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
+ REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+ OTG_MASTER_UPDATE_LOCK, 1);
+
+ /* Should be fast, status does not update on maximus */
+ if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
+ REG_WAIT(OTG_MASTER_UPDATE_LOCK,
+ UPDATE_LOCK_STATUS, 1,
+ 1, 10);
+}
+
+void optc2_lock(struct timing_generator *optc)
+{
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+ REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0);
+
+ REG_SET(OTG_GLOBAL_CONTROL0, 0,
+ OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
+ REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+ OTG_MASTER_UPDATE_LOCK, 1);
+
+ /* Should be fast, status does not update on maximus */
+ if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
+ REG_WAIT(OTG_MASTER_UPDATE_LOCK,
+ UPDATE_LOCK_STATUS, 1,
+ 1, 10);
+}
+
void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
@@ -424,8 +483,10 @@ static struct timing_generator_funcs dcn20_tg_funcs = {
.triplebuffer_lock = optc2_triplebuffer_lock,
.triplebuffer_unlock = optc2_triplebuffer_unlock,
.disable_reset_trigger = optc1_disable_reset_trigger,
- .lock = optc1_lock,
+ .lock = optc2_lock,
.unlock = optc1_unlock,
+ .lock_global = optc2_lock_global,
+ .setup_global_lock = optc2_setup_global_lock,
.lock_doublebuffer_enable = optc2_lock_doublebuffer_enable,
.lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
.enable_optc_clock = optc1_enable_optc_clock,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
[PATCH 388/459] drm/amd/display: Remove REFCYC regs
From: Yongqiang Sun
[Why]
Some register fields are not needed.
[How]
remove them
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
index 9f6858c32b22..9f56c1d2d188 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
@@ -176,11 +176,8 @@
type HUBPREQ_MASTER_UPDATE_LOCK_STATUS;\
type SURFACE_GSL_ENABLE;\
type SURFACE_TRIPLE_BUFFER_ENABLE;\
- type VMID;\
- type REFCYC_PER_VM_GROUP_FLIP;\
- type REFCYC_PER_VM_REQ_FLIP;\
- type REFCYC_PER_VM_GROUP_VBLANK;\
- type REFCYC_PER_VM_REQ_VBLANK
+ type VMID
+
struct dcn_hubp2_registers {
DCN2_HUBP_REG_COMMON_VARIABLE_LIST;
--
2.20.1
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[PATCH 379/459] drm/amd/display: Add some tm3dlut flags
From: Vitaly Prosyak
Move flags from color_gamma.h to mod_shared.h
and add more options and setting structures
Signed-off-by: Vitaly Prosyak
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
Acked-by: Vitaly Prosyak
Signed-off-by: Alex Deucher
---
.../amd/display/modules/color/color_gamma.h | 12 --
.../drm/amd/display/modules/inc/mod_shared.h | 37 +++
2 files changed, 37 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
index c56c203abfcb..369953fafadf 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
@@ -82,18 +82,6 @@ struct freesync_hdr_tf_params {
unsigned int skip_tm; // skip tm
};
-union tm3dlut_flags {
- unsigned int raw;
- struct {
- unsigned int dochroma_scale :1;
- unsigned int spec_version :3;
- unsigned int less_than_dcip3:1;
- unsigned int exp_shaper_max :6;
- unsigned int zero_display_black :1;
- unsigned int reseved:20;
- } bits;
-};
-
void setup_x_points_distribution(void);
void precompute_pq(void);
void precompute_de_pq(void);
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
b/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
index b711e7e6c204..5a631854efda 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
@@ -45,5 +45,42 @@ enum vrr_packet_type {
PACKET_TYPE_VTEM
};
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+union tm3dlut_internal_flags {
+ unsigned int raw;
+ struct {
+ unsigned int dochroma_scale :1;
+ unsigned int spec_version :3;
+ unsigned int use_zero_display_black :1;
+ unsigned int use_zero_source_black :1;
+ unsigned int force_display_black:6;
+ unsigned int apply_display_gamma:1;
+ unsigned int exp_shaper_max :6;
+ unsigned int unity3dlut :1;
+ unsigned int bypass3dlut:1;
+ unsigned int use3dlut :1;
+ unsigned int less_than_dcip3:1;
+ unsigned int override_lum :1;
+ unsigned int reseved:8;
+ } bits;
+};
+
+enum tm_show_option_internal {
+ tm_show_option_internal_single_file = 0,/*flags2 not in
use*/
+ tm_show_option_internal_duplicate_file,/*use flags2*/
+ tm_show_option_internal_duplicate_sidebyside/*use flags2*/
+};
+
+struct tm3dlut_settings {
+ unsigned char version;
+ union tm3dlut_internal_flags flags;
+ union tm3dlut_internal_flags flags2;
+ enum tm_show_option_internal option;
+ unsigned int min_lum;/*multiplied by 100*/
+ unsigned int max_lum;
+ unsigned int min_lum2;
+ unsigned int max_lum2;
+};
+#endif
#endif /* MOD_SHARED_H_ */
--
2.20.1
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[PATCH 373/459] drm/amd/display: fix fpga fclk programming
From: Dmytro Laktyushkin
We shouldnt need overhead on top of dppclk when setting fclk.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 34402dffd2ca..c1511c9edd48 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -249,6 +249,8 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
bool safe_to_lower)
{
struct dc_clocks *new_clocks = >bw_ctx.bw.dcn.clk;
+ /* Min fclk = 1GHz since all the extra scemi logic seems to run off of
it */
+ int fclk_adj = new_clocks->fclk_khz > 100 ? new_clocks->fclk_khz :
100;
if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz,
clk_mgr->clks.phyclk_khz)) {
clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
@@ -275,9 +277,8 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
}
- /* Add 250MHz as safety margin */
- if (should_set_clock(safe_to_lower, new_clocks->fclk_khz + 25,
clk_mgr->clks.fclk_khz)) {
- clk_mgr->clks.fclk_khz = new_clocks->fclk_khz + 25;
+ if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {
+ clk_mgr->clks.fclk_khz = fclk_adj;
}
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz,
clk_mgr->clks.dispclk_khz)) {
@@ -289,6 +290,8 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
*/
if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
+ if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
+ clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
dm_set_dcn_clocks(clk_mgr->ctx, _mgr->clks);
}
--
2.20.1
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[PATCH 380/459] drm/amd/display: DCN2 reg refactors
From: Yongqiang Sun
Added some regs and exposed some functions for future use
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 2 +-
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 47 ---
2 files changed, 42 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
index cabd070bc659..529bdc2f2975 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
@@ -149,7 +149,7 @@ void hubp2_set_vm_system_aperture_settings(struct hubp
*hubp,
SYSTEM_ACCESS_MODE, 0x3);
}
-static void hubp2_program_deadline(
+void hubp2_program_deadline(
struct hubp *hubp,
struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
index ac7ef02450e5..9f6858c32b22 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
@@ -31,7 +31,7 @@
#define TO_DCN20_HUBP(hubp)\
container_of(hubp, struct dcn20_hubp, base)
-#define HUBP_REG_LIST_DCN20(id)\
+#define HUBP_REG_LIST_DCN2_COMMON(id)\
HUBP_REG_LIST_DCN(id),\
HUBP_REG_LIST_DCN_VM(id),\
SRI(PREFETCH_SETTINGS, HUBPREQ, id),\
@@ -64,11 +64,14 @@
SRI(FLIP_PARAMETERS_2, HUBPREQ, id),\
SRI(DCN_CUR1_TTU_CNTL1, HUBPREQ, id),\
SRI(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \
- SRI(VMID_SETTINGS_0, HUBPREQ, id),\
+ SRI(VMID_SETTINGS_0, HUBPREQ, id)
+
+#define HUBP_REG_LIST_DCN20(id)\
+ HUBP_REG_LIST_DCN2_COMMON(id),\
SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB)
-#define HUBP_MASK_SH_LIST_DCN20(mask_sh)\
+#define HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh)\
HUBP_MASK_SH_LIST_DCN(mask_sh),\
HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
@@ -121,7 +124,10 @@
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL,
HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE,
mask_sh),\
- HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
+ HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh)
+
+#define HUBP_MASK_SH_LIST_DCN20(mask_sh)\
+ HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh),\
HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh)
@@ -141,7 +147,11 @@
uint32_t FLIP_PARAMETERS_1;\
uint32_t FLIP_PARAMETERS_2;\
uint32_t DCN_CUR1_TTU_CNTL1;\
- uint32_t VMID_SETTINGS_0
+ uint32_t VMID_SETTINGS_0;\
+ uint32_t FLIP_PARAMETERS_3;\
+ uint32_t FLIP_PARAMETERS_4;\
+ uint32_t VBLANK_PARAMETERS_5;\
+ uint32_t VBLANK_PARAMETERS_6
#define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
DCN_HUBP_REG_FIELD_LIST(type); \
@@ -166,7 +176,11 @@
type HUBPREQ_MASTER_UPDATE_LOCK_STATUS;\
type SURFACE_GSL_ENABLE;\
type SURFACE_TRIPLE_BUFFER_ENABLE;\
- type VMID
+ type VMID;\
+ type REFCYC_PER_VM_GROUP_FLIP;\
+ type REFCYC_PER_VM_REQ_FLIP;\
+ type REFCYC_PER_VM_GROUP_VBLANK;\
+ type REFCYC_PER_VM_REQ_VBLANK
struct dcn_hubp2_registers {
DCN2_HUBP_REG_COMMON_VARIABLE_LIST;
@@ -239,6 +253,27 @@ bool hubp2_is_triplebuffer_enabled(
void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable);
+void hubp2_program_deadline(
+ struct hubp *hubp,
+ struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
+ struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
+
+bool hubp2_program_surface_flip_and_addr(
+ struct hubp *hubp,
+ const struct dc_plane_address *address,
+ bool flip_immediate,
+ uint8_t vmid);
+
+void hubp2_program_surface_config(
+ struct hubp *hubp,
+ enum surface_pixel_format format,
+ union dc_tiling_info *tiling_info,
+ union plane_size *plane_size,
+ enum dc_rotation_angle rotation,
+ struct dc_plane_dcc_param *dcc,
+ bool horizontal_mirror,
+ unsigned int compat_level);
+
#endif /* __DC_MEM_INPUT_DCN20_H__ */
--
2.20.1
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[PATCH 375/459] drm/amd/display: Remove additional FEC link bandwidth reduction
From: Nikola Cornij
[why]
This is now done in the original link bandwidth calculation and DSC
must not do this anymore.
[how]
Remove the line of code that should have been removed when transition
to correctly applying FEC overhead was made.
Signed-off-by: Nikola Cornij
Reviewed-by: Wenjing Liu
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index e71197d35d79..471eb9873885 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -311,19 +311,18 @@ static void get_dsc_bandwidth_range(
*
* Returns:
* - 'true' if DSC was required by policy and was successfully applied
- * - 'false' if DSC was not necessary (e.g. if uncompressed stream fits
'target_bandwidth'),
+ * - 'false' if DSC was not necessary (e.g. if uncompressed stream fits
'target_bandwidth_kbps'),
*or if it couldn't be applied based on DSC policy.
*/
static bool decide_dsc_target_bpp_x16(
const struct dc_dsc_policy *policy,
const struct dsc_enc_caps *dsc_common_caps,
- const int target_bandwidth,
+ const int target_bandwidth_kbps,
const struct dc_crtc_timing *timing,
int *target_bpp_x16)
{
bool should_use_dsc = false;
struct dc_dsc_bw_range range;
- float target_bandwidth_kbps = target_bandwidth * 0.97f; // 3% overhead
for FEC
memset(, 0, sizeof(range));
--
2.20.1
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[PATCH 377/459] drm/amd/display: Use 1/8th DSC target bitrate precision for N4:2:2 and 4:2:0 formats
From: Nikola Cornij [why] On at least some of the devices (e.g. Realtek scaler) we get a black screen if 1/16th precision is used. [how] Work around it by reducing precision to 1/8th for N4:2:2 and 4:2:0 color formats. This is a safe workaround and would have a very mild impact on the quality. The issue is still to be root-caused and fixed correctly. Signed-off-by: Nikola Cornij Reviewed-by: Wenjing Liu Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 471eb9873885..c649f62d183d 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -228,6 +228,10 @@ static bool dc_intersect_dsc_caps( dsc_common_caps->bpp_increment_div = min(dsc_sink_caps->bpp_increment_div, dsc_enc_caps->bpp_increment_div); + // TODO DSC: Remove this workaround for N422 and 420 once it's fixed, or move it to get_dsc_encoder_caps() + if (pixel_encoding == PIXEL_ENCODING_YCBCR422 || pixel_encoding == PIXEL_ENCODING_YCBCR420) + dsc_common_caps->bpp_increment_div = min(dsc_common_caps->bpp_increment_div, (uint32_t)8); + return true; } -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 372/459] drm/amd/display: remove target_dpp hack for dsc
From: Wenjing Liu
Remove dc_dsc hack for MST policy
Signed-off-by: Wenjing Liu
Reviewed-by: Nikola Cornij
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 27 +
1 file changed, 6 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index fe63af836f1e..e71197d35d79 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -490,7 +490,7 @@ static int fit_num_slices_up(union dsc_enc_slice_caps
slice_caps, int num_slices
* dsc_enc_caps- DSC encoder capabilities
*
* target_bandwidth- Target bandwidth to fit the stream into.
- * If 0, use maximum compression as per DSC policy.
+ * If 0, do not calculate target bpp.
*
* timing - The stream timing to fit into 'target_bandwidth' or
apply
* maximum compression to, if 'target_badwidth == 0'
@@ -517,7 +517,6 @@ static bool setup_dsc_config(
int slice_width;
int target_bpp;
int sink_per_slice_throughput;
- // TODO DSC: See if it makes sense to use 2.4% for SST
bool is_dsc_possible = false;
int num_slices_v;
int pic_height;
@@ -534,20 +533,11 @@ static bool setup_dsc_config(
if (target_bandwidth > 0) {
is_dsc_possible = decide_dsc_target_bpp_x16(_policy,
_common_caps, target_bandwidth, timing, _bpp);
- } else if (timing->pix_clk_100hz * 12 <=
dc_bandwidth_in_kbps_from_timing(timing) * 10) {
- /* use 12 target bpp for MST display
-* TODO: implement new MST DSC target bpp policy */
- target_bpp = 16*12;
- is_dsc_possible = true;
- } else {
- is_dsc_possible = false;
+ dsc_cfg->bits_per_pixel = target_bpp;
}
-
if (!is_dsc_possible)
goto done;
- dsc_cfg->bits_per_pixel = target_bpp;
-
sink_per_slice_throughput = 0;
// Validate available DSC settings against the mode timing
@@ -773,18 +763,13 @@ bool dc_dsc_compute_config(
struct dc_dsc_config *dsc_cfg)
{
bool is_dsc_possible = false;
-
struct dsc_enc_caps dsc_enc_caps;
- struct dsc_enc_caps dsc_common_caps;
get_dsc_enc_caps(dc, _enc_caps, timing->pix_clk_100hz);
- is_dsc_possible = dc_intersect_dsc_caps(dsc_sink_caps, _enc_caps,
- timing->pixel_encoding, _common_caps);
- if (is_dsc_possible)
- is_dsc_possible = setup_dsc_config(dsc_sink_caps,
- _enc_caps,
- target_bandwidth,
- timing, dsc_cfg);
+ is_dsc_possible = setup_dsc_config(dsc_sink_caps,
+ _enc_caps,
+ target_bandwidth,
+ timing, dsc_cfg);
return is_dsc_possible;
}
#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */
--
2.20.1
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[PATCH 364/459] drm/amd/display: clean up validation failure log spam
From: Dmytro Laktyushkin
Currently dcn2+ validation will unconditionally print a failure
reason before validation completes. This change categorizes the
failure reason as a warning log and only prints at the end of
validation resolving false positives.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Nikola Cornij
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c| 3 +++
.../gpu/drm/amd/display/dc/dml/display_mode_vba.c| 12 +---
2 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index e2a6e80013f3..49114d823240 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1880,6 +1880,7 @@ bool dcn20_validate_bandwidth(struct dc *dc,
int split_threshold = dc->res_pool->pipe_count / 2;
bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count *
sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
+ DC_LOGGER_INIT(dc->ctx->logger);
ASSERT(pipes);
if (!pipes)
@@ -2183,6 +2184,8 @@ bool dcn20_validate_bandwidth(struct dc *dc,
return true;
validate_fail:
+ DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
+
dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
kfree(pipes);
return false;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 3560319a5c6f..7f3ea740bfe8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -73,17 +73,7 @@ unsigned int dml_get_voltage_level(
fetch_pipe_params(mode_lib);
PixelClockAdjustmentForProgressiveToInterlaceUnit(mode_lib);
}
- mode_lib->funcs.validate(mode_lib);
-
- /* check if Mode Support Validation failed */
- if (mode_lib->vba.VoltageLevel > mode_lib->vba.soc.num_states) {
- /* get the validation status for highest voltage level and
output console message */
- enum dm_validation_status status =
mode_lib->vba.ValidationStatus[mode_lib->vba.soc.num_states];
- if (status != DML_FAIL_PITCH_SUPPORT) {
- /*AlignedYPitch is based on swizzle mode, so it is
normal if some swizzle mode not supported*/
- dm_output_to_console("Mode Validation Error: %s failed
validation.\n", dml_get_status_message(status));
- }
- }
+ mode_lib->funcs.validate(mode_lib);
return mode_lib->vba.VoltageLevel;
}
--
2.20.1
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[PATCH 362/459] drm/amd/display: Clean up locking in dcn*_apply_ctx_for_surface()
From: Leo Li
[Why]
dcn*_disable_plane() doesn't unlock the pipe anymore, making the extra
lock unnecessary.
In addition - during full plane updates - all necessary pipes should be
locked/unlocked together when modifying hubp to avoid tearing in
pipesplit setups.
[How]
Remove redundant locks, and add function to lock all pipes. If an
interdependent pipe update is required, lock down all pipes. Otherwise,
lock only the top pipe for the updated pipe tree.
Signed-off-by: Leo Li
Acked-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 11 ++---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 46 +++
2 files changed, 22 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 704de7369e86..a2d3c4fdc805 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2456,6 +2456,11 @@ static void dcn10_apply_ctx_for_surface(
if (num_planes > 0)
program_all_pipe_in_tree(dc, top_pipe_to_program, context);
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /* Program secondary blending tree and writeback pipes */
+ if ((stream->num_wb_info > 0) &&
(dc->hwss.program_all_writeback_pipes_in_tree))
+ dc->hwss.program_all_writeback_pipes_in_tree(dc, stream,
context);
+#endif
if (interdependent_update)
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx =
>res_ctx.pipe_ctx[i];
@@ -2470,12 +2475,6 @@ static void dcn10_apply_ctx_for_surface(
_ctx->ttu_regs);
}
-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
- /* Program secondary blending tree and writeback pipes */
- if ((stream->num_wb_info > 0) &&
(dc->hwss.program_all_writeback_pipes_in_tree))
- dc->hwss.program_all_writeback_pipes_in_tree(dc, stream,
context);
-#endif
-
if (interdependent_update)
lock_all_pipes(dc, context, false);
else
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index f2e5e4928119..ccb9f277911a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1270,8 +1270,6 @@ static void dcn20_pipe_control_lock(
}
}
-
-
static void dcn20_apply_ctx_for_surface(
struct dc *dc,
const struct dc_stream_state *stream,
@@ -1282,6 +1280,7 @@ static void dcn20_apply_ctx_for_surface(
int i;
struct timing_generator *tg;
bool removed_pipe[6] = { false };
+ bool interdependent_update = false;
struct pipe_ctx *top_pipe_to_program =
find_top_pipe_for_stream(dc, context, stream);
DC_LOGGER_INIT(dc->ctx->logger);
@@ -1291,7 +1290,13 @@ static void dcn20_apply_ctx_for_surface(
tg = top_pipe_to_program->stream_res.tg;
- dcn20_pipe_control_lock(dc, top_pipe_to_program, true);
+ interdependent_update = top_pipe_to_program->plane_state &&
+ top_pipe_to_program->plane_state->update_flags.bits.full_update;
+
+ if (interdependent_update)
+ lock_all_pipes(dc, context, true);
+ else
+ dcn20_pipe_control_lock(dc, top_pipe_to_program, true);
if (num_planes == 0) {
/* OTG blank before remove all front end */
@@ -1311,16 +1316,9 @@ static void dcn20_apply_ctx_for_surface(
*/
if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
if (old_pipe_ctx->stream_res.tg == tg &&
- old_pipe_ctx->plane_res.hubp &&
- old_pipe_ctx->plane_res.hubp->opp_id != 0xf) {
+ old_pipe_ctx->plane_res.hubp &&
+ old_pipe_ctx->plane_res.hubp->opp_id != 0xf)
dcn20_disable_plane(dc, old_pipe_ctx);
-
- /*
-* power down fe will unlock when calling
reset, need
-* to lock it back here. Messy, need rework.
-*/
-
pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
- }
}
if ((!pipe_ctx->plane_state ||
@@ -1343,35 +1341,25 @@ static void dcn20_apply_ctx_for_surface(
if ((stream->num_wb_info > 0) &&
(dc->hwss.program_all_writeback_pipes_in_tree))
dc->hwss.program_all_writeback_pipes_in_tree(dc, stream,
context);
- dcn20_pipe_control_lock(dc, top_pipe_to_program, false);
-
- if (top_pipe_to_program->plane_state &&
-
[PATCH 384/459] drm/amd/display: Guard DML_FAIL_DSC_VALIDATION_FAILURE
From: Leo Li
[Why]
Usage of this enum is DSC-only.
[How]
Guard it with CONFIG_DRM_AMD_DC_DSC_SUPPORT.
Signed-off-by: Leo Li
Reviewed-by: Harry Wentland
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
index e8da21f04454..2a65af31eaa9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
@@ -130,7 +130,9 @@ enum dm_validation_status {
DML_FAIL_DIO_SUPPORT,
DML_FAIL_NOT_ENOUGH_DSC,
DML_FAIL_DSC_CLK_REQUIRED,
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
DML_FAIL_DSC_VALIDATION_FAILURE,
+#endif
DML_FAIL_URGENT_LATENCY,
DML_FAIL_REORDERING_BUFFER,
DML_FAIL_DISPCLK_DPPCLK,
--
2.20.1
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[PATCH 363/459] drm/amd/display: fixed DCC corruption
From: Bob Yang [Description] swath_bytes_horz_wc should be 256/64/64 for 2160p 32bpp surface Signed-off-by: Bob Yang Reviewed-by: Charlene Liu Acked-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c index 09e8d10a7a01..b3a99b10cfbd 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c @@ -194,8 +194,8 @@ static void hubbub2_det_request_size( hubbub2_get_blk256_size(_width, _height, bpe); - swath_bytes_horz_wc = height * blk256_height * bpe; - swath_bytes_vert_wc = width * blk256_width * bpe; + swath_bytes_horz_wc = width * blk256_height * bpe; + swath_bytes_vert_wc = height * blk256_width * bpe; *req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ? false : /* full 256B request */ -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 365/459] drm/amd/display: Add a flags union for 3dlut transformation matrix
From: Vitaly Prosyak
[Why & How]
When TM is enabled with 3dlut, we apply conversion to
dcip3 in gamut remap matrix, if source area less than
dcip3. If it is bigger, we remap to bt2020. The added
flags will be used to facilitate this logic.
Signed-off-by: Vitaly Prosyak
Reviewed-by: Aric Cyr
Acked-by: Krunoslav Kovac
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/modules/color/color_gamma.h | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
index 369953fafadf..c56c203abfcb 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
@@ -82,6 +82,18 @@ struct freesync_hdr_tf_params {
unsigned int skip_tm; // skip tm
};
+union tm3dlut_flags {
+ unsigned int raw;
+ struct {
+ unsigned int dochroma_scale :1;
+ unsigned int spec_version :3;
+ unsigned int less_than_dcip3:1;
+ unsigned int exp_shaper_max :6;
+ unsigned int zero_display_black :1;
+ unsigned int reseved:20;
+ } bits;
+};
+
void setup_x_points_distribution(void);
void precompute_pq(void);
void precompute_de_pq(void);
--
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[PATCH 369/459] drm/amd/display: fix dsc validation
From: Dmytro Laktyushkin
Currently dsc is validated not taking the image width limitation into
mind.
This change addresses that, but due to previous design being limited
to non odm dsc validation additional sequence changes are made.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Nikola Cornij
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 5 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h | 2 +
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 91 +++
.../drm/amd/display/dc/dcn20/dcn20_resource.h | 1 -
.../amd/display/dc/dml/display_mode_enums.h | 1 +
5 files changed, 60 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index 4865cc341dec..be49fc7f4abe 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -91,6 +91,8 @@ void dsc2_construct(struct dcn20_dsc *dsc,
dsc->dsc_regs = dsc_regs;
dsc->dsc_shift = dsc_shift;
dsc->dsc_mask = dsc_mask;
+
+ dsc->max_image_width = 5184;
}
@@ -161,6 +163,9 @@ static bool dsc2_validate_stream(struct
display_stream_compressor *dsc, const st
{
struct dsc_optc_config dsc_optc_cfg;
+ if (dsc_cfg->pic_width > TO_DCN20_DSC(dsc)->max_image_width)
+ return false;
+
return dsc_prepare_config(dsc, dsc_cfg, _optc_cfg);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
index 5cbb9df8272f..168865a16288 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
@@ -558,6 +558,8 @@ struct dcn20_dsc {
const struct dcn20_dsc_mask *dsc_mask;
struct dsc_reg_values reg_vals;
+
+ int max_image_width;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 7aa2859b35fc..33f1a1d972a9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1869,6 +1869,38 @@ void dcn20_set_mcif_arb_params(
}
}
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
+{
+ int i;
+
+ /* Validate DSC config, dsc count validation is already done */
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx = _ctx->res_ctx.pipe_ctx[i];
+ struct dc_stream_state *stream = pipe_ctx->stream;
+ struct dsc_config dsc_cfg;
+
+ /* Only need to validate top pipe */
+ if (pipe_ctx->top_pipe || !stream || !stream->timing.flags.DSC)
+ continue;
+
+ dsc_cfg.pic_width = stream->timing.h_addressable +
stream->timing.h_border_left
+ + stream->timing.h_border_right;
+ dsc_cfg.pic_height = stream->timing.v_addressable +
stream->timing.v_border_top
+ + stream->timing.v_border_bottom;
+ if (dc_res_get_odm_bottom_pipe(pipe_ctx))
+ dsc_cfg.pic_width /= 2;
+ dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
+ dsc_cfg.color_depth = stream->timing.display_color_depth;
+ dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
+
+ if
(!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc,
_cfg))
+ return false;
+ }
+ return true;
+}
+#endif
+
bool dcn20_validate_bandwidth(struct dc *dc,
struct dc_state *context,
bool fast_validate)
@@ -1877,6 +1909,9 @@ bool dcn20_validate_bandwidth(struct dc *dc,
int pipe_split_from[MAX_PIPES];
bool odm_capable = context->bw_ctx.dml.ip.odm_capable;
bool force_split = false;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool failed_non_odm_dsc = false;
+#endif
int split_threshold = dc->res_pool->pipe_count / 2;
bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count *
sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
@@ -1920,6 +1955,15 @@ bool dcn20_validate_bandwidth(struct dc *dc,
vlevel = dml_get_voltage_level(>bw_ctx.dml, pipes, pipe_cnt);
context->bw_ctx.dml.ip.odm_capable = odm_capable;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* 1 dsc per stream dsc validation */
+ if (vlevel <= context->bw_ctx.dml.soc.num_states)
+ if (!dcn20_validate_dsc(dc, context)) {
+ failed_non_odm_dsc = true;
+ vlevel = context->bw_ctx.dml.soc.num_states + 1;
+ }
+#endif
+
if (vlevel >
[PATCH 382/459] drm/amd/display: fix can not turn on two displays due to DSC_RESOURCE failed.
From: Charlene Liu
[Why]
Can not turn on two displays at the same time with the asic having only one DSC.
DC_DSC_RESOURCE allocation failed.
[Solution]
Only add_dsc if the timing is dsc capable based on diag_dc and num_dsc
Signed-off-by: Charlene Liu
Reviewed-by: Wesley Chalmers
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index dc3aa7debad5..e3cd3e3db2c4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1284,6 +1284,12 @@ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc,
struct dc_state *new_ctx,
if (pipe_ctx->stream != dc_stream)
continue;
+ if (IS_DIAG_DC(dc->ctx->dce_environment) ||
+ dc->res_pool->res_cap->num_dsc == 1) {
+ // Diags build can also run on platforms that
have fewer DSCs than pipes.
+ // In that case, add DSC only if needed by
timing.
+ is_add_dsc = (dc_stream->timing.flags.DSC == 1);
+ }
if (is_add_dsc) {
pipe_ctx->stream_res.dsc =
acquire_dsc(_ctx->res_ctx, pool);
--
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[PATCH 353/459] drm/amd/display: Add writeback_config to VBA vars
From: Ilya Bakoulin
Adding writeback_config enum to vba_vars_st, replacing old flag.
Initialize to dm_normal.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Charlene Liu
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 1 +
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 2 +-
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 +
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 139a8740c070..5678472546ab 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -152,6 +152,7 @@ struct _vcs_dpi_ip_params_st {
unsigned int writeback_line_buffer_luma_buffer_size;
unsigned int writeback_line_buffer_chroma_buffer_size;
#endif
+
unsigned int max_page_table_levels;
unsigned int max_num_dpp;
unsigned int max_num_otg;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index e5e4c4ba9011..3560319a5c6f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -306,7 +306,6 @@ static void fetch_ip_params(struct display_mode_lib
*mode_lib)
mode_lib->vba.WritebackInterfaceBufferSize =
ip->writeback_interface_buffer_size_kbytes;
mode_lib->vba.WritebackLineBufferSize =
ip->writeback_line_buffer_buffer_size;
-
mode_lib->vba.WritebackSupportInterleaveAndUsingWholeBufferForASingleStream =
false;
mode_lib->vba.MinVoltageLevel = 0;
mode_lib->vba.MaxVoltageLevel = 5;
@@ -323,6 +322,7 @@ static void fetch_ip_params(struct display_mode_lib
*mode_lib)
mode_lib->vba.WritebackMinVSCLRatio = ip->writeback_min_vscl_ratio;
mode_lib->vba.WritebackMaxHSCLTaps = ip->writeback_max_hscl_taps;
mode_lib->vba.WritebackMaxVSCLTaps = ip->writeback_max_vscl_taps;
+ mode_lib->vba.WritebackConfiguration = dm_normal;
mode_lib->vba.GPUVMMaxPageTableLevels = ip->gpuvm_max_page_table_levels;
mode_lib->vba.HostVMMaxNonCachedPageTableLevels =
ip->hostvm_max_page_table_levels;
mode_lib->vba.HostVMMaxPageTableLevels =
ip->hostvm_max_page_table_levels;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index d488c05131f9..38fc0ab32d7b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -237,6 +237,7 @@ struct vba_vars_st {
unsigned int WritebackInterfaceLumaBufferSize;
unsigned int WritebackInterfaceChromaBufferSize;
unsigned int WritebackChromaLineBufferWidth;
+ enum writeback_config WritebackConfiguration;
double MaxDCHUBToPSCLThroughput;
double MaxPSCLToLBThroughput;
unsigned int PTEBufferSizeInRequestsLuma;
--
2.20.1
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