[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Le Ma
Regards,
Ma Le
-Original Message-
From: Andrey Grodzovsky
Sent: Thursday, December 12, 2019 4:39 AM
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Ma, Le ;
Zhang,
[AMD Official Use Only - Internal Distribution Only]
-Original Message-
From: Andrey Grodzovsky
Sent: Thursday, December 12, 2019 4:39 AM
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Ma, Le ;
Zhang, Hawking ; Quan, Evan ;
Grodzovsky,
[AMD Official Use Only - Internal Distribution Only]
-Original Message-
From: Andrey Grodzovsky
Sent: Thursday, December 12, 2019 4:39 AM
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Ma, Le ;
Zhang, Hawking ; Quan, Evan ;
Grodzovsky,
[AMD Official Use Only - Internal Distribution Only]
-Original Message-
From: Andrey Grodzovsky
Sent: Thursday, December 12, 2019 4:39 AM
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Ma, Le ;
Zhang, Hawking ; Quan, Evan ;
Grodzovsky,
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Le Ma
Regards,
Ma Le
-Original Message-
From: Andrey Grodzovsky
Sent: Thursday, December 12, 2019 4:39 AM
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Ma, Le ;
Zhang,
Hi Christian,
Alex started trying to invalidate PTEs in the MMU notifiers and we're
finding that we still need to reserve the VM reservation for
amdgpu_sync_resv in amdgpu_vm_sdma_prepare. Is that sync_resv still
needed now, given that VM fences aren't in that reservation object any more?
The log will be useful for easily getting the CU info on various
emulation models or ASICs.
Change-Id: Ic1c914938aa3445d8dbfdf6a237bc1d58b0d5267
Signed-off-by: Yong Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
Hi Dave, Daniel,
Kicking off 5.6 with new stuff from AMD. There is a UAPI addition. We
added a new firmware for display, and this just adds the version query
to our existing firmware query interface. UMDs like mesa use this interface to
query things like CP or UVD firmware versions to see what
On Wed, Dec 11, 2019 at 3:26 PM Yong Zhao wrote:
>
> The log will be useful for easily getting the CU info on various
> emulation models or ASICs.
>
You can probably just put this all in once place at the end of init
rather than sprinkling the print statements across all the IP modules.
Also,
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 4
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 61d13d8..5cf920d
This is to avoid queueing jobs to same CPU during XGMI hive reset
because there is a strict timeline for when the reset commands
must reach all the GPUs in the hive.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 insertion(+), 1
Use task barrier in XGMI hive to synchronize ASIC resets
across devices in XGMI hive.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 42 +-
1 file changed, 36 insertions(+), 6 deletions(-)
diff --git
It is used to synchronize N threads at a rendevouz point before execution
of critical code that has to be started by all the threads at approximatly
the same time.
Signed-off-by: Andrey Grodzovsky
---
include/drm/task_barrier.h | 106 +
1 file
In preparation for doing XGMI reset synchronization using task barrier.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 76 +-
2 files changed, 12 insertions(+), 66 deletions(-)
The log will be useful for easily getting the CU info on various
emulation models or ASICs.
Change-Id: Ic1c914938aa3445d8dbfdf6a237bc1d58b0d5267
Signed-off-by: Yong Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 ++
On Wed, Dec 11, 2019 at 3:07 PM Andrey Grodzovsky
wrote:
>
> It is used to synchronize N threads at a rendevouz point before execution
> of critical code that has to be started by all the threads at approximatly
> the same time.
>
> Signed-off-by: Andrey Grodzovsky
You should resend to
In preparation for doing XGMI reset synchronization using task barrier.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 76 +-
2 files changed, 12 insertions(+), 66 deletions(-)
It is used to synchronize N threads at a rendevouz point before execution
of critical code that has to be started by all the threads at approximatly
the same time.
Signed-off-by: Andrey Grodzovsky
---
include/drm/task_barrier.h | 106 +
1 file
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 4
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 61d13d8..5cf920d
This is to avoid queueing jobs to same CPU during XGMI hive reset
because there is a strict timeline for when the reset commands
must reach all the GPUs in the hive.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 insertion(+), 1
Use task barrier in XGMI hive to synchronize ASIC resets
across devices in XGMI hive.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 42 +-
1 file changed, 36 insertions(+), 6 deletions(-)
diff --git
This patch is
Reviewed-by: Boyuan Zhang
-Original Message-
From: amd-gfx On Behalf Of Leo Liu
Sent: December 11, 2019 2:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Leo
Subject: [PATCH] drm/amdgpu: add JPEG check to VCN idle handler and begin use
Since it's only needed with
On Wed, Dec 11, 2019 at 2:49 PM Leo Liu wrote:
>
> Since it's only needed with VCN1.0 when HW has no its
> own JPEG HW IP block
typo "HW does not have its own"
With that fixed:
Reviewed-by: Alex Deucher
>
> Signed-off-by: Leo Liu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 29
Since it's only needed with VCN1.0 when HW has no its
own JPEG HW IP block
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 29 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 ++
2 files changed, 20 insertions(+), 11 deletions(-)
diff --git
This reverts commit f2efc6e60089c99c342a6b7da47f1037e06c4296.
This was fixed properly for 5.5, but came back via 5.4 merge
into drm-next, so revert it again.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff
Hi,
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.4.2, v5.3.15, v4.19.88, v4.14.158,
v4.9.206, v4.4.206.
v5.4.2: Failed to
Rename to SECURE to align with the CS flag naming.
Signed-off-by: Alex Deucher
---
Several other teams thought it would be cleaner to call it SECURE
since it aligns better with the CS interface. I don't have a
strong opinion either way.
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 6 +++---
Am 11.12.19 um 16:33 schrieb Alex Deucher:
amdgpu is MIT licensed.
Fixes: ec8f24b7faaf3d ("treewide: Add SPDX license identifier -
Makefile/Kconfig")
Signed-off-by: Alex Deucher
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/acp/Kconfig | 2 +-
From: Roman Li
[Why]
The earlier change: "check phy dpalt lane count config"
uses link encoder registers not defined properly.
That caused regression with mst-enabled display not
lighting up.
[How]
Add missing reg definitions.
Signed-off-by: Roman Li
---
entity should not keep copy and maintain sched list for
itself.
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/scheduler/sched_entity.c | 19 ---
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/scheduler/sched_entity.c
drm_sched_entity_init() takes drm gpu scheduler list instead of
drm_sched_rq list. This makes conversion of drm_sched_rq list
to drm gpu scheduler list unnecessary
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
This sched array can be passed on to entity creation routine
instead of manually creating such sched array on every context creation.
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 113 +
Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a
From: abdoulaye berthe
[Why]
DCN21 and DCN2 extended timeout support cap is not set correctly.
[How]
Set extended timeout support for ASIC families to their right values.
Signed-off-by: abdoulaye berthe
Reviewed-by: Martin Leung
Acked-by: Rodrigo Siqueira
---
From: Hugo Hu
Signed-off-by: Hugo Hu
Reviewed-by: Abdoulaye Berthe
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
From: Josip Pavic
[Why]
When the global variable pow_buffer_ptr is set to -1, by definition
optimizations should not be used to build the regamma. Since
translate_from_linear_space unconditionally increments this global, it
inadvertently enables the optimization.
[How]
Increment pow_buffer_ptr
From: Eric Yang
[Why]
Need previously implemented chroma vp wa to work for rotation cases.
[How]
Implement rotation specific wa.
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 3 +-
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
From: Noah Abradjian
[Why]
Currently, pipe resources are assigned to an index that matches the pipe
position.
However, if pipe 1 or 2 is disabled, there will be a gap in the arrays which
causes a crash when iterating based on pipe_count.
[How]
Fix resource construct to assign resources to
From: Sung Lee
[Why]
A corner case currently exists where DPP DTO is lowered before
pipes are updated to a higher viewport. This causes underflow
as the DPPCLK is too low for the current viewport.
[How]
Only lower DPP DTO when it is safe to lower, or if
the newer clocks are higher than the
From: Anthony Koo
[Why]
eDP is internal link and link loss is unexpected.
It is typically going to be PSR related errors, which is
handled separately.
[How]
Check for eDP and skip check for link loss
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
---
From: Jun Lei
[why]
DAL3 should support SRIOV
[how]
Add support for the virtual dal flag. This flag should skip
most/all of DC construction since the HW isn't accessible, but
still construct WindowsDM (almost) normally but with only SW display
targets
Signed-off-by: Jun Lei
Reviewed-by: Aric
From: Samson Tam
[Why]
When we rotate 270 in mixed SLS mode, the recouts occupy the
right side of the display. So all the recout_skip_v values
are relative to the left side of the display. This causes
adjust_vp_and_init_for_seamless_clip() to incorrectly increase
the data->viewport.height for
From: Derek Lai
[Why]
After read the 3rd Edid blocks, we will reset segment to 0,
which causes this VR fail to read Edid successfully.
[How]
Skip to reset segment to 0 for this VR device.
Signed-off-by: Derek Lai
Reviewed-by: Aric Cyr
Acked-by: Anthony Koo
Acked-by: Rodrigo Siqueira
---
From: Aric Cyr
Fix manual trigger source correctly be TRIGA for DCN2
rather than MANUAL_FLOW.
Signed-off-by: Aric Cyr
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 8 +---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h | 1
From: Nicholas Kazlauskas
[Why]
CW0 and CW1 need to use physical addressing mode for dcn20 and dcn21.
The current code for dcn20 is using virtual.
[How]
We already program the DMCUB like this on dcn21 so we should just use
the same sequence for both.
Copy the dcn21 sequences into the
From: Paul Hsieh
[Why]
1. Set second screen only then unplug external monitor
2. Enter to S4 then plug in external monitor
3. Resume from S4, eDP will not turn off when OS set
second screen only
Sometimes OS will not set eDP power up cause eDP dpms_off
keep true then driver skipp disable
From: Nikola Cornij
[why]
Up to 4 ODM memory pieces are required per ODM combine and cannot
overlap, i.e. each ODM "session" has to use its own memory pieces.
The ODM-memory mapping is currently broken for generic case.
The maximum number of memory pieces is ASIC-dependent, but it's always
big
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Sung Lee
[Why]
Previous formula for calculating DPP CLK DTO was
hard to understand.
[How]
Replace with easier to understand formula that produces
same results.
Signed-off-by: Sung Lee
Reviewed-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Rodrigo Siqueira
---
From: Nikola Cornij
[why]
It's required for debug purposes.
[how]
Add a dsc_bpp_increment_div debug option that overrides DPCD
BITS_PER_PIXEL_INCREMENT value. The value dsc_bpp_increment_div should
be set to is the one after parsing, i.e. it could be 1, 2, 4, 8 or 16
(meaning 1pix, 1/2pix, ...,
From: Samson Tam
[Why]
Cursor disappears for some SLS displays that are rotated 180
and 270 degrees. This occurs when there is no pipe split being
done ( ex. 3 or more displays ). The cursor calculations assume
pipe splitting is done so when it calculates the new cursor
position in
From: Dale Zhao
[Why]:
According to eDP spec, max T7 delay should be 50 ms. Current code uses 300
retry counters may not be accurate enough for different panels.
[How]:
Use absolute time stamp to achive accurate delay.
Signed-off-by: Dale Zhao
Reviewed-by: Anthony Koo
Acked-by: Rodrigo
From: Sung Lee
[Why]
Previously update_bw_bounding_box for RN was commented out
due to incorrect values causing BSOD on Hybrid Graphics.
However, commenting out this function also may cause issues
such as underflow in certain cases such as 2x4K displays.
[How]
Fix dram_speed_mts calculations.
From: Roman Li
[Why]
Some 10bit eDP panels don't lightup after we cap bpc to 8.
[How]
Set default max_bpc to 16 for edp connector type.
Signed-off-by: Roman Li
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++---
1
From: Noah Abradjian
[Why]
There is one opp per pipe. For certain RN parts, the fourth pipe is disabled,
so there is no opp for it.
res_cap->num_opp is hardcoded to 4, so if we use that to iterate over opps we
will crash.
[How]
Use the pipe_count value instead, which is not hardcoded and so
From: Noah Abradjian
[Why]
Lack of proper timing caused intermittent underflow on unplug external DP.
A previous fix was invalid and caused S0i3 regression, so had to be reverted.
[How]
When unlocking pipe, wait for no pipes to have flip pending before unlocking.
Signed-off-by: Noah Abradjian
From: Nicholas Kazlauskas
[Why]
The DMUB is put into reset on suspend and is not running on resume,
disabling PSR/ABM features.
[How]
Move the allocation of the framebuffer to sw_init.
Do DMUB hardware init and framebuffer filling only from hw_init.
On resume the contents of the framebuffer
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Fixes on DCN2, bounding box calcs, regamma, and other;
* Enhancements in DMUB;
* Improvements on DCN20/21, freesync, DSC and others.
Aidan Yang (1):
drm/amd/display: Disable integerscaling for downscale and MPO
From: Joshua Aberback
[Why]
For some use cases we need to be able to adjust the maximum target bpp
allowed by DSC policy.
[How]
New interface dc_dsc_policy_set_max_target_bpp_limit
Signed-off-by: Joshua Aberback
Reviewed-by: Nikola Cornij
Acked-by: Rodrigo Siqueira
---
From: Charlene Liu
Add warmup escape support, for diags, in a way that is possible to
choose a new or an existing sequence. For achieving this goal, this
commit adds separated MCIF buffer as VCN request.
Signed-off-by: Charlene Liu
Reviewed-by: Chris Park
Acked-by: Rodrigo Siqueira
---
From: Amanda Liu
[why]
We want to streamline the calculations made when entering LFC.
Previously, the optimizations led to screen tearing and were backed out
to unblock development.
[how]
Integrate deflicker window calculations as well as screen tearing fixes
with the original LFC calculation
From: Nicholas Kazlauskas
[Why]
Firmware state and tracebuffer shouldn't be considered stable API
between firmware versions.
Driver shouldn't be querying anything from firmware state or tracebuffer
outside of debugging.
Commands are the stable API for this once we have the outbox.
[How]
Add
From: Noah Abradjian
[Why]
In certain instances, there was a reliance on pipe indexing being accurate.
However, this
assumption fails with harvesting of pipes 1 or 2, which can occur in production
B6 parts.
HW hang would occur as a result.
[How]
Use hubp index for mpcc, and do mpc_init for
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
amdgpu is MIT licensed.
Fixes: ec8f24b7faaf3d ("treewide: Add SPDX license identifier -
Makefile/Kconfig")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/acp/Kconfig | 2 +-
drivers/gpu/drm/amd/amdgpu/Kconfig| 2 +-
drivers/gpu/drm/amd/amdkfd/Kconfig|
From: Aric Cyr
[Why]
Scaling better handled by upper layers before pipe splitting.
[How]
Remove DC code for integer scaling and force cursor update if
viewport or scaling changes occur to prevent underflow from
invalid cursor position.
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by:
From: Nicholas Kazlauskas
[Why]
These values can differ per ASIC and should follow the full DC style
register programming model.
[How]
Define a common list and fill in the common list separately for
dcn20 and dcn21.
Unlike DC we're not using designated initializers for better compiler
From: Qingqing Zhuo
YQ should be limited range for all cases.
Signed-off-by: Qingqing Zhuo
Reviewed-by: Charlene Liu
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Camille Cho
[Why]
A hardcoded number is used today
[How]
Add definition for number of BL data points
Signed-off-by: Camille Cho
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dm_services_types.h | 3 ++-
1 file changed, 2 insertions(+), 1
From: abdoulaye berthe
Signed-off-by: abdoulaye berthe
Reviewed-by: George Shen
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
From: Aidan Yang
[Why]
Integer scaling is applied to MPO planes when downscaling,
MPO planes use variable taps and integer scaling sets taps=1
[How]
Disable integer scaling on MPO planes,
Disable integer scaling for downscaling planes
Signed-off-by: Aidan Yang
Reviewed-by: Aric Cyr
Acked-by:
On Wed, Dec 11, 2019 at 8:07 AM Christian König
wrote:
>
> Am 11.12.19 um 03:26 schrieb zhoucm1:
> >
> > On 2019/12/11 上午6:08, Alex Deucher wrote:
> >> Add a safety check to runtime suspend to make sure all outstanding
> >> fences have signaled before we suspend. Doesn't fix any known issue.
>
On Wed, Dec 11, 2019 at 5:27 AM Simon Ser wrote:
>
> This makes it easier to figure out whether the kernel parameter has been
> taken into account.
>
> Signed-off-by: Simon Ser
> Cc: Harry Wentland
> Cc: Alex Deucher
Applied. thanks.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
entity should not keep copy and maintain sched list for
itself.
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/scheduler/sched_entity.c | 19 ---
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/scheduler/sched_entity.c
Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a
drm_sched_entity_init() takes drm gpu scheduler list instead of
drm_sched_rq list. This makes conversion of drm_sched_rq list
to drm gpu scheduler list unnecessary
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
This sched array can be passed on to entity creation routine
instead of manually creating such sched array on every context creation.
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 113 +
Great! I will update the patches to also use the barrier in PSP MODE 1
reset case and resend the patches for formal review.
Andrey
On 12/11/19 7:18 AM, Ma, Le wrote:
[AMD Official Use Only - Internal Distribution Only]
I tried your new patches to run BACO for about 10 loops and the result
Am 11.12.19 um 03:26 schrieb zhoucm1:
On 2019/12/11 上午6:08, Alex Deucher wrote:
Add a safety check to runtime suspend to make sure all outstanding
fences have signaled before we suspend. Doesn't fix any known issue.
We already do this via the fence driver suspend function, but we
just force
Am 10.12.19 um 19:17 schrieb Nirmoy Das:
entity should not keep copy and maintain sched list for
itself.
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/scheduler/sched_entity.c | 19 ---
1 file changed, 4 insertions(+), 15 deletions(-)
diff
Am 11.12.19 um 08:36 schrieb Changfeng.Zhu:
From: changzhu
It may fail to load guest driver in round 2 or cause Xstart problem
when using invalidate semaphore for SRIOV or picasso. So it needs avoid
using invalidate semaphore for SRIOV and picasso.
Change-Id:
[AMD Official Use Only - Internal Distribution Only]
I tried your new patches to run BACO for about 10 loops and the result looks
positive, without observing enter/exit baco message failure again.
The time interval between BACO entries or exits in my environment was almost
less than 10 us: max
Series is Reviewed-by: Feifei Xu
-Original Message-
From: Tianci Yin
Sent: Wednesday, December 11, 2019 8:00 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xu, Feifei ;
Yuan, Xiaojie ; Long, Gang ; Li,
Pauline ; Yin, Tianci (Rico)
Subject: [PATCH 2/2] drm/amdgpu/gfx10:
From: "Tianci.Yin"
add registers: mmPA_SC_BINNER_TIMEOUT_COUNTER and mmPA_SC_ENHANCE_2
Change-Id: I23dabb0e706af0b5376f9749200832e894944eca
Signed-off-by: Tianci.Yin
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: "Tianci.Yin"
add registers: mmPA_SC_BINNER_TIMEOUT_COUNTER and mmPA_SC_ENHANCE_2
Change-Id: I1fc3fb481b2d9edc482a32497242a8be6cd6b8d7
Signed-off-by: Tianci.Yin
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
This makes it easier to figure out whether the kernel parameter has been
taken into account.
Signed-off-by: Simon Ser
Cc: Harry Wentland
Cc: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
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