RE: [PATCH] drm/amdgpu: Add a chunk ID for spm trace

[AMD Official Use Only - Internal Distribution Only] Vulkan UMD makes sure that the SPM_VMID will be updated if the application enables the SPM. So there is no this kind of problem for Vulkan application. It’s kind of “atomic” operation to enable SPM and update SPM_VMID. Vulkan application

RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence V2

[AMD Official Use Only - Internal Distribution Only] Yes, we are not 100% confident on the sequence of SETUP_VMR command in guest driver, although it indeed happens after PMFW loading in GPUV driver. I think now the concern was removed now. The current sequence should work in guest driver as

RE: [PATCH] drm/amdgpu: log TA versions on init

[AMD Official Use Only - Internal Distribution Only] Specific for your case, you just need add dtm and hdcp ta version in amdgpu_debugfs_firmware_info, Similar as xgmi and ras ta. The following cmd will give you all the firmware version information. sudo cat

RE: [PATCH] drm/amdgpu: log TA versions on init

[AMD Official Use Only - Internal Distribution Only] Hold on please. I don't think this is the best approach as we already had existing debugfs interface for that purpose. We shall centralize all the firmware information query under amdgpu_debugfs_firmware_info, and user should go through

RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence V2

Hi Hawking, Do you mean SRIOV may need this change also? Currently this covers bare-metal case only(SRIOV still follows old firmwares loading sequence). Regards, Evan -Original Message- From: Zhang, Hawking Sent: Monday, February 24, 2020 7:34 PM To: Quan, Evan ;

[PATCH 5/6] drm/amdkfd: Delete excessive printings

Those printings are duplicated or useless. Change-Id: I88fbe8f5748bbd0a20bcf1f6ca67b9dde99733fe Signed-off-by: Yong Zhao --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 -- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 4 +--- 2 files changed, 1 insertion(+), 5

[PATCH 1/6] drm/amdkfd: Rename queue_count to active_queue_count

The name is easier to understand the code. Change-Id: I9064dab1d022e02780023131f940fff578a06b72 Signed-off-by: Yong Zhao --- .../drm/amd/amdkfd/kfd_device_queue_manager.c | 38 +-- .../drm/amd/amdkfd/kfd_device_queue_manager.h | 2 +- .../gpu/drm/amd/amdkfd/kfd_packet_manager.c

[PATCH 6/6] drm/amdkfd: Delete unnecessary unmap queue package submissions

The previous SDMA queue counting was wrong. In addition, after confirming with MEC firmware team, we understands that only one unmap queue package, instead of one unmap queue package for CP and each SDMA engine, is needed, which results in much simpler driver code. Change-Id:

[PATCH 2/6] drm/amdkfd: Avoid ambiguity by indicating it's cp queue

The queues represented in queue_bitmap are only CP queues. Change-Id: I7e6a75de39718d7c4da608166b85b9377d06d1b3 Signed-off-by: Yong Zhao --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 4 ++-- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c| 12 ++--

[PATCH 3/6] drm/amdkfd: Count active CP queues directly

The previous code of calculating active CP queues is problematic if some SDMA queues are inactive. Fix that by counting CP queues directly. Change-Id: I5ffaa75a95cbebc984558199ba2f3db6909c52a9 Signed-off-by: Yong Zhao --- .../drm/amd/amdkfd/kfd_device_queue_manager.c | 47 +--

[PATCH 4/6] drm/amdkfd: Fix a memory leak in queue creation error handling

When the queue creation failed, some resources were not freed. Fix it. Change-Id: Ia24b6ad31528dceddfd4d1c58bb1d22c35d3eabf Signed-off-by: Yong Zhao --- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 3 +++ 1 file changed, 3 insertions(+) diff --git

Re: [PATCH] drm/amd/display: add HDCP caps debugfs

On 2020-02-24 4:51 p.m., Bhawanpreet Lakha wrote: > > On 2020-02-24 4:15 p.m., Harry Wentland wrote: >> >> On 2020-02-24 2:55 p.m., Bhawanpreet Lakha wrote: >>> Add debugfs to get HDCP capability. This is also useful for >>> kms_content_protection igt test. >>> >>> Use: >>> cat

Re: [PATCH] drm/amd/display: add HDCP caps debugfs

On 2020-02-24 4:15 p.m., Harry Wentland wrote: On 2020-02-24 2:55 p.m., Bhawanpreet Lakha wrote: Add debugfs to get HDCP capability. This is also useful for kms_content_protection igt test. Use: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability cat

Re: [PATCH] drm/amd/display: add HDCP caps debugfs

On 2020-02-24 2:55 p.m., Bhawanpreet Lakha wrote: > Add debugfs to get HDCP capability. This is also useful for > kms_content_protection igt test. > > Use: > cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability > cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability > >

Re: [PATCH 13/15] drm/amdgpu/display: split dp connector registration (v3)

On 2020-02-07 4:17 p.m., Alex Deucher wrote: > Split into init and register functions to avoid a segfault > in some configs when the load/unload callbacks are removed. > Looks like MST is completely broken with this change with a NULL pointer dereference in drm_dp_aux_register. > v2: > - add

RE: [PATCH] drm/amdgpu: log TA versions on init

> -Original Message- > From: amd-gfx On Behalf Of > Bhawanpreet Lakha > Sent: 2020/February/24, Monday 2:45 PM > To: amd-gfx@lists.freedesktop.org; Deucher, Alexander > ; Zhang, Hawking > > Cc: Lakha, Bhawanpreet > Subject: [PATCH] drm/amdgpu: log TA versions on init > > It is

Re: [PATCH 2/3] drm/radeon: Inline drm_get_pci_dev

On Mon, Feb 24, 2020 at 9:46 PM Daniel Vetter wrote: > > On Mon, Feb 24, 2020 at 5:31 PM Emil Velikov wrote: > > > > On Sat, 22 Feb 2020 at 17:54, Daniel Vetter wrote: > > > > > > It's the last user, and more importantly, it's the last non-legacy > > > user of anything in drm_pci.c. > > > > > >

Re: [PATCH 2/3] drm/radeon: Inline drm_get_pci_dev

On Mon, Feb 24, 2020 at 5:31 PM Emil Velikov wrote: > > On Sat, 22 Feb 2020 at 17:54, Daniel Vetter wrote: > > > > It's the last user, and more importantly, it's the last non-legacy > > user of anything in drm_pci.c. > > > > The only tricky bit is the agp initialization. But a close look shows >

[PATCH] drm/amd/display: add HDCP caps debugfs

Add debugfs to get HDCP capability. This is also useful for kms_content_protection igt test. Use: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability Signed-off-by: Bhawanpreet Lakha ---

[PATCH] drm/amdgpu: log TA versions on init

It is helpful to know what version the TA's are for debugging Signed-off-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index

Re: [PATCH] drm/amdgpu: Add a chunk ID for spm trace

Leave the old spm_vmid there is not a problem because other new spm enabled job will update it before it’s running and other spm disabled job will not access spm_vmid register. Do you have a high level description of how SPM works? For example would it be possible to cause a problem in another

Re: [RFC PATCH 1/1] drm/amdgpu: wait for sched to become ready on job submit

I think that the IB tests already set the ready flag to false when something goes wrong, but for the ring tests your probably want to double check and maybe generalize that. Christian. Am 24.02.20 um 19:15 schrieb Das, Nirmoy: [AMD Official Use Only - Internal Distribution Only] Thanks

Re: [RFC PATCH 1/1] drm/amdgpu: wait for sched to become ready on job submit

[AMD Official Use Only - Internal Distribution Only] Thanks Christian. I will try to send a updated patch soon. Get Outlook for Android From: Koenig, Christian Sent: Monday, February 24, 2020, 18:06 To: Nirmoy Das Cc:

Re: [RFC PATCH 1/1] drm/amdgpu: wait for sched to become ready on job submit

Hi Nirmoy, Am 24.02.2020 17:48 schrieb Nirmoy Das : On reset, amdgpu can set a drm sched's ready status to false temporarily. drm job init will fail if all of the drm scheds are not ready for a HW IP. This patch tries to make kernel's internal drm job submit handle, amdgpu_job_submit() a bit

[RFC PATCH 1/1] drm/amdgpu: wait for sched to become ready on job submit

On reset, amdgpu can set a drm sched's ready status to false temporarily. drm job init will fail if all of the drm scheds are not ready for a HW IP. This patch tries to make kernel's internal drm job submit handle, amdgpu_job_submit() a bit more fault tolerant. Signed-off-by: Nirmoy Das ---

[RFC PATCH 1/1] drm/amdgpu: wait for sched to become ready on job submit

On reset, amdgpu can set a drm sched's ready status to false temporarily. drm job init will fail if all of the drm scheds are not ready for a HW IP. This patch tries to make kernel's internal drm job submit handle, amdgpu_job_submit() a bit more fault tolerant. Signed-off-by: Nirmoy Das ---

Re: [PATCH 2/3] drm/radeon: Inline drm_get_pci_dev

On Sat, 22 Feb 2020 at 17:54, Daniel Vetter wrote: > > It's the last user, and more importantly, it's the last non-legacy > user of anything in drm_pci.c. > > The only tricky bit is the agp initialization. But a close look shows > that radeon does not use the drm_agp midlayer (the main use of

Re: [PATCH] drm/amd/amdgpu: Add gfxoff debugfs entry

On 2020-02-21 1:59 p.m., Alex Deucher wrote: On Fri, Feb 21, 2020 at 1:45 PM Tom St Denis wrote: Write a 32-bit value of zero to disable GFXOFF and write a 32-bit value of non-zero to enable GFXOFF. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 56

Re: [PATCH 2/2] add DST_SEL=8 field name for WRITE_DATA packet

Thanks, both pushed out to the master branch. Cheers, Tom On 2020-02-24 5:59 a.m., Xiaojie Yuan wrote: otherwise we'll out-of-bound when accessing op_37_dst_sel[8] Signed-off-by: Xiaojie Yuan --- src/lib/ring_decode.c| 2 +- src/lib/umr_pm4_decode_opcodes.c | 2 +- 2 files

RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence V2

[AMD Official Use Only - Internal Distribution Only] The patch looks good for bare-metal case now. Frank is still on the way to clean up our concern on SETUP_VMR command (i.e. SETUP_TMR for bare-metal case). After that settled, please push the patch with my RB. Thanks. Regards, Hawking

[PATCH 2/2] add DST_SEL=8 field name for WRITE_DATA packet

otherwise we'll out-of-bound when accessing op_37_dst_sel[8] Signed-off-by: Xiaojie Yuan --- src/lib/ring_decode.c| 2 +- src/lib/umr_pm4_decode_opcodes.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c index

[PATCH 1/2] print the missing 0x prefix in WRITE_DATA packet

Signed-off-by: Xiaojie Yuan --- src/lib/ring_decode.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c index fa44f27..c5582f5 100644 --- a/src/lib/ring_decode.c +++ b/src/lib/ring_decode.c @@ -664,7 +664,7 @@ static void

[PATCH] drm/amdgpu: update psp firmwares loading sequence V2

For those ASICs with DF Cstate management centralized to PMFW, TMR setup should be performed between pmfw loading and other non-psp firmwares loading. V2: skip possible SMU firmware reloading Change-Id: I8986ddb4d9ffe63ed0823d1dce8d9d52812a1240 Signed-off-by: Evan Quan ---

[PATCH] drm/amdgpu/display: clean up some indenting

These lines were accidentally indented 4 spaces more than they should be. Signed-off-by: Dan Carpenter --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence

Thanks. Will update that in V2. Only Arcturus was affected since Navi1x was already protected by autoload_supported. As I know, psp will skip smu fw loading if SMU is already alive. So, there should be no reloading. But there should be a skip in driver. Regards, Evan -Original Message-

Recall: [PATCH] drm/amdgpu: update psp firmwares loading sequence

Zhang, Hawking would like to recall the message, "[PATCH] drm/amdgpu: update psp firmwares loading sequence". ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence

[AMD Official Use Only - Internal Distribution Only] Sorry just for Navi12. Arcturus should be fine as it doesn't support autoload. Regards, Hawking -Original Message- From: Zhang, Hawking Sent: Monday, February 24, 2020 18:18 To: Quan, Evan ; 'amd-gfx@lists.freedesktop.org' Cc:

RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence

[AMD Official Use Only - Internal Distribution Only] That's saying I suspect the PMFW was loaded twice with the patch for Arcturus and Navi12. Regards, Hawking -Original Message- From: Zhang, Hawking Sent: Monday, February 24, 2020 18:16 To: Quan, Evan ; amd-gfx@lists.freedesktop.org

RE: [PATCH 3/3] drm/amdgpu: toggle DF-Cstate to protect DF reg access

Patch1 is reviewed-by: Evan Quan Patch2 & 3 are acked-by: Evan Quan -Original Message- From: Hawking Zhang Sent: Monday, February 24, 2020 6:06 PM To: amd-gfx@lists.freedesktop.org; Clements, John ; Deucher, Alexander ; Feng, Kenneth ; Quan, Evan Cc: Zhang, Hawking Subject: [PATCH

RE: [PATCH] drm/amdgpu: update psp firmwares loading sequence

[AMD Official Use Only - Internal Distribution Only] Can you double check the following logic after your setup the TMR in psp_np_fw_load? For Arcturus and Navi12, it should be skipped as well. if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && (psp_smu_reload_quirk(psp) ||

[PATCH 2/3] drm/amdgpu: move get_xgmi_relative_phy_addr to amdgpu_xgmi.c

centralize all the xgmi related function to amdgpu_xgmi.c Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 20 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 15 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h | 2 ++ 3 files changed, 21

[PATCH 3/3] drm/amdgpu: toggle DF-Cstate to protect DF reg access

driver needs to take DF out Cstate before any DF register access. otherwise, the DF register may not be accessible. Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 25 +++- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git

[PATCH 1/3] drm/amdgpu: add dpm helper function for DF Cstate control

The helper function hides software smu and legacy powerplay implementation for DF Cstate control. Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 17 + drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 3 +++ 2 files changed, 20 insertions(+) diff --git

[PATCH] drm/amdgpu: update psp firmwares loading sequence

For those ASICs with DF Cstate management centralized to PMFW, TMR setup should be performed between pmfw loading and other non-psp firmwares loading. Change-Id: I8986ddb4d9ffe63ed0823d1dce8d9d52812a1240 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 61

RE: [PATCH] drm/amdgpu: Add a chunk ID for spm trace

Ok, I’m glad that there is no uapi change needed. I checked the git log, and reserve_vmid was added for shader debugger, not gpa. I’m fine to re-use it since the spm will not enabled for shader debug in general. I’ll try to change my patch. BTW, “ring->funcs->setup_spm(ring, NULL)” to clear the

Re: [PATCH 8/8] drm/ttm: do not keep GPU dependent addresses

Hi, > 2 unfortunately I can't say the same for bochs but it works with this patch > series so I think bochs is fine as well. bochs needs the offset only to scanout framebuffers, which in turn requires framebuffers being pinned to vram. So all green here. cheers, Gerd

Re: [PATCH 6/8] drm/vram-helper: don't use ttm bo->offset

On Mon, Feb 17, 2020 at 04:04:25PM +0100, Nirmoy Das wrote: > Calculate GPU offset within vram-helper without depending on > bo->offset > > Signed-off-by: Nirmoy Das Acked-by: Gerd Hoffmann ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org

Re: [PATCH 7/8] drm/bochs: use drm_gem_vram_offset to get bo offset

On Mon, Feb 17, 2020 at 04:04:26PM +0100, Nirmoy Das wrote: > Switch over to GEM VRAM's implementation to retrieve bo->offset > > Signed-off-by: Nirmoy Das Acked-by: Gerd Hoffmann ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org