[AMD Official Use Only - Internal Distribution Only]
Series reviewed-by: Emily Deng
>-Original Message-
>From: amd-gfx On Behalf Of
>Christian König
>Sent: Thursday, March 5, 2020 9:37 PM
>To: Liu, Monk ; amd-gfx@lists.freedesktop.org
>Subject: Re: [enable VCN2.0 for NV12 SRIOV 6/6]
No, this is an existed warning
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: Liu, Leo
Sent: Friday, March 6, 2020 12:17 AM
To: Liu, Monk ; amd-gfx@lists.freedesktop.org
Subject: Re: [enable VCN2.0 for NV12 SRIOV 6/6] drm/amdgpu:
Okay, no problem
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: Liu, Leo
Sent: Friday, March 6, 2020 12:08 AM
To: Liu, Monk ; amd-gfx@lists.freedesktop.org
Subject: Re: [enable VCN2.0 for NV12 SRIOV 3/6] drm/amdgpu: implement
[AMD Public Use]
Patch3: Acked-by: Feifei Xu
Regards,
Feifei
From: amd-gfx On Behalf Of Xu, Feifei
Sent: 2020年3月6日 9:54
To: Deucher, Alexander ; Alex Deucher
; amd-gfx list
Cc: Tawfik, Aly
Subject: RE: [PATCH 1/2] drm/amdgpu/display: fix pci revision id fetching
[AMD Public Use]
Patch1,
[AMD Public Use]
Patch1, Patch2 are :
Reviewed-by: Feifei Xu
From: Deucher, Alexander
Sent: 2020年3月6日 0:00
To: Xu, Feifei ; Alex Deucher ;
amd-gfx list
Cc: Tawfik, Aly
Subject: Re: [PATCH 1/2] drm/amdgpu/display: fix pci revision id fetching
[AMD Public Use]
Is this for the series, or
On 2020-03-05 16:13, Nirmoy wrote:
>
> On 3/5/20 7:42 PM, Luben Tuikov wrote:
>>
>>> A quick search leads me amdgpu_sched_ioctl() which is using
>>> DRM_SCHED_PRIORITY_INVALID
>>>
>>> to indicate a invalid value from userspace. I don't know much about drm
>>> api to suggest any useful
>>>
>>>
On Mon, Mar 2, 2020 at 2:57 PM Kazlauskas, Nicholas
wrote:
>
> On 2020-03-02 1:17 a.m., Mario Kleiner wrote:
> > Commit '16f17eda8bad ("drm/amd/display: Send vblank and user
> > events at vsartup for DCN")' introduces a new way of pageflip
> > completion handling for DCN, and some trouble.
> >
>
Commit '16f17eda8bad ("drm/amd/display: Send vblank and user
events at vsartup for DCN")' introduces a new way of pageflip
completion handling for DCN, and some trouble.
The current implementation introduces a race condition, which
can cause pageflip completion events to be sent out one vblank
On 3/5/20 7:42 PM, Luben Tuikov wrote:
A quick search leads me amdgpu_sched_ioctl() which is using
DRM_SCHED_PRIORITY_INVALID
to indicate a invalid value from userspace. I don't know much about drm
api to suggest any useful
changes regarding this. But again this isn't in the scope of this
[AMD Official Use Only - Internal Distribution Only]
Okay, I will change back to its original format.
Yong
From: Kuehling, Felix
Sent: Thursday, March 5, 2020 3:49 PM
To: amd-gfx@lists.freedesktop.org ; Zhao, Yong
Subject: Re: [PATCH] drm/amdkfd: Consolidate
On 2020-03-04 3:21 p.m., Yong Zhao wrote:
ALLOC_MEM_FLAGS_* used are the same as the KFD_IOC_ALLOC_MEM_FLAGS_*,
but they are interweavedly used in kernel driver, resulting in bad
readability. For example, KFD_IOC_ALLOC_MEM_FLAGS_COHERENT is totally
not referenced in kernel, and it functions in
On 2020-03-05 14:37, Ho, Kenny wrote:
> [AMD Official Use Only - Internal Distribution Only]
>
>
> I believe bo->tbo.mem.mem_type is of uint32_t type and not an enum, is the
> index lookup method safe? (i.e., how do you deal with the possibility of
> having value TTM_PL_PRIV or above or are
On Thu, 2020-03-05 at 13:52 -0500, Lyude Paul wrote:
> On Thu, 2020-03-05 at 20:29 +0200, Ville Syrjälä wrote:
> > On Thu, Mar 05, 2020 at 01:13:36PM -0500, Lyude Paul wrote:
> > > On Thu, 2020-03-05 at 15:11 +0200, Ville Syrjälä wrote:
> > > > On Wed, Mar 04, 2020 at 05:36:12PM -0500, Lyude Paul
[AMD Official Use Only - Internal Distribution Only]
I believe bo->tbo.mem.mem_type is of uint32_t type and not an enum, is the
index lookup method safe? (i.e., how do you deal with the possibility of having
value TTM_PL_PRIV or above or are you suggesting those are not possible for
this
On 2020-03-05 08:29, Nirmoy Das wrote:
> Store ttm bo->offset in struct nouveau_bo instead.
>
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/nouveau/dispnv04/crtc.c | 6 +++---
> drivers/gpu/drm/nouveau/dispnv04/disp.c | 2 +-
> drivers/gpu/drm/nouveau/dispnv04/overlay.c | 6
On 2020-03-05 08:29, Nirmoy Das wrote:
> Calculate GPU offset in radeon_bo_gpu_offset without depending on
> bo->offset.
>
> Signed-off-by: Nirmoy Das
> Reviewed-and-tested-by: Christian König
> ---
> drivers/gpu/drm/radeon/radeon.h| 1 +
> drivers/gpu/drm/radeon/radeon_object.h | 16
On 2020-03-05 08:29, Nirmoy Das wrote:
> GPU address should belong to driver not in memory management.
> This patch moves ttm bo.offset and gpu_offset calculation to amdgpu driver.
>
> Signed-off-by: Nirmoy Das
> Acked-by: Huang Rui
> Reviewed-by: Christian König
> ---
>
Hi Dave, Daniel,
Fixes for 5.6.
The following changes since commit 70b8ea1ab1d3ff3ad5c7491bf8995c912506da6c:
Merge tag 'mediatek-drm-fixes-5.6' of
https://github.com/ckhu-mediatek/linux.git-tags into drm-fixes (2020-03-05
12:59:44 +1000)
are available in the Git repository at:
On 2020-03-05 04:10, Nirmoy wrote:
>
> On 3/4/20 11:00 PM, Luben Tuikov wrote:
>> struct drm_sched_entity *entity,
>>>void *owner);
>>> +void drm_sched_entity_modify_sched(struct drm_sched_entity *entity,
>>> + struct drm_gpu_scheduler **sched_list,
On Thu, 2020-03-05 at 20:29 +0200, Ville Syrjälä wrote:
> On Thu, Mar 05, 2020 at 01:13:36PM -0500, Lyude Paul wrote:
> > On Thu, 2020-03-05 at 15:11 +0200, Ville Syrjälä wrote:
> > > On Wed, Mar 04, 2020 at 05:36:12PM -0500, Lyude Paul wrote:
> > > > It's next to impossible for us to do connector
On 2020-03-05 01:28, Nirmoy wrote:
>
> On 3/4/20 11:25 PM, Luben Tuikov wrote:
>> On 2020-03-03 7:50 a.m., Nirmoy Das wrote:
>>> Switch to appropriate sched list for an entity on priority override.
>>>
>>> Signed-off-by: Nirmoy Das
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 32
On 2020-03-05 01:23, Nirmoy wrote:
>
> On 3/4/20 11:00 PM, Luben Tuikov wrote:
>> On 2020-03-03 7:50 a.m., Nirmoy Das wrote:
>>> implement drm_sched_entity_modify_sched() which can modify existing
>>> sched_list with a different one. This is going to be helpful when
>>> userspace changes priority
It is very difficult to find your comment replies when
you do not add an empty line around them.
Do you not see how everyone responds and adds
an empty line around them?
Why don't you?
cont'd below
On 2020-03-05 01:21, Nirmoy wrote:
>
> On 3/4/20 10:41 PM, Luben Tuikov wrote:
>> On 2020-03-03
On Thu, Mar 05, 2020 at 01:13:36PM -0500, Lyude Paul wrote:
> On Thu, 2020-03-05 at 15:11 +0200, Ville Syrjälä wrote:
> > On Wed, Mar 04, 2020 at 05:36:12PM -0500, Lyude Paul wrote:
> > > It's next to impossible for us to do connector probing on topologies
> > > without occasionally racing with
On Thu, 2020-03-05 at 15:11 +0200, Ville Syrjälä wrote:
> On Wed, Mar 04, 2020 at 05:36:12PM -0500, Lyude Paul wrote:
> > It's next to impossible for us to do connector probing on topologies
> > without occasionally racing with userspace, since creating a connector
> > itself causes a hotplug
From: Monk Liu
[ Upstream commit 4829f89855f1d3a3d8014e74cceab51b421503db ]
fix system memory leak
v2:
fix coding style
Signed-off-by: Monk Liu
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 +-
1
From: Monk Liu
[ Upstream commit 4829f89855f1d3a3d8014e74cceab51b421503db ]
fix system memory leak
v2:
fix coding style
Signed-off-by: Monk Liu
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 +-
1
Hi Lyude,
On 3/4/20 11:36 PM, Lyude Paul wrote:
AMD's patch series for adding DSC support to the MST helpers
unfortunately introduced a few regressions into the kernel that I didn't
get around to fixing until just now. I would have reverted the changes
earlier, but seeing as that would have
Is this warning introduced by your patch 4?
On 2020-03-05 8:33 a.m., Monk Liu wrote:
Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
This patch is:
Acked-by: Leo Liu
On 2020-03-05 8:33 a.m., Monk Liu wrote:
and disable MC resum in VCN2.0 as well
those are not concerned by VF driver
Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 23 +++
1 file changed, 23 insertions(+)
diff
This patch is:
Reviewed-by: Leo Liu
On 2020-03-05 8:33 a.m., Monk Liu wrote:
support IB test on dec/enc ring
disable ring test on dec/enc ring (MMSCH limitation)
Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 11 +++
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
On 2020-03-05 8:33 a.m., Monk Liu wrote:
one dec ring and one enc ring
It seems more than that, you might add more messages.
Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 231 +-
1 file changed, 228 insertions(+), 3 deletions(-)
[moving to public mailing list]
Thank you. I'll also apply patch 2/2 to amd-staging-drm-next. It's not
fixing a memory leak there, but it should make cleanup after process
termination more efficient by avoiding delayed delete of BOs.
Regards,
Felix
On 2020-03-04 10:46 p.m., Pan, Xinhui
On 2020-03-05 8:39 a.m., Liu, Monk wrote:
This is not supported by MMSCH FW...
With this added to commit message, this patch is:
Reviewed-by: Leo Liu
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: Christian König
Sent:
[AMD Public Use]
Is this for the series, or just this patch? Thanks!
Alex
From: Xu, Feifei
Sent: Thursday, March 5, 2020 12:24 AM
To: Alex Deucher ; amd-gfx list
Cc: Deucher, Alexander ; Tawfik, Aly
Subject: RE: [PATCH 1/2] drm/amdgpu/display: fix pci
On 2020-03-05 6:27 a.m., Christian König wrote:
Am 05.03.20 um 12:25 schrieb Christian König:
Am 04.03.20 um 17:34 schrieb James Zhu:
Fix race condition issue when multiple vcn starts are called.
v2: Removed checking the return value of cancel_delayed_work_sync()
to prevent possible races
Am 05.03.20 um 15:35 schrieb Nirmoy:
On 3/5/20 3:07 PM, Gerd Hoffmann wrote:
On Thu, Mar 05, 2020 at 02:29:08PM +0100, Nirmoy Das wrote:
Calculate GEM VRAM bo's offset within vram-helper without depending on
bo->offset.
Signed-off-by: Nirmoy Das
Reviewed-by: Daniel Vetter
---
On 3/5/20 3:07 PM, Gerd Hoffmann wrote:
On Thu, Mar 05, 2020 at 02:29:08PM +0100, Nirmoy Das wrote:
Calculate GEM VRAM bo's offset within vram-helper without depending on
bo->offset.
Signed-off-by: Nirmoy Das
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_gem_vram_helper.c | 9
Hi
Am 05.03.20 um 15:07 schrieb Gerd Hoffmann:
> On Thu, Mar 05, 2020 at 02:29:08PM +0100, Nirmoy Das wrote:
>> Calculate GEM VRAM bo's offset within vram-helper without depending on
>> bo->offset.
>>
>> Signed-off-by: Nirmoy Das
>> Reviewed-by: Daniel Vetter
>> ---
>>
On Thu, Mar 05, 2020 at 02:29:08PM +0100, Nirmoy Das wrote:
> Calculate GEM VRAM bo's offset within vram-helper without depending on
> bo->offset.
>
> Signed-off-by: Nirmoy Das
> Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/drm_gem_vram_helper.c | 9 -
> 1 file changed, 8
This is not supported by MMSCH FW...
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: Christian König
Sent: Thursday, March 5, 2020 9:38 PM
To: Liu, Monk ; amd-gfx@lists.freedesktop.org
Subject: Re: [enable VCN2.0 for NV12 SRIOV
Am 05.03.20 um 14:33 schrieb Monk Liu:
Signed-off-by: Monk Liu
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index
Am 05.03.20 um 14:29 schrieb Nirmoy Das:
GPU address handling is device specific and should be handle by its device
driver.
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c| 7 ---
include/drm/ttm/ttm_bo_api.h| 2 --
and disable MC resum in VCN2.0 as well
those are not concerned by VF driver
Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
Am 05.03.20 um 14:29 schrieb Nirmoy Das:
Store ttm bo->offset in struct nouveau_bo instead.
Signed-off-by: Nirmoy Das
Looks like this is the only patch without an rb or at least acked-by.
Can anybody comment or at least throw a quick tested-by on it?
With that done I would say I would
one dec ring and one enc ring
Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 231 +-
1 file changed, 228 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index
GPU address should belong to driver not in memory management.
This patch moves ttm bo.offset and gpu_offset calculation to amdgpu driver.
Signed-off-by: Nirmoy Das
Acked-by: Huang Rui
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 22 ++--
With this patch series I am trying to remove GPU address dependency in
TTM and moving GPU address calculation to individual drm drivers. This
cleanup will simplify introduction of drm_mem_region/domain work started
by Brian Welty[1].
It would be nice if someone test this for nouveau. Rest of the
Calculate GPU offset in radeon_bo_gpu_offset without depending on
bo->offset.
Signed-off-by: Nirmoy Das
Reviewed-and-tested-by: Christian König
---
drivers/gpu/drm/radeon/radeon.h| 1 +
drivers/gpu/drm/radeon/radeon_object.h | 16 +++-
drivers/gpu/drm/radeon/radeon_ttm.c
Calculate GPU offset within vmwgfx driver itself without depending on
bo->offset.
Signed-off-by: Nirmoy Das
Acked-by: Christian König
Acked-by: Thomas Hellstrom
Tested-by: Thomas Hellstrom
---
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c | 4 ++--
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c| 2
GPU address handling is device specific and should be handle by its device
driver.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/ttm/ttm_bo.c| 7 ---
include/drm/ttm/ttm_bo_api.h| 2 --
include/drm/ttm/ttm_bo_driver.h | 1 -
3 files changed, 10 deletions(-)
diff --git
Store ttm bo->offset in struct nouveau_bo instead.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/nouveau/dispnv04/crtc.c | 6 +++---
drivers/gpu/drm/nouveau/dispnv04/disp.c | 2 +-
drivers/gpu/drm/nouveau/dispnv04/overlay.c | 6 +++---
drivers/gpu/drm/nouveau/dispnv50/base507c.c |
This patch removes slot->gpu_offset which is not required as
VRAM and PRIV slot are in separate PCI bar.
This patch also removes unused qxl_bo_gpu_offset()
Signed-off-by: Nirmoy Das
Acked-by: Christian König
Acked-by: Gerd Hoffmann
---
drivers/gpu/drm/qxl/qxl_drv.h| 6 ++
Switch over to GEM VRAM's implementation to retrieve bo->offset.
Signed-off-by: Nirmoy Das
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/bochs/bochs_kms.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bochs/bochs_kms.c
Calculate GEM VRAM bo's offset within vram-helper without depending on
bo->offset.
Signed-off-by: Nirmoy Das
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_gem_vram_helper.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c
On Wed, Mar 04, 2020 at 05:36:12PM -0500, Lyude Paul wrote:
> It's next to impossible for us to do connector probing on topologies
> without occasionally racing with userspace, since creating a connector
> itself causes a hotplug event which we have to send before probing the
> available PBN of a
[AMD Public Use]
We'd better keep original comment "/* skip error address process if -ENOMEM
*/", if err_addr is not allocated successfully.
Regards,
Guchun
From: Zhang, Hawking
Sent: Thursday, March 5, 2020 7:23 PM
To: Clements, John ; amd-gfx@lists.freedesktop.org; Li,
Dennis ; Zhou1, Tao
Am 05.03.20 um 13:08 schrieb Jacob He:
SPM access the video memory according to SPM_VMID. It should be updated
with the job's vmid right before the job is scheduled. SPM_VMID is a
global resource
Change-Id: Id3881908960398f87e7c95026a54ff83ff826700
Signed-off-by: Jacob He
Reviewed-by:
SPM access the video memory according to SPM_VMID. It should be updated
with the job's vmid right before the job is scheduled. SPM_VMID is a
global resource
Change-Id: Id3881908960398f87e7c95026a54ff83ff826700
Signed-off-by: Jacob He
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 20
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Tao Zhou mailto:tao.zh...@amd.com>>
From: Clements, John
Sent: 2020年3月5日 17:40
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking ; Li,
Dennis ; Zhou1, Tao ; Chen, Guchun
Subject: [PATCH] drm/amdgpu: update page retirement
Am 04.03.20 um 21:35 schrieb Yong Zhao:
Add "CP" to AMDGPU_GEM_CREATE_MQD_GFX9 to indicate it is only for CP MQD.
You should probably note that we can do this because it was always
illegal for userspace to use the flag.
Change-Id: Ie69cd3ba477e4bac161ea5b20ec2919a35f3528e
Signed-off-by:
Am 04.03.20 um 20:40 schrieb Yong Zhao:
Because too many things are involved in this workaround, we need more
comments to avoid pitfalls.
Change-Id: I5d7917296dd5f5edb45921118cf8e7d778d40de1
Signed-off-by: Yong Zhao
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
Am 05.03.20 um 12:25 schrieb Christian König:
Am 04.03.20 um 17:34 schrieb James Zhu:
Fix race condition issue when multiple vcn starts are called.
v2: Removed checking the return value of cancel_delayed_work_sync()
to prevent possible races here.
Signed-off-by: James Zhu
Reviewed-by:
Am 04.03.20 um 17:34 schrieb James Zhu:
Fix race condition issue when multiple vcn starts are called.
v2: Removed checking the return value of cancel_delayed_work_sync()
to prevent possible races here.
Signed-off-by: James Zhu
Reviewed-by: Christian König
---
[AMD Official Use Only - Internal Distribution Only]
I see. So it's the following programming that is in risk to corrupt data for
other instances.
/* clear umc status */
WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);
For error injection,
Am 04.03.20 um 05:06 schrieb Jacob He:
SPM access the video memory according to SPM_VMID. It should be updated
with the job's vmid right before the job is scheduled. SPM_VMID is a
global resource
Change-Id: Id3881908960398f87e7c95026a54ff83ff826700
Signed-off-by: Jacob He
---
[AMD Official Use Only - Internal Distribution Only]
In the original sequence, if the key bits are not set in the mca_status, the
page retirement will not happen and the status register will be cleared.
If there is a UMC UE, that register will be cleared erroneously 31 times.
If MCA Status == 0
[AMD Official Use Only - Internal Distribution Only]
Hi John,
Can you please explain more on the differences between (a). exit immediately
when mca_status is 0 and (b). exit when some of critical field in mca_status is
0?
Regards,
Hawking
From: Clements, John
Sent: Thursday, March 5, 2020
this a patch that port from SRIOV project branch
to fix those IB/RING test fail on VCN 2.0 rings
Signed-off-by: Darlington Opara
Signed-off-by: Jiange Zhao
Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: John Clements
-Original Message-
From: Chen, Guchun
Sent: Wednesday, March 4, 2020 10:47 PM
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking ; Li,
Dennis ; Zhou1, Tao ; Clements, John
Cc: Chen, Guchun
Subject:
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
From: Clements, John
Sent: Thursday, March 5, 2020 17:39
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking ; Li,
Dennis ; Zhou1, Tao ; Chen, Guchun
Subject: [PATCH] drm/amdgpu: increase atombios
[AMD Official Use Only - Internal Distribution Only]
check UMC status and exit prior to making and erroneus register access
0001-drm-amdgpu-update-page-retirement-sequence.patch
Description: 0001-drm-amdgpu-update-page-retirement-sequence.patch
___
[AMD Official Use Only - Internal Distribution Only]
mitigates race condition on BACO reset between GPU bootcode and driver reload
0001-drm-amdgpu-increase-atombios-cmd-timeout.patch
Description: 0001-drm-amdgpu-increase-atombios-cmd-timeout.patch
___
On 3/4/20 11:00 PM, Luben Tuikov wrote:
struct drm_sched_entity *entity,
void *owner);
+void drm_sched_entity_modify_sched(struct drm_sched_entity *entity,
+ struct drm_gpu_scheduler **sched_list,
+
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