Maybe copy paste typo inline.
Philip
On 2020-03-20 10:41 a.m., Felix Kuehling wrote:
On 2020-03-19 20:27, Alex Sierra wrote:
[Why]
Previously these registers were set to 0. This was causing an
infinite retry on the UTCL1 RB, preventing higher priority RB such as
paging RB.
[How]
Set to one
Check of the pointer exists and we are actually on AC power.
v2: fix error message to reflect AC/DC mode.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
On 3/20/20 9:48 AM, Jason Gunthorpe wrote:
From: Jason Gunthorpe
I've had these in my work queue for a bit, nothing profound here, just some
small edits for clarity.
Ralph's hmm tester will need a small diff to work after this - which
illustrates how setting default_flags == 0 is the same
On 3/20/20 9:49 AM, Jason Gunthorpe wrote:
From: Jason Gunthorpe
Delete several functions that are never called, fix some desync between
comments and structure content, remove an unused ret, and move one
function only used by hmm.c into hmm.c
Signed-off-by: Jason Gunthorpe
Reviewed-by:
On Fri, Mar 20, 2020 at 11:51:47AM -0700, Ralph Campbell wrote:
>
> On 3/20/20 9:48 AM, Jason Gunthorpe wrote:
> > From: Jason Gunthorpe
> >
> > I've had these in my work queue for a bit, nothing profound here, just some
> > small edits for clarity.
>
> The hmm tester changes are clear enough
Am 20.03.20 um 15:20 schrieb Felix Kuehling:
On 2020-03-20 10:06, Deucher, Alexander wrote:
[AMD Public Use]
This seems kind of complicated and error prone. I didn't realize the
extent to the changes required. I think it would be better to either
add arcturus specific versions of these
On 3/20/20 9:48 AM, Jason Gunthorpe wrote:
From: Jason Gunthorpe
I've had these in my work queue for a bit, nothing profound here, just some
small edits for clarity.
The hmm tester changes are clear enough but I'm having a bit of trouble
figuring out
what this series applies cleanly to
The smu_v11_0 version works for navi1x.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index d66dfa7410b6..a23eaac28095 100644
Check of the pointer exists and we are actually on AC power.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
Am 20.03.20 um 10:46 schrieb Tianci Yin:
From: "Tianci.Yin"
[why]
When GTT domain size is smaller than VRAM, if APP apply a very large
buffer whose size is larger than GTT but smaller than VRAM, the size
validation will fail.
[how]
Validate VRAM domain size at first place, then GTT domain.
Driver needs to send the ack message when it receives the
AC/DC interrupt from the SMU.
TODO: verify the client and src ids.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 16
1 file changed, 16 insertions(+)
diff --git
For boards that do not support automatic AC/DC transitions
in firmware, manually tell the firmware when the status
changes.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 3 +++
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 23 +++
Add a common smu11 helper to set the AC/DC power source.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 3 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 15 +++
2 files changed, 18 insertions(+)
diff --git
Check the platform caps in the vbios pptable to decide
whether to enable automatic AC/DC transitions.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 +
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 7 ++-
2 files changed, 7 insertions(+), 1 deletion(-)
From: Jason Gunthorpe
This code can be compiled when CONFIG_TRANSPARENT_HUGEPAGE is off, so
remove the ifdef.
Signed-off-by: Jason Gunthorpe
---
mm/hmm.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/mm/hmm.c b/mm/hmm.c
index 7f77fb6e35cf78..a09b4908e9c81a 100644
--- a/mm/hmm.c
+++
From: Jason Gunthorpe
Now that flags are handled on a fine-grained per-page basis this global
flag is redundant and has a confusing overlap with the pfn_flags_mask and
default_flags.
Normalize the HMM_FAULT_SNAPSHOT behavior into one place. Callers needing
the SNAPSHOT behavior should set a
From: Jason Gunthorpe
swp_offset() should not be called directly, the wrappers are supposed to
abstract away the encoding of the device_private specific information in
the swap entry.
Signed-off-by: Jason Gunthorpe
---
mm/hmm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
From: Jason Gunthorpe
Delete several functions that are never called, fix some desync between
comments and structure content, remove an unused ret, and move one
function only used by hmm.c into hmm.c
Signed-off-by: Jason Gunthorpe
---
include/linux/hmm.h | 50
From: Jason Gunthorpe
Using two bools instead of flags return is not necessary and leads to
bugs. Returning a value is easier for the compiler to check and easier to
pass around the code flow.
Convert the two bools into flags and push the change to all callers.
Signed-off-by: Jason Gunthorpe
From: Jason Gunthorpe
I've had these in my work queue for a bit, nothing profound here, just some
small edits for clarity.
Ralph's hmm tester will need a small diff to work after this - which
illustrates how setting default_flags == 0 is the same as what was called
SNAPSHOT:
diff --git
Yes, it worked.
Thanks!
Tristan
On Wed, Mar 18, 2020 at 9:53 AM Alex Deucher wrote:
> On Tue, Mar 17, 2020 at 6:24 PM Tristan Vroom
> wrote:
> >
> > I don't have a lot of experience reading kernel logs, so I apologize if
> I misread something, but it seems like I'm having some trouble with
[AMD Official Use Only - Internal Distribution Only]
My bad, please ignore this.
I re-sent this in a separate one patch.
Alejandro S
-Original Message-
From: Kuehling, Felix
Sent: Friday, March 20, 2020 9:37 AM
To: Sierra Guiza, Alejandro (Alex) ;
amd-gfx@lists.freedesktop.org
From: Aric Cyr
[Why]
Nominal pixel clock and EDID information differ in precision so although
monitor reports maximum refresh is 2x minimum, LFC was not being
enabled.
[How]
Use minimum refresh rate as nominal/2 when EDID dictates that min
refresh = max refresh/2.
Signed-off-by: Aric Cyr
From: Stylon Wang
[Why]
CTM was only supported at CRTC level and we need color space conversion
in linear space at plane level.
[How]
- Add plane-level CTM to dc interface
- Program plane-level CTM in DCN
Signed-off-by: Stylon Wang
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
From: Yongqiang Sun
[Why]
In some scenario like 1366x768 VSR enabled connected with a 4K monitor
and playing 4K video in clone mode, underflow will be observed due to
decrease dppclk when previouse surface scan isn't finished
[How]
In this use case, surface flip is switching between 4K and
From: Isabel Zhang
[Why]
Change is causing a regression where the OPC app no longer functions
properly.
[How]
Revert the changelist causing the issue.
Signed-off-by: Isabel Zhang
Reviewed-by: Yongqiang Sun
Acked-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/modules/hdcp/hdcp.c | 5
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Rework part of the backlight function call;
* Support plane level CTM, and P010 pixel format;
* Get optimal number of taps;
Aric Cyr (2):
drm/amd/display: 3.2.77
drm/amd/display: LFC not working on 2.0x
From: Nicholas Kazlauskas
[Why]
For some monitors extreme flickering can occur while using LFC for if
we're not doing the DRR timing update for V_TOTAL_MIN / V_TOTAL_MAX at
the DP start of frame.
Hardware can default to any time in the frame which isn't the behavior
we want.
[How]
Add a new
From: Wyatt Wood
[Why]
Can't call dmub_abm_enable_fractional_pwm from dmub_abm_create as
dmub_srv is still null at this init stage, and therefore can't call to
fw.
[How]
Move call to dmub_abm_init_backlight. This should be the first call from
the driver for ABM.
Signed-off-by: Wyatt Wood
From: Stylon Wang
[Why]
P010 pixel format is not declared as supported in DRM and DM.
[How]
Add P010 format to the support list presented to DRM and checked in DM
Signed-off-by: Stylon Wang
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
---
From: Wyatt Wood
[Why]
Moving ABM from DMCU to DMCUB.
[How]
Add ABM driver files and implementation.
Signed-off-by: Wyatt Wood
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dce/Makefile | 2 +-
From: Stylon Wang
[Why]
BT2020 is not supported in COLOR_ENCODING property of planes. Only
BT601 and BT709 was available.
[How]
Allow BT2020 as legit value in setting COLOR_ENCODING property.
Signed-off-by: Stylon Wang
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
---
From: Eric Bernstein
[Why]
Diagnostics scaling test failing to set required number of vertical taps
in 4:2:0 surface case
[How]
In dpp3_get_optimal_number_of_taps() need to use LB_MEMORY_CONFIG_3 for
4:2:0 surface case. In resource_build_scaling_params() make sure to also
set plane res alpha
From: Dmytro Laktyushkin
[Why]
DML expects num_states to exclude the duplicate state.
[How]
Set num_states to correct value to prevent array off-by-one error. Also
refactor max clock level code for diags.
Signed-off-by: Dmytro Laktyushkin
Signed-off-by: George Shen
Reviewed-by: Dmytro
[AMD Public Use]
Yes, something like that.
Alex
From: Kuehling, Felix
Sent: Friday, March 20, 2020 10:47 AM
To: Deucher, Alexander ; Sierra Guiza, Alejandro
(Alex) ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/4] drm/amdgpu: add stride to calculate
On 2020-03-20 10:39, Deucher, Alexander wrote:
[AMD Public Use]
I'm worried we'll miss a register by accident. We went with per IP
sub drivers to avoid handling complexities around IP differences if
possible. Also the scheme seems like kind of a one off compared to
what we do for other
On Mon, Mar 16, 2020 at 08:32:16PM +0100, Christoph Hellwig wrote:
> diff --git a/mm/hmm.c b/mm/hmm.c
> index cfad65f6a67b..b75b3750e03d 100644
> +++ b/mm/hmm.c
> @@ -216,6 +216,14 @@ int hmm_vma_handle_pmd(struct mm_walk *walk, unsigned
> long addr,
> unsigned long end, uint64_t
On Thu, Mar 19, 2020 at 06:33:04PM -0700, Ralph Campbell wrote:
> > > + .default_flags = dmirror_hmm_flags[HMM_PFN_VALID] |
> > > + (write ? dmirror_hmm_flags[HMM_PFN_WRITE] : 0),
> > > + .dev_private_owner = dmirror->mdevice,
> > > + };
> > > + int ret =
On 2020-03-19 20:27, Alex Sierra wrote:
[Why]
Previously these registers were set to 0. This was causing an
infinite retry on the UTCL1 RB, preventing higher priority RB such as paging RB.
[How]
Set to one the SDMAx_UTLC1_TIMEOUT registers for all SDMAs on Arcturus.
Please update this
[AMD Public Use]
I'm worried we'll miss a register by accident. We went with per IP sub drivers
to avoid handling complexities around IP differences if possible. Also the
scheme seems like kind of a one off compared to what we do for other IPs. Can
we structure it more like how we handle
On 2020-03-19 20:24, Alex Sierra wrote:
[Why]
nbio v7.4 size of ih doorbell range is 64 bit. This requires 2 DWords per
register.
[How]
Change ih doorbell size from 2 to 4. This means two Dwords per ring.
Current configuration uses two ih rings.
Signed-off-by: Alex Sierra
Why is the
On 2020-03-19 20:22, Alex Sierra wrote:
This macro calculates the IH ring register offset based on
the three ring numbers and asic type.
The parameters needed are the register's name without the prefix mmIH
and the ring number taken from RING0, RING1 or RING2 macros.
Signed-off-by: Alex Sierra
[AMD Public Use]
Series is:
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Kent Russell
Sent: Friday, March 20, 2020 9:24 AM
To: amd-gfx@lists.freedesktop.org
Cc: Russell, Kent
Subject: [PATCH 3/3] drm/amdgpu: Add documentation for unique_id
Add the
On 2020-03-20 10:06, Deucher, Alexander wrote:
[AMD Public Use]
This seems kind of complicated and error prone. I didn't realize the
extent to the changes required. I think it would be better to either
add arcturus specific versions of these functions or just go with your
original
[AMD Public Use]
This seems kind of complicated and error prone. I didn't realize the extent to
the changes required. I think it would be better to either add arcturus
specific versions of these functions or just go with your original approach and
add a new arcturus_ih.c. If you go with the
Add the amdgpu.rst tie-ins for the mem_info documentation
Signed-off-by: Kent Russell
---
Documentation/gpu/amdgpu.rst | 41
1 file changed, 41 insertions(+)
diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index
Add the amdgpu.rst tie-ins for the unique_id documentation
Signed-off-by: Kent Russell
---
Documentation/gpu/amdgpu.rst | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index 9afcc30e0f42..4cc74325bf91 100644
---
Add the amdgpu.rst tie-ins for the pcie accounting documentation
Signed-off-by: Kent Russell
---
Documentation/gpu/amdgpu.rst | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index
The "shadow" variable was never set to false.
There is a quirk in current versions of GCC where it will sometimes set
it to false and not warn about the uninitiliazed variable. That means
that this bug wouldn't have been discovered in normal testing.
Fixes: 2e0cc4d48b91 ("drm/amdgpu: revise
From: "Tianci.Yin"
[why]
When GTT domain size is smaller than VRAM, if APP apply a very large
buffer whose size is larger than GTT but smaller than VRAM, the size
validation will fail.
[how]
Validate VRAM domain size at first place, then GTT domain.
Change-Id:
On Tue, Mar 17, 2020 at 04:14:31PM -0700, Ralph Campbell wrote:
> +static int dmirror_fault(struct dmirror *dmirror, unsigned long start,
> + unsigned long end, bool write)
> +{
> + struct mm_struct *mm = dmirror->mm;
> + unsigned long addr;
> + uint64_t pfns[64];
On Thu, Mar 19, 2020 at 03:56:50PM -0700, Ralph Campbell wrote:
> Adding linux-kselft...@vger.kernel.org for the test config question.
>
> On 3/19/20 11:17 AM, Jason Gunthorpe wrote:
> > On Tue, Mar 17, 2020 at 04:14:31PM -0700, Ralph Campbell wrote:
> > >
> > > On 3/17/20 5:59 AM, Christoph
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