date:20220728

RE: [PATCH 1/5] drm/amdgpu: send msg to IMU for the front-door loading

2022-07-28 Thread Huang, Tim

Hi Xiaojian,

Please move the power up IPU to "smu->is_apu" as Evan' comment and make sure 
this is only called for PSP FW load type as 
backdoor loading already included this in the IMU start process.  After this, 

Series is
Reviewed-by: Tim Huang 

Best Regards,
Tim Huang

-Original Message-
From: Quan, Evan  
Sent: Thursday, July 28, 2022 4:14 PM
To: Du, Xiaojian ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Tim 
; Du, Xiaojian ; Zhang, Yifan 

Subject: RE: [PATCH 1/5] drm/amdgpu: send msg to IMU for the front-door loading

[AMD Official Use Only - General]



> -Original Message-
> From: amd-gfx  On Behalf Of 
> Xiaojian Du
> Sent: Thursday, July 28, 2022 3:04 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Tim 
> ; Du, Xiaojian ; Zhang, Yifan 
> 
> Subject: [PATCH 1/5] drm/amdgpu: send msg to IMU for the front-door 
> loading
> 
> This patch will make SMU send msg to IMU for the front-door loading, 
> it is required by some ASICs.
> 
> Signed-off-by: Yifan Zhang 
> Signed-off-by: Xiaojian Du 
> ---
>  drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 6d9b3c6af164..79c01fa4b875 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -1360,6 +1360,14 @@ static int smu_hw_init(void *handle)
>   return ret;
>   }
> 
> + if (smu->ppt_funcs->set_gfx_power_up_by_imu) {
> + ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
> + if (ret) {
> + dev_err(adev->dev, "Failed to Enable gfx imu!\n");
> + return ret;
> + }
> + }
[Quan, Evan] Per my understandings, this should be needed by APU only. Can you 
move this under "smu->is_apu" control as other features below?

Evan
> +
>   if (smu->is_apu) {
>   smu_dpm_set_vcn_enable(smu, true);
>   smu_dpm_set_jpeg_enable(smu, true);
> --
> 2.25.1

[PATCH 2/2] drm/amdgpu: Pessimistic availability based on rounded up allocations

2022-07-28 Thread Daniel Phillips

Seperately accumulate a statistic of rounded up allocations to use
to report availability, with a view to increasing the likelihood a
buffer object can be successfully allocated at exactly the size
reported by the availability API.
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h   | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 73bf8b5f2aa9..781274be5f27 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -96,6 +96,7 @@ struct amdgpu_amdkfd_fence {
 struct amdgpu_kfd_dev {
struct kfd_dev *dev;
uint64_t vram_used;
+   uint64_t vram_used_aligned;
bool init_complete;
struct work_struct reset_work;
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 014a594899fb..e5ea897f56bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -181,6 +181,7 @@ static int amdgpu_amdkfd_reserve_mem_limit(struct 
amdgpu_device *adev,
 * memory, TTM memory and GPU memory as computed above
 */
adev->kfd.vram_used += vram_needed;
+   adev->kfd.vram_used_aligned += ALIGN(vram_needed, 
VRAM_AVAILABLITY_ALIGN);
kfd_mem_limit.system_mem_used += system_mem_needed;
kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
 
@@ -199,6 +200,7 @@ static void unreserve_mem_limit(struct amdgpu_device *adev,
kfd_mem_limit.ttm_mem_used -= size;
} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
adev->kfd.vram_used -= size;
+   adev->kfd.vram_used_aligned -= ALIGN(size, 
VRAM_AVAILABLITY_ALIGN);
} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
kfd_mem_limit.system_mem_used -= size;
} else if (!(alloc_flag &
@@ -1644,7 +1646,7 @@ size_t amdgpu_amdkfd_get_available_memory(struct 
amdgpu_device *adev)
size_t available;
spin_lock(_mem_limit.mem_limit_lock);
available = adev->gmc.real_vram_size
-   - adev->kfd.vram_used
+   - adev->kfd.vram_used_aligned
- atomic64_read(>vram_pin_size)
- reserved_for_pt;
spin_unlock(_mem_limit.mem_limit_lock);
-- 
2.34.1

[PATCH 1/2] drm/amdgpu: Remove rounding from vram allocation path

2022-07-28 Thread Daniel Phillips

Rounding up allocations in the allocation path caused test regressions,
so now just round in the availability path.
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 11 +--
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 043a808c88a3..014a594899fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -40,10 +40,10 @@
 #define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
 
 /*
- * Align VRAM allocations to 2MB to avoid fragmentation caused by 4K 
allocations in the tail 2MB
+ * Align VRAM availability to 2MB to avoid fragmentation caused by 4K 
allocations in the tail 2MB
  * BO chunk
  */
-#define VRAM_ALLOCATION_ALIGN (1 << 21)
+#define VRAM_AVAILABLITY_ALIGN (1 << 21)
 
 /* Impose limit on how much memory KFD can use */
 static struct {
@@ -149,7 +149,7 @@ static int amdgpu_amdkfd_reserve_mem_limit(struct 
amdgpu_device *adev,
 * to avoid fragmentation caused by 4K allocations in the tail
 * 2M BO chunk.
 */
-   vram_needed = ALIGN(size, VRAM_ALLOCATION_ALIGN);
+   vram_needed = size;
} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
system_mem_needed = size;
} else if (!(alloc_flag &
@@ -198,7 +198,7 @@ static void unreserve_mem_limit(struct amdgpu_device *adev,
kfd_mem_limit.system_mem_used -= size;
kfd_mem_limit.ttm_mem_used -= size;
} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
-   adev->kfd.vram_used -= ALIGN(size, VRAM_ALLOCATION_ALIGN);
+   adev->kfd.vram_used -= size;
} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
kfd_mem_limit.system_mem_used -= size;
} else if (!(alloc_flag &
@@ -1642,7 +1642,6 @@ size_t amdgpu_amdkfd_get_available_memory(struct 
amdgpu_device *adev)
uint64_t reserved_for_pt =
ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
size_t available;
-
spin_lock(_mem_limit.mem_limit_lock);
available = adev->gmc.real_vram_size
- adev->kfd.vram_used
@@ -1650,7 +1649,7 @@ size_t amdgpu_amdkfd_get_available_memory(struct 
amdgpu_device *adev)
- reserved_for_pt;
spin_unlock(_mem_limit.mem_limit_lock);
 
-   return ALIGN_DOWN(available, VRAM_ALLOCATION_ALIGN);
+   return ALIGN_DOWN(available, VRAM_AVAILABLITY_ALIGN);
 }
 
 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
-- 
2.34.1

Re: [RESEND RFC 00/18] drm/display/dp_mst: Drop Radeon MST support, make MST atomic-only

2022-07-28 Thread Lyude Paul

Sorry for taking a while on respinning this! I've been busy with trying to
review as much nouveau patches as possible before we passed the deadline for
getting pulled into the kernel, since we've got quite a lot of pending patches
coming up. The pull deadline we had from Dave has passed at this point though,
so I should have a chance to respin this in the next few business days.

On Tue, 2022-06-07 at 15:29 -0400, Lyude Paul wrote:
> Ugh, thanks ./scripts/get_maintainers.pl for confusing and breaking
> git-send email <<. Sorry for the resend everyone.
> 
> For quite a while we've been carrying around a lot of legacy modesetting
> code in the MST helpers that has been rather annoying to keep around,
> and very often gets in the way of trying to implement additional
> functionality in MST such as fallback link rate retraining, dynamic BPC
> management and DSC support, etc. because of the fact that we can't rely
> on atomic for everything.
> 
> Luckily, we only actually have one user of the legacy MST code in the
> kernel - radeon. Originally I was thinking of trying to maintain this
> code and keep it around in some form, but I'm pretty unconvinced anyone
> is actually using this. My reasoning for that is because I've seen
> nearly no issues regarding MST on radeon for quite a while now - despite
> the fact my local testing seems to indicate it's quite broken. This
> isn't too surprising either, as MST support in radeon.ko is gated behind
> a module parameter that isn't enabled by default. This isn't to say I
> wouldn't be open to alternative suggestions, but I'd rather not be the
> one to have to spend time on that if at all possible! Plus, I already
> floated the idea of dropping this code by AMD folks a few times and
> didn't get much resistance.
> 
> As well, this series has some basic refactoring that I did along the way
> and some bugs I had to fix in order to get my atomic-only MST code
> working. Most of this is pretty straight forward and simply renaming
> things to more closely match the DisplayPort specification, as I think
> this will also make maintaining this code a lot easier in the long run
> (I've gotten myself confused way too many times because of this).
> 
> So far I've tested this on all three MST drivers: amdgpu, i915 and
> nouveau, along with making sure that removing the radeon MST code
> doesn't break anything else. The one thing I very much could use help
> with regarding testing though is making sure that this works with
> amdgpu's DSC support on MST.
> 
> So, with this we should be using the atomic state as much as possible
> with MST modesetting, hooray!
> 
> Cc: Wayne Lin 
> Cc: Ville Syrjälä 
> Cc: Fangzhi Zuo 
> Cc: Jani Nikula 
> Cc: Imre Deak 
> Cc: Daniel Vetter 
> Cc: Sean Paul 
> 
> Lyude Paul (18):
>   drm/amdgpu/dc/mst: Rename dp_mst_stream_allocation(_table)
>   drm/amdgpu/dm/mst: Rename get_payload_table()
>   drm/display/dp_mst: Rename drm_dp_mst_vcpi_allocation
>   drm/display/dp_mst: Call them time slots, not VCPI slots
>   drm/display/dp_mst: Fix confusing docs for
>     drm_dp_atomic_release_time_slots()
>   drm/display/dp_mst: Add some missing kdocs for atomic MST structs
>   drm/display/dp_mst: Add helper for finding payloads in atomic MST
>     state
>   drm/display/dp_mst: Add nonblocking helpers for DP MST
>   drm/display/dp_mst: Don't open code modeset checks for releasing time
>     slots
>   drm/display/dp_mst: Fix modeset tracking in
>     drm_dp_atomic_release_vcpi_slots()
>   drm/nouveau/kms: Cache DP encoders in nouveau_connector
>   drm/nouveau/kms: Pull mst state in for all modesets
>   drm/display/dp_mst: Add helpers for serializing SST <-> MST
>     transitions
>   drm/display/dp_mst: Drop all ports from topology on CSNs before
>     queueing link address work
>   drm/display/dp_mst: Skip releasing payloads if last connected port
>     isn't connected
>   drm/display/dp_mst: Maintain time slot allocations when deleting
>     payloads
>   drm/radeon: Drop legacy MST support
>   drm/display/dp_mst: Move all payload info into the atomic state
> 
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   72 +-
>  .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  111 +-
>  .../display/amdgpu_dm/amdgpu_dm_mst_types.c   |  126 +-
>  drivers/gpu/drm/amd/display/dc/core/dc_link.c |   10 +-
>  drivers/gpu/drm/amd/display/dc/dm_helpers.h   |    4 +-
>  .../amd/display/include/link_service_types.h  |   18 +-
>  drivers/gpu/drm/display/drm_dp_mst_topology.c | 1160 -
>  drivers/gpu/drm/i915/display/intel_display.c  |   11 +
>  drivers/gpu/drm/i915/display/intel_dp.c   |    9 +
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   |   91 +-
>  drivers/gpu/drm/i915/display/intel_hdcp.c |   24 +-
>  drivers/gpu/drm/nouveau/dispnv50/disp.c   |  202 ++-
>  drivers/gpu/drm/nouveau/dispnv50/disp.h   |    2 +
>  drivers/gpu/drm/nouveau/nouveau_connector.c   |   18 +-
>  drivers/gpu/drm/nouveau/nouveau_connector.h   |    3 +
>

Re: [PATCH v2] drm/amdkfd: use time_is_before_jiffies(a + b) to replace "jiffies - a > b"

2022-07-28 Thread Felix Kuehling


Am 2022-07-27 um 23:30 schrieb Yu Zhe:

time_is_before_jiffies deals with timer wrapping correctly.

Signed-off-by: Yu Zhe 


Thank you. This patch looks good to me. I'm applying it to 
amd-staging-drm-next.


Reviewed-by: Felix Kuehling 



---
  drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
index a9466d154395..34772fe74296 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
@@ -146,7 +146,7 @@ static void interrupt_wq(struct work_struct *work)
struct kfd_dev *dev = container_of(work, struct kfd_dev,
interrupt_work);
uint32_t ih_ring_entry[KFD_MAX_RING_ENTRY_SIZE];
-   long start_jiffies = jiffies;
+   unsigned long start_jiffies = jiffies;
  
  	if (dev->device_info.ih_ring_entry_size > sizeof(ih_ring_entry)) {

dev_err_once(dev->adev->dev, "Ring entry too small\n");
@@ -156,7 +156,7 @@ static void interrupt_wq(struct work_struct *work)
while (dequeue_ih_ring_entry(dev, ih_ring_entry)) {
dev->device_info.event_interrupt_class->interrupt_wq(dev,
ih_ring_entry);
-   if (jiffies - start_jiffies > HZ) {
+   if (time_is_before_jiffies(start_jiffies + HZ)) {
/* If we spent more than a second processing signals,
 * reschedule the worker to avoid soft-lockup warnings
 */

Re: [PATCH v4 16/41] dyndbg: add drm.debug style bitmap support

2022-07-28 Thread jim . cromie

On Fri, Jul 22, 2022 at 2:33 PM Jason Baron  wrote:
>
>
>
> On 7/20/22 11:32, Jim Cromie wrote:
> > Add kernel_param_ops and callbacks to apply a class-map to a
> > sysfs-node, which then can control classes defined in that class-map.
> > This supports uses like:
> >
> >   echo 0x3 > /sys/module/drm/parameters/debug
> >
> > IE add these:
> >
> >  - int param_set_dyndbg_classes()
> >  - int param_get_dyndbg_classes()
> >  - struct kernel_param_ops param_ops_dyndbg_classes
> >
> > Following the model of kernel/params.c STANDARD_PARAM_DEFS, these are
> > non-static and exported.  This might be unnecessary here.
> >
> > get/set use an augmented kernel_param; the arg refs a new struct
> > ddebug_classes_bitmap_param, initialized by DYNAMIC_DEBUG_CLASSBITS
> > macro, which contains:
> >
> > BITS: a pointer to the user module's ulong holding the bits/state.  By
> > ref'g the client's bit-state _var, we coordinate with existing code
> > (such as drm_debug_enabled) which uses the _var, so it works
> > unchanged, even as the foundation is switched out underneath it..
> > Using a ulong allows use of BIT() etc.
> >
> > FLAGS: dyndbg.flags toggled by changes to bitmap. Usually just "p".
> >
> > MAP: a pointer to struct ddebug_classes_map, which maps those
> > class-names to .class_ids 0..N that the module is using.  This
> > class-map is declared & initialized by DEFINE_DYNDBG_CLASSMAP.
> >
> > map-type: add support here for DD_CLASS_DISJOINT, DD_CLASS_VERBOSE.
> >
> > These 2 class-types both expect an integer; _DISJOINT treats input
> > like a bit-vector (ala drm.debug), and sets each bit accordingly.
> >
> > _VERBOSE treats input like a bit-pos:N, then sets bits(0..N)=1, and
> > bits(N+1..max)=0.  This applies (bit > bits.
> >
> > cases DD_CLASS_SYMBOLIC, DD_CLASS_LEVELS are included for the complete
> > picture, with commented out call to a following commit.
> >
> > NOTES:
> >
> > this now includes SYMBOLIC/LEVELS support, too tedious to keep
> > separate thru all the tweaking.
> >
> > get-param undoes the bit-pos -> bitmap transform that set-param does
> > on VERBOSE inputs, this gives the read-what-was-written property.
> >
> > _VERBOSE is overlay on _DISJOINT:
> >
> > verbose-maps still need class-names, even though theyre not usable at
> > the sysfs interface (unlike with _SYMBOLIC/_LEVELS).
> >
> >  - It must have a "V0" name,
> >something below "V1" to turn "V1" off.
> >__pr_debug_cls(V0,..) is printk, don't do that.
> >
> >  - "class names" is required at the >control interface.
> >  - relative levels are not enforced at >control
> >
> > IOW this is possible, and maybe confusing:
> >
> >   echo class V3 +p > control
> >   echo class V1 -p > control
> >
> > IMO thats ok, relative verbosity is an interface property.
> >
> > Signed-off-by: Jim Cromie 
> > ---
> > . drop kp->mod->name as unneeded (build-dependent) 
> > ---
> >  include/linux/dynamic_debug.h |  18 
> >  lib/dynamic_debug.c   | 193 ++
> >  2 files changed, 211 insertions(+)
> >
> > diff --git a/include/linux/dynamic_debug.h b/include/linux/dynamic_debug.h
> > index f57076e02767..b50bdd5c8184 100644
> > --- a/include/linux/dynamic_debug.h
> > +++ b/include/linux/dynamic_debug.h
> > @@ -113,6 +113,12 @@ struct ddebug_class_map {
> >  #define NUM_TYPE_ARGS(eltype, ...)   \
> >   (sizeof((eltype[]) {__VA_ARGS__}) / sizeof(eltype))
> >
> > +struct ddebug_classes_bitmap_param {
> > + unsigned long *bits;
> > + char flags[8];
> > + const struct ddebug_class_map *map;
> > +};
> > +
> >  #if defined(CONFIG_DYNAMIC_DEBUG_CORE)
> >
> >  int ddebug_add_module(struct _ddebug *tab, unsigned int num_debugs,
> > @@ -274,6 +280,10 @@ void __dynamic_ibdev_dbg(struct _ddebug *descriptor,
> >  KERN_DEBUG, prefix_str, prefix_type, \
> >  rowsize, groupsize, buf, len, ascii)
> >
> > +struct kernel_param;
> > +int param_set_dyndbg_classes(const char *instr, const struct kernel_param 
> > *kp);
> > +int param_get_dyndbg_classes(char *buffer, const struct kernel_param *kp);
> > +
> >  /* for test only, generally expect drm.debug style macro wrappers */
> >  #define __pr_debug_cls(cls, fmt, ...) do {   \
> >   BUILD_BUG_ON_MSG(!__builtin_constant_p(cls),\
> > @@ -322,6 +332,14 @@ static inline int ddebug_dyndbg_module_param_cb(char 
> > *param, char *val,
> >   rowsize, groupsize, buf, len, ascii);   \
> >   } while (0)
> >
> > +struct kernel_param;
> > +static inline int param_set_dyndbg_classes(const char *instr, const struct 
> > kernel_param *kp)
> > +{ return 0; }
> > +static inline int param_get_dyndbg_classes(char *buffer, const struct 
> > kernel_param *kp)
> > +{ return 0; }
> > +
> >  #endif /* !CONFIG_DYNAMIC_DEBUG_CORE */
> >
> > +extern const struct kernel_param_ops param_ops_dyndbg_classes;
> > +
> >  #endif
> > diff --git

Re: [PATCH] drm/amd/display: Fix a compilation failure on PowerPC caused by FPU code

2022-07-28 Thread Alex Deucher

On Thu, Jul 28, 2022 at 4:34 PM Rodrigo Siqueira
 wrote:
>
> We got a report from Stephen/Michael that the PowerPC build was failing
> with the following error:
>
> ld: drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.o uses hard float, 
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o uses soft float
> ld: failed to merge target specific data of file 
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o
>
> This error happened because of the function optc3_set_vrr_m_const. This
> function expects a double as a parameter in a code that is not allowed
> to have FPU operations. After further investigation, it became clear
> that optc3_set_vrr_m_const was never invoked, so we can safely drop this
> function and fix the ld issue.
>
> Cc: Alex Deucher 
> Cc: Melissa Wen 
> Reported-by: Stephen Rothwell 
> Reported-by: Michael Ellerman 
> Signed-off-by: Rodrigo Siqueira 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c| 8 
>  drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h| 3 ---
>  drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c| 1 -
>  drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 2 --
>  4 files changed, 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c 
> b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
> index d072997477dd..1782b9c26cf4 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
> @@ -184,14 +184,6 @@ void optc3_set_dsc_config(struct timing_generator *optc,
> REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0);
>  }
>
> -void optc3_set_vrr_m_const(struct timing_generator *optc,
> -   double vtotal_avg)
> -{
> -   DC_FP_START();
> -   optc3_fpu_set_vrr_m_const(optc, vtotal_avg);
> -   DC_FP_END();
> -}
> -
>  void optc3_set_odm_bypass(struct timing_generator *optc,
> const struct dc_crtc_timing *dc_crtc_timing)
>  {
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h 
> b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
> index 33bd12f5dc17..dd45a5499b07 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
> @@ -329,9 +329,6 @@ void optc3_lock_doublebuffer_enable(struct 
> timing_generator *optc);
>
>  void optc3_lock_doublebuffer_disable(struct timing_generator *optc);
>
> -void optc3_set_vrr_m_const(struct timing_generator *optc,
> -   double vtotal_avg);
> -
>  void optc3_set_drr_trigger_window(struct timing_generator *optc,
> uint32_t window_start, uint32_t window_end);
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c 
> b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
> index 992e56c6907e..eff1f4e17689 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
> @@ -281,7 +281,6 @@ static struct timing_generator_funcs dcn32_tg_funcs = {
> .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
> .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
> .enable_optc_clock = optc1_enable_optc_clock,
> -   .set_vrr_m_const = optc3_set_vrr_m_const,
> .set_drr = optc31_set_drr, // TODO: Update to optc32_set_drr 
> once FW headers are promoted
> .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
> .set_vtotal_min_max = optc3_set_vtotal_min_max,
> diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h 
> b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
> index 62d4683f17a2..4cfa733cf96f 100644
> --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
> +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
> @@ -302,8 +302,6 @@ struct timing_generator_funcs {
> int group_idx,
> uint32_t gsl_ready_signal);
> void (*set_out_mux)(struct timing_generator *tg, enum 
> otg_out_mux_dest dest);
> -   void (*set_vrr_m_const)(struct timing_generator *optc,
> -   double vtotal_avg);
> void (*set_drr_trigger_window)(struct timing_generator *optc,
> uint32_t window_start, uint32_t window_end);
> void (*set_vtotal_change_limit)(struct timing_generator *optc,
> --
> 2.35.1
>

[PATCH] drm/amd/display: Fix a compilation failure on PowerPC caused by FPU code

2022-07-28 Thread Rodrigo Siqueira

We got a report from Stephen/Michael that the PowerPC build was failing
with the following error:

ld: drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.o uses hard float, 
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o uses soft float
ld: failed to merge target specific data of file 
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o

This error happened because of the function optc3_set_vrr_m_const. This
function expects a double as a parameter in a code that is not allowed
to have FPU operations. After further investigation, it became clear
that optc3_set_vrr_m_const was never invoked, so we can safely drop this
function and fix the ld issue.

Cc: Alex Deucher 
Cc: Melissa Wen 
Reported-by: Stephen Rothwell 
Reported-by: Michael Ellerman 
Signed-off-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c| 8 
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h| 3 ---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c| 1 -
 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 2 --
 4 files changed, 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
index d072997477dd..1782b9c26cf4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
@@ -184,14 +184,6 @@ void optc3_set_dsc_config(struct timing_generator *optc,
REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0);
 }
 
-void optc3_set_vrr_m_const(struct timing_generator *optc,
-   double vtotal_avg)
-{
-   DC_FP_START();
-   optc3_fpu_set_vrr_m_const(optc, vtotal_avg);
-   DC_FP_END();
-}
-
 void optc3_set_odm_bypass(struct timing_generator *optc,
const struct dc_crtc_timing *dc_crtc_timing)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
index 33bd12f5dc17..dd45a5499b07 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
@@ -329,9 +329,6 @@ void optc3_lock_doublebuffer_enable(struct timing_generator 
*optc);
 
 void optc3_lock_doublebuffer_disable(struct timing_generator *optc);
 
-void optc3_set_vrr_m_const(struct timing_generator *optc,
-   double vtotal_avg);
-
 void optc3_set_drr_trigger_window(struct timing_generator *optc,
uint32_t window_start, uint32_t window_end);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
index 992e56c6907e..eff1f4e17689 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
@@ -281,7 +281,6 @@ static struct timing_generator_funcs dcn32_tg_funcs = {
.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
.enable_optc_clock = optc1_enable_optc_clock,
-   .set_vrr_m_const = optc3_set_vrr_m_const,
.set_drr = optc31_set_drr, // TODO: Update to optc32_set_drr 
once FW headers are promoted
.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
.set_vtotal_min_max = optc3_set_vtotal_min_max,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 62d4683f17a2..4cfa733cf96f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -302,8 +302,6 @@ struct timing_generator_funcs {
int group_idx,
uint32_t gsl_ready_signal);
void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest 
dest);
-   void (*set_vrr_m_const)(struct timing_generator *optc,
-   double vtotal_avg);
void (*set_drr_trigger_window)(struct timing_generator *optc,
uint32_t window_start, uint32_t window_end);
void (*set_vtotal_change_limit)(struct timing_generator *optc,
-- 
2.35.1

[PATCH 16/16] drm/amd/display: Remove never used VBA variables

2022-07-28 Thread Maíra Canal

The variables OutputBPP, VTotal_Min,
TotalBandwidthConsumedGBytePerSecond, BandwidthSupport,
dummy_integer_array, dummysinglestring,
SurfaceRequiredDISPCLKWithoutODMCombine, SurfaceRequiredDISPCLK,
MinVoltageLevel, and MaxVoltageLevel are never used. So, remove the
variables entries from the struct vba_vars_st.

Signed-off-by: Maíra Canal 
---
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 10 --
 1 file changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 5eaedc3bf2c8..839f8fde4b47 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -527,7 +527,6 @@ struct vba_vars_st {
unsigned int MinCompressedBufferSizeInKByte;
unsigned int NumberOfActiveSurfaces;
bool ViewportStationary[DC__NUM_DPP__MAX];
-   double   OutputBPP[DC__NUM_DPP__MAX];
unsigned int GPUVMMinPageSizeKBytes[DC__NUM_DPP__MAX];
bool SynchronizeTimingsFinal;
bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
@@ -557,7 +556,6 @@ struct vba_vars_st {
unsigned int HTotal[DC__NUM_DPP__MAX];
unsigned int VTotal[DC__NUM_DPP__MAX];
unsigned int VTotal_Max[DC__NUM_DPP__MAX];
-   unsigned int VTotal_Min[DC__NUM_DPP__MAX];
int DPPPerPlane[DC__NUM_DPP__MAX];
double PixelClock[DC__NUM_DPP__MAX];
double PixelClockBackEnd[DC__NUM_DPP__MAX];
@@ -690,12 +688,10 @@ struct vba_vars_st {
/*outputs*/
bool ScaleRatioAndTapsSupport;
bool SourceFormatPixelAndScanSupport;
-   double TotalBandwidthConsumedGBytePerSecond;
bool DCCEnabledInAnyPlane;
bool WritebackLatencySupport;
bool WritebackModeSupport;
bool Writeback10bpc420Supported;
-   bool BandwidthSupport[DC__VOLTAGE_STATES];
unsigned int TotalNumberOfActiveWriteback;
double CriticalPoint;
double ReturnBWToDCNPerState;
@@ -955,9 +951,7 @@ struct vba_vars_st {
unsigned intdummyinteger9;
unsigned intdummyinteger10;
unsigned intdummyinteger11;
-   unsigned intdummy_integer_array[8][DC__NUM_DPP__MAX];
 
-   bool   dummysinglestring;
bool   SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
double PlaneRequiredDISPCLKWithODMCombine2To1;
double PlaneRequiredDISPCLKWithODMCombine4To1;
@@ -1248,11 +1242,7 @@ struct vba_vars_st {
unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2];
double ReadBandwidthSurfaceLuma[DC__NUM_DPP__MAX];
double ReadBandwidthSurfaceChroma[DC__NUM_DPP__MAX];
-   double SurfaceRequiredDISPCLKWithoutODMCombine;
-   double SurfaceRequiredDISPCLK;
double MinActiveFCLKChangeLatencySupported;
-   int MinVoltageLevel;
-   int MaxVoltageLevel;
unsigned int TotalNumberOfSingleDPPSurfaces[DC__VOLTAGE_STATES][2];
unsigned int 
CompressedBufferSizeInkByteAllStates[DC__VOLTAGE_STATES][2];
unsigned int 
DETBufferSizeInKByteAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
-- 
2.37.1

[PATCH 15/16] drm/amd/display: Remove only mencioned once VBA variables

2022-07-28 Thread Maíra Canal

The variables PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE,
RefreshRate, FECEnable, ScalerRecoutWidth, MaxNumDP2p0Streams, and
MaxNumDP2p0Outputs are only used on assignments, so there values are not
used on code. So, remove the variables entries from the struct
vba_vars_st.

Signed-off-by: Maíra Canal 
---
 .../amd/display/dc/dml/dcn32/display_mode_vba_32.c  |  1 -
 .../gpu/drm/amd/display/dc/dml/display_mode_vba.c   | 13 ++---
 .../gpu/drm/amd/display/dc/dml/display_mode_vba.h   |  6 --
 3 files changed, 2 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 3c044549c95f..e9c6cc45bfc3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -3715,7 +3715,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
}
 
mode_lib->vba.DSCEnabled[k] = 
mode_lib->vba.RequiresDSC[mode_lib->vba.VoltageLevel][k];
-   mode_lib->vba.FECEnable[k] = 
mode_lib->vba.RequiresFEC[mode_lib->vba.VoltageLevel][k];
mode_lib->vba.OutputBpp[k] = 
mode_lib->vba.OutputBppPerState[mode_lib->vba.VoltageLevel][k];
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 7a4a013f195a..1176a73813aa 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -340,7 +340,6 @@ static void fetch_socbb_params(struct display_mode_lib 
*mode_lib)
mode_lib->vba.SMNLatency = soc->smn_latency_us;
mode_lib->vba.MALLAllocatedForDCNFinal = 
soc->mall_allocated_for_dcn_mbytes;
 
-   mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE = 
soc->pct_ideal_dram_bw_after_urgent_strobe;

mode_lib->vba.MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation
 =
soc->max_avg_fabric_bw_use_normal_percent;

mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE
 =
@@ -441,11 +440,9 @@ static void fetch_ip_params(struct display_mode_lib 
*mode_lib)
mode_lib->vba.CompbufReservedSpaceZs = ip->compbuf_reserved_space_zs;
mode_lib->vba.CompressedBufferSegmentSizeInkByteFinal = 
ip->compressed_buffer_segment_size_in_kbytes;
mode_lib->vba.LineBufferSizeFinal = ip->line_buffer_size_bits;
-   mode_lib->vba.AlphaPixelChunkSizeInKByte = 
ip->alpha_pixel_chunk_size_kbytes; // not ysed
-   mode_lib->vba.MinPixelChunkSizeBytes = ip->min_pixel_chunk_size_bytes; 
// not used
+   mode_lib->vba.AlphaPixelChunkSizeInKByte = 
ip->alpha_pixel_chunk_size_kbytes;
+   mode_lib->vba.MinPixelChunkSizeBytes = ip->min_pixel_chunk_size_bytes;
mode_lib->vba.MaximumPixelsPerLinePerDSCUnit = 
ip->maximum_pixels_per_line_per_dsc_unit;
-   mode_lib->vba.MaxNumDP2p0Outputs = ip->max_num_dp2p0_outputs;
-   mode_lib->vba.MaxNumDP2p0Streams = ip->max_num_dp2p0_streams;
mode_lib->vba.DCCMetaBufferSizeBytes = ip->dcc_meta_buffer_size_bytes;
 
mode_lib->vba.PixelChunkSizeInKByte = ip->pixel_chunk_size_kbytes;
@@ -560,7 +557,6 @@ static void fetch_pipe_params(struct display_mode_lib 
*mode_lib)

mode_lib->vba.UsesMALLForPStateChange[mode_lib->vba.NumberOfActivePlanes] = 
src->use_mall_for_pstate_change;

mode_lib->vba.UseMALLForStaticScreen[mode_lib->vba.NumberOfActivePlanes] = 
src->use_mall_for_static_screen;

mode_lib->vba.GPUVMMinPageSizeKBytes[mode_lib->vba.NumberOfActivePlanes] = 
src->gpuvm_min_page_size_kbytes;
-   mode_lib->vba.RefreshRate[mode_lib->vba.NumberOfActivePlanes] = 
dst->refresh_rate; //todo remove this

mode_lib->vba.OutputLinkDPRate[mode_lib->vba.NumberOfActivePlanes] = 
dout->dp_rate;
mode_lib->vba.ODMUse[mode_lib->vba.NumberOfActivePlanes] = 
dst->odm_combine_policy;

mode_lib->vba.DETSizeOverride[mode_lib->vba.NumberOfActivePlanes] = 
src->det_size_override;
@@ -606,8 +602,6 @@ static void fetch_pipe_params(struct display_mode_lib 
*mode_lib)
mode_lib->vba.VActive[mode_lib->vba.NumberOfActivePlanes] = 
dst->vactive;
mode_lib->vba.SurfaceTiling[mode_lib->vba.NumberOfActivePlanes] 
=
(enum dm_swizzle_mode) (src->sw_mode);
-   
mode_lib->vba.ScalerRecoutWidth[mode_lib->vba.NumberOfActivePlanes] =
-   dst->recout_width; // TODO: or should this be 
full_recout_width???...maybe only when in hsplit mode?

mode_lib->vba.ODMCombineEnabled[mode_lib->vba.NumberOfActivePlanes] =
dst->odm_combine;
mode_lib->vba.OutputFormat[mode_lib->vba.NumberOfActivePlanes] =
@@

Re: [PATCH v2 1/6] drm/amdgpu: add mode2 reset for sienna_cichlid

2022-07-28 Thread Andrey Grodzovsky




On 2022-07-28 06:30, Victor Zhao wrote:

To meet the requirement for multi container usecase which needs
a quicker reset and not causing VRAM lost, adding the Mode2
reset handler for sienna_cichlid.

v2: move skip mode2 flag part separately

Signed-off-by: Victor Zhao 
---
  drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c |   7 +
  drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c   | 297 ++
  drivers/gpu/drm/amd/amdgpu/sienna_cichlid.h   |  32 ++
  .../pm/swsmu/inc/pmfw_if/smu_v11_0_7_ppsmc.h  |   4 +-
  drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h  |   3 +-
  .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   |  54 
  7 files changed, 395 insertions(+), 4 deletions(-)
  create mode 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
  create mode 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index c7d0cd15b5ef..7030ac2d7d2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -75,7 +75,7 @@ amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o 
vega10_reg_init.o \
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o 
mxgpu_nv.o \
nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o 
soc21.o \
-   nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o
+   sienna_cichlid.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o 
lsdma_v6_0.o
  
  # add DF block

  amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
index 32c86a0b145c..f778466bb9db 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
@@ -23,6 +23,7 @@
  
  #include "amdgpu_reset.h"

  #include "aldebaran.h"
+#include "sienna_cichlid.h"
  
  int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,

 struct amdgpu_reset_handler *handler)
@@ -40,6 +41,9 @@ int amdgpu_reset_init(struct amdgpu_device *adev)
case IP_VERSION(13, 0, 2):
ret = aldebaran_reset_init(adev);
break;
+   case IP_VERSION(11, 0, 7):
+   ret = sienna_cichlid_reset_init(adev);
+   break;
default:
break;
}
@@ -55,6 +59,9 @@ int amdgpu_reset_fini(struct amdgpu_device *adev)
case IP_VERSION(13, 0, 2):
ret = aldebaran_reset_fini(adev);
break;
+   case IP_VERSION(11, 0, 7):
+   ret = sienna_cichlid_reset_fini(adev);
+   break;
default:
break;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c 
b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
new file mode 100644
index ..0512960bed23
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
@@ -0,0 +1,297 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "sienna_cichlid.h"
+#include "amdgpu_reset.h"
+#include "amdgpu_amdkfd.h"
+#include "amdgpu_dpm.h"
+#include "amdgpu_job.h"
+#include "amdgpu_ring.h"
+#include "amdgpu_ras.h"
+#include "amdgpu_psp.h"
+#include "amdgpu_xgmi.h"
+
+static struct amdgpu_reset_handler *
+sienna_cichlid_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
+   struct amdgpu_reset_context *reset_context)
+{
+   struct amdgpu_reset_handler *handler;
+   struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
+
+   if (reset_context->method != AMD_RESET_METHOD_NONE) {
+   list_for_each_entry(handler, _ctl->reset_handlers,
+handler_list) {
+   if (handler->reset_method == reset_context->method)
+   return handler;

Re: [PATCH v2 6/6] drm/amdgpu: reduce reset time

2022-07-28 Thread Andrey Grodzovsky




On 2022-07-28 06:30, Victor Zhao wrote:

In multi container use case, reset time is important, so skip ring
tests and cp halt wait during ip suspending for reset as they are
going to fail and cost more time on reset

v2: add a hang flag to indicate the reset comes from a job timeout,
skip ring test and cp halt wait in this case

Signed-off-by: Victor Zhao 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c   |  3 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c   |  2 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c |  1 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h |  1 +
  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 11 +--
  5 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 222d3d7ea076..c735a17c6afb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -27,6 +27,7 @@
  #include "amdgpu_gfx.h"
  #include "amdgpu_rlc.h"
  #include "amdgpu_ras.h"
+#include "amdgpu_reset.h"
  
  /* delay 0.1 second to enable gfx off feature */

  #define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(100)
@@ -477,7 +478,7 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
kiq->pmf->kiq_unmap_queues(kiq_ring, >gfx.compute_ring[i],
   RESET_QUEUES, 0, 0);
  
-	if (adev->gfx.kiq.ring.sched.ready)

+   if (adev->gfx.kiq.ring.sched.ready && !(amdgpu_in_reset(adev) && 
adev->reset_domain->hang))



I think it's enough to look at adev->reset_domain->hang and you can drop 
the amdgpu_in_reset check.



r = amdgpu_ring_test_helper(kiq_ring);
spin_unlock(>gfx.kiq.ring_lock);
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

index 6c3e7290153f..bb40880a557f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -49,6 +49,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct 
drm_sched_job *s_job)
}
  
  	memset(, 0, sizeof(struct amdgpu_task_info));

+   adev->reset_domain->hang = true;
  
  	if (amdgpu_gpu_recovery &&

amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) 
{
@@ -83,6 +84,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct 
drm_sched_job *s_job)
}
  
  exit:

+   adev->reset_domain->hang = false;
drm_dev_exit(idx);
return DRM_GPU_SCHED_STAT_NOMINAL;
  }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
index 9da5ead50c90..b828fe773f50 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
@@ -155,6 +155,7 @@ struct amdgpu_reset_domain 
*amdgpu_reset_create_reset_domain(enum amdgpu_reset_d
atomic_set(_domain->in_gpu_reset, 0);
atomic_set(_domain->reset_res, 0);
init_rwsem(_domain->sem);
+   reset_domain->hang = false;
  
  	return reset_domain;

  }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
index cc4b2eeb24cf..29e324add552 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
@@ -84,6 +84,7 @@ struct amdgpu_reset_domain {
struct rw_semaphore sem;
atomic_t in_gpu_reset;
atomic_t reset_res;
+   bool hang;
  };
  
  
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

index fafbad3cf08d..a384e04d916c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -29,6 +29,7 @@
  #include "amdgpu.h"
  #include "amdgpu_gfx.h"
  #include "amdgpu_psp.h"
+#include "amdgpu_reset.h"
  #include "nv.h"
  #include "nvd.h"
  
@@ -5971,6 +5972,9 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)

WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
}
  
+	if ((amdgpu_in_reset(adev) && adev->reset_domain->hang) && !enable)

+   return 0;
+



Same as above



for (i = 0; i < adev->usec_timeout; i++) {
if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
break;
@@ -7569,8 +7573,10 @@ static int gfx_v10_0_kiq_disable_kgq(struct 
amdgpu_device *adev)
for (i = 0; i < adev->gfx.num_gfx_rings; i++)
kiq->pmf->kiq_unmap_queues(kiq_ring, >gfx.gfx_ring[i],
   PREEMPT_QUEUES, 0, 0);
-
-   return amdgpu_ring_test_helper(kiq_ring);
+   if (!(amdgpu_in_reset(adev) && adev->reset_domain->hang))



Same as above

Andrey



+   return amdgpu_ring_test_helper(kiq_ring);
+   else
+   return 0;
  }
  #endif
  
@@ -7610,6 +7616,7 @@ static int gfx_v10_0_hw_fini(void *handle)
  
  		return 0;

}
+
gfx_v10_0_cp_enable(adev, false);
gfx_v10_0_enable_gui_idle_interrupt(adev, false);

[PATCH 13/16] drm/amd/display: Remove TFinalxFill VBA variable

2022-07-28 Thread Maíra Canal

The TFinalxFill variable from the struct vba_vars_st is only used
on assignments, so its value is not used on code. So,
remove the TFinalxFill entry from the struct vba_vars_st.

Signed-off-by: Maíra Canal 
---
 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 3 ---
 .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c   | 3 ---
 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 3 ---
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h  | 1 -
 4 files changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index 7effe4be61b2..91e74c0f3c3c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -2618,9 +2618,6 @@ static void 
dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
mode_lib->vba.RemainingFillLevel = dml_max(
0.0,
mode_lib->vba.FinalFillLevel - 
mode_lib->vba.InitFillLevel);
-   mode_lib->vba.TFinalxFill = 
mode_lib->vba.RemainingFillLevel
-   / (mode_lib->vba.SrcActiveDrainRate
-   * 
mode_lib->vba.XFCFillBWOverhead / 100);
}
}
{
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index a23b400f615b..9b52f9f3e4a0 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -2691,9 +2691,6 @@ static void 
dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
mode_lib->vba.RemainingFillLevel = dml_max(
0.0,
mode_lib->vba.FinalFillLevel - 
mode_lib->vba.InitFillLevel);
-   mode_lib->vba.TFinalxFill = 
mode_lib->vba.RemainingFillLevel
-   / (mode_lib->vba.SrcActiveDrainRate
-   * 
mode_lib->vba.XFCFillBWOverhead / 100);
}
}
{
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index 4ba9fa17ea39..bc8cc21cf3f6 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -2627,9 +2627,6 @@ static void 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
mode_lib->vba.RemainingFillLevel = dml_max(
0.0,
mode_lib->vba.FinalFillLevel - 
mode_lib->vba.InitFillLevel);
-   mode_lib->vba.TFinalxFill = 
mode_lib->vba.RemainingFillLevel
-   / (mode_lib->vba.SrcActiveDrainRate
-   * 
mode_lib->vba.XFCFillBWOverhead / 100);
}
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index f973d0ee82f9..46e69f941bff 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -421,7 +421,6 @@ struct vba_vars_st {
double FinalFillMargin;
double FinalFillLevel;
double RemainingFillLevel;
-   double TFinalxFill;
 
//
// SOC Bounding Box Parameters
-- 
2.37.1

[PATCH 14/16] drm/amd/display: Remove MaximumDCCCompressionYSurface VBA variable

2022-07-28 Thread Maíra Canal

The MaximumDCCCompressionYSurface variable from the struct vba_vars_st is
only used on assignments, so its value is not used on code. So,
remove the MaximumDCCCompressionYSurface entry from the struct vba_vars_st.

Signed-off-by: Maíra Canal 
---
 .../amd/display/dc/dml/dcn21/display_mode_vba_21.c  | 13 +++--
 .../gpu/drm/amd/display/dc/dml/display_mode_vba.h   |  1 -
 2 files changed, 3 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index bc8cc21cf3f6..7007b6e16e7d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -143,7 +143,7 @@ static bool CalculatePrefetchSchedule(
double *VReadyOffsetPix);
 static double RoundToDFSGranularityUp(double Clock, double VCOSpeed);
 static double RoundToDFSGranularityDown(double Clock, double VCOSpeed);
-static double CalculateDCCConfiguration(
+static void CalculateDCCConfiguration(
bool DCCEnabled,
bool DCCProgrammingAssumesScanDirectionUnknown,
unsigned int ViewportWidth,
@@ -1072,7 +1072,7 @@ static double RoundToDFSGranularityDown(double Clock, 
double VCOSpeed)
return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4 / Clock, 1);
 }
 
-static double CalculateDCCConfiguration(
+static void CalculateDCCConfiguration(
bool DCCEnabled,
bool DCCProgrammingAssumesScanDirectionUnknown,
unsigned int ViewportWidth,
@@ -1087,7 +1087,6 @@ static double CalculateDCCConfiguration(
unsigned int *MaxCompressedBlock,
unsigned int *Independent64ByteBlock)
 {
-   double MaximumDCCCompressionSurface = 0.0;
enum {
REQ_256Bytes,
REQ_128BytesNonContiguous,
@@ -1185,25 +1184,19 @@ static double CalculateDCCConfiguration(
*MaxUncompressedBlock = 256;
*MaxCompressedBlock = 256;
*Independent64ByteBlock = false;
-   MaximumDCCCompressionSurface = 4.0;
} else if (Request == REQ_128BytesContiguous) {
*MaxUncompressedBlock = 128;
*MaxCompressedBlock = 128;
*Independent64ByteBlock = false;
-   MaximumDCCCompressionSurface = 2.0;
} else if (Request == REQ_128BytesNonContiguous) {
*MaxUncompressedBlock = 256;
*MaxCompressedBlock = 64;
*Independent64ByteBlock = true;
-   MaximumDCCCompressionSurface = 4.0;
} else {
*MaxUncompressedBlock = 0;
*MaxCompressedBlock = 0;
*Independent64ByteBlock = 0;
-   MaximumDCCCompressionSurface = 0.0;
}
-
-   return MaximumDCCCompressionSurface;
 }
 
 static double CalculatePrefetchSourceLines(
@@ -2568,7 +2561,7 @@ static void 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
// DCC Configuration
mode_lib->vba.ActiveDPPs = 0;
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-   locals->MaximumDCCCompressionYSurface[k] = 
CalculateDCCConfiguration(
+   CalculateDCCConfiguration(
mode_lib->vba.DCCEnable[k],
false, // We should always know the direction 
DCCProgrammingAssumesScanDirectionUnknown,
mode_lib->vba.ViewportWidth[k],
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 46e69f941bff..a07e97035dd1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -1032,7 +1032,6 @@ struct vba_vars_st {
unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX];
unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX];
unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX];
-   double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX];
unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX];
unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX];
unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX];
-- 
2.37.1

[PATCH 07/16] drm/amd/display: Remove WritebackAllowFCLKChangeEndPosition VBA variable

2022-07-28 Thread Maíra Canal

The WritebackAllowFCLKChangeEndPosition variable from the struct
vba_vars_st is only used on assignments, so its value is not used on
code. So, remove the WritebackAllowFCLKChangeEndPosition entry
from the struct vba_vars_st.

Signed-off-by: Maíra Canal 
---
 .../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c| 4 
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 -
 2 files changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index e2e1d6e77902..756a55f69799 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -1219,12 +1219,8 @@ static void 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
v->WritebackAllowDRAMClockChangeEndPosition[k] 
= dml_max(0,
v->VStartup[k] * 
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]
- 
v->Watermark.WritebackDRAMClockChangeWatermark);
-   v->WritebackAllowFCLKChangeEndPosition[k] = 
dml_max(0,
-   v->VStartup[k] * 
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]
-   - 
v->Watermark.WritebackFCLKChangeWatermark);
} else {
v->WritebackAllowDRAMClockChangeEndPosition[k] 
= 0;
-   v->WritebackAllowFCLKChangeEndPosition[k] = 0;
}
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 76cba5d7ac10..518e599d74e2 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -1303,7 +1303,6 @@ struct vba_vars_st {
bool OutputMultistreamEn[DC__NUM_DPP__MAX];
bool UsesMALLForStaticScreen[DC__NUM_DPP__MAX];
double MaxActiveDRAMClockChangeLatencySupported[DC__NUM_DPP__MAX];
-   double WritebackAllowFCLKChangeEndPosition[DC__NUM_DPP__MAX];
bool PTEBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
bool DCCMetaBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in 
DML32
bool NotEnoughDSCSlices[DC__VOLTAGE_STATES];
-- 
2.37.1

[PATCH 12/16] drm/amd/display: Remove NumberOfDP2p0Support VBA variable

2022-07-28 Thread Maíra Canal

The NumberOfDP2p0Support variable from the struct vba_vars_st is
only used on assignments, so its value is not used on code. So,
remove the NumberOfDP2p0Support entry from the struct vba_vars_st.

Signed-off-by: Maíra Canal 
---
 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 --
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h  | 1 -
 2 files changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 6d4907656f9f..3c044549c95f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -2186,8 +2186,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
 
mode_lib->vba.NumberOfOTGSupport = 
(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveOTG
 <= mode_lib->vba.MaxNumOTG);
mode_lib->vba.NumberOfHDMIFRLSupport = 
(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveHDMIFRL
 <= mode_lib->vba.MaxNumHDMIFRLOutputs);
-   mode_lib->vba.NumberOfDP2p0Support = 
(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveDP2p0
 <= mode_lib->vba.MaxNumDP2p0Streams
-   && 
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveDP2p0Outputs
 <= mode_lib->vba.MaxNumDP2p0Outputs);
 
/* Display IO and DSC Support Check */
mode_lib->vba.NonsupportedDSCInputBPC = false;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 31cf144860b9..f973d0ee82f9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -754,7 +754,6 @@ struct vba_vars_st {
bool DCCProgrammingAssumesScanDirectionUnknownFinal;
bool EnoughWritebackUnits;
bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES];
-   bool NumberOfDP2p0Support;
unsigned int MaxNumDP2p0Streams;
unsigned int MaxNumDP2p0Outputs;
enum dm_output_type 
OutputTypePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
-- 
2.37.1

[PATCH 11/16] drm/amd/display: Remove MPCCombineEnable VBA variable

2022-07-28 Thread Maíra Canal

The MPCCombineEnable variable from the struct vba_vars_st is only
used on assignments, so its value is not used on code. So, remove
the MPCCombineEnable entry from the struct vba_vars_st.

Signed-off-by: Maíra Canal 
---
 drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c  | 1 -
 drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c  | 1 -
 .../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c| 1 -
 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c  | 2 --
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h   | 1 -
 5 files changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index b776a7940fac..7dd51fe88d4f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -5259,7 +5259,6 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
}
v->ImmediateFlipSupport = 
v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine];
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
-   v->MPCCombineEnable[k] = 
v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
v->DPPPerPlane[k] = 
v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
}
v->DCFCLK = v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine];
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index b338e72d96d8..2e906f01950b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -5530,7 +5530,6 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
}
v->ImmediateFlipSupport = 
v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine];
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
-   v->MPCCombineEnable[k] = 
v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
v->DPPPerPlane[k] = 
v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
}
v->DCFCLK = v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine];
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
index 6c60731687bf..6a5b3c39ec60 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -5645,7 +5645,6 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_
}
v->ImmediateFlipSupport = 
v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine];
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
-   v->MPCCombineEnable[k] = 
v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
v->DPPPerPlane[k] = 
v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
}
v->DCFCLK = v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine];
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 5fce4bbb4e85..6d4907656f9f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -3685,8 +3685,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l

mode_lib->vba.CompressedBufferSizeInkByteAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
 // Not used, informational
 
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
-   mode_lib->vba.MPCCombineEnable[k] =
-   
mode_lib->vba.MPCCombine[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
mode_lib->vba.DPPPerPlane[k] = 
mode_lib->vba.NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
mode_lib->vba.SwathHeightY[k] =

mode_lib->vba.SwathHeightYAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index f4d4bf7b6111..31cf144860b9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -1147,7 +1147,6 @@ struct vba_vars_st {
double GPUVMMinPageSize;
double HostVMMinPageSize;
 
-   bool   MPCCombineEnable[DC__NUM_DPP__MAX];
unsigned int HostVMMaxNonCachedPageTableLevels;

[PATCH 10/16] drm/amd/display: Remove ModeIsSupported VBA variable

2022-07-28 Thread Maíra Canal

The ModeIsSupported variable from the struct vba_vars_st is only used on
assignments, so its value is not used on code. So, remove the
ModeIsSupported entry from the struct vba_vars_st.

Signed-off-by: Maíra Canal 
---
 drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c  | 1 -
 drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c  | 1 -
 .../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c| 1 -
 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c  | 2 --
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h   | 1 -
 5 files changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index 4fac83c776ad..b776a7940fac 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -5250,7 +5250,6 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
for (i = v->soc.num_states; i >= 0; i--) {
if (i == v->soc.num_states || v->ModeSupport[i][0] == 
true || v->ModeSupport[i][1] == true) {
v->VoltageLevel = i;
-   v->ModeIsSupported = v->ModeSupport[i][0] == 
true || v->ModeSupport[i][1] == true;
if (v->ModeSupport[i][1] == true) {
MaximumMPCCombine = 1;
} else {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index 9ea2d2fd56f1..b338e72d96d8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -5521,7 +5521,6 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
for (i = v->soc.num_states; i >= 0; i--) {
if (i == v->soc.num_states || v->ModeSupport[i][0] == 
true || v->ModeSupport[i][1] == true) {
v->VoltageLevel = i;
-   v->ModeIsSupported = v->ModeSupport[i][0] == 
true || v->ModeSupport[i][1] == true;
if (v->ModeSupport[i][0] == true) {
MaximumMPCCombine = 0;
} else {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
index ae749d39db2a..6c60731687bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -5636,7 +5636,6 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_
for (i = v->soc.num_states; i >= 0; i--) {
if (i == v->soc.num_states || v->ModeSupport[i][0] == 
true || v->ModeSupport[i][1] == true) {
v->VoltageLevel = i;
-   v->ModeIsSupported = v->ModeSupport[i][0] == 
true || v->ModeSupport[i][1] == true;
if (v->ModeSupport[i][0] == true) {
MaximumMPCCombine = 0;
} else {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index a88cfce3b771..5fce4bbb4e85 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -3668,8 +3668,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
if (i == v->soc.num_states || mode_lib->vba.ModeSupport[i][0] 
== true ||
mode_lib->vba.ModeSupport[i][1] == true) {
mode_lib->vba.VoltageLevel = i;
-   mode_lib->vba.ModeIsSupported = 
mode_lib->vba.ModeSupport[i][0] == true
-   || mode_lib->vba.ModeSupport[i][1] == 
true;
 
if (mode_lib->vba.ModeSupport[i][0] == true) {
MaximumMPCCombine = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index ac8131b52b78..f4d4bf7b6111 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -1132,7 +1132,6 @@ struct vba_vars_st {
double VRatioChroma[DC__NUM_DPP__MAX];
int WritebackSourceWidth[DC__NUM_DPP__MAX];
 
-   bool ModeIsSupported;
bool ODMCombine4To1Supported;
 
unsigned int SurfaceWidthY[DC__NUM_DPP__MAX];
-- 
2.37.1

[PATCH 06/16] drm/amd/display: Remove ImmediateFlipSupportedSurface VBA variable

2022-07-28 Thread Maíra Canal

The ImmediateFlipSupportedSurface variable from the struct
vba_vars_st is only used on assignments, so its value is not used
on code. So, remove the ImmediateFlipSupportedSurface entry from the struct
vba_vars_st.

Signed-off-by: Maíra Canal 
---
 .../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c  | 6 --
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h   | 2 --
 2 files changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index f199ef475ed0..e2e1d6e77902 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -355,12 +355,6 @@ static void 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
if (j != k && mode_lib->vba.BlendingAndTiming[k] == j 
&& mode_lib->vba.DSCEnabled[j])
v->DSCDelay[k] = v->DSCDelay[j];
 
-   //Immediate Flip
-   for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
-   v->ImmediateFlipSupportedSurface[k] = 
mode_lib->vba.ImmediateFlipSupport
-   && (mode_lib->vba.ImmediateFlipRequirement[k] 
!= dm_immediate_flip_not_required);
-   }
-
// Prefetch
dml32_CalculateSurfaceSizeInMall(
mode_lib->vba.NumberOfActiveSurfaces,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 841a05bea57e..76cba5d7ac10 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -659,8 +659,6 @@ struct vba_vars_st {
double DISPCLK_calculated;
double DPPCLK_calculated[DC__NUM_DPP__MAX];
 
-   bool ImmediateFlipSupportedSurface[DC__NUM_DPP__MAX];
-
bool Use_One_Row_For_Frame[DC__NUM_DPP__MAX];
bool Use_One_Row_For_Frame_Flip[DC__NUM_DPP__MAX];
unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
-- 
2.37.1

[PATCH 09/16] drm/amd/display: Remove SwathWidthCSingleDPP VBA variable

2022-07-28 Thread Maíra Canal

The SwathWidthCSingleDPP variable from the struct vba_vars_st is only
used on assignments, so its value is not used on code. So, remove the
SwathWidthCSingleDPP entry from the struct vba_vars_st.

Signed-off-by: Maíra Canal 
---
 drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c  | 2 --
 drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c  | 2 --
 .../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c| 2 --
 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c  | 2 --
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h   | 1 -
 5 files changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index caa3a9c598ce..4fac83c776ad 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -3660,10 +3660,8 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
if (v->SourceScan[k] != dm_vert) {
v->SwathWidthYSingleDPP[k] = v->ViewportWidth[k];
-   v->SwathWidthCSingleDPP[k] = v->ViewportWidthChroma[k];
} else {
v->SwathWidthYSingleDPP[k] = v->ViewportHeight[k];
-   v->SwathWidthCSingleDPP[k] = v->ViewportHeightChroma[k];
}
}
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index eca05bbc0fb5..9ea2d2fd56f1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -3965,10 +3965,8 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
for (k = 0; k < v->NumberOfActivePlanes; k++) {
if (v->SourceScan[k] != dm_vert) {
v->SwathWidthYSingleDPP[k] = v->ViewportWidth[k];
-   v->SwathWidthCSingleDPP[k] = v->ViewportWidthChroma[k];
} else {
v->SwathWidthYSingleDPP[k] = v->ViewportHeight[k];
-   v->SwathWidthCSingleDPP[k] = v->ViewportHeightChroma[k];
}
}
for (k = 0; k < v->NumberOfActivePlanes; k++) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
index acb47cdaaa05..ae749d39db2a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -4077,10 +4077,8 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_
for (k = 0; k < v->NumberOfActivePlanes; k++) {
if (v->SourceScan[k] != dm_vert) {
v->SwathWidthYSingleDPP[k] = v->ViewportWidth[k];
-   v->SwathWidthCSingleDPP[k] = v->ViewportWidthChroma[k];
} else {
v->SwathWidthYSingleDPP[k] = v->ViewportHeight[k];
-   v->SwathWidthCSingleDPP[k] = v->ViewportHeightChroma[k];
}
}
for (k = 0; k < v->NumberOfActivePlanes; k++) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 756a55f69799..a88cfce3b771 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -1721,10 +1721,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
if (!IsVertical(mode_lib->vba.SourceRotation[k])) {
v->SwathWidthYSingleDPP[k] = 
mode_lib->vba.ViewportWidth[k];
-   v->SwathWidthCSingleDPP[k] = 
mode_lib->vba.ViewportWidthChroma[k];
} else {
v->SwathWidthYSingleDPP[k] = 
mode_lib->vba.ViewportHeight[k];
-   v->SwathWidthCSingleDPP[k] = 
mode_lib->vba.ViewportHeightChroma[k];
}
}
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 91562c0d35f2..ac8131b52b78 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -939,7 +939,6 @@ struct vba_vars_st {
 
 
bool   MPCCombine[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
-   double

[PATCH 08/16] drm/amd/display: Remove some XFC variables from VBA

2022-07-28 Thread Maíra Canal

The variables XFCSupported, XFCTSlvVupdateOffset, XFCSlaveVupdateWidth,
XFCSlaveVReadyOffset, XFCTransferDelay, XFCPrechargeDelay,
XFCRemoteSurfaceFlipLatency and XFCPrefetchMargin are are only
used on assignments, so their values are not used on code. So, remove
the variables entries from the struct vba_vars_st.

Signed-off-by: Maíra Canal 
---
 .../dc/dml/dcn20/display_mode_vba_20.c| 38 ---
 .../dc/dml/dcn20/display_mode_vba_20v2.c  | 38 ---
 .../dc/dml/dcn21/display_mode_vba_21.c| 38 ---
 .../drm/amd/display/dc/dml/display_mode_vba.c |  1 -
 .../drm/amd/display/dc/dml/display_mode_vba.h |  8 
 5 files changed, 123 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index 1424aa7a5018..7effe4be61b2 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -2580,9 +2580,6 @@ static void 
dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
if (mode_lib->vba.XFCEnabled[k] == true) {
double TWait;
 
-   mode_lib->vba.XFCSlaveVUpdateOffset[k] = 
mode_lib->vba.XFCTSlvVupdateOffset;
-   mode_lib->vba.XFCSlaveVupdateWidth[k] = 
mode_lib->vba.XFCTSlvVupdateWidth;
-   mode_lib->vba.XFCSlaveVReadyOffset[k] = 
mode_lib->vba.XFCTSlvVreadyOffset;
TWait = CalculateTWait(

mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
mode_lib->vba.DRAMClockChangeLatency,
@@ -2606,26 +2603,6 @@ static void 
dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
_lib->vba.SrcActiveDrainRate,
_lib->vba.TInitXFill,
_lib->vba.TslvChk);
-   mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] =
-   dml_floor(
-   
mode_lib->vba.XFCRemoteSurfaceFlipDelay
-   / 
(mode_lib->vba.HTotal[k]
-   
/ mode_lib->vba.PixelClock[k]),
-   1);
-   mode_lib->vba.XFCTransferDelay[k] =
-   dml_ceil(
-   
mode_lib->vba.XFCBusTransportTime
-   / 
(mode_lib->vba.HTotal[k]
-   
/ mode_lib->vba.PixelClock[k]),
-   1);
-   mode_lib->vba.XFCPrechargeDelay[k] =
-   dml_ceil(
-   
(mode_lib->vba.XFCBusTransportTime
-   + 
mode_lib->vba.TInitXFill
-   + 
mode_lib->vba.TslvChk)
-   / 
(mode_lib->vba.HTotal[k]
-   
/ mode_lib->vba.PixelClock[k]),
-   1);
mode_lib->vba.InitFillLevel = 
mode_lib->vba.XFCXBUFLatencyTolerance
* mode_lib->vba.SrcActiveDrainRate;
mode_lib->vba.FinalFillMargin =
@@ -2644,21 +2621,6 @@ static void 
dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
mode_lib->vba.TFinalxFill = 
mode_lib->vba.RemainingFillLevel
/ (mode_lib->vba.SrcActiveDrainRate
* 
mode_lib->vba.XFCFillBWOverhead / 100);
-   mode_lib->vba.XFCPrefetchMargin[k] =
-   mode_lib->vba.XFCRemoteSurfaceFlipDelay
-   + 
mode_lib->vba.TFinalxFill
-   + 
(mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
-   + 
mode_lib->vba.DestinationLinesToRequestRowInVBlank[k])
-   * 
mode_lib->vba.HTotal[k]
-   /

[PATCH 05/16] drm/amd/display: Remove VStartupMargin and FirstMainPlane VBA variables

2022-07-28 Thread Maíra Canal

The variables VStartupMargin and FirstMainPlane from the struct
vba_vars_st are only used on assignments, so there values are not used
on code. So, remove the variables entries from the struct vba_vars_st.

Signed-off-by: Maíra Canal 
---
 .../display/dc/dml/dcn20/display_mode_vba_20.c  | 14 +++---
 .../dc/dml/dcn20/display_mode_vba_20v2.c| 14 +++---
 .../display/dc/dml/dcn30/display_mode_vba_30.c  | 17 ++---
 .../drm/amd/display/dc/dml/display_mode_vba.h   |  2 --
 4 files changed, 12 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index d86d5c346e42..1424aa7a5018 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -2662,19 +2662,12 @@ static void 
dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
}
}
{
-   unsigned int VStartupMargin = 0;
bool FirstMainPlane = true;
 
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-   if (mode_lib->vba.BlendingAndTiming[k] == k) {
-   unsigned int Margin = 
(mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k])
-   * mode_lib->vba.HTotal[k] / 
mode_lib->vba.PixelClock[k];
-
-   if (FirstMainPlane) {
-   VStartupMargin = Margin;
-   FirstMainPlane = false;
-   } else
-   VStartupMargin = 
dml_min(VStartupMargin, Margin);
+   if (mode_lib->vba.BlendingAndTiming[k] == k && 
FirstMainPlane) {
+   FirstMainPlane = false;
+   }
}
 
if (mode_lib->vba.UseMaximumVStartup) {
@@ -2685,7 +2678,6 @@ static void 
dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
}
}
 }
-}
 
 static void dml20_DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index effd02574a0e..03613dbb3e61 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -2735,19 +2735,12 @@ static void 
dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
}
}
{
-   unsigned int VStartupMargin = 0;
bool FirstMainPlane = true;
 
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-   if (mode_lib->vba.BlendingAndTiming[k] == k) {
-   unsigned int Margin = 
(mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k])
-   * mode_lib->vba.HTotal[k] / 
mode_lib->vba.PixelClock[k];
-
-   if (FirstMainPlane) {
-   VStartupMargin = Margin;
-   FirstMainPlane = false;
-   } else
-   VStartupMargin = 
dml_min(VStartupMargin, Margin);
+   if (mode_lib->vba.BlendingAndTiming[k] == k && 
FirstMainPlane) {
+   FirstMainPlane = false;
+   }
}
 
if (mode_lib->vba.UseMaximumVStartup) {
@@ -2758,7 +2751,6 @@ static void 
dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
}
}
 }
-}
 
 static void dml20v2_DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index fe7fcb0d7b1f..caa3a9c598ce 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -3028,17 +3028,12 @@ static void 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
}
 
// VStartup Margin
-   v->VStartupMargin = 0;
-   v->FirstMainPlane = true;
-   for (k = 0; k < v->NumberOfActivePlanes; ++k) {
-   if (v->BlendingAndTiming[k] == k) {
-   double margin = (v->MaxVStartupLines[k] - 
v->VStartup[k]) * v->HTotal[k]
-   / v->PixelClock[k];
-   if (v->FirstMainPlane == true) {
-   v->VStartupMargin = margin;
-   v->FirstMainPlane = false;
-   }

[PATCH 04/16] drm/amd/display: Remove AllowDRAMSelfRefreshDuringVBlank VBA variable

2022-07-28 Thread Maíra Canal

The AllowDRAMSelfRefreshDuringVBlank variable from the struct vba_vars_st
is only used on assignments, so its value is not used on code. So, remove
it the AllowDRAMSelfRefreshDuringVBlank entry from the struct vba_vars_st.

Signed-off-by: Maíra Canal 
---
 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 3 ---
 .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c   | 3 ---
 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 3 ---
 drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 3 ---
 drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 3 ---
 .../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c   | 3 ---
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h  | 1 -
 7 files changed, 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index 37a8b418a24d..d86d5c346e42 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -2350,7 +2350,6 @@ static void 
dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
if 
(mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb]
 == 0) {
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = 
true;
-   mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = 
true;
mode_lib->vba.MinTTUVBlank[k] = dml_max(
mode_lib->vba.DRAMClockChangeWatermark,
dml_max(
@@ -2358,13 +2357,11 @@ static void 
dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer

mode_lib->vba.UrgentWatermark));
} else if 
(mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb]
 == 1) {
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = 
false;
-   mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = 
true;
mode_lib->vba.MinTTUVBlank[k] = dml_max(

mode_lib->vba.StutterEnterPlusExitWatermark,
mode_lib->vba.UrgentWatermark);
} else {
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = 
false;
-   mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = 
false;
mode_lib->vba.MinTTUVBlank[k] = 
mode_lib->vba.UrgentWatermark;
}
if (!mode_lib->vba.DynamicMetadataEnable[k])
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index 0e0697326717..effd02574a0e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -2384,7 +2384,6 @@ static void 
dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
if 
(mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb]
 == 0) {
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = 
true;
-   mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = 
true;
mode_lib->vba.MinTTUVBlank[k] = dml_max(
mode_lib->vba.DRAMClockChangeWatermark,
dml_max(
@@ -2392,13 +2391,11 @@ static void 
dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP

mode_lib->vba.UrgentWatermark));
} else if 
(mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb]
 == 1) {
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = 
false;
-   mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = 
true;
mode_lib->vba.MinTTUVBlank[k] = dml_max(

mode_lib->vba.StutterEnterPlusExitWatermark,
mode_lib->vba.UrgentWatermark);
} else {
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = 
false;
-   mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = 
false;
mode_lib->vba.MinTTUVBlank[k] = 
mode_lib->vba.UrgentWatermark;
}
if (!mode_lib->vba.DynamicMetadataEnable[k])
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

[PATCH 03/16] drm/amd/display: Remove DSCCLK_calculated VBA variable

2022-07-28 Thread Maíra Canal

The DSCCLK_calculated variable from the struct vba_vars_st is
only used on assignments, so its value is not used on code. Moreover,
its getter function is not used also. So, remove the DSCCLK_calculated
entry from the struct vba_vars_st.

Signed-off-by: Maíra Canal 
---
 .../dc/dml/dcn20/display_mode_vba_20.c| 21 ++
 .../dc/dml/dcn20/display_mode_vba_20v2.c  | 21 ++
 .../dc/dml/dcn21/display_mode_vba_21.c| 18 +--
 .../dc/dml/dcn30/display_mode_vba_30.c| 19 ++--
 .../dc/dml/dcn31/display_mode_vba_31.c| 19 ++--
 .../dc/dml/dcn314/display_mode_vba_314.c  | 19 ++--
 .../dc/dml/dcn32/display_mode_vba_32.c| 22 ++-
 .../drm/amd/display/dc/dml/display_mode_vba.c |  1 -
 .../drm/amd/display/dc/dml/display_mode_vba.h |  2 --
 9 files changed, 13 insertions(+), 129 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index 8a499f8066b7..37a8b418a24d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -1770,28 +1770,11 @@ static void 
dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
 
// DSCCLK
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-   if ((mode_lib->vba.BlendingAndTiming[k] != k) || 
!mode_lib->vba.DSCEnabled[k]) {
-   mode_lib->vba.DSCCLK_calculated[k] = 0.0;
-   } else {
-   if (mode_lib->vba.OutputFormat[k] == dm_420
-   || mode_lib->vba.OutputFormat[k] == 
dm_n422)
+   if ((mode_lib->vba.BlendingAndTiming[k] == k) || 
mode_lib->vba.DSCEnabled[k]) {
+   if (mode_lib->vba.OutputFormat[k] == dm_420 || 
mode_lib->vba.OutputFormat[k] == dm_n422)
mode_lib->vba.DSCFormatFactor = 2;
else
mode_lib->vba.DSCFormatFactor = 1;
-   if (mode_lib->vba.ODMCombineEnabled[k])
-   mode_lib->vba.DSCCLK_calculated[k] =
-   
mode_lib->vba.PixelClockBackEnd[k] / 6
-   / 
mode_lib->vba.DSCFormatFactor
-   / (1
-   
- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-   
/ 100);
-   else
-   mode_lib->vba.DSCCLK_calculated[k] =
-   
mode_lib->vba.PixelClockBackEnd[k] / 3
-   / 
mode_lib->vba.DSCFormatFactor
-   / (1
-   
- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-   
/ 100);
}
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index ef7f0b8ed2d5..0e0697326717 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -1806,28 +1806,11 @@ static void 
dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
 
// DSCCLK
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-   if ((mode_lib->vba.BlendingAndTiming[k] != k) || 
!mode_lib->vba.DSCEnabled[k]) {
-   mode_lib->vba.DSCCLK_calculated[k] = 0.0;
-   } else {
-   if (mode_lib->vba.OutputFormat[k] == dm_420
-   || mode_lib->vba.OutputFormat[k] == 
dm_n422)
+   if ((mode_lib->vba.BlendingAndTiming[k] == k) || 
mode_lib->vba.DSCEnabled[k]) {
+   if (mode_lib->vba.OutputFormat[k] == dm_420 || 
mode_lib->vba.OutputFormat[k] == dm_n422)
mode_lib->vba.DSCFormatFactor = 2;
else
mode_lib->vba.DSCFormatFactor = 1;
-   if (mode_lib->vba.ODMCombineEnabled[k])
-   mode_lib->vba.DSCCLK_calculated[k] =
-   
mode_lib->vba.PixelClockBackEnd[k] / 6
-   / 
mode_lib->vba.DSCFormatFactor
-

[PATCH 02/16] drm/amd/display: Remove CompBufReservedSpace* VBA variable

2022-07-28 Thread Maíra Canal

The variables CompBufReservedSpaceZs, CompBufReservedSpace64B and
CompBufReservedSpaceNeedAdjustment from the struct vba_vars_st are
only used on assignments, so their values are not used on code. Moreover,
their getter functions are not used also. So, remove the variables
entries from the struct vba_vars_st.

Signed-off-by: Maíra Canal 
---
 .../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c   | 3 ---
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c| 2 --
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h| 5 -
 3 files changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 573504de1789..a1fb2d1d1cdb 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -307,9 +307,6 @@ static void 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 .dummy_boolean); /* bool 
*ViewportSizeSupport */
}
 
-   v->CompBufReservedSpaceZs = v->CompBufReservedSpaceKBytes * 1024.0 
/ 256.0;
-   v->CompBufReservedSpace64B= v->CompBufReservedSpaceKBytes * 1024.0 
/ 64.0;
-
// DCFCLK Deep Sleep
dml32_CalculateDCFCLKDeepSleep(
mode_lib->vba.NumberOfActiveSurfaces,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 5dc2f52165fb..d1c720b48b0c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -122,8 +122,6 @@ dml_get_attr_func(fclk_watermark, 
mode_lib->vba.Watermark.FCLKChangeWatermark);
 dml_get_attr_func(usr_retraining_watermark, 
mode_lib->vba.Watermark.USRRetrainingWatermark);
 
 dml_get_attr_func(comp_buffer_reserved_space_kbytes, 
mode_lib->vba.CompBufReservedSpaceKBytes);
-dml_get_attr_func(comp_buffer_reserved_space_64bytes, 
mode_lib->vba.CompBufReservedSpace64B);
-dml_get_attr_func(comp_buffer_reserved_space_zs, 
mode_lib->vba.CompBufReservedSpaceZs);
 dml_get_attr_func(unbounded_request_enabled, 
mode_lib->vba.UnboundedRequestEnabled);
 
 #define dml_get_pipe_attr_func(attr, var)  double get_##attr(struct 
display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned 
int num_pipes, unsigned int which_pipe) \
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index cb125f7d0814..632041cf49bb 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -67,8 +67,6 @@ dml_get_attr_decl(min_meta_chunk_size_in_byte);
 dml_get_attr_decl(fclk_watermark);
 dml_get_attr_decl(usr_retraining_watermark);
 dml_get_attr_decl(comp_buffer_reserved_space_kbytes);
-dml_get_attr_decl(comp_buffer_reserved_space_64bytes);
-dml_get_attr_decl(comp_buffer_reserved_space_zs);
 dml_get_attr_decl(unbounded_request_enabled);
 
 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib 
*mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, 
unsigned int which_pipe)
@@ -655,9 +653,6 @@ struct vba_vars_st {
Watermarks  Watermark;
bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
unsigned int CompBufReservedSpaceKBytes;
-   unsigned int CompBufReservedSpace64B;
-   unsigned int CompBufReservedSpaceZs;
-   bool CompBufReservedSpaceNeedAdjustment;
 
// These are the clocks calcuated by the library but they are not 
actually
// used explicitly. They are fetched by tests and then possibly used. 
The
-- 
2.37.1

[PATCH 01/16] drm/amd/display: Remove NonUrgentLatencyTolerance VBA variable

2022-07-28 Thread Maíra Canal

The NonUrgentLatencyTolerance variable from the struct vba_vars_st is
only used on assignments, so its value is not used on code. Moreover,
its getter function is not used also. So, remove the
NonUrgentLatencyTolerance entry from the struct vba_vars_st.

Signed-off-by: Maíra Canal 
---
 .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c| 4 
 .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c  | 4 
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 1 -
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 2 --
 4 files changed, 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index d3b5b6fedf04..8a499f8066b7 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -1768,10 +1768,6 @@ static void 
dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
mode_lib->vba.UrgentLatencySupportUs[k]);
}
 
-   // Non-Urgent Latency Tolerance
-   mode_lib->vba.NonUrgentLatencyTolerance = 
mode_lib->vba.MinUrgentLatencySupportUs
-   - mode_lib->vba.UrgentWatermark;
-
// DSCCLK
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
if ((mode_lib->vba.BlendingAndTiming[k] != k) || 
!mode_lib->vba.DSCEnabled[k]) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index 63bbdf8b8678..ef7f0b8ed2d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -1804,10 +1804,6 @@ static void 
dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
mode_lib->vba.UrgentLatencySupportUs[k]);
}
 
-   // Non-Urgent Latency Tolerance
-   mode_lib->vba.NonUrgentLatencyTolerance = 
mode_lib->vba.MinUrgentLatencySupportUs
-   - mode_lib->vba.UrgentWatermark;
-
// DSCCLK
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
if ((mode_lib->vba.BlendingAndTiming[k] != k) || 
!mode_lib->vba.DSCEnabled[k]) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 503e7d984ff0..5dc2f52165fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -102,7 +102,6 @@ dml_get_attr_func(stutter_efficiency_no_vblank, 
mode_lib->vba.StutterEfficiencyN
 dml_get_attr_func(stutter_period, mode_lib->vba.StutterPeriod);
 dml_get_attr_func(urgent_latency, mode_lib->vba.UrgentLatency);
 dml_get_attr_func(urgent_extra_latency, mode_lib->vba.UrgentExtraLatency);
-dml_get_attr_func(nonurgent_latency, mode_lib->vba.NonUrgentLatencyTolerance);
 dml_get_attr_func(dram_clock_change_latency, 
mode_lib->vba.MinActiveDRAMClockChangeLatencySupported);
 dml_get_attr_func(dispclk_calculated, mode_lib->vba.DISPCLK_calculated);
 dml_get_attr_func(total_data_read_bw, mode_lib->vba.TotalDataReadBandwidth);
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 8460aefe7b6d..cb125f7d0814 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -50,7 +50,6 @@ dml_get_attr_decl(stutter_efficiency);
 dml_get_attr_decl(stutter_period);
 dml_get_attr_decl(urgent_latency);
 dml_get_attr_decl(urgent_extra_latency);
-dml_get_attr_decl(nonurgent_latency);
 dml_get_attr_decl(dram_clock_change_latency);
 dml_get_attr_decl(dispclk_calculated);
 dml_get_attr_decl(total_data_read_bw);
@@ -648,7 +647,6 @@ struct vba_vars_st {
double WritebackDRAMClockChangeWatermark;
double StutterEfficiency;
double StutterEfficiencyNotIncludingVBlank;
-   double NonUrgentLatencyTolerance;
double MinActiveDRAMClockChangeLatencySupported;
double Z8StutterEfficiencyBestCase;
unsigned int Z8NumberOfStutterBurstsPerFrameBestCase;
-- 
2.37.1

[PATCH 00/16] Remove entries from struct vba_vars_st

2022-07-28 Thread Maíra Canal

A while ago, I sent a patch removing some entries from the struct vba_vars_st
[1]. At that time, I used git grep and checked if they were used anywhere else
manually. But the struct vba_vars_st has more than 900 variables, so git grep
every variable is a pretty huge work. So, I grabbed all the variables' names
and put them in a text file, and wrote a bash script to analyze if the
variables were used.

I ended up finding a bunch of variables that were only assigned but never used.
I manually checked the results of the script in order to make sure that no
functional changes were made to the code.

I only removed variables that were only assigned but never used or variables
that were never even mentioned.

Best Regards,
- Maíra Canal

[1] 
https://lore.kernel.org/amd-gfx/20220630215316.1078841-1-mairaca...@riseup.net/T/#u

Maíra Canal (16):
  drm/amd/display: Remove NonUrgentLatencyTolerance VBA variable
  drm/amd/display: Remove CompBufReservedSpace* VBA variable
  drm/amd/display: Remove DSCCLK_calculated VBA variable
  drm/amd/display: Remove AllowDRAMSelfRefreshDuringVBlank VBA variable
  drm/amd/display: Remove VStartupMargin and FirstMainPlane VBA
variables
  drm/amd/display: Remove ImmediateFlipSupportedSurface VBA variable
  drm/amd/display: Remove WritebackAllowFCLKChangeEndPosition VBA
variable
  drm/amd/display: Remove some XFC variables from VBA
  drm/amd/display: Remove SwathWidthCSingleDPP VBA variable
  drm/amd/display: Remove ModeIsSupported VBA variable
  drm/amd/display: Remove MPCCombineEnable VBA variable
  drm/amd/display: Remove NumberOfDP2p0Support VBA variable
  drm/amd/display: Remove TFinalxFill VBA variable
  drm/amd/display: Remove MaximumDCCCompressionYSurface VBA variable
  drm/amd/display: Remove only mencioned once VBA variables
  drm/amd/display: Remove never used VBA variables

 .../dc/dml/dcn20/display_mode_vba_20.c| 83 ++-
 .../dc/dml/dcn20/display_mode_vba_20v2.c  | 83 ++-
 .../dc/dml/dcn21/display_mode_vba_21.c| 75 +
 .../dc/dml/dcn30/display_mode_vba_30.c| 43 ++
 .../dc/dml/dcn31/display_mode_vba_31.c| 26 +-
 .../dc/dml/dcn314/display_mode_vba_314.c  | 26 +-
 .../dc/dml/dcn32/display_mode_vba_32.c| 44 +-
 .../drm/amd/display/dc/dml/display_mode_vba.c | 18 +---
 .../drm/amd/display/dc/dml/display_mode_vba.h | 45 --
 9 files changed, 30 insertions(+), 413 deletions(-)

-- 
2.37.1

RE: [PATCH] drm/amdgpu: fix hive reference leak when reflecting psp topology info

2022-07-28 Thread Kim, Jonathan

[Public]

> -Original Message-
> From: Liu, Shaoyun 
> Sent: July 28, 2022 1:10 PM
> To: Kim, Jonathan ; amd-
> g...@lists.freedesktop.org
> Cc: Kim, Jonathan 
> Subject: RE: [PATCH] drm/amdgpu: fix hive reference leak when reflecting
> psp topology info
>
> [AMD Official Use Only - General]
>
> Looks good to me .
> BTW , why we didn't catch it on baremetal mode  ?

Thanks for the review Shaoyun.
Good question.  I'll double check what we're doing for unload testing.

Thanks,

Jon

>
> Reviewed-by: Shaoyun.liu 
>
> -Original Message-
> From: amd-gfx  On Behalf Of
> Jonathan Kim
> Sent: Thursday, July 28, 2022 1:06 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Kim, Jonathan 
> Subject: [PATCH] drm/amdgpu: fix hive reference leak when reflecting psp
> topology info
>
> Hives that require psp topology info to be reflected will leak hive reference
> so fix it.
>
> Signed-off-by: Jonathan Kim 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 3ee363bfbac2..6c23e89366bf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -1292,6 +1292,8 @@ static void psp_xgmi_reflect_topology_info(struct
> psp_context *psp,
>
> break;
> }
> +
> +   amdgpu_put_xgmi_hive(hive);
>  }
>
>  int psp_xgmi_get_topology_info(struct psp_context *psp,
> --
> 2.25.1
>

RE: [PATCH] drm/amdgpu: fix hive reference leak when reflecting psp topology info

2022-07-28 Thread Liu, Shaoyun

[AMD Official Use Only - General]

Looks good to me .
BTW , why we didn't catch it on baremetal mode  ?

Reviewed-by: Shaoyun.liu 

-Original Message-
From: amd-gfx  On Behalf Of Jonathan Kim
Sent: Thursday, July 28, 2022 1:06 PM
To: amd-gfx@lists.freedesktop.org
Cc: Kim, Jonathan 
Subject: [PATCH] drm/amdgpu: fix hive reference leak when reflecting psp 
topology info

Hives that require psp topology info to be reflected will leak hive reference 
so fix it.

Signed-off-by: Jonathan Kim 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 3ee363bfbac2..6c23e89366bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1292,6 +1292,8 @@ static void psp_xgmi_reflect_topology_info(struct 
psp_context *psp,

break;
}
+
+   amdgpu_put_xgmi_hive(hive);
 }

 int psp_xgmi_get_topology_info(struct psp_context *psp,
--
2.25.1

[PATCH] drm/amdgpu: fix hive reference leak when reflecting psp topology info

2022-07-28 Thread Jonathan Kim

Hives that require psp topology info to be reflected will leak hive
reference so fix it.

Signed-off-by: Jonathan Kim 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 3ee363bfbac2..6c23e89366bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1292,6 +1292,8 @@ static void psp_xgmi_reflect_topology_info(struct 
psp_context *psp,
 
break;
}
+
+   amdgpu_put_xgmi_hive(hive);
 }
 
 int psp_xgmi_get_topology_info(struct psp_context *psp,
-- 
2.25.1

Re: [PATCH v3 6/6] drm/ttm: Switch to using the new res callback

2022-07-28 Thread Matthew Auld


On 28/07/2022 15:33, Arunpravin Paneer Selvam wrote:

Apply new intersect and compatible callback instead
of having a generic placement range verfications.

v2: Added a separate callback for compatiblilty
 checks (Christian)

Signed-off-by: Christian König 
Signed-off-by: Arunpravin Paneer Selvam 


There is also some code at the bottom of i915_ttm_buddy_man_alloc() 
playing games with res->start, which I think can be safely deleted with 
this series (now that we have proper ->compatible() hook).


Also, is the plan to remove res->start completely, or does that still 
have a use?



---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 45 +++--
  drivers/gpu/drm/ttm/ttm_bo.c|  9 +++--
  drivers/gpu/drm/ttm/ttm_resource.c  |  5 +--
  3 files changed, 20 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 170935c294f5..7d25a10395c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1328,11 +1328,12 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device 
*adev, struct ttm_tt *ttm,
  static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
const struct ttm_place *place)
  {
-   unsigned long num_pages = bo->resource->num_pages;
struct dma_resv_iter resv_cursor;
-   struct amdgpu_res_cursor cursor;
struct dma_fence *f;
  
+	if (!amdgpu_bo_is_amdgpu_bo(bo))

+   return ttm_bo_eviction_valuable(bo, place);
+
/* Swapout? */
if (bo->resource->mem_type == TTM_PL_SYSTEM)
return true;
@@ -1351,40 +1352,20 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct 
ttm_buffer_object *bo,
return false;
}
  
-	switch (bo->resource->mem_type) {

-   case AMDGPU_PL_PREEMPT:
-   /* Preemptible BOs don't own system resources managed by the
-* driver (pages, VRAM, GART space). They point to resources
-* owned by someone else (e.g. pageable memory in user mode
-* or a DMABuf). They are used in a preemptible context so we
-* can guarantee no deadlocks and good QoS in case of MMU
-* notifiers or DMABuf move notifiers from the resource owner.
-*/
+   /* Preemptible BOs don't own system resources managed by the
+* driver (pages, VRAM, GART space). They point to resources
+* owned by someone else (e.g. pageable memory in user mode
+* or a DMABuf). They are used in a preemptible context so we
+* can guarantee no deadlocks and good QoS in case of MMU
+* notifiers or DMABuf move notifiers from the resource owner.
+*/
+   if (bo->resource->mem_type == AMDGPU_PL_PREEMPT)
return false;
-   case TTM_PL_TT:
-   if (amdgpu_bo_is_amdgpu_bo(bo) &&
-   amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
-   return false;
-   return true;
  
-	case TTM_PL_VRAM:

-   /* Check each drm MM node individually */
-   amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT,
-);
-   while (cursor.remaining) {
-   if (place->fpfn < PFN_DOWN(cursor.start + cursor.size)
-   && !(place->lpfn &&
-place->lpfn <= PFN_DOWN(cursor.start)))
-   return true;
-
-   amdgpu_res_next(, cursor.size);
-   }
+   if (bo->resource->mem_type == TTM_PL_TT &&
+   amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
return false;
  
-	default:

-   break;
-   }
-
return ttm_bo_eviction_valuable(bo, place);
  }
  
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c

index c1bd006a5525..03409409e43e 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -518,6 +518,9 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo,
  bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
  const struct ttm_place *place)
  {
+   struct ttm_resource *res = bo->resource;
+   struct ttm_device *bdev = bo->bdev;
+
dma_resv_assert_held(bo->base.resv);
if (bo->resource->mem_type == TTM_PL_SYSTEM)
return true;
@@ -525,11 +528,7 @@ bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
/* Don't evict this BO if it's outside of the
 * requested placement range
 */
-   if (place->fpfn >= (bo->resource->start + bo->resource->num_pages) ||
-   (place->lpfn && place->lpfn <= bo->resource->start))
-   return false;
-
-   return true;
+   return ttm_resource_intersect(bdev, res, place, bo->base.size);
  }

Re: [PATCH v3 4/6] drm/i915: Implement intersect/compatible functions

2022-07-28 Thread Matthew Auld


On 28/07/2022 15:33, Arunpravin Paneer Selvam wrote:

Implemented a new intersect and compatible callback function
fetching start offset from drm buddy allocator.

v2: move the bits that are specific to buddy_man (Matthew)

Signed-off-by: Christian König 
Signed-off-by: Arunpravin Paneer Selvam 
---
  drivers/gpu/drm/i915/gem/i915_gem_ttm.c   | 39 +---
  drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 62 +++
  2 files changed, 64 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 70e2ed4e99df..54eead15d74b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -396,43 +396,8 @@ static bool i915_ttm_eviction_valuable(struct 
ttm_buffer_object *bo,
if (!i915_gem_object_evictable(obj))
return false;
  
-	switch (res->mem_type) {

-   case I915_PL_LMEM0: {
-   struct ttm_resource_manager *man =
-   ttm_manager_type(bo->bdev, res->mem_type);
-   struct i915_ttm_buddy_resource *bman_res =
-   to_ttm_buddy_resource(res);
-   struct drm_buddy *mm = bman_res->mm;
-   struct drm_buddy_block *block;
-
-   if (!place->fpfn && !place->lpfn)
-   return true;
-
-   GEM_BUG_ON(!place->lpfn);
-
-   /*
-* If we just want something mappable then we can quickly check
-* if the current victim resource is using any of the CPU
-* visible portion.
-*/
-   if (!place->fpfn &&
-   place->lpfn == i915_ttm_buddy_man_visible_size(man))
-   return bman_res->used_visible_size > 0;
-
-   /* Real range allocation */
-   list_for_each_entry(block, _res->blocks, link) {
-   unsigned long fpfn =
-   drm_buddy_block_offset(block) >> PAGE_SHIFT;
-   unsigned long lpfn = fpfn +
-   (drm_buddy_block_size(mm, block) >> PAGE_SHIFT);
-
-   if (place->fpfn < lpfn && place->lpfn > fpfn)
-   return true;
-   }
-   return false;
-   } default:
-   break;
-   }
+   if (res->mem_type == I915_PL_LMEM0)
+   return ttm_bo_eviction_valuable(bo, place);


We should be able to drop the mem_type == I915_PL_LMEM0 check here I 
think, and just unconditionally do:


return ttm_bo_eviction_valuable(bo, place);

  
  	return true;

  }
diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c 
b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
index a5109548abc0..9d2a31154d58 100644
--- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
+++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
@@ -178,6 +178,66 @@ static void i915_ttm_buddy_man_free(struct 
ttm_resource_manager *man,
kfree(bman_res);
  }
  
+static bool i915_ttm_buddy_man_intersect(struct ttm_resource_manager *man,


Nit: intersects


+struct ttm_resource *res,
+const struct ttm_place *place,
+size_t size)
+{
+   struct i915_ttm_buddy_resource *bman_res = to_ttm_buddy_resource(res);
+   u32 start, num_pages = PFN_UP(size);
+   struct drm_buddy_block *block;
+
+   if (!place->fpfn && !place->lpfn)
+   return true;
+
+   /*
+* If we just want something mappable then we can quickly check
+* if the current victim resource is using any of the CP
+* visible portion.
+*/
+   if (!place->fpfn &&
+   place->lpfn == i915_ttm_buddy_man_visible_size(man))
+   return bman_res->used_visible_size > 0;
+
+   /* Check each drm buddy block individually */
+   list_for_each_entry(block, _res->blocks, link) {
+   start = drm_buddy_block_offset(block) >> PAGE_SHIFT;
+   /* Don't evict BOs outside of the requested placement range */
+   if (place->fpfn >= (start + num_pages) ||
+   (place->lpfn && place->lpfn <= start))
+   return false;
+   }
+
+   return true;


We need to account for the block size somewhere. Also same bug in the 
amdgpu patch it seems. We also need to do this the other way around and 
keep checking until we find something that overlaps, for example if the 
first block doesn't intersect/overlap we will incorrectly return false 
here, even if one of the other blocks does intersect.


list_for_each_entry() {
fpfn = drm_buddy_block_size(mm, block) >> PAGE_SHIFT;
lpfn = fpfn + drm_buddy_block_size(mm, block) >> PAGE_SHIFT);

if (place->fpfn < lpfn && place->lpfn > fpfn)
return true;
}

return false;


+}
+
+static bool

Re: [PATCH v2 4/6] drm/i915: Implement intersect/compatible functions

2022-07-28 Thread Arunpravin Paneer Selvam


Hi Matthew,

On 7/26/2022 4:11 PM, Matthew Auld wrote:

On 25/07/2022 12:42, Arunpravin Paneer Selvam wrote:

Implemented a new intersect and compatible callback function
fetching start offset from drm buddy allocator.

Signed-off-by: Christian König 
Signed-off-by: Arunpravin Paneer Selvam 


---
  drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 43 +++
  1 file changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c 
b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c

index a5109548abc0..b5801c05bd41 100644
--- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
+++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
@@ -178,6 +178,47 @@ static void i915_ttm_buddy_man_free(struct 
ttm_resource_manager *man,

  kfree(bman_res);
  }
  +static bool i915_ttm_buddy_man_intersect(struct 
ttm_resource_manager *man,

+ struct ttm_resource *res,
+ const struct ttm_place *place,
+ size_t size)
+{
+    struct i915_ttm_buddy_resource *bman_res = 
to_ttm_buddy_resource(res);

+    u32 start, num_pages = PFN_UP(size);
+    struct drm_buddy_block *block;
+
+    /* Check each drm buddy block individually */
+    list_for_each_entry(block, _res->blocks, link) {
+    start = drm_buddy_block_offset(block) >> PAGE_SHIFT;
+    /* Don't evict BOs outside of the requested placement range */
+    if (place->fpfn >= (start + num_pages) ||
+    (place->lpfn && place->lpfn <= start))
+    return false;
+    }
+
+    return true;
+}


This looks like a nice idea. We should be able to clean up 
i915_ttm_eviction_valuable() a fair bit I think, if we now call 
ttm_bo_eviction_valuable() at the end (like in amdgpu), and move the 
bits that are specific to buddy_man here?


So something like:

if (!place->fpfn && !place->lpfn)
    return true;

if (!place->fpfn &&
    place->lpfn == i915_buddy_man_visible_size(man))
    return bman_res->used_visible_size > 0;

/* Check each drm buddy block individually */

modified in v3

+
+static bool i915_ttm_buddy_man_compatible(struct 
ttm_resource_manager *man,

+  struct ttm_resource *res,
+  const struct ttm_place *place,
+  size_t size)


Is it not possible to derive the size from res->num_pages?
I think it is possible, I will check with Christian for any specific 
case that might

require ttm_buffer_object->base.size



+{
+    struct i915_ttm_buddy_resource *bman_res = 
to_ttm_buddy_resource(res);

+    u32 start, num_pages = PFN_UP(size);
+    struct drm_buddy_block *block;
+
+    /* Check each drm buddy block individually */
+    list_for_each_entry(block, _res->blocks, link) {
+    start = drm_buddy_block_offset(block) >> PAGE_SHIFT;
+    if (start < place->fpfn ||
+    (place->lpfn && (start + num_pages) > place->lpfn))
+    return false;
+    }


if (!place->fpfn && !place->lpfn)
    return true;

if (!place->fpfn &&
    place->lpfn == i915_buddy_man_visible_size(man))
    return bman_res->used_visible_size == res->num_pages;

/* Check each drm buddy block individually */
...
modified in v3

+
+    return true;
+}
+
  static void i915_ttm_buddy_man_debug(struct ttm_resource_manager *man,
   struct drm_printer *printer)
  {
@@ -205,6 +246,8 @@ static void i915_ttm_buddy_man_debug(struct 
ttm_resource_manager *man,
  static const struct ttm_resource_manager_func 
i915_ttm_buddy_manager_func = {

  .alloc = i915_ttm_buddy_man_alloc,
  .free = i915_ttm_buddy_man_free,
+    .intersect = i915_ttm_buddy_man_intersect,


s/intersect/intersects/ ?
okay.

+    .compatible = i915_ttm_buddy_man_compatible,
  .debug = i915_ttm_buddy_man_debug,
  };

[PATCH v3 4/6] drm/i915: Implement intersect/compatible functions

2022-07-28 Thread Arunpravin Paneer Selvam

Implemented a new intersect and compatible callback function
fetching start offset from drm buddy allocator.

v2: move the bits that are specific to buddy_man (Matthew)

Signed-off-by: Christian König 
Signed-off-by: Arunpravin Paneer Selvam 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c   | 39 +---
 drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 62 +++
 2 files changed, 64 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 70e2ed4e99df..54eead15d74b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -396,43 +396,8 @@ static bool i915_ttm_eviction_valuable(struct 
ttm_buffer_object *bo,
if (!i915_gem_object_evictable(obj))
return false;
 
-   switch (res->mem_type) {
-   case I915_PL_LMEM0: {
-   struct ttm_resource_manager *man =
-   ttm_manager_type(bo->bdev, res->mem_type);
-   struct i915_ttm_buddy_resource *bman_res =
-   to_ttm_buddy_resource(res);
-   struct drm_buddy *mm = bman_res->mm;
-   struct drm_buddy_block *block;
-
-   if (!place->fpfn && !place->lpfn)
-   return true;
-
-   GEM_BUG_ON(!place->lpfn);
-
-   /*
-* If we just want something mappable then we can quickly check
-* if the current victim resource is using any of the CPU
-* visible portion.
-*/
-   if (!place->fpfn &&
-   place->lpfn == i915_ttm_buddy_man_visible_size(man))
-   return bman_res->used_visible_size > 0;
-
-   /* Real range allocation */
-   list_for_each_entry(block, _res->blocks, link) {
-   unsigned long fpfn =
-   drm_buddy_block_offset(block) >> PAGE_SHIFT;
-   unsigned long lpfn = fpfn +
-   (drm_buddy_block_size(mm, block) >> PAGE_SHIFT);
-
-   if (place->fpfn < lpfn && place->lpfn > fpfn)
-   return true;
-   }
-   return false;
-   } default:
-   break;
-   }
+   if (res->mem_type == I915_PL_LMEM0)
+   return ttm_bo_eviction_valuable(bo, place);
 
return true;
 }
diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c 
b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
index a5109548abc0..9d2a31154d58 100644
--- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
+++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
@@ -178,6 +178,66 @@ static void i915_ttm_buddy_man_free(struct 
ttm_resource_manager *man,
kfree(bman_res);
 }
 
+static bool i915_ttm_buddy_man_intersect(struct ttm_resource_manager *man,
+struct ttm_resource *res,
+const struct ttm_place *place,
+size_t size)
+{
+   struct i915_ttm_buddy_resource *bman_res = to_ttm_buddy_resource(res);
+   u32 start, num_pages = PFN_UP(size);
+   struct drm_buddy_block *block;
+
+   if (!place->fpfn && !place->lpfn)
+   return true;
+
+   /*
+* If we just want something mappable then we can quickly check
+* if the current victim resource is using any of the CP
+* visible portion.
+*/
+   if (!place->fpfn &&
+   place->lpfn == i915_ttm_buddy_man_visible_size(man))
+   return bman_res->used_visible_size > 0;
+
+   /* Check each drm buddy block individually */
+   list_for_each_entry(block, _res->blocks, link) {
+   start = drm_buddy_block_offset(block) >> PAGE_SHIFT;
+   /* Don't evict BOs outside of the requested placement range */
+   if (place->fpfn >= (start + num_pages) ||
+   (place->lpfn && place->lpfn <= start))
+   return false;
+   }
+
+   return true;
+}
+
+static bool i915_ttm_buddy_man_compatible(struct ttm_resource_manager *man,
+ struct ttm_resource *res,
+ const struct ttm_place *place,
+ size_t size)
+{
+   struct i915_ttm_buddy_resource *bman_res = to_ttm_buddy_resource(res);
+   u32 start, num_pages = PFN_UP(size);
+   struct drm_buddy_block *block;
+
+   if (!place->fpfn && !place->lpfn)
+   return true;
+
+   if (!place->fpfn &&
+   place->lpfn == i915_ttm_buddy_man_visible_size(man))
+   return bman_res->used_visible_size == res->num_pages;
+
+   /* Check each drm buddy block individually */
+   list_for_each_entry(block, _res->blocks, link) {
+   start = drm_buddy_block_offset(block) >>

[PATCH v3 6/6] drm/ttm: Switch to using the new res callback

2022-07-28 Thread Arunpravin Paneer Selvam

Apply new intersect and compatible callback instead
of having a generic placement range verfications.

v2: Added a separate callback for compatiblilty
checks (Christian)

Signed-off-by: Christian König 
Signed-off-by: Arunpravin Paneer Selvam 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 45 +++--
 drivers/gpu/drm/ttm/ttm_bo.c|  9 +++--
 drivers/gpu/drm/ttm/ttm_resource.c  |  5 +--
 3 files changed, 20 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 170935c294f5..7d25a10395c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1328,11 +1328,12 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device 
*adev, struct ttm_tt *ttm,
 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
const struct ttm_place *place)
 {
-   unsigned long num_pages = bo->resource->num_pages;
struct dma_resv_iter resv_cursor;
-   struct amdgpu_res_cursor cursor;
struct dma_fence *f;
 
+   if (!amdgpu_bo_is_amdgpu_bo(bo))
+   return ttm_bo_eviction_valuable(bo, place);
+
/* Swapout? */
if (bo->resource->mem_type == TTM_PL_SYSTEM)
return true;
@@ -1351,40 +1352,20 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct 
ttm_buffer_object *bo,
return false;
}
 
-   switch (bo->resource->mem_type) {
-   case AMDGPU_PL_PREEMPT:
-   /* Preemptible BOs don't own system resources managed by the
-* driver (pages, VRAM, GART space). They point to resources
-* owned by someone else (e.g. pageable memory in user mode
-* or a DMABuf). They are used in a preemptible context so we
-* can guarantee no deadlocks and good QoS in case of MMU
-* notifiers or DMABuf move notifiers from the resource owner.
-*/
+   /* Preemptible BOs don't own system resources managed by the
+* driver (pages, VRAM, GART space). They point to resources
+* owned by someone else (e.g. pageable memory in user mode
+* or a DMABuf). They are used in a preemptible context so we
+* can guarantee no deadlocks and good QoS in case of MMU
+* notifiers or DMABuf move notifiers from the resource owner.
+*/
+   if (bo->resource->mem_type == AMDGPU_PL_PREEMPT)
return false;
-   case TTM_PL_TT:
-   if (amdgpu_bo_is_amdgpu_bo(bo) &&
-   amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
-   return false;
-   return true;
 
-   case TTM_PL_VRAM:
-   /* Check each drm MM node individually */
-   amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT,
-);
-   while (cursor.remaining) {
-   if (place->fpfn < PFN_DOWN(cursor.start + cursor.size)
-   && !(place->lpfn &&
-place->lpfn <= PFN_DOWN(cursor.start)))
-   return true;
-
-   amdgpu_res_next(, cursor.size);
-   }
+   if (bo->resource->mem_type == TTM_PL_TT &&
+   amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
return false;
 
-   default:
-   break;
-   }
-
return ttm_bo_eviction_valuable(bo, place);
 }
 
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index c1bd006a5525..03409409e43e 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -518,6 +518,9 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo,
 bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
  const struct ttm_place *place)
 {
+   struct ttm_resource *res = bo->resource;
+   struct ttm_device *bdev = bo->bdev;
+
dma_resv_assert_held(bo->base.resv);
if (bo->resource->mem_type == TTM_PL_SYSTEM)
return true;
@@ -525,11 +528,7 @@ bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
/* Don't evict this BO if it's outside of the
 * requested placement range
 */
-   if (place->fpfn >= (bo->resource->start + bo->resource->num_pages) ||
-   (place->lpfn && place->lpfn <= bo->resource->start))
-   return false;
-
-   return true;
+   return ttm_resource_intersect(bdev, res, place, bo->base.size);
 }
 EXPORT_SYMBOL(ttm_bo_eviction_valuable);
 
diff --git a/drivers/gpu/drm/ttm/ttm_resource.c 
b/drivers/gpu/drm/ttm/ttm_resource.c
index 84a6fe9e976e..c745faf72b1a 100644
--- a/drivers/gpu/drm/ttm/ttm_resource.c
+++ b/drivers/gpu/drm/ttm/ttm_resource.c
@@ -316,6 +316,8 @@ static bool ttm_resource_places_compat(struct ttm_resource 
*res,

[PATCH v3 5/6] drm/nouveau: Implement intersect/compatible functions

2022-07-28 Thread Arunpravin Paneer Selvam

Implemented a new intersect and compatible callback function
fetching the start offset from struct ttm_resource.

Signed-off-by: Christian König 
Signed-off-by: Arunpravin Paneer Selvam 
---
 drivers/gpu/drm/nouveau/nouveau_mem.c | 29 +++
 drivers/gpu/drm/nouveau/nouveau_mem.h |  6 ++
 drivers/gpu/drm/nouveau/nouveau_ttm.c | 24 ++
 3 files changed, 59 insertions(+)

diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c 
b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 2e517cdc24c9..18f1c22fbc2c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -187,3 +187,32 @@ nouveau_mem_new(struct nouveau_cli *cli, u8 kind, u8 comp,
*res = >base;
return 0;
 }
+
+bool
+nouveau_mem_intersect(struct ttm_resource *res,
+ const struct ttm_place *place,
+ size_t size)
+{
+   u32 num_pages = PFN_UP(size);
+
+   /* Don't evict BOs outside of the requested placement range */
+   if (place->fpfn >= (res->start + num_pages) ||
+   (place->lpfn && place->lpfn <= res->start))
+   return false;
+
+   return true;
+}
+
+bool
+nouveau_mem_compatible(struct ttm_resource *res,
+  const struct ttm_place *place,
+  size_t size)
+{
+   u32 num_pages = PFN_UP(size);
+
+   if (res->start < place->fpfn ||
+   (place->lpfn && (res->start + num_pages) > place->lpfn))
+   return false;
+
+   return true;
+}
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.h 
b/drivers/gpu/drm/nouveau/nouveau_mem.h
index 325551eba5cd..4910e0e992ea 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.h
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.h
@@ -25,6 +25,12 @@ int nouveau_mem_new(struct nouveau_cli *, u8 kind, u8 comp,
struct ttm_resource **);
 void nouveau_mem_del(struct ttm_resource_manager *man,
 struct ttm_resource *);
+bool nouveau_mem_intersect(struct ttm_resource *res,
+  const struct ttm_place *place,
+  size_t size);
+bool nouveau_mem_compatible(struct ttm_resource *res,
+   const struct ttm_place *place,
+   size_t size);
 int nouveau_mem_vram(struct ttm_resource *, bool contig, u8 page);
 int nouveau_mem_host(struct ttm_resource *, struct ttm_tt *);
 void nouveau_mem_fini(struct nouveau_mem *);
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c 
b/drivers/gpu/drm/nouveau/nouveau_ttm.c
index 85f1f5a0fe5d..5dd6b4d25177 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ttm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c
@@ -42,6 +42,24 @@ nouveau_manager_del(struct ttm_resource_manager *man,
nouveau_mem_del(man, reg);
 }
 
+static bool
+nouveau_manager_intersect(struct ttm_resource_manager *man,
+ struct ttm_resource *res,
+ const struct ttm_place *place,
+ size_t size)
+{
+   return nouveau_mem_intersect(res, place, size);
+}
+
+static bool
+nouveau_manager_compatible(struct ttm_resource_manager *man,
+  struct ttm_resource *res,
+  const struct ttm_place *place,
+  size_t size)
+{
+   return nouveau_mem_compatible(res, place, size);
+}
+
 static int
 nouveau_vram_manager_new(struct ttm_resource_manager *man,
 struct ttm_buffer_object *bo,
@@ -73,6 +91,8 @@ nouveau_vram_manager_new(struct ttm_resource_manager *man,
 const struct ttm_resource_manager_func nouveau_vram_manager = {
.alloc = nouveau_vram_manager_new,
.free = nouveau_manager_del,
+   .intersects = nouveau_manager_intersect,
+   .compatible = nouveau_manager_compatible,
 };
 
 static int
@@ -97,6 +117,8 @@ nouveau_gart_manager_new(struct ttm_resource_manager *man,
 const struct ttm_resource_manager_func nouveau_gart_manager = {
.alloc = nouveau_gart_manager_new,
.free = nouveau_manager_del,
+   .intersects = nouveau_manager_intersect,
+   .compatible = nouveau_manager_compatible,
 };
 
 static int
@@ -130,6 +152,8 @@ nv04_gart_manager_new(struct ttm_resource_manager *man,
 const struct ttm_resource_manager_func nv04_gart_manager = {
.alloc = nv04_gart_manager_new,
.free = nouveau_manager_del,
+   .intersects = nouveau_manager_intersect,
+   .compatible = nouveau_manager_compatible,
 };
 
 static int
-- 
2.25.1

[PATCH v3 3/6] drm/amdgpu: Implement intersect/compatible functions

2022-07-28 Thread Arunpravin Paneer Selvam

Implemented a new intersect and compatible callback function
fetching start offset from backend drm buddy allocator.

Signed-off-by: Christian König 
Signed-off-by: Arunpravin Paneer Selvam 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c  | 38 
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 63 
 2 files changed, 101 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 8c6b2284cf56..c38752622e9e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -204,6 +204,42 @@ void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr)
amdgpu_gart_invalidate_tlb(adev);
 }
 
+/**
+ * amdgpu_gtt_mgr_intersect - test for intersection
+ *
+ * @man: Our manager object
+ * @res: The resource to test
+ * @place: The place for the new allocation
+ * @size: The size of the new allocation
+ *
+ * Simplified intersection test, only interesting if we need GART or not.
+ */
+static bool amdgpu_gtt_mgr_intersect(struct ttm_resource_manager *man,
+struct ttm_resource *res,
+const struct ttm_place *place,
+size_t size)
+{
+   return !place->lpfn || amdgpu_gtt_mgr_has_gart_addr(res);
+}
+
+/**
+ * amdgpu_gtt_mgr_compatible - test for compatibility
+ *
+ * @man: Our manager object
+ * @res: The resource to test
+ * @place: The place for the new allocation
+ * @size: The size of the new allocation
+ *
+ * Simplified compatibility test.
+ */
+static bool amdgpu_gtt_mgr_compatible(struct ttm_resource_manager *man,
+ struct ttm_resource *res,
+ const struct ttm_place *place,
+ size_t size)
+{
+   return !place->lpfn || amdgpu_gtt_mgr_has_gart_addr(res);
+}
+
 /**
  * amdgpu_gtt_mgr_debug - dump VRAM table
  *
@@ -225,6 +261,8 @@ static void amdgpu_gtt_mgr_debug(struct 
ttm_resource_manager *man,
 static const struct ttm_resource_manager_func amdgpu_gtt_mgr_func = {
.alloc = amdgpu_gtt_mgr_new,
.free = amdgpu_gtt_mgr_del,
+   .intersects = amdgpu_gtt_mgr_intersect,
+   .compatible = amdgpu_gtt_mgr_compatible,
.debug = amdgpu_gtt_mgr_debug
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 7a5e8a7b4a1b..0876d370dbb0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -720,6 +720,67 @@ uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr 
*mgr)
return atomic64_read(>vis_usage);
 }
 
+/**
+ * amdgpu_vram_mgr_intersect - test each drm buddy block for intersection
+ *
+ * @man: TTM memory type manager
+ * @res: The resource to test
+ * @place: The place to test against
+ * @size: Size of the new allocation
+ *
+ * Test each drm buddy block for intersection for eviction decision.
+ */
+static bool amdgpu_vram_mgr_intersect(struct ttm_resource_manager *man,
+ struct ttm_resource *res,
+ const struct ttm_place *place,
+ size_t size)
+{
+   struct amdgpu_vram_mgr_resource *mgr = to_amdgpu_vram_mgr_resource(res);
+   u32 start, num_pages = PFN_UP(size);
+   struct drm_buddy_block *block;
+
+   /* Check each drm buddy block individually */
+   list_for_each_entry(block, >blocks, link) {
+   start = amdgpu_vram_mgr_block_start(block) >> PAGE_SHIFT;
+   /* Don't evict BOs outside of the requested placement range */
+   if (place->fpfn >= (start + num_pages) ||
+   (place->lpfn && place->lpfn <= start))
+   return false;
+   }
+
+   return true;
+}
+
+/**
+ * amdgpu_vram_mgr_compatible - test each drm buddy block for compatibility
+ *
+ * @man: TTM memory type manager
+ * @res: The resource to test
+ * @place: The place to test against
+ * @size: Size of the new allocation
+ *
+ * Test each drm buddy block for placement compatibility.
+ */
+static bool amdgpu_vram_mgr_compatible(struct ttm_resource_manager *man,
+  struct ttm_resource *res,
+  const struct ttm_place *place,
+  size_t size)
+{
+   struct amdgpu_vram_mgr_resource *mgr = to_amdgpu_vram_mgr_resource(res);
+   u32 start, num_pages = PFN_UP(size);
+   struct drm_buddy_block *block;
+
+   /* Check each drm buddy block individually */
+   list_for_each_entry(block, >blocks, link) {
+   start = amdgpu_vram_mgr_block_start(block) >> PAGE_SHIFT;
+   if (start < place->fpfn ||
+   (place->lpfn && (start + num_pages) > place->lpfn))
+   return false;
+

[PATCH v3 1/6] drm/ttm: Add new callbacks to ttm res mgr

2022-07-28 Thread Arunpravin Paneer Selvam

We are adding two new callbacks to ttm resource manager
function to handle intersection and compatibility of
placement and resources.

v2: move the amdgpu and ttm_range_manager changes to
separate patches (Christian)
v3: rename "intersect" to "intersects" (Matthew)

Signed-off-by: Christian König 
Signed-off-by: Arunpravin Paneer Selvam 
---
 drivers/gpu/drm/ttm/ttm_resource.c | 59 ++
 include/drm/ttm/ttm_resource.h | 39 
 2 files changed, 98 insertions(+)

diff --git a/drivers/gpu/drm/ttm/ttm_resource.c 
b/drivers/gpu/drm/ttm/ttm_resource.c
index 20f9adcc3235..84a6fe9e976e 100644
--- a/drivers/gpu/drm/ttm/ttm_resource.c
+++ b/drivers/gpu/drm/ttm/ttm_resource.c
@@ -253,6 +253,65 @@ void ttm_resource_free(struct ttm_buffer_object *bo, 
struct ttm_resource **res)
 }
 EXPORT_SYMBOL(ttm_resource_free);
 
+/**
+ * ttm_resource_intersect - test for intersection
+ *
+ * @bdev: TTM device structure
+ * @res: The resource to test
+ * @place: The placement to test
+ * @size: How many bytes the new allocation needs.
+ *
+ * Test if @res intersects with @place and @size. Used for testing if evictions
+ * are valueable or not.
+ *
+ * Returns true if the res placement intersects with @place and @size.
+ */
+bool ttm_resource_intersect(struct ttm_device *bdev,
+   struct ttm_resource *res,
+   const struct ttm_place *place,
+   size_t size)
+{
+   struct ttm_resource_manager *man;
+
+   if (!res)
+   return false;
+
+   man = ttm_manager_type(bdev, res->mem_type);
+   if (!place || !man->func->intersects)
+   return true;
+
+   return man->func->intersects(man, res, place, size);
+}
+
+/**
+ * ttm_resource_compatible - test for compatibility
+ *
+ * @bdev: TTM device structure
+ * @res: The resource to test
+ * @place: The placement to test
+ * @size: How many bytes the new allocation needs.
+ *
+ * Test if @res compatible with @place and @size.
+ *
+ * Returns true if the res placement compatible with @place and @size.
+ */
+bool ttm_resource_compatible(struct ttm_device *bdev,
+struct ttm_resource *res,
+const struct ttm_place *place,
+size_t size)
+{
+   struct ttm_resource_manager *man;
+
+   if (!res)
+   return false;
+
+   man = ttm_manager_type(bdev, res->mem_type);
+   if (!place || !man->func->compatible)
+   return true;
+
+   return man->func->compatible(man, res, place, size);
+}
+
 static bool ttm_resource_places_compat(struct ttm_resource *res,
   const struct ttm_place *places,
   unsigned num_placement)
diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h
index ca89a48c2460..93c0ac338be8 100644
--- a/include/drm/ttm/ttm_resource.h
+++ b/include/drm/ttm/ttm_resource.h
@@ -88,6 +88,37 @@ struct ttm_resource_manager_func {
void (*free)(struct ttm_resource_manager *man,
 struct ttm_resource *res);
 
+   /**
+* struct ttm_resource_manager_func member intersect
+*
+* @man: Pointer to a memory type manager.
+* @res: Pointer to a struct ttm_resource to be checked.
+* @place: Placement to check against.
+* @size: Size of the check.
+*
+* Test if @res intersects with @place + @size. Used to judge if
+* evictions are valueable or not.
+*/
+   bool (*intersects)(struct ttm_resource_manager *man,
+  struct ttm_resource *res,
+  const struct ttm_place *place,
+  size_t size);
+
+   /**
+* struct ttm_resource_manager_func member compatible
+*
+* @man: Pointer to a memory type manager.
+* @res: Pointer to a struct ttm_resource to be checked.
+* @place: Placement to check against.
+* @size: Size of the check.
+*
+* Test if @res compatible with @place + @size.
+*/
+   bool (*compatible)(struct ttm_resource_manager *man,
+  struct ttm_resource *res,
+  const struct ttm_place *place,
+  size_t size);
+
/**
 * struct ttm_resource_manager_func member debug
 *
@@ -329,6 +360,14 @@ int ttm_resource_alloc(struct ttm_buffer_object *bo,
   const struct ttm_place *place,
   struct ttm_resource **res);
 void ttm_resource_free(struct ttm_buffer_object *bo, struct ttm_resource 
**res);
+bool ttm_resource_intersect(struct ttm_device *bdev,
+   struct ttm_resource *res,
+   const struct ttm_place *place,
+   size_t size);
+bool ttm_resource_compatible(struct ttm_device *bdev,
+

[PATCH v3 2/6] drm/ttm: Implement intersect/compatible functions

2022-07-28 Thread Arunpravin Paneer Selvam

Implemented a new intersect and compatible callback functions
to ttm range manager fetching start offset from drm mm range
allocator.

Signed-off-by: Christian König 
Signed-off-by: Arunpravin Paneer Selvam 
---
 drivers/gpu/drm/ttm/ttm_range_manager.c | 33 +
 1 file changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/ttm/ttm_range_manager.c 
b/drivers/gpu/drm/ttm/ttm_range_manager.c
index d91666721dc6..19247aaeb5ce 100644
--- a/drivers/gpu/drm/ttm/ttm_range_manager.c
+++ b/drivers/gpu/drm/ttm/ttm_range_manager.c
@@ -113,6 +113,37 @@ static void ttm_range_man_free(struct ttm_resource_manager 
*man,
kfree(node);
 }
 
+static bool ttm_range_man_intersect(struct ttm_resource_manager *man,
+   struct ttm_resource *res,
+   const struct ttm_place *place,
+   size_t size)
+{
+   struct drm_mm_node *node = _ttm_range_mgr_node(res)->mm_nodes[0];
+   u32 num_pages = PFN_UP(size);
+
+   /* Don't evict BOs outside of the requested placement range */
+   if (place->fpfn >= (node->start + num_pages) ||
+   (place->lpfn && place->lpfn <= node->start))
+   return false;
+
+   return true;
+}
+
+static bool ttm_range_man_compatible(struct ttm_resource_manager *man,
+struct ttm_resource *res,
+const struct ttm_place *place,
+size_t size)
+{
+   struct drm_mm_node *node = _ttm_range_mgr_node(res)->mm_nodes[0];
+   u32 num_pages = PFN_UP(size);
+
+   if (node->start < place->fpfn ||
+   (place->lpfn && (node->start + num_pages) > place->lpfn))
+   return false;
+
+   return true;
+}
+
 static void ttm_range_man_debug(struct ttm_resource_manager *man,
struct drm_printer *printer)
 {
@@ -126,6 +157,8 @@ static void ttm_range_man_debug(struct ttm_resource_manager 
*man,
 static const struct ttm_resource_manager_func ttm_range_manager_func = {
.alloc = ttm_range_man_alloc,
.free = ttm_range_man_free,
+   .intersects = ttm_range_man_intersect,
+   .compatible = ttm_range_man_compatible,
.debug = ttm_range_man_debug
 };
 
-- 
2.25.1

Re: [PATCH] drm/amdgpu: Fix stub fence refcount underflow

2022-07-28 Thread Felix Kuehling


Am 2022-07-27 um 23:52 schrieb Alex Deucher:

On Wed, Jul 27, 2022 at 7:08 PM Felix Kuehling  wrote:

Don't drop the stub fence reference after installing it as a replacement
for the eviction fence. dma_resv_replace_fences doesn't take another
reference to the fence, so it takes ownership of the reference passed
in by us.

Fixes: 548e7432dc2d ("dma-buf: add dma_resv_replace_fences v2")
CC: Christian König 
Signed-off-by: Felix Kuehling 

Acked-by: Alex Deucher 


This patch is the wrong solution. Xinhui added a dma_fence_get in 
dma_resv_replace_fences in his patch "dma-buf: Fix one use-after-free of 
fence". So this patch is not needed any more.


Regards,
  Felix



---
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 1 -
  1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 87a3a3ae9448..a6c7dcd8c345 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -294,7 +294,6 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct 
amdgpu_bo *bo,
 replacement = dma_fence_get_stub();
 dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context,
 replacement, DMA_RESV_USAGE_READ);
-   dma_fence_put(replacement);
 return 0;
  }

--
2.32.0

[PATCH v2] drm/amd/display: Fix vblank refcount in vrr transition

2022-07-28 Thread Yunxiang Li

manage_dm_interrupts disable/enable vblank using drm_crtc_vblank_off/on
which causes drm_crtc_vblank_get in vrr_transition to fail, and later
when drm_crtc_vblank_put is called the refcount on vblank will be messed
up. Therefore move the call to after manage_dm_interrupts.

Unchecked calls to drm_crtc_vblank_get seems to be common in other
drivers as well so it may make sense to let get always succeed during
modset, see
https://lists.freedesktop.org/archives/dri-devel/2022-July/365589.html

Signed-off-by: Yunxiang Li 
---
v2: check the return code for calls that might fail and warn on them

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 34 ---
 1 file changed, 14 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 92470a0e0262..9f3fdb92e7a4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7480,15 +7480,15 @@ static void amdgpu_dm_handle_vrr_transition(struct 
dm_crtc_state *old_state,
 * We also need vupdate irq for the actual core vblank handling
 * at end of vblank.
 */
-   dm_set_vupdate_irq(new_state->base.crtc, true);
-   drm_crtc_vblank_get(new_state->base.crtc);
+   WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, true) != 0);
+   WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
 __func__, new_state->base.crtc->base.id);
} else if (old_vrr_active && !new_vrr_active) {
/* Transition VRR active -> inactive:
 * Allow vblank irq disable again for fixed refresh rate.
 */
-   dm_set_vupdate_irq(new_state->base.crtc, false);
+   WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, false) != 0);
drm_crtc_vblank_put(new_state->base.crtc);
DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
 __func__, new_state->base.crtc->base.id);
@@ -8252,23 +8252,6 @@ static void amdgpu_dm_atomic_commit_tail(struct 
drm_atomic_state *state)
mutex_unlock(>dc_lock);
}
 
-   /* Count number of newly disabled CRTCs for dropping PM refs later. */
-   for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
- new_crtc_state, i) {
-   if (old_crtc_state->active && !new_crtc_state->active)
-   crtc_disable_count++;
-
-   dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
-   dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
-
-   /* For freesync config update on crtc state and params for irq 
*/
-   update_stream_irq_parameters(dm, dm_new_crtc_state);
-
-   /* Handle vrr on->off / off->on transitions */
-   amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
-   dm_new_crtc_state);
-   }
-
/**
 * Enable interrupts for CRTCs that are newly enabled or went through
 * a modeset. It was intentionally deferred until after the front end
@@ -8287,7 +8270,15 @@ static void amdgpu_dm_atomic_commit_tail(struct 
drm_atomic_state *state)
cur_crc_src = acrtc->dm_irq_params.crc_src;
spin_unlock_irqrestore(_to_drm(adev)->event_lock, flags);
 #endif
+   /* Count number of newly disabled CRTCs for dropping PM refs 
later. */
+   if (old_crtc_state->active && !new_crtc_state->active)
+   crtc_disable_count++;
+
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+   dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
+
+   /* For freesync config update on crtc state and params for irq 
*/
+   update_stream_irq_parameters(dm, dm_new_crtc_state);
 
if (new_crtc_state->active &&
(!old_crtc_state->active ||
@@ -8324,6 +8315,9 @@ static void amdgpu_dm_atomic_commit_tail(struct 
drm_atomic_state *state)
DRM_DEBUG_DRIVER("Failed to configure 
crc source");
 #endif
}
+
+   /* Handle vrr on->off / off->on transitions */
+   amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, 
dm_new_crtc_state);
}
 
for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
-- 
2.37.1

[PATCH v2 3/6] drm/amdgpu: add debugfs amdgpu_reset_level

2022-07-28 Thread Victor Zhao

Introduce amdgpu_reset_level debugfs in order to help debug and
test specific type of reset. Also helps blocking unwanted type of
resets.

By default, mode2 reset will not be enabled

v2: make this debugfs in adev and use debugfs_create_u32

Signed-off-by: Victor Zhao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c   | 8 
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c| 3 +++
 4 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e146810c700b..895d74c8aace 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -274,6 +274,9 @@ extern int amdgpu_vcnfw_log;
 #define AMDGPU_RESET_VCE   (1 << 13)
 #define AMDGPU_RESET_VCE1  (1 << 14)
 
+#define AMDGPU_RESET_LEVEL_SOFT_RECOVERY (1 << 0)
+#define AMDGPU_RESET_LEVEL_MODE2 (1 << 1)
+
 /* max cursor sizes (in pixels) */
 #define CIK_CURSOR_WIDTH 128
 #define CIK_CURSOR_HEIGHT 128
@@ -1060,6 +1063,8 @@ struct amdgpu_device {
uint32_tscpm_status;
 
struct work_struct  reset_work;
+
+   uint32_t
amdgpu_reset_level_mask;
 };
 
 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index e2eec985adb3..c21b04463de8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1785,6 +1785,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
return PTR_ERR(ent);
}
 
+   debugfs_create_u32("amdgpu_reset_level", 0600, root, 
>amdgpu_reset_level_mask);
+
/* Register debugfs entries for amdgpu_ttm */
amdgpu_ttm_debugfs_init(adev);
amdgpu_debugfs_pm_init(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
index 831fb222139c..9da5ead50c90 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
@@ -37,6 +37,8 @@ int amdgpu_reset_init(struct amdgpu_device *adev)
 {
int ret = 0;
 
+   adev->amdgpu_reset_level_mask = 0x1;
+
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 2):
ret = aldebaran_reset_init(adev);
@@ -74,6 +76,9 @@ int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
 {
struct amdgpu_reset_handler *reset_handler = NULL;
 
+   if (!(adev->amdgpu_reset_level_mask & AMDGPU_RESET_LEVEL_MODE2))
+   return -ENOSYS;
+
if (test_bit(AMDGPU_SKIP_MODE2_RESET, _context->flags))
return -ENOSYS;
 
@@ -93,6 +98,9 @@ int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
int ret;
struct amdgpu_reset_handler *reset_handler = NULL;
 
+   if (!(adev->amdgpu_reset_level_mask & AMDGPU_RESET_LEVEL_MODE2))
+   return -ENOSYS;
+
if (test_bit(AMDGPU_SKIP_MODE2_RESET, _context->flags))
return -ENOSYS;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index d3558c34d406..3e316b013fd9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -405,6 +405,9 @@ bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, 
unsigned int vmid,
 {
ktime_t deadline = ktime_add_us(ktime_get(), 1);
 
+   if (!(ring->adev->amdgpu_reset_level_mask & 
AMDGPU_RESET_LEVEL_SOFT_RECOVERY))
+   return false;
+
if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || 
!fence)
return false;
 
-- 
2.25.1

[PATCH v2 4/6] drm/amdgpu: save and restore gc hub regs

2022-07-28 Thread Victor Zhao

Save and restore gfxhub regs as they will be reset during mode 2

Signed-off-by: Victor Zhao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h|  2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h   | 26 +++
 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c  | 72 +++
 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c   |  7 +-
 .../include/asic_reg/gc/gc_10_3_0_offset.h|  4 ++
 5 files changed, 110 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
index beabab515836..f8036f2b100e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
@@ -35,6 +35,8 @@ struct amdgpu_gfxhub_funcs {
void (*init)(struct amdgpu_device *adev);
int (*get_xgmi_info)(struct amdgpu_device *adev);
void (*utcl2_harvest)(struct amdgpu_device *adev);
+   void (*mode2_save_regs)(struct amdgpu_device *adev);
+   void (*mode2_restore_regs)(struct amdgpu_device *adev);
 };
 
 struct amdgpu_gfxhub {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 008eaca27151..0305b660cd17 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -264,6 +264,32 @@ struct amdgpu_gmc {
u64 mall_size;
/* number of UMC instances */
int num_umc;
+   /* mode2 save restore */
+   u64 VM_L2_CNTL;
+   u64 VM_L2_CNTL2;
+   u64 VM_DUMMY_PAGE_FAULT_CNTL;
+   u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32;
+   u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32;
+   u64 VM_L2_PROTECTION_FAULT_CNTL;
+   u64 VM_L2_PROTECTION_FAULT_CNTL2;
+   u64 VM_L2_PROTECTION_FAULT_MM_CNTL3;
+   u64 VM_L2_PROTECTION_FAULT_MM_CNTL4;
+   u64 VM_L2_PROTECTION_FAULT_ADDR_LO32;
+   u64 VM_L2_PROTECTION_FAULT_ADDR_HI32;
+   u64 VM_DEBUG;
+   u64 VM_L2_MM_GROUP_RT_CLASSES;
+   u64 VM_L2_BANK_SELECT_RESERVED_CID;
+   u64 VM_L2_BANK_SELECT_RESERVED_CID2;
+   u64 VM_L2_CACHE_PARITY_CNTL;
+   u64 VM_L2_IH_LOG_CNTL;
+   u64 VM_CONTEXT_CNTL[16];
+   u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[16];
+   u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[16];
+   u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[16];
+   u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[16];
+   u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[16];
+   u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[16];
+   u64 MC_VM_MX_L1_TLB_CNTL;
 };
 
 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) 
((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
index d8c531581116..51cf8acd2d79 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
@@ -576,6 +576,76 @@ static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device 
*adev)
}
 }
 
+static void gfxhub_v2_1_save_regs(struct amdgpu_device *adev)
+{
+   int i;
+   adev->gmc.VM_L2_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
+   adev->gmc.VM_L2_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
+   adev->gmc.VM_DUMMY_PAGE_FAULT_CNTL = RREG32_SOC15(GC, 0, 
mmGCVM_DUMMY_PAGE_FAULT_CNTL);
+   adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0, 
mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32);
+   adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0, 
mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32);
+   adev->gmc.VM_L2_PROTECTION_FAULT_CNTL = RREG32_SOC15(GC, 0, 
mmGCVM_L2_PROTECTION_FAULT_CNTL);
+   adev->gmc.VM_L2_PROTECTION_FAULT_CNTL2 = RREG32_SOC15(GC, 0, 
mmGCVM_L2_PROTECTION_FAULT_CNTL2);
+   adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL3 = RREG32_SOC15(GC, 0, 
mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3);
+   adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL4 = RREG32_SOC15(GC, 0, 
mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4);
+   adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0, 
mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32);
+   adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0, 
mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32);
+   adev->gmc.VM_DEBUG = RREG32_SOC15(GC, 0, mmGCVM_DEBUG);
+   adev->gmc.VM_L2_MM_GROUP_RT_CLASSES = RREG32_SOC15(GC, 0, 
mmGCVM_L2_MM_GROUP_RT_CLASSES);
+   adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID = RREG32_SOC15(GC, 0, 
mmGCVM_L2_BANK_SELECT_RESERVED_CID);
+   adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID2 = RREG32_SOC15(GC, 0, 
mmGCVM_L2_BANK_SELECT_RESERVED_CID2);
+   adev->gmc.VM_L2_CACHE_PARITY_CNTL = RREG32_SOC15(GC, 0, 
mmGCVM_L2_CACHE_PARITY_CNTL);
+   adev->gmc.VM_L2_IH_LOG_CNTL = RREG32_SOC15(GC, 0, 
mmGCVM_L2_IH_LOG_CNTL);
+
+   for (i = 0; i <= 15; i++) {
+   adev->gmc.VM_CONTEXT_CNTL[i] = RREG32_SOC15_OFFSET(GC, 0, 
mmGCVM_CONTEXT0_CNTL, i);
+   adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[i] = 
RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, i * 2);
+

[PATCH v2 5/6] drm/amdgpu: revert context to stop engine before mode2 reset

2022-07-28 Thread Victor Zhao

For some hang caused by slow tests, engine cannot be stopped which
may cause resume failure after reset. In this case, force halt
engine by reverting context addresses

Signed-off-by: Victor Zhao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c  |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h  |  1 +
 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c| 36 +
 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c |  2 ++
 4 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f03750b64f61..debbba842fce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5038,6 +5038,7 @@ static void amdgpu_device_recheck_guilty_jobs(
 
/* set guilty */
drm_sched_increase_karma(s_job);
+   amdgpu_reset_prepare_hwcontext(adev, reset_context);
 retry:
/* do hw reset */
if (amdgpu_sriov_vf(adev)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
index f8036f2b100e..c7b44aeb671b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
@@ -37,6 +37,7 @@ struct amdgpu_gfxhub_funcs {
void (*utcl2_harvest)(struct amdgpu_device *adev);
void (*mode2_save_regs)(struct amdgpu_device *adev);
void (*mode2_restore_regs)(struct amdgpu_device *adev);
+   void (*halt)(struct amdgpu_device *adev);
 };
 
 struct amdgpu_gfxhub {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
index 51cf8acd2d79..8cf53e039c11 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
@@ -646,6 +646,41 @@ static void gfxhub_v2_1_restore_regs(struct amdgpu_device 
*adev)
WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, 
adev->gmc.MC_VM_MX_L1_TLB_CNTL);
 }
 
+static void gfxhub_v2_1_halt(struct amdgpu_device *adev)
+{
+   struct amdgpu_vmhub *hub = >vmhub[AMDGPU_GFXHUB_0];
+   int i;
+   uint32_t tmp;
+   int time = 1000;
+
+   gfxhub_v2_1_set_fault_enable_default(adev, false);
+
+   for (i = 0; i <= 14; i++) {
+   WREG32_SOC15_OFFSET(GC, 0, 
mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
+   i * hub->ctx_addr_distance, ~0);
+   WREG32_SOC15_OFFSET(GC, 0, 
mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
+   i * hub->ctx_addr_distance, ~0);
+   WREG32_SOC15_OFFSET(GC, 0, 
mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
+   i * hub->ctx_addr_distance,
+   0);
+   WREG32_SOC15_OFFSET(GC, 0, 
mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
+   i * hub->ctx_addr_distance,
+   0);
+   }
+   tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
+   while ((tmp & (GRBM_STATUS2__EA_BUSY_MASK |
+ GRBM_STATUS2__EA_LINK_BUSY_MASK)) != 0 &&
+  time) {
+   udelay(100);
+   time--;
+   tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
+   }
+
+   if (!time) {
+   DRM_WARN("failed to wait for GRBM(EA) idle\n");
+   }
+}
+
 const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
.get_fb_location = gfxhub_v2_1_get_fb_location,
.get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset,
@@ -658,4 +693,5 @@ const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
.utcl2_harvest = gfxhub_v2_1_utcl2_harvest,
.mode2_save_regs = gfxhub_v2_1_save_regs,
.mode2_restore_regs = gfxhub_v2_1_restore_regs,
+   .halt = gfxhub_v2_1_halt,
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c 
b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
index 51a5b68f77d3..fead7251292f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
+++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
@@ -97,6 +97,8 @@ sienna_cichlid_mode2_prepare_hwcontext(struct 
amdgpu_reset_control *reset_ctl,
if (!amdgpu_sriov_vf(adev)) {
if (adev->gfxhub.funcs->mode2_save_regs)
adev->gfxhub.funcs->mode2_save_regs(adev);
+   if (adev->gfxhub.funcs->halt)
+   adev->gfxhub.funcs->halt(adev);
r = sienna_cichlid_mode2_suspend_ip(adev);
}
 
-- 
2.25.1

[PATCH v2 6/6] drm/amdgpu: reduce reset time

2022-07-28 Thread Victor Zhao

In multi container use case, reset time is important, so skip ring
tests and cp halt wait during ip suspending for reset as they are
going to fail and cost more time on reset

v2: add a hang flag to indicate the reset comes from a job timeout,
skip ring test and cp halt wait in this case

Signed-off-by: Victor Zhao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c   |  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c   |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h |  1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 11 +--
 5 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 222d3d7ea076..c735a17c6afb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -27,6 +27,7 @@
 #include "amdgpu_gfx.h"
 #include "amdgpu_rlc.h"
 #include "amdgpu_ras.h"
+#include "amdgpu_reset.h"
 
 /* delay 0.1 second to enable gfx off feature */
 #define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(100)
@@ -477,7 +478,7 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
kiq->pmf->kiq_unmap_queues(kiq_ring, >gfx.compute_ring[i],
   RESET_QUEUES, 0, 0);
 
-   if (adev->gfx.kiq.ring.sched.ready)
+   if (adev->gfx.kiq.ring.sched.ready && !(amdgpu_in_reset(adev) && 
adev->reset_domain->hang))
r = amdgpu_ring_test_helper(kiq_ring);
spin_unlock(>gfx.kiq.ring_lock);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 6c3e7290153f..bb40880a557f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -49,6 +49,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct 
drm_sched_job *s_job)
}
 
memset(, 0, sizeof(struct amdgpu_task_info));
+   adev->reset_domain->hang = true;
 
if (amdgpu_gpu_recovery &&
amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) 
{
@@ -83,6 +84,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct 
drm_sched_job *s_job)
}
 
 exit:
+   adev->reset_domain->hang = false;
drm_dev_exit(idx);
return DRM_GPU_SCHED_STAT_NOMINAL;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
index 9da5ead50c90..b828fe773f50 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
@@ -155,6 +155,7 @@ struct amdgpu_reset_domain 
*amdgpu_reset_create_reset_domain(enum amdgpu_reset_d
atomic_set(_domain->in_gpu_reset, 0);
atomic_set(_domain->reset_res, 0);
init_rwsem(_domain->sem);
+   reset_domain->hang = false;
 
return reset_domain;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
index cc4b2eeb24cf..29e324add552 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
@@ -84,6 +84,7 @@ struct amdgpu_reset_domain {
struct rw_semaphore sem;
atomic_t in_gpu_reset;
atomic_t reset_res;
+   bool hang;
 };
 
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index fafbad3cf08d..a384e04d916c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -29,6 +29,7 @@
 #include "amdgpu.h"
 #include "amdgpu_gfx.h"
 #include "amdgpu_psp.h"
+#include "amdgpu_reset.h"
 #include "nv.h"
 #include "nvd.h"
 
@@ -5971,6 +5972,9 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device 
*adev, bool enable)
WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
}
 
+   if ((amdgpu_in_reset(adev) && adev->reset_domain->hang) && !enable)
+   return 0;
+
for (i = 0; i < adev->usec_timeout; i++) {
if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
break;
@@ -7569,8 +7573,10 @@ static int gfx_v10_0_kiq_disable_kgq(struct 
amdgpu_device *adev)
for (i = 0; i < adev->gfx.num_gfx_rings; i++)
kiq->pmf->kiq_unmap_queues(kiq_ring, >gfx.gfx_ring[i],
   PREEMPT_QUEUES, 0, 0);
-
-   return amdgpu_ring_test_helper(kiq_ring);
+   if (!(amdgpu_in_reset(adev) && adev->reset_domain->hang))
+   return amdgpu_ring_test_helper(kiq_ring);
+   else
+   return 0;
 }
 #endif
 
@@ -7610,6 +7616,7 @@ static int gfx_v10_0_hw_fini(void *handle)
 
return 0;
}
+
gfx_v10_0_cp_enable(adev, false);
gfx_v10_0_enable_gui_idle_interrupt(adev, false);
 
-- 
2.25.1

[PATCH v2 2/6] drm/amdgpu: let mode2 reset fallback to default when failure

2022-07-28 Thread Victor Zhao

- introduce AMDGPU_SKIP_MODE2_RESET flag
- let mode2 reset fallback to default reset method if failed

v2: move this part out from the asic specific part

Signed-off-by: Victor Zhao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c| 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c| 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c  | 6 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h  | 1 +
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c  | 1 +
 9 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 5e53a5293935..091415a4abf0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -135,6 +135,7 @@ static void amdgpu_amdkfd_reset_work(struct work_struct 
*work)
reset_context.method = AMD_RESET_METHOD_NONE;
reset_context.reset_req_dev = adev;
clear_bit(AMDGPU_NEED_FULL_RESET, _context.flags);
+   clear_bit(AMDGPU_SKIP_MODE2_RESET, _context.flags);
 
amdgpu_device_gpu_recover(adev, NULL, _context);
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 041bd906449d..f03750b64f61 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5147,6 +5147,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
 
reset_context->job = job;
reset_context->hive = hive;
+
/*
 * Build list of devices to reset.
 * In case we are in XGMI hive mode, resort the device list
@@ -5266,8 +5267,11 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
amdgpu_ras_resume(adev);
} else {
r = amdgpu_do_asic_reset(device_list_handle, reset_context);
-   if (r && r == -EAGAIN)
+   if (r && r == -EAGAIN) {
+   set_bit(AMDGPU_SKIP_MODE2_RESET, _context->flags);
+   adev->asic_reset_res = 0;
goto retry;
+   }
}
 
 skip_hw_reset:
@@ -5695,6 +5699,7 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev 
*pdev)
reset_context.reset_req_dev = adev;
set_bit(AMDGPU_NEED_FULL_RESET, _context.flags);
set_bit(AMDGPU_SKIP_HW_RESET, _context.flags);
+   set_bit(AMDGPU_SKIP_MODE2_RESET, _context.flags);
 
adev->no_hw_access = true;
r = amdgpu_device_pre_asic_reset(adev, _context);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 5071b96be982..6c3e7290153f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -71,6 +71,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct 
drm_sched_job *s_job)
reset_context.method = AMD_RESET_METHOD_NONE;
reset_context.reset_req_dev = adev;
clear_bit(AMDGPU_NEED_FULL_RESET, _context.flags);
+   clear_bit(AMDGPU_SKIP_MODE2_RESET, _context.flags);
 
r = amdgpu_device_gpu_recover(ring->adev, job, _context);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index ff5361f5c2d4..ab9ba5a9c33d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1949,6 +1949,7 @@ static void amdgpu_ras_do_recovery(struct work_struct 
*work)
reset_context.method = AMD_RESET_METHOD_NONE;
reset_context.reset_req_dev = adev;
clear_bit(AMDGPU_NEED_FULL_RESET, _context.flags);
+   clear_bit(AMDGPU_SKIP_MODE2_RESET, _context.flags);
 
amdgpu_device_gpu_recover(ras->adev, NULL, _context);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
index f778466bb9db..831fb222139c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
@@ -74,6 +74,9 @@ int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
 {
struct amdgpu_reset_handler *reset_handler = NULL;
 
+   if (test_bit(AMDGPU_SKIP_MODE2_RESET, _context->flags))
+   return -ENOSYS;
+
if (adev->reset_cntl && adev->reset_cntl->get_reset_handler)
reset_handler = adev->reset_cntl->get_reset_handler(
adev->reset_cntl, reset_context);
@@ -90,6 +93,9 @@ int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
int ret;
struct amdgpu_reset_handler *reset_handler = NULL;
 
+   if (test_bit(AMDGPU_SKIP_MODE2_RESET, _context->flags))
+   return -ENOSYS;
+
if (adev->reset_cntl)

[PATCH v2 1/6] drm/amdgpu: add mode2 reset for sienna_cichlid

2022-07-28 Thread Victor Zhao

To meet the requirement for multi container usecase which needs
a quicker reset and not causing VRAM lost, adding the Mode2
reset handler for sienna_cichlid.

v2: move skip mode2 flag part separately

Signed-off-by: Victor Zhao 
---
 drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c |   7 +
 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c   | 297 ++
 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.h   |  32 ++
 .../pm/swsmu/inc/pmfw_if/smu_v11_0_7_ppsmc.h  |   4 +-
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h  |   3 +-
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   |  54 
 7 files changed, 395 insertions(+), 4 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index c7d0cd15b5ef..7030ac2d7d2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -75,7 +75,7 @@ amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o 
vega10_reg_init.o \
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o 
mxgpu_nv.o \
nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o 
soc21.o \
-   nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o
+   sienna_cichlid.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o 
lsdma_v6_0.o
 
 # add DF block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
index 32c86a0b145c..f778466bb9db 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
@@ -23,6 +23,7 @@
 
 #include "amdgpu_reset.h"
 #include "aldebaran.h"
+#include "sienna_cichlid.h"
 
 int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
 struct amdgpu_reset_handler *handler)
@@ -40,6 +41,9 @@ int amdgpu_reset_init(struct amdgpu_device *adev)
case IP_VERSION(13, 0, 2):
ret = aldebaran_reset_init(adev);
break;
+   case IP_VERSION(11, 0, 7):
+   ret = sienna_cichlid_reset_init(adev);
+   break;
default:
break;
}
@@ -55,6 +59,9 @@ int amdgpu_reset_fini(struct amdgpu_device *adev)
case IP_VERSION(13, 0, 2):
ret = aldebaran_reset_fini(adev);
break;
+   case IP_VERSION(11, 0, 7):
+   ret = sienna_cichlid_reset_fini(adev);
+   break;
default:
break;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c 
b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
new file mode 100644
index ..0512960bed23
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
@@ -0,0 +1,297 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "sienna_cichlid.h"
+#include "amdgpu_reset.h"
+#include "amdgpu_amdkfd.h"
+#include "amdgpu_dpm.h"
+#include "amdgpu_job.h"
+#include "amdgpu_ring.h"
+#include "amdgpu_ras.h"
+#include "amdgpu_psp.h"
+#include "amdgpu_xgmi.h"
+
+static struct amdgpu_reset_handler *
+sienna_cichlid_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
+   struct amdgpu_reset_context *reset_context)
+{
+   struct amdgpu_reset_handler *handler;
+   struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
+
+   if (reset_context->method != AMD_RESET_METHOD_NONE) {
+   list_for_each_entry(handler, _ctl->reset_handlers,
+handler_list) {
+   if (handler->reset_method == reset_context->method)
+   return handler;
+   }
+   } else {
+

RE: [PATCH 1/5] drm/amdgpu: send msg to IMU for the front-door loading

2022-07-28 Thread Du, Xiaojian

Of course, I will move it under "smu->is_apu". 

Thanks,
Xiaojian

>-Original Message-
>From: Quan, Evan  
>Sent: 2022年7月28日 16:14
>To: Du, Xiaojian ; amd-gfx@lists.freedesktop.org
>Cc: Deucher, Alexander ; Huang, Tim 
>; Du, Xiaojian ; Zhang, Yifan 
>
>Subject: RE: [PATCH 1/5] drm/amdgpu: send msg to IMU for the front-door loading
>
>
>
>
>
>> -Original Message-
>> From: amd-gfx  On Behalf Of 
>> Xiaojian Du
>> Sent: Thursday, July 28, 2022 3:04 PM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Deucher, Alexander ; Huang, Tim 
>> ; Du, Xiaojian ; Zhang, Yifan 
>> 
>> Subject: [PATCH 1/5] drm/amdgpu: send msg to IMU for the front-door 
>> loading
>> 
>> This patch will make SMU send msg to IMU for the front-door loading, 
>> it is required by some ASICs.
>> 
>> Signed-off-by: Yifan Zhang 
>> Signed-off-by: Xiaojian Du 
>> ---
>>  drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 8 
>>  1 file changed, 8 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> index 6d9b3c6af164..79c01fa4b875 100644
>> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> @@ -1360,6 +1360,14 @@ static int smu_hw_init(void *handle)
>>  return ret;
>>  }
>> 
>> +if (smu->ppt_funcs->set_gfx_power_up_by_imu) {
>> +ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
>> +if (ret) {
>> +dev_err(adev->dev, "Failed to Enable gfx imu!\n");
>> +return ret;
>> +}
>> +}
>[Quan, Evan] Per my understandings, this should be needed by APU only. Can you 
>move this under "smu->is_apu" control as other features below?
>
>Evan
>> +
>>  if (smu->is_apu) {
>>  smu_dpm_set_vcn_enable(smu, true);
>>  smu_dpm_set_jpeg_enable(smu, true);
>> --
>> 2.25.1
>

RE: [PATCH 1/5] drm/amdgpu: send msg to IMU for the front-door loading

2022-07-28 Thread Quan, Evan

[AMD Official Use Only - General]



> -Original Message-
> From: amd-gfx  On Behalf Of
> Xiaojian Du
> Sent: Thursday, July 28, 2022 3:04 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Tim
> ; Du, Xiaojian ; Zhang, Yifan
> 
> Subject: [PATCH 1/5] drm/amdgpu: send msg to IMU for the front-door
> loading
> 
> This patch will make SMU send msg to IMU for the front-door loading, it is
> required by some ASICs.
> 
> Signed-off-by: Yifan Zhang 
> Signed-off-by: Xiaojian Du 
> ---
>  drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 6d9b3c6af164..79c01fa4b875 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -1360,6 +1360,14 @@ static int smu_hw_init(void *handle)
>   return ret;
>   }
> 
> + if (smu->ppt_funcs->set_gfx_power_up_by_imu) {
> + ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
> + if (ret) {
> + dev_err(adev->dev, "Failed to Enable gfx imu!\n");
> + return ret;
> + }
> + }
[Quan, Evan] Per my understandings, this should be needed by APU only. Can you 
move this under "smu->is_apu" control as other features below?

Evan
> +
>   if (smu->is_apu) {
>   smu_dpm_set_vcn_enable(smu, true);
>   smu_dpm_set_jpeg_enable(smu, true);
> --
> 2.25.1

[PATCH 5/5] drm/amdgpu: enable support for psp 13.0.4 block

2022-07-28 Thread Xiaojian Du

This patch will enable support for psp 13.0.4 blcok.

Signed-off-by: Xiaojian Du 
---
 drivers/gpu/drm/amd/amdgpu/Makefile   |  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c |  4 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c   | 13 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h   |  1 +
 4 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index c7d0cd15b5ef..5a283d12f8e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -115,7 +115,8 @@ amdgpu-y += \
psp_v11_0.o \
psp_v11_0_8.o \
psp_v12_0.o \
-   psp_v13_0.o
+   psp_v13_0.o \
+   psp_v13_0_4.o
 
 # add DCE block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 242d1847c4aa..95d34590cad1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1630,12 +1630,14 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct 
amdgpu_device *adev)
case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 2):
case IP_VERSION(13, 0, 3):
-   case IP_VERSION(13, 0, 4):
case IP_VERSION(13, 0, 5):
case IP_VERSION(13, 0, 7):
case IP_VERSION(13, 0, 8):
amdgpu_device_ip_block_add(adev, _v13_0_ip_block);
break;
+   case IP_VERSION(13, 0, 4):
+   amdgpu_device_ip_block_add(adev, _v13_0_4_ip_block);
+   break;
default:
dev_err(adev->dev,
"Failed to add psp ip block(MP0_HWIP:0x%x)\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 3ee363bfbac2..bf41374e3ea0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -37,6 +37,7 @@
 #include "psp_v11_0_8.h"
 #include "psp_v12_0.h"
 #include "psp_v13_0.h"
+#include "psp_v13_0_4.h"
 
 #include "amdgpu_ras.h"
 #include "amdgpu_securedisplay.h"
@@ -151,6 +152,10 @@ static int psp_early_init(void *handle)
psp_v13_0_set_psp_funcs(psp);
psp->autoload_supported = true;
break;
+   case IP_VERSION(13, 0, 4):
+   psp_v13_0_4_set_psp_funcs(psp);
+   psp->autoload_supported = true;
+   break;
default:
return -EINVAL;
}
@@ -3692,3 +3697,11 @@ const struct amdgpu_ip_block_version psp_v13_0_ip_block 
= {
.rev = 0,
.funcs = _ip_funcs,
 };
+
+const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
+   .type = AMD_IP_BLOCK_TYPE_PSP,
+   .major = 13,
+   .minor = 0,
+   .rev = 4,
+   .funcs = _ip_funcs,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 180634616b0f..c32b74bd970f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -439,6 +439,7 @@ extern const struct amdgpu_ip_block_version 
psp_v11_0_ip_block;
 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block;
 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
+extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;
 
 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
uint32_t field_val, uint32_t mask, bool check_changed);
-- 
2.25.1

[PATCH 4/5] drm/amdgpu: add files for PSP 13.0.4

2022-07-28 Thread Xiaojian Du

This patch will add files for PSP 13.0.4.

Signed-off-by: Xiaojian Du 
---
 drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c | 387 +++
 drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.h |  30 ++
 2 files changed, 417 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.h

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c
new file mode 100644
index ..321089dfa7db
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c
@@ -0,0 +1,387 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "amdgpu_psp.h"
+#include "amdgpu_ucode.h"
+#include "soc15_common.h"
+#include "psp_v13_0_4.h"
+
+#include "mp/mp_13_0_4_offset.h"
+#include "mp/mp_13_0_4_sh_mask.h"
+
+MODULE_FIRMWARE("amdgpu/psp_13_0_4_toc.bin");
+MODULE_FIRMWARE("amdgpu/psp_13_0_4_ta.bin");
+
+static int psp_v13_0_4_init_microcode(struct psp_context *psp)
+{
+   struct amdgpu_device *adev = psp->adev;
+   const char *chip_name;
+   char ucode_prefix[30];
+   int err = 0;
+
+   switch (adev->ip_versions[MP0_HWIP][0]) {
+   case IP_VERSION(13, 0, 4):
+   amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, 
sizeof(ucode_prefix));
+   chip_name = ucode_prefix;
+   break;
+   default:
+   BUG();
+   }
+
+   switch (adev->ip_versions[MP0_HWIP][0]) {
+   case IP_VERSION(13, 0, 4):
+   err = psp_init_toc_microcode(psp, chip_name);
+   if (err)
+   return err;
+   err = psp_init_ta_microcode(psp, chip_name);
+   if (err)
+   return err;
+   break;
+   default:
+   BUG();
+   }
+
+   return 0;
+}
+
+static bool psp_v13_0_4_is_sos_alive(struct psp_context *psp)
+{
+   struct amdgpu_device *adev = psp->adev;
+   uint32_t sol_reg;
+
+   sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
+
+   return sol_reg != 0x0;
+}
+
+static int psp_v13_0_4_wait_for_bootloader(struct psp_context *psp)
+{
+   struct amdgpu_device *adev = psp->adev;
+
+   int ret;
+   int retry_loop;
+
+   for (retry_loop = 0; retry_loop < 10; retry_loop++) {
+   /* Wait for bootloader to signify that is
+   ready having bit 31 of C2PMSG_35 set to 1 */
+   ret = psp_wait_for(psp,
+  SOC15_REG_OFFSET(MP0, 0, 
regMP0_SMN_C2PMSG_35),
+  0x8000,
+  0x8000,
+  false);
+
+   if (ret == 0)
+   return 0;
+   }
+
+   return ret;
+}
+
+static int psp_v13_0_4_bootloader_load_component(struct psp_context*psp,
+  struct psp_bin_desc  
*bin_desc,
+  enum psp_bootloader_cmd  bl_cmd)
+{
+   int ret;
+   uint32_t psp_gfxdrv_command_reg = 0;
+   struct amdgpu_device *adev = psp->adev;
+
+   /* Check tOS sign of life register to confirm sys driver and sOS
+* are already been loaded.
+*/
+   if (psp_v13_0_4_is_sos_alive(psp))
+   return 0;
+
+   ret = psp_v13_0_4_wait_for_bootloader(psp);
+   if (ret)
+   return ret;
+
+   memset(psp->fw_pri_buf, 0, PSP_1_MEG);
+
+   /* Copy PSP KDB binary to memory */
+   memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
+
+   /* Provide the PSP KDB to bootloader */
+   WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
+  (uint32_t)(psp->fw_pri_mc_addr >> 20));
+   psp_gfxdrv_command_reg = bl_cmd;
+   WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
+

[PATCH 1/5] drm/amdgpu: send msg to IMU for the front-door loading

2022-07-28 Thread Xiaojian Du

This patch will make SMU send msg to IMU for the front-door loading, it is
required by some ASICs.

Signed-off-by: Yifan Zhang 
Signed-off-by: Xiaojian Du 
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 6d9b3c6af164..79c01fa4b875 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1360,6 +1360,14 @@ static int smu_hw_init(void *handle)
return ret;
}
 
+   if (smu->ppt_funcs->set_gfx_power_up_by_imu) {
+   ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
+   if (ret) {
+   dev_err(adev->dev, "Failed to Enable gfx imu!\n");
+   return ret;
+   }
+   }
+
if (smu->is_apu) {
smu_dpm_set_vcn_enable(smu, true);
smu_dpm_set_jpeg_enable(smu, true);
-- 
2.25.1

[PATCH 3/5] drm/amdgpu: add header files for MP 13.0.4

2022-07-28 Thread Xiaojian Du

This patch will add header files for MP 13.0.4.

Signed-off-by: Xiaojian Du 
---
 .../include/asic_reg/mp/mp_13_0_4_offset.h| 402 
 .../include/asic_reg/mp/mp_13_0_4_sh_mask.h   | 595 ++
 2 files changed, 997 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_4_offset.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_4_sh_mask.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_4_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_4_offset.h
new file mode 100644
index ..82312ecc0216
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_4_offset.h
@@ -0,0 +1,402 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+#ifndef _mp_13_0_4_OFFSET_HEADER
+#define _mp_13_0_4_OFFSET_HEADER
+
+
+
+// addressBlock: mp_SmuMp0_SmnDec
+// base address: 0x0
+#define regMP0_SMN_C2PMSG_32   
 0x0060
+#define regMP0_SMN_C2PMSG_32_BASE_IDX  
 1
+#define regMP0_SMN_C2PMSG_33   
 0x0061
+#define regMP0_SMN_C2PMSG_33_BASE_IDX  
 1
+#define regMP0_SMN_C2PMSG_34   
 0x0062
+#define regMP0_SMN_C2PMSG_34_BASE_IDX  
 1
+#define regMP0_SMN_C2PMSG_35   
 0x0063
+#define regMP0_SMN_C2PMSG_35_BASE_IDX  
 1
+#define regMP0_SMN_C2PMSG_36   
 0x0064
+#define regMP0_SMN_C2PMSG_36_BASE_IDX  
 1
+#define regMP0_SMN_C2PMSG_37   
 0x0065
+#define regMP0_SMN_C2PMSG_37_BASE_IDX  
 1
+#define regMP0_SMN_C2PMSG_38   
 0x0066
+#define regMP0_SMN_C2PMSG_38_BASE_IDX  
 1
+#define regMP0_SMN_C2PMSG_39   
 0x0067
+#define regMP0_SMN_C2PMSG_39_BASE_IDX  
 1
+#define regMP0_SMN_C2PMSG_40   
 0x0068
+#define regMP0_SMN_C2PMSG_40_BASE_IDX  
 1
+#define regMP0_SMN_C2PMSG_41   
 0x0069
+#define regMP0_SMN_C2PMSG_41_BASE_IDX  
 1
+#define regMP0_SMN_C2PMSG_42   
 0x006a
+#define regMP0_SMN_C2PMSG_42_BASE_IDX  
 1
+#define regMP0_SMN_C2PMSG_43   
 0x006b
+#define regMP0_SMN_C2PMSG_43_BASE_IDX  
 1
+#define regMP0_SMN_C2PMSG_44   
 0x006c
+#define regMP0_SMN_C2PMSG_44_BASE_IDX  
 1
+#define regMP0_SMN_C2PMSG_45   
 0x006d
+#define

[PATCH 2/5] drm/amdgpu: correct RLC_RLCS_BOOTLOAD_STATUS offset and index

2022-07-28 Thread Xiaojian Du

This patch corrects RLC_RLCS_BOOTLOAD_STATUS offset and index for
GC 11.0.1.

Signed-off-by: Yifan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 0d8193b30fc5..6fd71cb10e54 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -56,6 +56,8 @@
 
 #define regCGTT_WD_CLK_CTRL0x5086
 #define regCGTT_WD_CLK_CTRL_BASE_IDX   1
+#define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1  0x4e7e
+#define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1
 
 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin");
@@ -2765,7 +2767,13 @@ static int 
gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
 
for (i = 0; i < adev->usec_timeout; i++) {
cp_status = RREG32_SOC15(GC, 0, regCP_STAT);
-   bootload_status = RREG32_SOC15(GC, 0, 
regRLC_RLCS_BOOTLOAD_STATUS);
+
+   if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1))
+   bootload_status = RREG32_SOC15(GC, 0,
+   regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1);
+   else
+   bootload_status = RREG32_SOC15(GC, 0, 
regRLC_RLCS_BOOTLOAD_STATUS);
+
if ((cp_status == 0) &&
(REG_GET_FIELD(bootload_status,
RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
-- 
2.25.1

Re: [PATCH v2] drm/ttm: Fix dummy res NULL ptr deref bug

2022-07-28 Thread Arunpravin Paneer Selvam


Hi Andre,

On 7/27/2022 8:56 PM, André Almeida wrote:

Hi Arunpravin,

Às 02:30 de 27/07/22, Arunpravin Paneer Selvam escreveu:

Check the bo->resource value before accessing the resource
mem_type.

v2: Fix commit description unwrapped warning


[   40.191227][  T184] general protection fault, probably for non-canonical 
address 0xdc02:  [#1] SMP KASAN PTI
[   40.192995][  T184] KASAN: null-ptr-deref in range 
[0x0010-0x0017]
[   40.194411][  T184] CPU: 1 PID: 184 Comm: systemd-udevd Not tainted 
5.19.0-rc4-00721-gb297c22b7070 #1
[   40.196063][  T184] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), 
BIOS 1.16.0-debian-1.16.0-4 04/01/2014
[   40.199605][  T184] RIP: 0010:ttm_bo_validate+0x1b3/0x240 [ttm]
[   40.200754][  T184] Code: e8 72 c5 ff ff 83 f8 b8 74 d4 85 c0 75 54 49 8b 9e 58 01 
00 00 48 b8 00 00 00 00 00 fc ff df 48 8d 7b 10 48 89 fa 48 c1 ea 03 <0f> b6 04 
02 84 c0 74 04 3c 03 7e 44 8b 53 10 31 c0 85 d2 0f 85 58
[   40.203685][  T184] RSP: 0018:c96df0c8 EFLAGS: 00010202
[   40.204630][  T184] RAX: dc00 RBX:  RCX: 
11102f4bb71b
[   40.205864][  T184] RDX: 0002 RSI: c96df208 RDI: 
0010
[   40.207102][  T184] RBP: 192dbe1a R08: c96df208 R09: 

[   40.208394][  T184] R10: 88817a5f R11: 0001 R12: 
c96df110
[   40.209692][  T184] R13: c96df0f0 R14: 88817a5db800 R15: 
c96df208
[   40.210862][  T184] FS:  7f6b1d16e8c0() GS:88839d70() 
knlGS:
[   40.212250][  T184] CS:  0010 DS:  ES:  CR0: 80050033
[   40.213275][  T184] CR2: 55a1001d4ff0 CR3: 0001700f4000 CR4: 
06e0
[   40.214469][  T184] Call Trace:
[   40.214974][  T184]  
[   40.215438][  T184]  ? ttm_bo_bounce_temp_buffer+0x140/0x140 [ttm]
[   40.216572][  T184]  ? mutex_spin_on_owner+0x240/0x240
[   40.217456][  T184]  ? drm_vma_offset_add+0xaa/0x100 [drm]
[   40.218457][  T184]  ttm_bo_init_reserved+0x3d6/0x540 [ttm]
[   40.219410][  T184]  ? shmem_get_inode+0x744/0x980
[   40.220231][  T184]  ttm_bo_init_validate+0xb1/0x200 [ttm]
[   40.221172][  T184]  ? bo_driver_evict_flags+0x340/0x340 [drm_vram_helper]
[   40.222530][  T184]  ? ttm_bo_init_reserved+0x540/0x540 [ttm]
[   40.223643][  T184]  ? __do_sys_finit_module+0x11a/0x1c0
[   40.224654][  T184]  ? __shmem_file_setup+0x102/0x280
[   40.234764][  T184]  drm_gem_vram_create+0x305/0x480 [drm_vram_helper]
[   40.235766][  T184]  ? bo_driver_evict_flags+0x340/0x340 [drm_vram_helper]
[   40.236846][  T184]  ? __kasan_slab_free+0x108/0x180
[   40.237650][  T184]  drm_gem_vram_fill_create_dumb+0x134/0x340 
[drm_vram_helper]
[   40.238864][  T184]  ? local_pci_probe+0xdf/0x180
[   40.239674][  T184]  ? drmm_vram_helper_init+0x400/0x400 [drm_vram_helper]
[   40.240826][  T184]  drm_client_framebuffer_create+0x19c/0x400 [drm]
[   40.241955][  T184]  ? drm_client_buffer_delete+0x200/0x200 [drm]
[   40.243001][  T184]  ? drm_client_pick_crtcs+0x554/0xb80 [drm]
[   40.244030][  T184]  drm_fb_helper_generic_probe+0x23f/0x940 [drm_kms_helper]
[   40.245226][  T184]  ? __cond_resched+0x1c/0xc0
[   40.245987][  T184]  ? drm_fb_helper_memory_range_to_clip+0x180/0x180 
[drm_kms_helper]
[   40.247316][  T184]  ? mutex_unlock+0x80/0x100
[   40.248005][  T184]  ? __mutex_unlock_slowpath+0x2c0/0x2c0
[   40.249083][  T184]  drm_fb_helper_single_fb_probe+0x907/0xf00 
[drm_kms_helper]
[   40.250314][  T184]  ? drm_fb_helper_check_var+0x1180/0x1180 [drm_kms_helper]
[   40.251540][  T184]  ? __cond_resched+0x1c/0xc0
[   40.252321][  T184]  ? mutex_lock+0x9f/0x100
[   40.253062][  T184]  __drm_fb_helper_initial_config_and_unlock+0xb9/0x2c0 
[drm_kms_helper]
[   40.254394][  T184]  drm_fbdev_client_hotplug+0x56f/0x840 [drm_kms_helper]
[   40.255477][  T184]  drm_fbdev_generic_setup+0x165/0x3c0 [drm_kms_helper]
[   40.256607][  T184]  bochs_pci_probe+0x6b7/0x900 [bochs]
[   40.257515][  T184]  ? _raw_spin_lock_irqsave+0x87/0x100
[   40.258312][  T184]  ? bochs_hw_init+0x480/0x480 [bochs]
[   40.259244][  T184]  ? bochs_hw_init+0x480/0x480 [bochs]
[   40.260186][  T184]  local_pci_probe+0xdf/0x180
[   40.260928][  T184]  pci_call_probe+0x15f/0x500
[   40.265798][  T184]  ? _raw_spin_lock+0x81/0x100
[   40.266508][  T184]  ? pci_pm_suspend_noirq+0x980/0x980
[   40.267322][  T184]  ? pci_assign_irq+0x81/0x280
[   40.268096][  T184]  ? pci_match_device+0x351/0x6c0
[   40.268883][  T184]  ? kernfs_put+0x18/0x40
[   40.269611][  T184]  pci_device_probe+0xee/0x240
[   40.270352][  T184]  really_probe+0x435/0xa80
[   40.271021][  T184]  __driver_probe_device+0x2ab/0x480
[   40.271828][  T184]  driver_probe_device+0x49/0x140
[   40.272627][  T184]  __driver_attach+0x1bd/0x4c0
[   40.273372][  T184]  ? __device_attach_driver+0x240/0x240
[   40.274273][  T184]  bus_for_each_dev+0x11e/0x1c0
[   40.275080][  T184]  ? subsys_dev_iter_exit+0x40/0x40
[   40.275951][

Fwd: [drm-tip:drm-tip 4/8] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1565:27: error: 'drm_primary_helper_destroy' undeclared here (not in a function); did you mean 'drm_plane_h

2022-07-28 Thread Thomas Zimmermann


Forwarding this to amd-gfx


 Weitergeleitete Nachricht 
Betreff: [drm-tip:drm-tip 4/8] 
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1565:27: 
error: 'drm_primary_helper_destroy' undeclared here (not in a function); 
did you mean 'drm_plane_helper_destroy'?

Datum: Thu, 28 Jul 2022 14:10:58 +0800
Von: kernel test robot 
An: Thomas Zimmermann 
Kopie (CC): intel-...@lists.freedesktop.org, kbuild-...@lists.01.org, 
dri-de...@lists.freedesktop.org


Hi Thomas,

First bad commit (maybe != root cause):

tree:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
head:   df865a97749db8fbb9ec3491f34bf40771ce1f7b
commit: 9c7f5cf088789957dcfb460cca1ab0fb578f2376 [4/8] Merge 
remote-tracking branch 'drm-misc/drm-misc-next' into drm-tip
config: alpha-randconfig-r003-20220728 
(https://download.01.org/0day-ci/archive/20220728/202207281420.mnf0xrnj-...@intel.com/config)

compiler: alpha-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross 
-O ~/bin/make.cross

chmod +x ~/bin/make.cross
git remote add drm-tip git://anongit.freedesktop.org/drm/drm-tip
git fetch --no-tags drm-tip drm-tip
git checkout 9c7f5cf088789957dcfb460cca1ab0fb578f2376
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross 
W=1 O=build_dir ARCH=alpha SHELL=/bin/bash drivers/gpu/drm/


If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot 

All errors (new ones prefixed by >>):


drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:83:31: 
warning: no previous prototype for 'amd_get_format_info' 
[-Wmissing-prototypes]
  83 | const struct drm_format_info *amd_get_format_info(const 
struct drm_mode_fb_cmd2 *cmd)

 |   ^~~

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:88:6: 
warning: no previous prototype for 'fill_blending_from_plane_state' 
[-Wmissing-prototypes]
  88 | void fill_blending_from_plane_state(const struct 
drm_plane_state *plane_state,

 |  ^~

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:152:6: 
warning: no previous prototype for 'modifier_has_dcc' [-Wmissing-prototypes]

 152 | bool modifier_has_dcc(uint64_t modifier)
 |  ^~~~

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:157:10: warning: 
no previous prototype for 'modifier_gfx9_swizzle_mode' 
[-Wmissing-prototypes]

 157 | unsigned modifier_gfx9_swizzle_mode(uint64_t modifier)
 |  ^~

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:752:5: 
warning: no previous prototype for 'fill_plane_buffer_attributes' 
[-Wmissing-prototypes]

 752 | int fill_plane_buffer_attributes(struct amdgpu_device *adev,
 | ^~~~

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:992:5: 
warning: no previous prototype for 'dm_plane_helper_check_state' 
[-Wmissing-prototypes]

 992 | int dm_plane_helper_check_state(struct drm_plane_state *state,
 | ^~~

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1046:5: warning: 
no previous prototype for 'fill_dc_scaling_info' [-Wmissing-prototypes]

1046 | int fill_dc_scaling_info(struct amdgpu_device *adev,
 | ^~~~

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1222:6: warning: 
no previous prototype for 'handle_cursor_update' [-Wmissing-prototypes]

1222 | void handle_cursor_update(struct drm_plane *plane,
 |  ^~~~

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1565:27: 
error: 'drm_primary_helper_destroy' undeclared here (not in a function); did 
you mean 'drm_plane_helper_destroy'?

1565 | .destroy= drm_primary_helper_destroy,
 |   ^~
 |   drm_plane_helper_destroy

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1576:5: warning: 
no previous prototype for 'amdgpu_dm_plane_init' [-Wmissing-prototypes]

1576 | int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
 | ^~~~
   In file included from 
drivers/gpu/drm/amd/amdgpu/../display/dc/inc/core_types.h:32,
from 
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_trace.h:41,
from 
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:36:


drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:137:22: warning: 
'SYNAPTICS_DEVICE_ID' defined but not used [-Wunused-const-variable=]

 137 | static

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