On 03/23/2017 09:07 PM, Nicolai Hähnle wrote:
Hi Jerry,
On 23.03.2017 03:26, Zhang, Jerry (Junwei) wrote:
On 03/22/2017 11:06 PM, Nicolai Hähnle wrote:
Hi all,
there's a bit of a puzzle where I'm wondering whether there's a subtle
bug in
the amdgpu kernel module.
Basically, the concern
On 03/24/2017 03:27 AM, Nicolai Hähnle wrote:
From: Nicolai Hähnle
Also, add the fence of the clear operations to the BO to ensure that
the underlying memory can only be re-used after all PTEs pointing to
it have been cleared.
This avoids the following sequence of
On 03/24/2017 11:42 AM, Zhang, Jerry (Junwei) wrote:
On 03/24/2017 03:27 AM, Nicolai Hähnle wrote:
From: Nicolai Hähnle <nicolai.haeh...@amd.com>
Also, add the fence of the clear operations to the BO to ensure that
the underlying memory can only be re-used after all PTEs pointing to
i
On 03/24/2017 10:30 AM, zhoucm1 wrote:
On 2017年03月24日 03:27, Nicolai Hähnle wrote:
From: Nicolai Hähnle
We will add the fence to freed buffer objects in a later commit, to ensure
that the underlying memory can only be re-used after all references in
page tables have
On 03/24/2017 06:38 PM, Monk Liu wrote:
for SRIOV we cannot use access register when in IRQ routine
with regular KIQ method
Change-Id: Ifae3164cf12311b851ae131f58175f6ec3174f82
Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 24
On 03/27/2017 02:39 PM, Christian König wrote:
Am 27.03.2017 um 03:51 schrieb Zhang, Jerry (Junwei):
On 03/24/2017 06:38 PM, Monk Liu wrote:
for SRIOV we cannot use access register when in IRQ routine
with regular KIQ method
Change-Id: Ifae3164cf12311b851ae131f58175f6ec3174f82
Signed-off
On 03/22/2017 11:06 PM, Nicolai Hähnle wrote:
Hi all,
there's a bit of a puzzle where I'm wondering whether there's a subtle bug in
the amdgpu kernel module.
Basically, the concern is that a buggy user space driver might trigger a
sequence like this:
1. Submit a CS that accesses some BO
Hi Alex,
I remember we had a patch to remove the FB location programming in gmc/vmhub.
I saw it's not in gmc v9 in this patch, but pre-gmcv9 still program FB register.
Is that any missing for sync here?
Or it's only supported for gmc v9 now.
Jerry
On 03/21/2017 04:29 AM, Alex Deucher wrote:
On 03/30/2017 02:07 AM, Felix Kuehling wrote:
On 17-03-29 01:40 PM, Christian König wrote:
Am 29.03.2017 um 19:22 schrieb Felix Kuehling:
Fix the start/end address calculation for address ranges that span
multiple page directories in amdgpu_vm_alloc_levels.
Add error messages if page tables
On 03/29/2017 11:24 PM, Deucher, Alexander wrote:
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Junwei Zhang
Sent: Wednesday, March 29, 2017 3:19 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Jerry
Subject: [PATCH v2] drm/amdgpu: fix vm
On 03/29/2017 09:00 AM, Felix Kuehling wrote:
Fix the start/end address calculation for address ranges that span
multiple page directories in amdgpu_vm_alloc_levels.
Add WARN_ONs if page tables aren't found. Otherwise the page table
update would just fail silently.
Signed-off-by: Felix
On 03/29/2017 02:00 PM, Zhang, Jerry (Junwei) wrote:
On 03/29/2017 09:00 AM, Felix Kuehling wrote:
I worked on these fixes on amd-kfd-staging with a merge of the recent multi-
level page table changes. With these changes KFDTest passes on Vega10,
including some tests that tend to stress VM
On 03/29/2017 02:52 PM, Christian König wrote:
Am 29.03.2017 um 07:58 schrieb Zhang, Jerry (Junwei):
Hi Felix,
Thanks for your illustration with patience.
I got your meaning then, and thanks to fix that.
> I think you're right, there are some extra high bits in saddr and eaddr, but
> th
On 03/29/2017 02:47 PM, Christian König wrote:
Am 29.03.2017 um 03:48 schrieb Felix Kuehling:
On 17-03-28 09:39 PM, Zhang, Jerry (Junwei) wrote:
On 03/29/2017 09:00 AM, Felix Kuehling wrote:
adev->family is not initialized yet when amdgpu_get_block_size is
called. Use adev->asic_type i
On 03/28/2017 06:06 PM, Christian König wrote:
Am 28.03.2017 um 10:55 schrieb Junwei Zhang:
Signed-off-by: Junwei Zhang
Good catch, patch is Reviewed-by: Christian König .
It doesn't matter for older versions because they don't have flags in
On 03/29/2017 09:00 AM, Felix Kuehling wrote:
I worked on these fixes on amd-kfd-staging with a merge of the recent multi-
level page table changes. With these changes KFDTest passes on Vega10,
including some tests that tend to stress VM memory management.
They applied cleanly to current
Vega10 VM fault handling
On 17-03-27 09:23 PM, Zhang, Jerry (Junwei) wrote:
>
>
> On 03/28/2017 06:25 AM, Felix Kuehling wrote:
>> Register AMDGPU_IH_CLIENTID_UTCL2 as a source of VM faults. Clean
>> up the VM fault message format and use rate-limiting similar to
>> ot
On 03/28/2017 05:27 PM, Jim Qu wrote:
1. security firmware loading has moved to sw init, so this code
is useless.
2. it seems that driver could not call request_firmware on
kernel 2.6, when S3 resume. for request firmware depends on
userspace, at this time, userspace is freeze.
On 03/29/2017 02:37 AM, Alex Xie wrote:
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c:187:2: warning: right shift count >=
width of type [enabled by default]
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:173:2: warning: right shift count >=
width of type [enabled by default]
On 03/29/2017 09:48 AM, Felix Kuehling wrote:
On 17-03-28 09:39 PM, Zhang, Jerry (Junwei) wrote:
On 03/29/2017 09:00 AM, Felix Kuehling wrote:
adev->family is not initialized yet when amdgpu_get_block_size is
called. Use adev->asic_type instead.
Minimum VM size is 512GB, not
On 03/27/2017 01:53 PM, Chunming Zhou wrote:
From: Christian König
Allows us to get the size for all levels as well.
Change-Id: Iaf2f9b2bf19c3623018a2215f8cf01a61bdbe8ea
Signed-off-by: Christian König
Reviewed-by: Alex Deucher
On 03/28/2017 12:05 AM, Deucher, Alexander wrote:
-Original Message-
From: Koenig, Christian
Sent: Monday, March 27, 2017 5:37 AM
To: Zhou, David(ChunMing); amd-gfx@lists.freedesktop.org; Deucher,
Alexander
Subject: Re: [PATCH 00/15] *** Multiple level VMPT enablement ***
Hi David,
On 03/28/2017 06:25 AM, Felix Kuehling wrote:
Register AMDGPU_IH_CLIENTID_UTCL2 as a source of VM faults. Clean
up the VM fault message format and use rate-limiting similar to
other ASICs.
Signed-off-by: Felix Kuehling
May be better to split it into 2 patches
On 03/27/2017 09:44 PM, Christian König wrote:
From: Christian König
Follow up to 'drm: don't access deprecated register on Vega10'.
The same information is available in enabled_rb_pipes_mask and reading that
register can cause GRBM bus problems.
Signed-off-by:
On 03/28/2017 11:46 AM, Chunming Zhou wrote:
Change-Id: I9d764e6e6cf214e64bd79435a8bbb4063260dc11
Signed-off-by: Chunming Zhou
Reviewed-by: Junwei Zhang
For the minimum size, PD is 0
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8
1 file
On 03/21/2017 09:30 PM, Nicolai Hähnle wrote:
This should use the proper procedure for updating amdgpu_drm.h, as explained in
include/drm/README. I can take care of this as soon as all the kernel patches
for PRT are in a tree that doesn't rebase (i.e. agd5f/drm-next-4.12 or
airlied/drm-next).
On 04/04/2017 03:23 AM, Alex Deucher wrote:
On Mon, Apr 3, 2017 at 8:39 AM, Christian König wrote:
From: Christian König
Match our defines with what the hw uses.
Signed-off-by: Christian König
Patches 1-4, 6-7:
On 04/04/2017 07:02 AM, Harry Wentland wrote:
Reviewed-by: Harry Wentland
Reviewed-by: Junwei Zhang
On 2017-04-03 04:58 PM, Alex Deucher wrote:
vega10 is the only soc15 asic at the moment so these
warnings are invalid, but add a default case
On 04/04/2017 03:34 AM, Deucher, Alexander wrote:
-Original Message-
From: Junwei Zhang [mailto:jerry.zh...@amd.com]
Sent: Friday, March 31, 2017 10:44 PM
To: Deucher, Alexander; Koenig, Christian
Cc: amd-gfx@lists.freedesktop.org; Zhang, Jerry
Subject: [PATCH] drm/amdgpu: fix vm size
On 04/05/2017 10:27 AM, Alex Deucher wrote:
On Tue, Apr 4, 2017 at 10:11 PM, Zhang, Jerry (Junwei)
<jerry.zh...@amd.com> wrote:
On 04/04/2017 03:34 AM, Deucher, Alexander wrote:
-Original Message-
From: Junwei Zhang [mailto:jerry.zh...@amd.com]
Sent: Friday, March 31, 2017 10
On 03/31/2017 12:05 PM, Deucher, Alexander wrote:
-Original Message-
From: Junwei Zhang [mailto:jerry.zh...@amd.com]
Sent: Thursday, March 30, 2017 10:52 PM
To: Deucher, Alexander; Koenig, Christian
Cc: amd-gfx@lists.freedesktop.org; Zhang, Jerry
Subject: [PATCH 1/2 v2] drm/amdgpu: fix
On 04/07/2017 04:44 PM, Christian König wrote:
From: Christian König
The offset must be 64bit and add back the accidential dropped line.
Signed-off-by: Christian König
Reviewed-by: Junwei Zhang
---
Thanks you all for the comments
Updated the v2, please help review
On 04/05/2017 09:39 PM, Christian König wrote:
Am 05.04.2017 um 15:32 schrieb Alex Deucher:
On Wed, Apr 5, 2017 at 5:01 AM, Christian König wrote:
Am 05.04.2017 um 08:43 schrieb Junwei Zhang:
By
On 04/18/2017 10:47 AM, zhoucm1 wrote:
On 2017年04月18日 09:51, Zhang, Jerry (Junwei) wrote:
Anyone could help to review it?
On 04/17/2017 05:04 PM, Junwei Zhang wrote:
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +
drivers/g
On 04/20/2017 01:49 PM, Zhang, Jerry (Junwei) wrote:
On 04/19/2017 10:07 PM, Christian König wrote:
From: Christian König <christian.koe...@amd.com>
Use amdgpu_vm_bo_update_mapping() instead of amdgpu_vm_bo_split_mapping() here.
We don't want any flags set in the cleared areas and spl
On 04/19/2017 10:07 PM, Christian König wrote:
From: Christian König
Use amdgpu_vm_bo_update_mapping() instead of amdgpu_vm_bo_split_mapping() here.
We don't want any flags set in the cleared areas and splitting
should be unnecessary.
Yeah, the mappings in the
On 04/19/2017 07:40 PM, Christian König wrote:
Am 19.04.2017 um 10:10 schrieb Zhang, Jerry (Junwei):
On 04/19/2017 03:28 PM, Christian König wrote:
Am 19.04.2017 um 03:53 schrieb Junwei Zhang:
v2: unify PRT bit for all ASICs
Signed-off-by: Junwei Zhang <jerry.zh...@amd.com>
Acked-by:
On 04/07/2017 03:56 AM, Alex Xie wrote:
warning: comparison of distinct pointer types lacks a cast
Thanks for your patch.
I have fixed it.
Please check in our branch.
Jerry
Change-Id: I317eddd1bd430c98a3c50ec170f592f944081a6e
Signed-off-by: Alex Xie
---
On 04/06/2017 03:31 PM, Monk Liu wrote:
should use kernel parm to judge instead of adev member,
which hasn't been set at that time
Change-Id: I58c83a8615cd4a54440c9de038e45bb70802cc2c
Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
1 file changed, 1
On 03/29/2017 10:27 PM, Christian König wrote:
Am 29.03.2017 um 16:17 schrieb Alex Deucher:
On Wed, Mar 29, 2017 at 4:47 AM, Christian König
wrote:
Am 29.03.2017 um 10:08 schrieb Junwei Zhang:
Signed-off-by: Junwei Zhang
---
Anyone could help to review it?
On 04/17/2017 05:04 PM, Junwei Zhang wrote:
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
3 files changed,
On 04/19/2017 03:28 PM, Christian König wrote:
Am 19.04.2017 um 03:53 schrieb Junwei Zhang:
v2: unify PRT bit for all ASICs
Signed-off-by: Junwei Zhang
Acked-by: David Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +
On 04/18/2017 07:25 PM, Nicolai Hähnle wrote:
On 18.04.2017 05:13, Zhang, Jerry (Junwei) wrote:
On 04/18/2017 10:47 AM, zhoucm1 wrote:
On 2017年04月18日 09:51, Zhang, Jerry (Junwei) wrote:
Anyone could help to review it?
On 04/17/2017 05:04 PM, Junwei Zhang wrote:
Signed-off-by: Junwei
On 04/19/2017 11:50 AM, Chunming Zhou wrote:
Change-Id: Ifea42c8ae2206143d7e22b35eea537ba9e928fe8
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 13 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 --
2 files changed,
On 07/31/2017 01:57 PM, Huang Rui wrote:
On Fri, Jul 28, 2017 at 05:11:18PM +0800, Junwei Zhang wrote:
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 17 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 22 ++
2
On 07/31/2017 04:41 PM, Huang Rui wrote:
On Mon, Jul 31, 2017 at 04:10:10PM +0800, Zhang, Jerry wrote:
On 07/31/2017 01:57 PM, Huang Rui wrote:
On Fri, Jul 28, 2017 at 05:11:18PM +0800, Junwei Zhang wrote:
Signed-off-by: Junwei Zhang
---
+ sta...@vger.kernel.org
On 07/17/2017 03:57 PM, Huang Rui wrote:
On Mon, Jul 17, 2017 at 03:52:10PM +0800, Huang Rui wrote:
On Fri, Jul 14, 2017 at 06:20:17PM +0800, Junwei Zhang wrote:
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +--
On 07/17/2017 07:45 PM, Huang Rui wrote:
On Mon, Jul 17, 2017 at 06:57:41PM +0800, Greg KH wrote:
On Mon, Jul 17, 2017 at 04:56:26PM +0800, Zhang, Jerry (Junwei) wrote:
> + sta...@vger.kernel.org
This is not the correct way to submit patches for inclusion in the
stable kernel tree. Ple
On 07/14/2017 10:43 PM, Deucher, Alexander wrote:
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Junwei Zhang
Sent: Friday, July 14, 2017 6:42 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Jerry
Subject: [PATCH 4/4] drm/amdgpu: add
the serial of patch are
Reviewed-by: Junwei Zhang
On 07/20/2017 03:36 PM, Huang Rui wrote:
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 07/25/2017 11:30 AM, Alex Deucher wrote:
Needs to be done when the MC is set up.
v2: make consistent with other asics
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
On 07/20/2017 10:21 AM, Huang Rui wrote:
There are 8 scratch registers on gfx v9 (scrach_reg0 -> scratch_reg7).
Yeah, nice catch.
Reviewed-by: Junwei Zhang
Additionally it looks incorrect from gfx v6 till gfx9.
Could you fix them all?
Jerry
Signed-off-by: Huang Rui
Hi Ray,
Thanks for your initial patch to enable PSP option for Raven.
To simplify it, we may leverage VEGA10 case for Raven directly.
And remove all Raven existing code under "case CHIP_RAVEN"
How do you think about it?
Jerry
On 07/04/2017 04:35 PM, Huang Rui wrote:
In previous case, driver
Yeah, when I had a glance at this func, flashed a similar idea.
A little comment inline, please confirm it.
Regards,
Jerry
On 07/04/2017 02:10 PM, Huang Rui wrote:
We would like to use a reserve vram to store all non-psp firmware data when it
is submmited. And needn't alloc/free when each
On 07/04/2017 05:59 PM, Huang Rui wrote:
On Tue, Jul 04, 2017 at 05:39:51PM +0800, Zhang, Jerry wrote:
Hi Ray,
Thanks for your initial patch to enable PSP option for Raven.
To simplify it, we may leverage VEGA10 case for Raven directly.
And remove all Raven existing code under "case
the series is
Reviewed-by: Junwei Zhang
Jerry
On 07/05/2017 01:32 PM, Huang Rui wrote:
Signed-off-by: Huang Rui
---
Changes from V1 -> V2
- amdgpu_bo_free_kernel is safe even the bo is NULL, so remove the "if" check.
Thanks,
Ray
---
On 07/01/2017 05:32 AM, Alex Deucher wrote:
Rather than checking the CONGIG_MEMSIZE register as that may
not be reliable on some APUs.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +-
1 file changed, 1 insertion(+), 9
Thanks for update.
That's fine for me.
Feel free to add my RB.
Reviewed-by: Junwei Zhang
On 07/04/2017 04:20 AM, Alex Deucher wrote:
Rather than checking the CONGIG_MEMSIZE register as that may
not be reliable on some APUs.
v2: The scratch register is only used on CIK+
On 04/24/2017 01:57 PM, Chunming Zhou wrote:
Change-Id: Id728e20366c8a1ae90d4e901dc80e136e2a613bb
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 ++
2 files changed, 18
On 04/24/2017 01:57 PM, Chunming Zhou wrote:
Change-Id: I5f80dc39dc9d44660a96a2b710b0dbb4d3b9039d
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 56 ++
1 file changed, 56 insertions(+)
diff --git
On 04/24/2017 01:57 PM, Chunming Zhou wrote:
v2: move #define to amdgpu_vm.h
Change-Id: Ie5958cf6dbdc1c8278e61d9158483472d6f5c6e3
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
On 04/26/2017 04:51 PM, Christian König wrote:
Am 26.04.2017 um 09:09 schrieb Zhang, Jerry (Junwei):
On 04/24/2017 01:57 PM, Chunming Zhou wrote:
Change-Id: I5f80dc39dc9d44660a96a2b710b0dbb4d3b9039d
Signed-off-by: Chunming Zhou <david1.z...@amd.com>
---
drivers/gpu/drm/amd/
On 04/26/2017 07:10 PM, Chunming Zhou wrote:
v2: move sync waiting only when flush needs
Change-Id: I64da2701c9fdcf986afb90ba1492a78d5bef1b6c
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 61 ++
1 file changed,
On 04/27/2017 10:13 AM, zhoucm1 wrote:
On 2017年04月26日 20:26, Christian König wrote:
Am 26.04.2017 um 13:10 schrieb Chunming Zhou:
add reserve/unreserve vmid funtions.
v3:
only reserve vmid from gfxhub
Change-Id: I5f80dc39dc9d44660a96a2b710b0dbb4d3b9039d
Signed-off-by: Chunming Zhou
On 04/26/2017 08:26 PM, Christian König wrote:
Am 26.04.2017 um 13:10 schrieb Chunming Zhou:
add reserve/unreserve vmid funtions.
v3:
only reserve vmid from gfxhub
Change-Id: I5f80dc39dc9d44660a96a2b710b0dbb4d3b9039d
Signed-off-by: Chunming Zhou
---
On 04/27/2017 01:00 PM, Chunming Zhou wrote:
add reserve/unreserve vmid funtions.
v3:
only reserve vmid from gfxhub
v4:
fix racy condition
Change-Id: I5f80dc39dc9d44660a96a2b710b0dbb4d3b9039d
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 62
On 04/27/2017 01:54 PM, Zhang, Jerry (Junwei) wrote:
On 04/27/2017 01:00 PM, Chunming Zhou wrote:
v2: move sync waiting only when flush needs
v3: fix racy
Change-Id: I64da2701c9fdcf986afb90ba1492a78d5bef1b6c
Signed-off-by: Chunming Zhou <david1.z...@amd.com>
---
drivers/gpu/drm/amd/
On 04/27/2017 01:00 PM, Chunming Zhou wrote:
v2: move sync waiting only when flush needs
v3: fix racy
Change-Id: I64da2701c9fdcf986afb90ba1492a78d5bef1b6c
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 72 --
1
It looks fine for me now.
Reviewed-by: Junwei Zhang
Jerry
On 04/27/2017 01:00 PM, Chunming Zhou wrote:
The current kernel implementation, which grabs the idle VMID from pool when
emitting the job may:
The back-to-back submission from one process could use
On 04/27/2017 04:25 PM, Chunming Zhou wrote:
the case could happen when gpu reset:
1. when gpu reset, cs can be continue until sw queue is full, then push job
will wait with holding pd reservation.
2. gpu_reset routine will also need pd reservation to restore page table from
their shadow.
3.
On 04/24/2017 04:56 PM, Christian König wrote:
Am 24.04.2017 um 10:55 schrieb Christian König:
Am 24.04.2017 um 08:43 schrieb Junwei Zhang:
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 18 +-
1 file changed, 9
On 04/27/2017 08:04 PM, Christian König wrote:
Am 27.04.2017 um 12:23 schrieb zhoucm1:
On 2017年04月27日 18:11, Christian König wrote:
Am 27.04.2017 um 11:08 schrieb Zhang, Jerry (Junwei):
On 04/27/2017 04:25 PM, Chunming Zhou wrote:
the case could happen when gpu reset:
1. when gpu reset, cs
Sorry about that missing, since it's originally created on amdgpu-pro stack,
which is a bit different about cu info definition.
I will keep an eye on those patches squashing when Alex prepares the patch
merging.
Jerry
On 04/28/2017 04:20 PM, Christian König wrote:
Do I get it right that the
On 05/03/2017 01:44 PM, Chunming Zhou wrote:
v2: delete unused comments.
Change-Id: If533576eb8a65bd019a3480d6fe2a64f23e3c944
Signed-off-by: Chunming Zhou
Reviewed-by: Monk Liu
Reviewed-by: Junwei Zhang
---
amdgpu/amdgpu.h|
On 04/28/2017 05:22 PM, Chunming Zhou wrote:
Change-Id: If533576eb8a65bd019a3480d6fe2a64f23e3c944
Signed-off-by: Chunming Zhou
---
amdgpu/amdgpu.h| 13 +
amdgpu/amdgpu_cs.c | 30 ++
2 files changed, 43 insertions(+)
diff
On 05/09/2017 04:14 PM, Chunming Zhou wrote:
The problem is that executing the jobs in the right order doesn't give you the
right result
because consecutive jobs executed on the same engine are pipelined.
In other words job B does it buffer read before job A has written it's result.
Change-Id:
On 05/09/2017 04:19 PM, Chunming Zhou wrote:
Change-Id: I26d3a2794272ba94b25753d4bf367326d12f6939
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
On 05/09/2017 04:14 PM, Chunming Zhou wrote:
Change-Id: Iced391f5c24a79ad7aecae33e22ff089f68f1337
Signed-off-by: Chunming Zhou
Good catch!
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 2 +-
1 file changed, 1
On 05/17/2017 05:22 PM, Christian König wrote:
From: Christian König
Rename adjust_mc_addr to get_vm_pde and check the address bits in one place.
v2: handle vcn as well, keep setting the valid bit manually,
add a BUG_ON() for GMC v6, v7 and v8 as well.
On 05/17/2017 06:08 PM, Zhou, David(ChunMing) wrote:
Patch#2: Reviewed-by: Chunming Zhou
Patch#3: RB should be from Hawking, so Acked-by: Chunming Zhou
Patch#5 #6, are Reviewed-by: Chunming Zhou
Feel free to add my RB about
On 05/16/2017 03:51 PM, Christian König wrote:
Am 16.05.2017 um 06:58 schrieb Zhang, Jerry (Junwei):
On 05/15/2017 07:57 PM, Christian König wrote:
From: Christian König <christian.koe...@amd.com>
I always wondered why this code uses the MC address. Now it came to me that
this is ac
On 05/10/2017 03:31 PM, Chunming Zhou wrote:
Change-Id: If24a62b9c3097c9b040225ab0e768145b7a3db1e
Signed-off-by: Chunming Zhou
I had same idea when read this code before.
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 92
On 06/13/2017 11:01 AM, Alex Deucher wrote:
This got lost when the code was revamped. Copy/paste bug from
gfx8.
Reported-by: Evan Quan
Fixes: 78c168342 (drm/amdgpu: allow split of queues with kfd at queue
granularity v4)
Signed-off-by: Alex Deucher
On 05/24/2017 05:18 PM, Christian König wrote:
Am 18.05.2017 um 07:33 schrieb Zhang, Jerry (Junwei):
On 05/17/2017 05:22 PM, Christian König wrote:
[SNIP]
+static uint64_t gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
+{
+BUG_ON(addr & 0xF000FFFULL);
+re
On 05/04/2017 10:33 PM, Alex Deucher wrote:
rather than defining it locally.
Signed-off-by: Alex Deucher
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 --
drivers/gpu/drm/amd/amdgpu/soc15d.h | 1 +
2 files
On 09/19/2017 04:30 PM, Christian König wrote:
I don't know why, but the HDP is generally not part of the register spec.
AFAIW, these regs may be used for HW guys to debug some special cases.
Usually they are not suggested to touch formally.
(e.g. GFX cannot access PRT unmap range, but with
On 09/20/2017 02:22 PM, Evan Quan wrote:
Change-Id: Ia41bf64501557723fa811ad98a7b5630f12d9ed8
Signed-off-by: Evan Quan
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
On 09/21/2017 10:56 AM, Evan Quan wrote:
Change-Id: I28e9ca38b68234d0325a5b8a01d135649939c0af
Signed-off-by: Evan Quan
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 23 +++
1 file changed, 23
On 09/16/2017 05:37 AM, Alex Deucher wrote:
So it gets picked up properly by the kernel.
Signed-off-by: Alex Deucher
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
looks fine to me, feel free to add my RB.
Reviewed-by: Junwei Zhang
BTW, we also has 1 or 2 patch to improve the name parsing.
Please also take a look.
Jerry
On 05/11/2017 05:10 AM, Li, Samuel wrote:
Also attach a sample ids file for reference. The names are from
On 09/11/2017 09:22 AM, Evan Quan wrote:
Change-Id: I9b7ebc99b7c75c03fb46d16c4c49348dd551325e
Signed-off-by: Evan Quan
The series patches is
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 16 +---
1 file
On 09/30/2017 09:10 AM, Evan Quan wrote:
Change-Id: I598f8ab583fc9c7045a4852d6972df90a82f7472
Signed-off-by: Evan Quan
the series is
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 7 ++-
1 file changed, 6
On 08/31/2017 08:53 PM, Tom St Denis wrote:
Working on a series of tidy up patches for gfx_v9 and found this block in
gfx_v9_0_sw_init().
for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
ring = >gfx.gfx_ring[i];
ring->ring_obj = NULL;
sprintf(ring->name, "gfx");
On 09/02/2017 02:18 PM, Alex Deucher wrote:
Was only being assigned for vega10.
Signed-off-by: Alex Deucher
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
On 10/06/2017 11:35 PM, Yong Zhao wrote:
From: Yong Zhao
Without the additional bits set in PDEs/PTEs, the ATC memory access
would have failed on Raven.
Change-Id: I28429ef6d39cdb01dc6f17fea4264ee22d7121d4
Signed-off-by: Yong Zhao
Acked-by: Alex Deucher
On 11/27/2017 07:29 PM, Feifei Xu wrote:
Remove folder amd/include/asic_reg/raven1 to avoid header files duplication.
Header files under this folder will be moved to asic_reg/.
Also removed some unused header files of raven1.
Patches are formated with flag --find-renames and
On 05/04/2018 02:44 PM, Chunming Zhou wrote:
Shadow BO is located on GTT and its parent (PT and PD) BO could located on VRAM.
In some case, the BO on GTT could be evicted but the parent did not. This may
cause the shadow BO not be put in the evict list and could not be invalidate
correctly.
v2:
On 05/10/2018 04:45 PM, zhoucm1 wrote:
On 2018年05月10日 13:07, Zhang, Jerry (Junwei) wrote:
On 05/09/2018 02:45 PM, Chunming Zhou wrote:
move implemenation from ttm to amdgpu driver. (suggested by Christian)
per-vm-lru is because of per-vm-bo, which has no chance to refresh lru, the
nagtive
On 05/09/2018 02:45 PM, Chunming Zhou wrote:
move implemenation from ttm to amdgpu driver. (suggested by Christian)
per-vm-lru is because of per-vm-bo, which has no chance to refresh lru, the
nagtive effect is game performance isn't stable.
so all per-vm-bo should have a default order, every
On 05/11/2018 10:11 AM, zhoucm1 wrote:
On 2018年05月11日 09:21, Zhang, Jerry (Junwei) wrote:
On 05/10/2018 10:40 PM, Christian König wrote:
Am 10.05.2018 um 07:01 schrieb Junwei Zhang:
Expect to add an evitable bo who has reservation object
to the correct lru[bo->priority] list
Nice ca
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