[PATCH] drm/amdgpu: Add back ring lock
lock ring from alloc to commit.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 10 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 5b75bdc..39172d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -73,12 +73,13 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned
ndw)
if (WARN_ON_ONCE(ndw > ring->max_dw))
return -ENOMEM;
- ring->count_dw = ndw;
- ring->wptr_old = ring->wptr;
-
if (ring->funcs->begin_use)
ring->funcs->begin_use(ring);
+ mutex_lock(>ring_lock);
+ ring->count_dw = ndw;
+ ring->wptr_old = ring->wptr;
+
return 0;
}
@@ -133,6 +134,8 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring)
mb();
amdgpu_ring_set_wptr(ring);
+ mutex_unlock(>ring_lock);
+
if (ring->funcs->end_use)
ring->funcs->end_use(ring);
}
@@ -317,6 +320,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct
amdgpu_ring *ring,
ring->max_dw = max_dw;
ring->priority = DRM_SCHED_PRIORITY_NORMAL;
mutex_init(>priority_mutex);
+ mutex_init(>ring_lock);
for (i = 0; i < DRM_SCHED_PRIORITY_MAX; ++i)
atomic_set(>num_jobs[i], 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 0beb01f..25976b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -214,6 +214,7 @@ struct amdgpu_ring {
atomic_tnum_jobs[DRM_SCHED_PRIORITY_MAX];
struct mutexpriority_mutex;
+ struct mutexring_lock;
/* protected by priority_mutex */
int priority;
--
1.9.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 3/4] drm/amdgpu: Use dynamical reserved vm size
Use dynamical reserved vm size instand of hardcode.
for gfx/sdma mcbp feature,
reserve AMDGPU_CSA_SIZ * AMDGPU_VM_MAX_NUM_CTX
at the top of VM space.
For sriov, only need to reserve AMDGPU_VA_RESERVED_SIZE
at the top.
v2: refine variable and function name(suggested by christian)
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 8
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 10 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 3 +--
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 3 +--
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 3 +--
9 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
index 567bdda..8d96ff3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
@@ -24,6 +24,14 @@
#include "amdgpu.h"
+uint64_t amdgpu_csa_get_reserved_vm_space(struct amdgpu_device *adev)
+{
+ if (amdgpu_sriov_vf(adev))
+ return AMDGPU_VA_RESERVED_SIZE;
+ else
+ return AMDGPU_CSA_SIZE * AMDGPU_VM_MAX_NUM_CTX;
+}
+
uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id)
{
uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
index a06e8b0..f0d780c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
@@ -38,6 +38,7 @@
#define AMDGPU_CSA_GDS_SIZE(64 * 1024)
#define AMDGPU_CSA_SDMA_SIZE (1024)
+uint64_t amdgpu_csa_get_reserved_vm_space(struct amdgpu_device *adev);
uint32_t amdgpu_get_total_csa_size(struct amdgpu_device *adev);
uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id);
int amdgpu_allocate_static_csa(struct amdgpu_device *adev, struct amdgpu_bo
**bo,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index f4f0021..6c500ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -557,6 +557,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
struct ww_acquire_ctx ticket;
struct list_head list, duplicates;
uint64_t va_flags;
+ uint64_t va_reserved, va_top;
int r = 0;
if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
@@ -565,6 +566,15 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
args->va_address, AMDGPU_VA_RESERVED_SIZE);
return -EINVAL;
}
+ va_top = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
+ va_reserved = adev->vm_manager.max_user_pfn * AMDGPU_GPU_PAGE_SIZE;
+
+ if (args->va_address > va_reserved && args->va_address < va_top) {
+ dev_dbg(>pdev->dev,
+ "va_address 0x%LX is in reserved area 0x%LX-0x%LX\n",
+ args->va_address, va_reserved, va_top);
+ return -EINVAL;
+ }
if (args->va_address >= AMDGPU_GMC_HOLE_START &&
args->va_address < AMDGPU_GMC_HOLE_END) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index ed440cd..ad1b7e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -698,8 +698,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file
if (amdgpu_sriov_vf(adev))
dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
- vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
- vm_size -= AMDGPU_VA_RESERVED_SIZE;
+ vm_size = adev->vm_manager.max_user_pfn * AMDGPU_GPU_PAGE_SIZE;
/* Older VCE FW versions are buggy and can handle only 40bits */
if (adev->vce.fw_version &&
@@ -977,7 +976,6 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
goto error_vm;
}
-
if (amdgpu_sriov_vf(adev)) {
uint64_t csa_addr = amdgpu_csa_vaddr(adev, 1) &
AMDGPU_GMC_HOLE_MASK;
r = amdgpu_map_static_csa(adev, >vm, adev->virt.csa_obj,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index e73d152..c8e51aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2898,6 +2898,8 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev,
uint32_t min_vm_size,
}
adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
+ adev->
[PATCH 2/4] drm/amdgpu: Refine function amdgpu_csa_vaddr
on baremetal, driver create csa per ctx.
So add a function argument: ctx_id to
get csa gpu addr.
v2: add SRIOV handling
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 8 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
5 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
index 7e22be7..567bdda 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
@@ -24,11 +24,15 @@
#include "amdgpu.h"
-uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
+uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id)
{
uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
- addr -= AMDGPU_VA_RESERVED_SIZE;
+ if (amdgpu_sriov_vf(adev))
+ addr -= AMDGPU_VA_RESERVED_SIZE;
+ else
+ addr -= AMDGPU_CSA_SIZE * id;
+
addr = amdgpu_gmc_sign_extend(addr);
return addr;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
index cca108e..a06e8b0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
@@ -39,7 +39,7 @@
#define AMDGPU_CSA_SDMA_SIZE (1024)
uint32_t amdgpu_get_total_csa_size(struct amdgpu_device *adev);
-uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev);
+uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id);
int amdgpu_allocate_static_csa(struct amdgpu_device *adev, struct amdgpu_bo
**bo,
u32 domain, uint32_t size);
int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index bc62bf4..ed440cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -977,9 +977,9 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
goto error_vm;
}
- if (amdgpu_sriov_vf(adev)) {
- uint64_t csa_addr = amdgpu_csa_vaddr(adev) &
AMDGPU_GMC_HOLE_MASK;
+ if (amdgpu_sriov_vf(adev)) {
+ uint64_t csa_addr = amdgpu_csa_vaddr(adev, 1) &
AMDGPU_GMC_HOLE_MASK;
r = amdgpu_map_static_csa(adev, >vm, adev->virt.csa_obj,
>csa_va, csa_addr,
AMDGPU_CSA_SIZE);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 52d6a5f..db813c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -7110,11 +7110,11 @@ static void gfx_v8_0_ring_emit_ce_meta(struct
amdgpu_ring *ring)
} ce_payload = {};
if (ring->adev->virt.chained_ib_support) {
- ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
+ ce_payload_addr = amdgpu_csa_vaddr(ring->adev, 1) +
offsetof(struct vi_gfx_meta_data_chained_ib,
ce_payload);
cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
} else {
- ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
+ ce_payload_addr = amdgpu_csa_vaddr(ring->adev, 1) +
offsetof(struct vi_gfx_meta_data, ce_payload);
cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2;
}
@@ -7138,7 +7138,7 @@ static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring
*ring)
struct vi_de_ib_state_chained_ib chained;
} de_payload = {};
- csa_addr = amdgpu_csa_vaddr(ring->adev);
+ csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
gds_addr = csa_addr + AMDGPU_CSA_CE_DE_SIZE;
if (ring->adev->virt.chained_ib_support) {
de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ae47110..f685718 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4244,7 +4244,7 @@ static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring
*ring)
int cnt;
cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
- csa_addr = amdgpu_csa_vaddr(ring->adev);
+ csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
@@ -4262,7 +4262,7 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring
*ring)
uint64_t csa_addr, gds_addr;
int cnt;
- csa_addr = amdgpu_csa_vaddr(ring->adev);
+ cs
[PATCH 1/4] drm/amdgpu: Add defines for CSA buffer
divide the reserve 128k CSA into four parts
1. first 4k for gfx CE/DE metadata
2. next 64K for GDS backup storage
3. next 28K reserved
4. last 32K for SDMA
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h | 11 +++
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
3 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
index 524b443..cca108e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
@@ -25,7 +25,18 @@
#ifndef AMDGPU_CSA_MANAGER_H
#define AMDGPU_CSA_MANAGER_H
+/* Reserve 128k CSA for MCBP feature
+ * first 4k for gfx CE/DE metadata
+ * next 64K for GDS backup storage.
+ * 28K reserved
+ * last 32K for SDMA
+ */
+
#define AMDGPU_CSA_SIZE(128 * 1024)
+#define AMDGPU_CSA_SDMA_OFFSET (96 * 1024)
+#define AMDGPU_CSA_CE_DE_SIZE (4 * 1024)
+#define AMDGPU_CSA_GDS_SIZE(64 * 1024)
+#define AMDGPU_CSA_SDMA_SIZE (1024)
uint32_t amdgpu_get_total_csa_size(struct amdgpu_device *adev);
uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index a9c853a..52d6a5f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -7139,7 +7139,7 @@ static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring
*ring)
} de_payload = {};
csa_addr = amdgpu_csa_vaddr(ring->adev);
- gds_addr = csa_addr + 4096;
+ gds_addr = csa_addr + AMDGPU_CSA_CE_DE_SIZE;
if (ring->adev->virt.chained_ib_support) {
de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
de_payload.chained.gds_backup_addrhi = upper_32_bits(gds_addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 7556716..ae47110 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4263,7 +4263,7 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring
*ring)
int cnt;
csa_addr = amdgpu_csa_vaddr(ring->adev);
- gds_addr = csa_addr + 4096;
+ gds_addr = csa_addr + AMDGPU_CSA_CE_DE_SIZE;
de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
--
1.9.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 4/4] drm/amdgpu: Delay map sriov csa addr to ctx init
1. meet kfd request
2. align with baremetal, in baremetal, driver map csa
when ctx init.
v2: Add csa_va test when rmv
do not need to free virt.csa_obj when map failed
update comments about function amdgpu_map_static_csa
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 17 -
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 14 --
3 files changed, 22 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
index 8d96ff3..369fdf0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
@@ -68,10 +68,10 @@ void amdgpu_free_static_csa(struct amdgpu_bo **bo)
}
/*
- * amdgpu_map_static_csa should be called during amdgpu_vm_init
+ * amdgpu_map_static_csa should be called during ctx_init
* it maps virtual address amdgpu_csa_vaddr() to this VM, and each command
* submission of GFX should use this virtual address within META_DATA init
- * package to support SRIOV gfx preemption.
+ * package to support gfx preemption.
*/
int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
struct amdgpu_bo *bo, struct amdgpu_bo_va **bo_va,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index d85184b..aab3516 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -69,11 +69,13 @@ static int amdgpu_ctx_priority_permit(struct drm_file *filp,
}
static int amdgpu_ctx_init(struct amdgpu_device *adev,
+ struct amdgpu_fpriv *fpriv,
enum drm_sched_priority priority,
struct drm_file *filp,
struct amdgpu_ctx *ctx)
{
unsigned num_entities = amdgput_ctx_total_num_entities();
+ uint64_t csa_addr;
unsigned i, j;
int r;
@@ -87,6 +89,19 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
memset(ctx, 0, sizeof(*ctx));
ctx->adev = adev;
+ if (amdgpu_sriov_vf(adev)) {
+ if (!fpriv->csa_va) {
+ csa_addr = amdgpu_csa_vaddr(adev, 1) &
AMDGPU_GMC_HOLE_MASK;
+ r = amdgpu_map_static_csa(adev, >vm,
+ adev->virt.csa_obj,
+ >csa_va,
+ csa_addr,
+ AMDGPU_CSA_SIZE);
+ if (r)
+ return -EINVAL;
+ }
+ }
+
ctx->fences = kcalloc(amdgpu_sched_jobs * num_entities,
sizeof(struct dma_fence*), GFP_KERNEL);
if (!ctx->fences)
@@ -256,7 +271,7 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
}
*id = (uint32_t)r;
- r = amdgpu_ctx_init(adev, priority, filp, ctx);
+ r = amdgpu_ctx_init(adev, fpriv, priority, filp, ctx);
if (r) {
idr_remove(>ctx_handles, *id);
*id = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index ad1b7e0..467a727 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -976,14 +976,6 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
goto error_vm;
}
- if (amdgpu_sriov_vf(adev)) {
- uint64_t csa_addr = amdgpu_csa_vaddr(adev, 1) &
AMDGPU_GMC_HOLE_MASK;
- r = amdgpu_map_static_csa(adev, >vm, adev->virt.csa_obj,
- >csa_va, csa_addr,
AMDGPU_CSA_SIZE);
- if (r)
- goto error_vm;
- }
-
mutex_init(>bo_list_lock);
idr_init(>bo_list_handles);
@@ -1041,8 +1033,10 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
if (amdgpu_sriov_vf(adev)) {
/* TODO: how to handle reserve failure */
BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
- amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
- fpriv->csa_va = NULL;
+ if (fpriv->csa_va) {
+ amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
+ fpriv->csa_va = NULL;
+ }
amdgpu_bo_unreserve(adev->virt.csa_obj);
}
--
1.9.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/9] drm/amdgpu: Refine function amdgpu_csa_vaddr
on baremetal, driver create csa per ctx.
So add a function argument: ctx_id to
get csa gpu addr.
In Sriov, driver create csa per process,
so ctx id always 1.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
index 0c590dd..44b046f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
@@ -24,11 +24,12 @@
#include "amdgpu.h"
-uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
+uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id)
{
uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
- addr -= AMDGPU_VA_RESERVED_SIZE;
+ addr -= AMDGPU_VA_RESERVED_SIZE * id;
+
addr = amdgpu_gmc_sign_extend(addr);
return addr;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
index 524b443..aaf1fba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
@@ -28,7 +28,7 @@
#define AMDGPU_CSA_SIZE(128 * 1024)
uint32_t amdgpu_get_total_csa_size(struct amdgpu_device *adev);
-uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev);
+uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id);
int amdgpu_allocate_static_csa(struct amdgpu_device *adev, struct amdgpu_bo
**bo,
u32 domain, uint32_t size);
int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 08d04f6..f736bda 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -977,9 +977,9 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
goto error_vm;
}
- if (amdgpu_sriov_vf(adev)) {
- uint64_t csa_addr = amdgpu_csa_vaddr(adev) &
AMDGPU_GMC_HOLE_MASK;
+ if (amdgpu_sriov_vf(adev)) {
+ uint64_t csa_addr = amdgpu_csa_vaddr(adev, 1) &
AMDGPU_GMC_HOLE_MASK;
r = amdgpu_map_static_csa(adev, >vm, adev->virt.csa_obj,
>csa_va, csa_addr,
AMDGPU_CSA_SIZE);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index bdae563..d529cef 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -7192,11 +7192,11 @@ static void gfx_v8_0_ring_emit_ce_meta(struct
amdgpu_ring *ring)
} ce_payload = {};
if (ring->adev->virt.chained_ib_support) {
- ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
+ ce_payload_addr = amdgpu_csa_vaddr(ring->adev, 1) +
offsetof(struct vi_gfx_meta_data_chained_ib,
ce_payload);
cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
} else {
- ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
+ ce_payload_addr = amdgpu_csa_vaddr(ring->adev, 1) +
offsetof(struct vi_gfx_meta_data, ce_payload);
cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2;
}
@@ -7220,7 +7220,7 @@ static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring
*ring)
struct vi_de_ib_state_chained_ib chained;
} de_payload = {};
- csa_addr = amdgpu_csa_vaddr(ring->adev);
+ csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
gds_addr = csa_addr + 4096;
if (ring->adev->virt.chained_ib_support) {
de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 928034c..81c1578 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4327,7 +4327,7 @@ static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring
*ring)
int cnt;
cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
- csa_addr = amdgpu_csa_vaddr(ring->adev);
+ csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
@@ -4345,7 +4345,7 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring
*ring)
uint64_t csa_addr, gds_addr;
int cnt;
- csa_addr = amdgpu_csa_vaddr(ring->adev);
+ csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
gds_addr = csa_addr + 4096;
[PATCH 2/9] drm/amdgpu: Refine function amdgpu_csa_vaddr
on baremetal, driver create csa per ctx.
So add a function argument: ctx_id to
get csa gpu addr.
In Sriov, driver create csa per process,
so ctx id always 1.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
index 0c590dd..44b046f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
@@ -24,11 +24,12 @@
#include "amdgpu.h"
-uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
+uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id)
{
uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
- addr -= AMDGPU_VA_RESERVED_SIZE;
+ addr -= AMDGPU_VA_RESERVED_SIZE * id;
+
addr = amdgpu_gmc_sign_extend(addr);
return addr;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
index 524b443..aaf1fba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
@@ -28,7 +28,7 @@
#define AMDGPU_CSA_SIZE(128 * 1024)
uint32_t amdgpu_get_total_csa_size(struct amdgpu_device *adev);
-uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev);
+uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id);
int amdgpu_allocate_static_csa(struct amdgpu_device *adev, struct amdgpu_bo
**bo,
u32 domain, uint32_t size);
int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 08d04f6..f736bda 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -977,9 +977,9 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
goto error_vm;
}
- if (amdgpu_sriov_vf(adev)) {
- uint64_t csa_addr = amdgpu_csa_vaddr(adev) &
AMDGPU_GMC_HOLE_MASK;
+ if (amdgpu_sriov_vf(adev)) {
+ uint64_t csa_addr = amdgpu_csa_vaddr(adev, 1) &
AMDGPU_GMC_HOLE_MASK;
r = amdgpu_map_static_csa(adev, >vm, adev->virt.csa_obj,
>csa_va, csa_addr,
AMDGPU_CSA_SIZE);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index bdae563..d529cef 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -7192,11 +7192,11 @@ static void gfx_v8_0_ring_emit_ce_meta(struct
amdgpu_ring *ring)
} ce_payload = {};
if (ring->adev->virt.chained_ib_support) {
- ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
+ ce_payload_addr = amdgpu_csa_vaddr(ring->adev, 1) +
offsetof(struct vi_gfx_meta_data_chained_ib,
ce_payload);
cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
} else {
- ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
+ ce_payload_addr = amdgpu_csa_vaddr(ring->adev, 1) +
offsetof(struct vi_gfx_meta_data, ce_payload);
cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2;
}
@@ -7220,7 +7220,7 @@ static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring
*ring)
struct vi_de_ib_state_chained_ib chained;
} de_payload = {};
- csa_addr = amdgpu_csa_vaddr(ring->adev);
+ csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
gds_addr = csa_addr + 4096;
if (ring->adev->virt.chained_ib_support) {
de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 928034c..81c1578 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4327,7 +4327,7 @@ static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring
*ring)
int cnt;
cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
- csa_addr = amdgpu_csa_vaddr(ring->adev);
+ csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
@@ -4345,7 +4345,7 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring
*ring)
uint64_t csa_addr, gds_addr;
int cnt;
- csa_addr = amdgpu_csa_vaddr(ring->adev);
+ csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
gds_addr = csa_addr + 4096;
[PATCH 6/9] drm/amdgpu: Create csa per ctx
create and map csa for gfx/sdma engine to save the
middle command buffer when gpu preemption triggered.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 9 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 55 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 4 +++
3 files changed, 56 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 2f189c5c..6f7a2dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -824,8 +824,9 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
struct amdgpu_device *adev = p->adev;
struct amdgpu_vm *vm = >vm;
struct amdgpu_bo_list_entry *e;
- struct amdgpu_bo_va *bo_va;
+ struct amdgpu_bo_va *bo_va = NULL;
struct amdgpu_bo *bo;
+ struct amdgpu_ctx *ctx = p->ctx;
int r;
/* Only for UVD/VCE VM emulation */
@@ -906,11 +907,11 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser
*p)
if (r)
return r;
- if (amdgpu_sriov_vf(adev)) {
+ bo_va = amdgpu_sriov_vf(adev) ? fpriv->csa_va : ctx->csa_va;
+
+ if (bo_va) {
struct dma_fence *f;
- bo_va = fpriv->csa_va;
- BUG_ON(!bo_va);
r = amdgpu_vm_bo_update(adev, bo_va, false);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 3ab7262..71831aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -71,7 +71,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
struct amdgpu_fpriv *fpriv,
enum drm_sched_priority priority,
struct drm_file *filp,
- struct amdgpu_ctx *ctx)
+ struct amdgpu_ctx *ctx, uint32_t id)
{
unsigned num_entities = amdgput_ctx_total_num_entities();
uint64_t csa_addr;
@@ -87,20 +87,36 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
memset(ctx, 0, sizeof(*ctx));
ctx->adev = adev;
+ csa_addr = amdgpu_csa_vaddr(adev, id) & AMDGPU_GMC_HOLE_MASK;
+ ctx->resv_space_id = id;
if (amdgpu_sriov_vf(adev)) {
if (!fpriv->csa_va) {
- csa_addr = amdgpu_csa_vaddr(adev, 1) &
AMDGPU_GMC_HOLE_MASK;
r = amdgpu_map_static_csa(adev, >vm,
- adev->virt.csa_obj,
- >csa_va,
- csa_addr,
- AMDGPU_CSA_SIZE);
+ adev->virt.csa_obj,
+ >csa_va,
+ csa_addr,
+ AMDGPU_CSA_SIZE);
if (r) {
amdgpu_free_static_csa(>virt.csa_obj);
return -EINVAL;
}
}
+ } else {
+ r = amdgpu_allocate_static_csa(adev, >csa_bo,
+ AMDGPU_GEM_DOMAIN_GTT,
+ AMDGPU_CSA_SIZE);
+ if (r) {
+ DRM_ERROR("allocate CSA failed %d\n", r);
+ return r;
+ }
+ r = amdgpu_map_static_csa(adev, >vm, ctx->csa_bo,
+ >csa_va, csa_addr,
+ AMDGPU_CSA_SIZE);
+ if (r) {
+ amdgpu_free_static_csa(>csa_bo);
+ return -EINVAL;
+ }
}
ctx->fences = kcalloc(amdgpu_sched_jobs * num_entities,
@@ -221,6 +237,16 @@ static void amdgpu_ctx_fini(struct kref *ref)
kfree(ctx->fences);
kfree(ctx->entities[0]);
+ if (!amdgpu_sriov_vf(adev) && ctx->csa_bo) {
+ BUG_ON(amdgpu_bo_reserve(ctx->csa_bo, true));
+ amdgpu_vm_bo_rmv(adev, ctx->csa_va);
+ ctx->csa_va = NULL;
+ amdgpu_bo_unreserve(ctx->csa_bo);
+ amdgpu_free_static_csa(>csa_bo);
+ if (ctx->ctx_mgr)
+ __clear_bit(ctx->resv_space_id - 1,
ctx->ctx_mgr->resv_vm_bitmap);
+ }
+
mutex_destroy(>lock);
kfree(ctx);
@@ -258,6 +284,7 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
struct amdgpu_ctx_mgr *mgr = >ctx_
[PATCH 8/9] drm/amdgpu: Add a argument in emit_cntxcntl interface
add a point of struct amdgpu_job in emit_cntxcntl
interface in order to get the csa mc address per ctx
when emit ce metadata in baremetal.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c| 4 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c| 4 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 20
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 16 ++--
6 files changed, 31 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index c48207b3..5329044 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -208,7 +208,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
status |= AMDGPU_HAVE_CTX_SWITCH;
status |= job->preamble_status;
- amdgpu_ring_emit_cntxcntl(ring, status);
+ amdgpu_ring_emit_cntxcntl(ring, job, status);
}
for (i = 0; i < num_ibs; ++i) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 0beb01f..7aa46cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -157,7 +157,7 @@ struct amdgpu_ring_funcs {
void (*begin_use)(struct amdgpu_ring *ring);
void (*end_use)(struct amdgpu_ring *ring);
void (*emit_switch_buffer) (struct amdgpu_ring *ring);
- void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
+ void (*emit_cntxcntl) (struct amdgpu_ring *ring, struct amdgpu_job
*job, uint32_t flags);
void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
@@ -236,7 +236,7 @@ struct amdgpu_ring {
#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as)
(r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
-#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
+#define amdgpu_ring_emit_cntxcntl(r, job, d) (r)->funcs->emit_cntxcntl((r),
(job), (d))
#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r),
(d), (v), (m))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 5b25c26..976f94a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2976,7 +2976,9 @@ static uint64_t gfx_v6_0_get_gpu_clock_counter(struct
amdgpu_device *adev)
return clock;
}
-static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
+static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring,
+ struct amdgpu_job *job,
+ uint32_t flags)
{
if (flags & AMDGPU_HAVE_CTX_SWITCH)
gfx_v6_0_ring_emit_vgt_flush(ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 243b8c5..ab62117 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2275,7 +2275,9 @@ static void gfx_v7_0_ring_emit_ib_compute(struct
amdgpu_ring *ring,
amdgpu_ring_write(ring, control);
}
-static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
+static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring,
+ struct amdgpu_job *job,
+ uint32_t flags)
{
uint32_t dw2 = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index d529cef..3ac2d8f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -723,8 +723,8 @@ enum {
static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
-static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring);
-static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring);
+static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring, struct
amdgpu_job *job);
+static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring, struct
amdgpu_job *job);
static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
{
@@ -6127,7 +6127,7 @@ static void gfx_v8_0_ring_emit
[PATCH 3/9] drm/amdgpu: Use dynamical reserved vm size
Use dynamical reserved vm size instand of hardcode.
driver always reserve AMDGPU_VA_RESERVED_SIZE at the
bottom of VM space.
for gfx/sdma mcbp feature,
reserve AMDGPU_VA_RESERVED_SIZ * AMDGPU_VM_MAX_NUM_CTX
at the top of VM space.
For sriov, only need to reserve AMDGPU_VA_RESERVED_SIZE
at the top.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 8
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 10 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
9 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
index 44b046f..caa71c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
@@ -24,6 +24,14 @@
#include "amdgpu.h"
+uint64_t amdgpu_get_reserved_csa_size(struct amdgpu_device *adev)
+{
+ if (amdgpu_sriov_vf(adev))
+ return AMDGPU_VA_RESERVED_SIZE;
+ else
+ return AMDGPU_VA_RESERVED_SIZE * AMDGPU_VM_MAX_NUM_CTX;
+}
+
uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id)
{
uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
index aaf1fba..7159d6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
@@ -27,6 +27,7 @@
#define AMDGPU_CSA_SIZE(128 * 1024)
+uint64_t amdgpu_get_reserved_csa_size(struct amdgpu_device *adev);
uint32_t amdgpu_get_total_csa_size(struct amdgpu_device *adev);
uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id);
int amdgpu_allocate_static_csa(struct amdgpu_device *adev, struct amdgpu_bo
**bo,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 7b3d1eb..4c12de8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -557,6 +557,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
struct ww_acquire_ctx ticket;
struct list_head list, duplicates;
uint64_t va_flags;
+ uint64_t va_reserved, va_top;
int r = 0;
if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
@@ -565,6 +566,15 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
args->va_address, AMDGPU_VA_RESERVED_SIZE);
return -EINVAL;
}
+ va_top = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
+ va_reserved = va_top - adev->vm_manager.reserved_vm_size;
+
+ if (args->va_address > va_reserved && args->va_address < va_top) {
+ dev_dbg(>pdev->dev,
+ "va_address 0x%LX is in reserved area 0x%LX\n",
+ args->va_address, adev->vm_manager.reserved_vm_size);
+ return -EINVAL;
+ }
if (args->va_address >= AMDGPU_GMC_HOLE_START &&
args->va_address < AMDGPU_GMC_HOLE_END) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index f736bda..52e4e90 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -702,7 +702,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file
dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
- vm_size -= AMDGPU_VA_RESERVED_SIZE;
+ vm_size -= adev->vm_manager.reserved_vm_size;
/* Older VCE FW versions are buggy and can handle only 40bits */
if (adev->vce.fw_version &&
@@ -977,7 +977,6 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
goto error_vm;
}
-
if (amdgpu_sriov_vf(adev)) {
uint64_t csa_addr = amdgpu_csa_vaddr(adev, 1) &
AMDGPU_GMC_HOLE_MASK;
r = amdgpu_map_static_csa(adev, >vm, adev->virt.csa_obj,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 352b304..2f2b9f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2901,6 +2901,7 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev,
uint32_t min_vm_size,
}
adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
+ adev->vm_manager.reserved_vm_size = amdgpu_get_reserved_csa_size(adev);
[PATCH 1/9] drm/amdgpu: Limit vm max ctx number to 4096
driver need to reserve resource for each ctx for
some hw features. so add this limitation.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 33f5f2c..3ef5c3e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -161,6 +161,7 @@ struct amdgpu_mgpu_info
extern int amdgpu_cik_support;
#endif
+#define AMDGPU_VM_MAX_NUM_CTX 4096
#define AMDGPU_SG_THRESHOLD(256*1024*1024)
#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index f9b5423..8edf54b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -247,7 +247,7 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
return -ENOMEM;
mutex_lock(>lock);
- r = idr_alloc(>ctx_handles, ctx, 1, 0, GFP_KERNEL);
+ r = idr_alloc(>ctx_handles, ctx, 1, AMDGPU_VM_MAX_NUM_CTX,
GFP_KERNEL);
if (r < 0) {
mutex_unlock(>lock);
kfree(ctx);
--
1.9.1
___
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[PATCH 2/9] drm/amdgpu: Refine function amdgpu_csa_vaddr
on baremetal, driver create csa per ctx.
So add a function argument: ctx_id to
get csa gpu addr.
In Sriov, driver create csa per process,
so ctx id always 1.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
index 0c590dd..44b046f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
@@ -24,11 +24,12 @@
#include "amdgpu.h"
-uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
+uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id)
{
uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
- addr -= AMDGPU_VA_RESERVED_SIZE;
+ addr -= AMDGPU_VA_RESERVED_SIZE * id;
+
addr = amdgpu_gmc_sign_extend(addr);
return addr;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
index 524b443..aaf1fba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
@@ -28,7 +28,7 @@
#define AMDGPU_CSA_SIZE(128 * 1024)
uint32_t amdgpu_get_total_csa_size(struct amdgpu_device *adev);
-uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev);
+uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id);
int amdgpu_allocate_static_csa(struct amdgpu_device *adev, struct amdgpu_bo
**bo,
u32 domain, uint32_t size);
int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 08d04f6..f736bda 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -977,9 +977,9 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
goto error_vm;
}
- if (amdgpu_sriov_vf(adev)) {
- uint64_t csa_addr = amdgpu_csa_vaddr(adev) &
AMDGPU_GMC_HOLE_MASK;
+ if (amdgpu_sriov_vf(adev)) {
+ uint64_t csa_addr = amdgpu_csa_vaddr(adev, 1) &
AMDGPU_GMC_HOLE_MASK;
r = amdgpu_map_static_csa(adev, >vm, adev->virt.csa_obj,
>csa_va, csa_addr,
AMDGPU_CSA_SIZE);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index bdae563..d529cef 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -7192,11 +7192,11 @@ static void gfx_v8_0_ring_emit_ce_meta(struct
amdgpu_ring *ring)
} ce_payload = {};
if (ring->adev->virt.chained_ib_support) {
- ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
+ ce_payload_addr = amdgpu_csa_vaddr(ring->adev, 1) +
offsetof(struct vi_gfx_meta_data_chained_ib,
ce_payload);
cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
} else {
- ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
+ ce_payload_addr = amdgpu_csa_vaddr(ring->adev, 1) +
offsetof(struct vi_gfx_meta_data, ce_payload);
cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2;
}
@@ -7220,7 +7220,7 @@ static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring
*ring)
struct vi_de_ib_state_chained_ib chained;
} de_payload = {};
- csa_addr = amdgpu_csa_vaddr(ring->adev);
+ csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
gds_addr = csa_addr + 4096;
if (ring->adev->virt.chained_ib_support) {
de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 928034c..81c1578 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4327,7 +4327,7 @@ static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring
*ring)
int cnt;
cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
- csa_addr = amdgpu_csa_vaddr(ring->adev);
+ csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
@@ -4345,7 +4345,7 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring
*ring)
uint64_t csa_addr, gds_addr;
int cnt;
- csa_addr = amdgpu_csa_vaddr(ring->adev);
+ csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
gds_addr = csa_addr + 4096;
[PATCH 4/9] drm/amdgpu: Add a bitmask in amdgpu_ctx_mgr
used to manager the reserverd vm space.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 8 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 4 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +-
3 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 8edf54b..8802ff2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -529,10 +529,14 @@ int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,
return 0;
}
-void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
+int amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
{
mutex_init(>lock);
idr_init(>ctx_handles);
+ mgr->resv_vm_bitmap = kzalloc(DIV_ROUND_UP(AMDGPU_VM_MAX_NUM_CTX,
BITS_PER_BYTE), GFP_KERNEL);
+ if (unlikely(!mgr->resv_vm_bitmap))
+ return -ENOMEM;
+ return 0;
}
void amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr)
@@ -601,7 +605,7 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
if (kref_put(>refcount, amdgpu_ctx_fini) != 1)
DRM_ERROR("ctx %p is still alive\n", ctx);
}
-
+ kfree(mgr->resv_vm_bitmap);
idr_destroy(>ctx_handles);
mutex_destroy(>lock);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
index b3b012c..94ac951 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
@@ -38,6 +38,7 @@ struct amdgpu_ctx_entity {
struct amdgpu_ctx {
struct kref refcount;
struct amdgpu_device*adev;
+
unsignedreset_counter;
unsignedreset_counter_query;
uint32_tvram_lost_counter;
@@ -56,6 +57,7 @@ struct amdgpu_ctx_mgr {
struct mutexlock;
/* protected by lock */
struct idr ctx_handles;
+ unsigned long *resv_vm_bitmap;
};
extern const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM];
@@ -80,7 +82,7 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,
struct drm_sched_entity *entity);
-void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
+int amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
void amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr);
void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 52e4e90..338a091 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -988,11 +988,15 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
mutex_init(>bo_list_lock);
idr_init(>bo_list_handles);
- amdgpu_ctx_mgr_init(>ctx_mgr);
+ if (amdgpu_ctx_mgr_init(>ctx_mgr))
+ goto error_ctx_mgr;
file_priv->driver_priv = fpriv;
goto out_suspend;
+error_ctx_mgr:
+ idr_destroy(>bo_list_handles);
+ mutex_destroy(>bo_list_lock);
error_vm:
amdgpu_vm_fini(adev, >vm);
--
1.9.1
___
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[PATCH 7/9] drm/amdgpu: Add csa mc address into job structure
save csa mc address in the job, so can patch the
address to pm4 when emit_ib even the ctx was freed.
suggested by Christian.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 4 +++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 6f7a2dd..13f0d7c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -230,6 +230,8 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p, union drm_amdgpu_cs
goto free_all_kdata;
}
+ p->job->csa_mc_addr = amdgpu_csa_vaddr(p->adev, p->ctx->resv_space_id)
& AMDGPU_GMC_HOLE_MASK;
+
if (p->uf_entry.tv.bo)
p->job->uf_addr = uf_offset;
kfree(chunk_array);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
index e1b46a6..42c959d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
@@ -34,6 +34,7 @@
container_of((sched_job), struct amdgpu_job, base)
#define AMDGPU_JOB_GET_VMID(job) ((job) ? (job)->vmid : 0)
+#define AMDGPU_JOB_GET_CSA_MC_ADDR(job) ((job) ? (job)->csa_mc_addr : 0)
struct amdgpu_fence;
@@ -56,10 +57,11 @@ struct amdgpu_job {
uint32_toa_base, oa_size;
uint32_tvram_lost_counter;
+ /* csa buffer mc address */
+ uint64_tcsa_mc_addr;
/* user fence handling */
uint64_tuf_addr;
uint64_tuf_sequence;
-
};
int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
--
1.9.1
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[PATCH 5/9] drm/amdgpu: Delay map sriov csa addr to ctx init
1. meet kfd request
2. align with baremetal, in baremetal, driver map csa
per ctx.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 19 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 8
2 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 8802ff2..3ab7262 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -68,11 +68,13 @@ static int amdgpu_ctx_priority_permit(struct drm_file *filp,
}
static int amdgpu_ctx_init(struct amdgpu_device *adev,
+ struct amdgpu_fpriv *fpriv,
enum drm_sched_priority priority,
struct drm_file *filp,
struct amdgpu_ctx *ctx)
{
unsigned num_entities = amdgput_ctx_total_num_entities();
+ uint64_t csa_addr;
unsigned i, j;
int r;
@@ -86,6 +88,21 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
memset(ctx, 0, sizeof(*ctx));
ctx->adev = adev;
+ if (amdgpu_sriov_vf(adev)) {
+ if (!fpriv->csa_va) {
+ csa_addr = amdgpu_csa_vaddr(adev, 1) &
AMDGPU_GMC_HOLE_MASK;
+ r = amdgpu_map_static_csa(adev, >vm,
+ adev->virt.csa_obj,
+ >csa_va,
+ csa_addr,
+ AMDGPU_CSA_SIZE);
+ if (r) {
+ amdgpu_free_static_csa(>virt.csa_obj);
+ return -EINVAL;
+ }
+ }
+ }
+
ctx->fences = kcalloc(amdgpu_sched_jobs * num_entities,
sizeof(struct dma_fence*), GFP_KERNEL);
if (!ctx->fences)
@@ -255,7 +272,7 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
}
*id = (uint32_t)r;
- r = amdgpu_ctx_init(adev, priority, filp, ctx);
+ r = amdgpu_ctx_init(adev, fpriv, priority, filp, ctx);
if (r) {
idr_remove(>ctx_handles, *id);
*id = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 338a091..34d000a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -977,14 +977,6 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
goto error_vm;
}
- if (amdgpu_sriov_vf(adev)) {
- uint64_t csa_addr = amdgpu_csa_vaddr(adev, 1) &
AMDGPU_GMC_HOLE_MASK;
- r = amdgpu_map_static_csa(adev, >vm, adev->virt.csa_obj,
- >csa_va, csa_addr,
AMDGPU_CSA_SIZE);
- if (r)
- goto error_vm;
- }
-
mutex_init(>bo_list_lock);
idr_init(>bo_list_handles);
--
1.9.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 9/9] drm/amdgpu: Remove sriov check when insert ce/de meta_data
to support cp gfx mid-command buffer preemption in baremetal
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 15 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 ++-
2 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 3ac2d8f..ccc461f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6123,7 +6123,7 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring
*ring,
control |= ib->length_dw | (vmid << 24);
- if (amdgpu_sriov_vf(ring->adev) && (ib->flags &
AMDGPU_IB_FLAG_PREEMPT)) {
+ if (ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
control |= INDIRECT_BUFFER_PRE_ENB(1);
if (!(ib->flags & AMDGPU_IB_FLAG_CE))
@@ -6392,8 +6392,7 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring
*ring,
{
uint32_t dw2 = 0;
- if (amdgpu_sriov_vf(ring->adev))
- gfx_v8_0_ring_emit_ce_meta(ring, job);
+ gfx_v8_0_ring_emit_ce_meta(ring, job);
dw2 |= 0x8000; /* set load_enable otherwise this package is just
NOPs */
if (flags & AMDGPU_HAVE_CTX_SWITCH) {
@@ -7194,8 +7193,11 @@ static void gfx_v8_0_ring_emit_ce_meta(struct
amdgpu_ring *ring,
struct vi_ce_ib_state_chained_ib chained;
} ce_payload = {};
+ if (!job)
+ return;
+
if (ring->adev->virt.chained_ib_support) {
- ce_payload_addr = amdgpu_csa_vaddr(ring->adev, 1) +
+ ce_payload_addr = AMDGPU_JOB_GET_CSA_MC_ADDR(job) +
offsetof(struct vi_gfx_meta_data_chained_ib,
ce_payload);
cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
} else {
@@ -7224,7 +7226,10 @@ static void gfx_v8_0_ring_emit_de_meta(struct
amdgpu_ring *ring,
struct vi_de_ib_state_chained_ib chained;
} de_payload = {};
- csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
+ if (!job)
+ return;
+
+ csa_addr = AMDGPU_JOB_GET_CSA_MC_ADDR(job);
gds_addr = csa_addr + 4096;
if (ring->adev->virt.chained_ib_support) {
de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index dd2d535..6d38834 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4063,7 +4063,7 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring
*ring,
control |= ib->length_dw | (vmid << 24);
- if (amdgpu_sriov_vf(ring->adev) && (ib->flags &
AMDGPU_IB_FLAG_PREEMPT)) {
+ if (ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
control |= INDIRECT_BUFFER_PRE_ENB(1);
if (!(ib->flags & AMDGPU_IB_FLAG_CE))
@@ -4327,8 +4327,11 @@ static void gfx_v9_0_ring_emit_ce_meta(struct
amdgpu_ring *ring,
uint64_t csa_addr;
int cnt;
+ if (!job)
+ return;
+
cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
- csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
+ csa_addr = AMDGPU_JOB_GET_CSA_MC_ADDR(job);
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
@@ -4347,7 +4350,10 @@ static void gfx_v9_0_ring_emit_de_meta(struct
amdgpu_ring *ring,
uint64_t csa_addr, gds_addr;
int cnt;
- csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
+ if (!job)
+ return;
+
+ csa_addr = AMDGPU_JOB_GET_CSA_MC_ADDR(job);
gds_addr = csa_addr + 4096;
de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
@@ -4375,8 +4381,7 @@ static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring
*ring,
{
uint32_t dw2 = 0;
- if (amdgpu_sriov_vf(ring->adev))
- gfx_v9_0_ring_emit_ce_meta(ring, job);
+ gfx_v9_0_ring_emit_ce_meta(ring, job);
gfx_v9_0_ring_emit_tmz(ring, true);
--
1.9.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 6/9] drm/amdgpu: Create csa per ctx
create and map csa for gfx/sdma engine to save the
middle command buffer when gpu preemption triggered.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 9 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 55 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 4 +++
3 files changed, 56 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 2f189c5c..6f7a2dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -824,8 +824,9 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
struct amdgpu_device *adev = p->adev;
struct amdgpu_vm *vm = >vm;
struct amdgpu_bo_list_entry *e;
- struct amdgpu_bo_va *bo_va;
+ struct amdgpu_bo_va *bo_va = NULL;
struct amdgpu_bo *bo;
+ struct amdgpu_ctx *ctx = p->ctx;
int r;
/* Only for UVD/VCE VM emulation */
@@ -906,11 +907,11 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser
*p)
if (r)
return r;
- if (amdgpu_sriov_vf(adev)) {
+ bo_va = amdgpu_sriov_vf(adev) ? fpriv->csa_va : ctx->csa_va;
+
+ if (bo_va) {
struct dma_fence *f;
- bo_va = fpriv->csa_va;
- BUG_ON(!bo_va);
r = amdgpu_vm_bo_update(adev, bo_va, false);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 3ab7262..71831aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -71,7 +71,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
struct amdgpu_fpriv *fpriv,
enum drm_sched_priority priority,
struct drm_file *filp,
- struct amdgpu_ctx *ctx)
+ struct amdgpu_ctx *ctx, uint32_t id)
{
unsigned num_entities = amdgput_ctx_total_num_entities();
uint64_t csa_addr;
@@ -87,20 +87,36 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
memset(ctx, 0, sizeof(*ctx));
ctx->adev = adev;
+ csa_addr = amdgpu_csa_vaddr(adev, id) & AMDGPU_GMC_HOLE_MASK;
+ ctx->resv_space_id = id;
if (amdgpu_sriov_vf(adev)) {
if (!fpriv->csa_va) {
- csa_addr = amdgpu_csa_vaddr(adev, 1) &
AMDGPU_GMC_HOLE_MASK;
r = amdgpu_map_static_csa(adev, >vm,
- adev->virt.csa_obj,
- >csa_va,
- csa_addr,
- AMDGPU_CSA_SIZE);
+ adev->virt.csa_obj,
+ >csa_va,
+ csa_addr,
+ AMDGPU_CSA_SIZE);
if (r) {
amdgpu_free_static_csa(>virt.csa_obj);
return -EINVAL;
}
}
+ } else {
+ r = amdgpu_allocate_static_csa(adev, >csa_bo,
+ AMDGPU_GEM_DOMAIN_GTT,
+ AMDGPU_CSA_SIZE);
+ if (r) {
+ DRM_ERROR("allocate CSA failed %d\n", r);
+ return r;
+ }
+ r = amdgpu_map_static_csa(adev, >vm, ctx->csa_bo,
+ >csa_va, csa_addr,
+ AMDGPU_CSA_SIZE);
+ if (r) {
+ amdgpu_free_static_csa(>csa_bo);
+ return -EINVAL;
+ }
}
ctx->fences = kcalloc(amdgpu_sched_jobs * num_entities,
@@ -221,6 +237,16 @@ static void amdgpu_ctx_fini(struct kref *ref)
kfree(ctx->fences);
kfree(ctx->entities[0]);
+ if (!amdgpu_sriov_vf(adev) && ctx->csa_bo) {
+ BUG_ON(amdgpu_bo_reserve(ctx->csa_bo, true));
+ amdgpu_vm_bo_rmv(adev, ctx->csa_va);
+ ctx->csa_va = NULL;
+ amdgpu_bo_unreserve(ctx->csa_bo);
+ amdgpu_free_static_csa(>csa_bo);
+ if (ctx->ctx_mgr)
+ __clear_bit(ctx->resv_space_id - 1,
ctx->ctx_mgr->resv_vm_bitmap);
+ }
+
mutex_destroy(>lock);
kfree(ctx);
@@ -258,6 +284,7 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
struct amdgpu_ctx_mgr *mgr = >ctx_
[PATCH 4/9] drm/amdgpu: Add a bitmask in amdgpu_ctx_mgr
used to manager the reserverd vm space.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 8 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 4 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +-
3 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 8edf54b..8802ff2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -529,10 +529,14 @@ int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,
return 0;
}
-void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
+int amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
{
mutex_init(>lock);
idr_init(>ctx_handles);
+ mgr->resv_vm_bitmap = kzalloc(DIV_ROUND_UP(AMDGPU_VM_MAX_NUM_CTX,
BITS_PER_BYTE), GFP_KERNEL);
+ if (unlikely(!mgr->resv_vm_bitmap))
+ return -ENOMEM;
+ return 0;
}
void amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr)
@@ -601,7 +605,7 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
if (kref_put(>refcount, amdgpu_ctx_fini) != 1)
DRM_ERROR("ctx %p is still alive\n", ctx);
}
-
+ kfree(mgr->resv_vm_bitmap);
idr_destroy(>ctx_handles);
mutex_destroy(>lock);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
index b3b012c..94ac951 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
@@ -38,6 +38,7 @@ struct amdgpu_ctx_entity {
struct amdgpu_ctx {
struct kref refcount;
struct amdgpu_device*adev;
+
unsignedreset_counter;
unsignedreset_counter_query;
uint32_tvram_lost_counter;
@@ -56,6 +57,7 @@ struct amdgpu_ctx_mgr {
struct mutexlock;
/* protected by lock */
struct idr ctx_handles;
+ unsigned long *resv_vm_bitmap;
};
extern const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM];
@@ -80,7 +82,7 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,
struct drm_sched_entity *entity);
-void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
+int amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
void amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr);
void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 52e4e90..338a091 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -988,11 +988,15 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
mutex_init(>bo_list_lock);
idr_init(>bo_list_handles);
- amdgpu_ctx_mgr_init(>ctx_mgr);
+ if (amdgpu_ctx_mgr_init(>ctx_mgr))
+ goto error_ctx_mgr;
file_priv->driver_priv = fpriv;
goto out_suspend;
+error_ctx_mgr:
+ idr_destroy(>bo_list_handles);
+ mutex_destroy(>bo_list_lock);
error_vm:
amdgpu_vm_fini(adev, >vm);
--
1.9.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 3/9] drm/amdgpu: Use dynamical reserved vm size
Use dynamical reserved vm size instand of hardcode.
driver always reserve AMDGPU_VA_RESERVED_SIZE at the
bottom of VM space.
for gfx/sdma mcbp feature,
reserve AMDGPU_VA_RESERVED_SIZ * AMDGPU_VM_MAX_NUM_CTX
at the top of VM space.
For sriov, only need to reserve AMDGPU_VA_RESERVED_SIZE
at the top.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 8
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 10 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
9 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
index 44b046f..caa71c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
@@ -24,6 +24,14 @@
#include "amdgpu.h"
+uint64_t amdgpu_get_reserved_csa_size(struct amdgpu_device *adev)
+{
+ if (amdgpu_sriov_vf(adev))
+ return AMDGPU_VA_RESERVED_SIZE;
+ else
+ return AMDGPU_VA_RESERVED_SIZE * AMDGPU_VM_MAX_NUM_CTX;
+}
+
uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id)
{
uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
index aaf1fba..7159d6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
@@ -27,6 +27,7 @@
#define AMDGPU_CSA_SIZE(128 * 1024)
+uint64_t amdgpu_get_reserved_csa_size(struct amdgpu_device *adev);
uint32_t amdgpu_get_total_csa_size(struct amdgpu_device *adev);
uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id);
int amdgpu_allocate_static_csa(struct amdgpu_device *adev, struct amdgpu_bo
**bo,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 7b3d1eb..4c12de8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -557,6 +557,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
struct ww_acquire_ctx ticket;
struct list_head list, duplicates;
uint64_t va_flags;
+ uint64_t va_reserved, va_top;
int r = 0;
if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
@@ -565,6 +566,15 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
args->va_address, AMDGPU_VA_RESERVED_SIZE);
return -EINVAL;
}
+ va_top = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
+ va_reserved = va_top - adev->vm_manager.reserved_vm_size;
+
+ if (args->va_address > va_reserved && args->va_address < va_top) {
+ dev_dbg(>pdev->dev,
+ "va_address 0x%LX is in reserved area 0x%LX\n",
+ args->va_address, adev->vm_manager.reserved_vm_size);
+ return -EINVAL;
+ }
if (args->va_address >= AMDGPU_GMC_HOLE_START &&
args->va_address < AMDGPU_GMC_HOLE_END) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index f736bda..52e4e90 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -702,7 +702,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file
dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
- vm_size -= AMDGPU_VA_RESERVED_SIZE;
+ vm_size -= adev->vm_manager.reserved_vm_size;
/* Older VCE FW versions are buggy and can handle only 40bits */
if (adev->vce.fw_version &&
@@ -977,7 +977,6 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
goto error_vm;
}
-
if (amdgpu_sriov_vf(adev)) {
uint64_t csa_addr = amdgpu_csa_vaddr(adev, 1) &
AMDGPU_GMC_HOLE_MASK;
r = amdgpu_map_static_csa(adev, >vm, adev->virt.csa_obj,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 352b304..2f2b9f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2901,6 +2901,7 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev,
uint32_t min_vm_size,
}
adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
+ adev->vm_manager.reserved_vm_size = amdgpu_get_reserved_csa_size(adev);
[PATCH] drm/amdgpu: Fix static checker warning
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c:49 amdgpu_allocate_static_csa() error: uninitialized symbol 'ptr'. the test if (!bo) doesn't work, as the bo is a pointer to a pointer. so need to check !*bo Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c index fea4555..d3a2536 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c @@ -52,7 +52,7 @@ int amdgpu_allocate_static_csa(struct amdgpu_device *adev, struct amdgpu_bo **bo r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, domain, bo, NULL, ); - if (!bo) + if (!*bo) return -ENOMEM; memset(ptr, 0, size); -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2] drm/amdgpu: Remove dead static variable
The static struct drm_driver *driver was
not used because drm_pci_init was deprecated
v2: Remove static pointer pdriver
Reviewed-by: Christian König
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 3b7d511..f3344c5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1235,9 +1235,6 @@ static int amdgpu_flush(struct file *f, fl_owner_t id)
.patchlevel = KMS_DRIVER_PATCHLEVEL,
};
-static struct drm_driver *driver;
-static struct pci_driver *pdriver;
-
static struct pci_driver amdgpu_kms_pci_driver = {
.name = DRIVER_NAME,
.id_table = pciidlist,
@@ -1267,16 +1264,14 @@ static int __init amdgpu_init(void)
goto error_fence;
DRM_INFO("amdgpu kernel modesetting enabled.\n");
- driver = _driver;
- pdriver = _kms_pci_driver;
- driver->num_ioctls = amdgpu_max_kms_ioctl;
+ kms_driver.num_ioctls = amdgpu_max_kms_ioctl;
amdgpu_register_atpx_handler();
/* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
amdgpu_amdkfd_init();
/* let modprobe override vga console setting */
- return pci_register_driver(pdriver);
+ return pci_register_driver(_kms_pci_driver);
error_fence:
amdgpu_sync_fini();
@@ -1288,7 +1283,7 @@ static int __init amdgpu_init(void)
static void __exit amdgpu_exit(void)
{
amdgpu_amdkfd_fini();
- pci_unregister_driver(pdriver);
+ pci_unregister_driver(_kms_pci_driver);
amdgpu_unregister_atpx_handler();
amdgpu_sync_fini();
amdgpu_fence_slab_fini();
--
1.9.1
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[PATCH v2] drm/amdgpu: Remove dead static variable
The static struct drm_driver *driver was
not used because drm_pci_init was deprecated
v2: Remove static pointer pdriver
Reviewed-by: Christian König
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 3b7d511..f3344c5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1235,9 +1235,6 @@ static int amdgpu_flush(struct file *f, fl_owner_t id)
.patchlevel = KMS_DRIVER_PATCHLEVEL,
};
-static struct drm_driver *driver;
-static struct pci_driver *pdriver;
-
static struct pci_driver amdgpu_kms_pci_driver = {
.name = DRIVER_NAME,
.id_table = pciidlist,
@@ -1267,16 +1264,14 @@ static int __init amdgpu_init(void)
goto error_fence;
DRM_INFO("amdgpu kernel modesetting enabled.\n");
- driver = _driver;
- pdriver = _kms_pci_driver;
- driver->num_ioctls = amdgpu_max_kms_ioctl;
+ kms_driver.num_ioctls = amdgpu_max_kms_ioctl;
amdgpu_register_atpx_handler();
/* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
amdgpu_amdkfd_init();
/* let modprobe override vga console setting */
- return pci_register_driver(pdriver);
+ return pci_register_driver(_kms_pci_driver);
error_fence:
amdgpu_sync_fini();
@@ -1288,7 +1283,7 @@ static int __init amdgpu_init(void)
static void __exit amdgpu_exit(void)
{
amdgpu_amdkfd_fini();
- pci_unregister_driver(pdriver);
+ pci_unregister_driver(_kms_pci_driver);
amdgpu_unregister_atpx_handler();
amdgpu_sync_fini();
amdgpu_fence_slab_fini();
--
1.9.1
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[PATCH] drm/amdgpu: Remove dead static variable
The static struct drm_driver *driver was
not used because drm_pci_init was deprecated
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 3b7d511..fa33e31 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1235,7 +1235,6 @@ static int amdgpu_flush(struct file *f, fl_owner_t id)
.patchlevel = KMS_DRIVER_PATCHLEVEL,
};
-static struct drm_driver *driver;
static struct pci_driver *pdriver;
static struct pci_driver amdgpu_kms_pci_driver = {
@@ -1267,9 +1266,8 @@ static int __init amdgpu_init(void)
goto error_fence;
DRM_INFO("amdgpu kernel modesetting enabled.\n");
- driver = _driver;
pdriver = _kms_pci_driver;
- driver->num_ioctls = amdgpu_max_kms_ioctl;
+ kms_driver.num_ioctls = amdgpu_max_kms_ioctl;
amdgpu_register_atpx_handler();
/* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
--
1.9.1
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[PATCH] drm/amd/pp: Fix truncated clock value when set watermark
the clk value should be tranferred to MHz first and
then transfer to uint16. otherwise, the clock value
will be truncated.
Reported-by: Hersen Wu
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
index 99a33c3..101c09b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
@@ -713,20 +713,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,
for (i = 0; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) {
table->WatermarkRow[1][i].MinClock =
cpu_to_le16((uint16_t)
-
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz) /
- 1000);
+
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
+ 1000));
table->WatermarkRow[1][i].MaxClock =
cpu_to_le16((uint16_t)
-
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz) /
- 1000);
+
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
+ 1000));
table->WatermarkRow[1][i].MinUclk =
cpu_to_le16((uint16_t)
-
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
- 1000);
+
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
+ 1000));
table->WatermarkRow[1][i].MaxUclk =
cpu_to_le16((uint16_t)
-
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz) /
- 1000);
+
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
+ 1000));
table->WatermarkRow[1][i].WmSetting = (uint8_t)
wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
}
@@ -734,20 +734,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,
for (i = 0; i < wm_with_clock_ranges->num_wm_mcif_sets; i++) {
table->WatermarkRow[0][i].MinClock =
cpu_to_le16((uint16_t)
-
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz) /
- 1000);
+
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
+ 1000));
table->WatermarkRow[0][i].MaxClock =
cpu_to_le16((uint16_t)
-
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz) /
- 1000);
+
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
+ 1000));
table->WatermarkRow[0][i].MinUclk =
cpu_to_le16((uint16_t)
-
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
- 1000);
+
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
+ 1000));
table->WatermarkRow[0][i].MaxUclk =
cpu_to_le16((uint16_t)
-
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz) /
- 1000);
+
(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
+ 1000));
table->WatermarkRow[0][i].WmSetting = (uint8_t)
wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
}
--
1.9.1
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[PATCH] drm/amdgpu: Fix CSA buffer alloc failed on Vega
Alloc_pte failed when the VA address located in
the higher arrange of 256T.
so reserve the csa buffer under 128T as a work around.
[ 122.979425] amdgpu :03:00.0: va above limit (0xFFF1F >=
0x10)
[ 122.987080] BUG: unable to handle kernel paging request at 880e1a79fff8
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
index fea4555..e2f325b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
@@ -36,9 +36,9 @@ uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev,
uint32_t id)
{
uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
- addr -= AMDGPU_VA_RESERVED_SIZE * id;
+ addr = min(addr, AMDGPU_GMC_HOLE_START);
- addr = amdgpu_gmc_sign_extend(addr);
+ addr -= (uint64_t)AMDGPU_VA_RESERVED_SIZE * id;
return addr;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 338a091..ea6a12a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -711,7 +711,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file
dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
dev_info.virtual_address_max =
- min(vm_size, AMDGPU_GMC_HOLE_START);
+ min(vm_size, AMDGPU_GMC_HOLE_START -
adev->vm_manager.reserved_vm_size);
if (vm_size > AMDGPU_GMC_HOLE_START) {
dev_info.high_va_offset = AMDGPU_GMC_HOLE_END;
--
1.9.1
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[PATCH 1/2] drm/amdgpu: Refine function name
there is no functional changes.just
refine function name to keep
consistence with other files.
change amdgpu_get_sdma_instance to
amdgpu_sdma_get_instance_from_ring.
suggested by alex.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 2 +-
drivers/gpu/drm/amd/amdgpu/cik_sdma.c| 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
6 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index 0fb9907..c912230 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -28,7 +28,7 @@
* GPU SDMA IP block helpers function.
*/
-struct amdgpu_sdma_instance * amdgpu_get_sdma_instance(struct amdgpu_ring
*ring)
+struct amdgpu_sdma_instance *amdgpu_sdma_get_instance_from_ring(struct
amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
int i;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index 479a245..664f549 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -94,6 +94,6 @@ struct amdgpu_buffer_funcs {
#define amdgpu_emit_fill_buffer(adev, ib, s, d, b)
(adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
struct amdgpu_sdma_instance *
-amdgpu_get_sdma_instance(struct amdgpu_ring *ring);
+amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 49275f3..003acbd 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -198,7 +198,7 @@ static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
{
- struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
+ struct amdgpu_sdma_instance *sdma =
amdgpu_sdma_get_instance_from_ring(ring);
int i;
for (i = 0; i < count; i++)
@@ -803,7 +803,7 @@ static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib,
uint64_t pe,
*/
static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib
*ib)
{
- struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
+ struct amdgpu_sdma_instance *sdma =
amdgpu_sdma_get_instance_from_ring(ring);
u32 pad_count;
int i;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index c4ab54a..11fb435 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -225,7 +225,7 @@ static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring
*ring)
static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
{
- struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
+ struct amdgpu_sdma_instance *sdma =
amdgpu_sdma_get_instance_from_ring(ring);
int i;
for (i = 0; i < count; i++)
@@ -740,7 +740,7 @@ static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib,
uint64_t pe,
*/
static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib
*ib)
{
- struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
+ struct amdgpu_sdma_instance *sdma =
amdgpu_sdma_get_instance_from_ring(ring);
u32 pad_count;
int i;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index e3adddb..4af413e 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -399,7 +399,7 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring
*ring)
static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
{
- struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
+ struct amdgpu_sdma_instance *sdma =
amdgpu_sdma_get_instance_from_ring(ring);
int i;
for (i = 0; i < count; i++)
@@ -1011,7 +1011,7 @@ static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib
*ib, uint64_t pe,
*/
static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib
*ib)
{
- struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
+ struct amdgpu_sdma_instance *sdma =
amdgpu_sdma_get_instance_from_ring(ring);
u32 pad_count;
int i;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 7f9a501..1d0fa0eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -477,7 +477,7 @@ static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring
*ring)
static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ri
[PATCH 2/2] drm/amdgpu: Add helper function to get sdma index
Get the sdma index from ring
v2: refine function name
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 16
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index c912230..115bb0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -40,3 +40,19 @@ struct amdgpu_sdma_instance
*amdgpu_sdma_get_instance_from_ring(struct amdgpu_ri
return NULL;
}
+
+int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index)
+{
+ struct amdgpu_device *adev = ring->adev;
+ int i;
+
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ if (ring == >sdma.instance[i].ring ||
+ ring == >sdma.instance[i].page) {
+ *index = i;
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index 664f549..16b1a6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -95,5 +95,6 @@ struct amdgpu_buffer_funcs {
struct amdgpu_sdma_instance *
amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
+int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
#endif
--
1.9.1
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[PATCH 5/6] drm/amdgpu: Add new ring interface ib_preempt
Used to trigger preemtption
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index a9ddb0d..cdd66a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -172,6 +172,7 @@ struct amdgpu_ring_funcs {
enum drm_sched_priority priority);
/* Try to soft recover the ring to make the fence signal */
void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
+ void (*ib_preempt)(struct amdgpu_ring *ring);
};
struct amdgpu_ring {
--
1.9.1
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[PATCH 4/6] drm/amdgpu: Add sdma ib preempt clear when emit fence
need to clear ib preempt in a proper time
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 13 +
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index e321d9d..de280d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -484,7 +484,11 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct
amdgpu_ring *ring)
static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64
seq,
unsigned flags)
{
+ struct amdgpu_device *adev = ring->adev;
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
+ bool clear_preempt = flags & AMDGPU_FENCE_FLAG_CLEAR_PREEMPT;
+ u32 index = 0;
+
/* write the fence */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
amdgpu_ring_write(ring, lower_32_bits(addr));
@@ -500,6 +504,15 @@ static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring
*ring, u64 addr, u64 se
amdgpu_ring_write(ring, upper_32_bits(seq));
}
+ if (!amdgpu_sriov_vf(adev) && adev->gpu_preemption && clear_preempt) {
+ if (!amdgpu_get_sdma_index(ring, )) {
+ amdgpu_ring_alloc(ring, 4);
+ amdgpu_ring_emit_wreg(ring, index == 0 ?
+ mmSDMA0_GFX_PREEMPT :
+ mmSDMA1_GFX_PREEMPT, 0);
+ }
+ }
+
/* generate an interrupt */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3eeac44..33bdeeb 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -591,7 +591,10 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct
amdgpu_ring *ring)
static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64
seq,
unsigned flags)
{
+ struct amdgpu_device *adev = ring->adev;
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
+ bool clear_preempt = flags & AMDGPU_FENCE_FLAG_CLEAR_PREEMPT;
+ u32 index = 0;
/* write the fence */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
/* zero in first two bits */
@@ -611,6 +614,15 @@ static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring
*ring, u64 addr, u64 se
amdgpu_ring_write(ring, upper_32_bits(seq));
}
+ if (!amdgpu_sriov_vf(adev) && adev->gpu_preemption && clear_preempt) {
+ if (!amdgpu_get_sdma_index(ring, )) {
+ amdgpu_ring_alloc(ring, 4);
+ amdgpu_ring_emit_wreg(ring, index == 0 ?
+ mmSDMA0_GFX_PREEMPT :
+ mmSDMA1_GFX_PREEMPT, 0);
+ }
+ }
+
/* generate an interrupt */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
--
1.9.1
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[PATCH 6/6] drm/amdgpu: Implement ib_preemmpt interface for sdma
sdma can be preempted via this interface
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 14 ++
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 15 +++
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index de280d4..388d3eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -545,6 +545,19 @@ static void sdma_v3_0_ring_patch_cond_exec(struct
amdgpu_ring *ring, unsigned of
ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
}
+static void sdma_v3_0_ring_ib_preempt(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ u32 index = 0;
+
+ if (!amdgpu_sriov_vf(adev) && adev->gpu_preemption) {
+ amdgpu_ring_alloc(ring, 16);
+ amdgpu_ring_set_preempt_cond_exec(ring, true);
+ WREG32(index == 0 ? mmSDMA0_GFX_PREEMPT : mmSDMA1_GFX_PREEMPT,
0x1);
+ amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr+8, 0xff,
AMDGPU_FENCE_FLAG_CLEAR_PREEMPT);
+ amdgpu_ring_commit(ring);
+ }
+}
/**
* sdma_v3_0_gfx_stop - stop the gfx async dma engines
@@ -1660,6 +1673,7 @@ static void sdma_v3_0_get_clockgating_state(void *handle,
u32 *flags)
.emit_wreg = sdma_v3_0_ring_emit_wreg,
.init_cond_exec = sdma_v3_0_ring_init_cond_exec,
.patch_cond_exec = sdma_v3_0_ring_patch_cond_exec,
+ .ib_preempt = sdma_v3_0_ring_ib_preempt,
};
static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 33bdeeb..f47a3d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -654,6 +654,20 @@ static void sdma_v4_0_ring_patch_cond_exec(struct
amdgpu_ring *ring, unsigned of
ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
}
+static void sdma_v4_0_ring_ib_preempt(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ u32 index = 0;
+
+ if (!amdgpu_sriov_vf(adev) && adev->gpu_preemption) {
+ amdgpu_ring_alloc(ring, 16);
+ amdgpu_ring_set_preempt_cond_exec(ring, true);
+ WREG32(index == 0 ? mmSDMA0_GFX_PREEMPT : mmSDMA1_GFX_PREEMPT,
0x1);
+ amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr+8, 0xff,
AMDGPU_FENCE_FLAG_CLEAR_PREEMPT);
+ amdgpu_ring_commit(ring);
+ }
+}
+
/**
* sdma_v4_0_gfx_stop - stop the gfx async dma engines
*
@@ -1996,6 +2010,7 @@ static void sdma_v4_0_get_clockgating_state(void *handle,
u32 *flags)
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
.init_cond_exec = sdma_v4_0_ring_init_cond_exec,
.patch_cond_exec = sdma_v4_0_ring_patch_cond_exec,
+ .ib_preempt = sdma_v4_0_ring_ib_preempt,
};
static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
--
1.9.1
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[PATCH 3/6] drm/amdgpu: Add helper function to get sdma index
Get the sdma index from sdma ring
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 16
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index 0fb9907..99668a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -40,3 +40,19 @@ struct amdgpu_sdma_instance *
amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
return NULL;
}
+
+int amdgpu_get_sdma_index(struct amdgpu_ring *ring, uint32_t *index)
+{
+ struct amdgpu_device *adev = ring->adev;
+ int i;
+
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ if (ring == >sdma.instance[i].ring ||
+ ring == >sdma.instance[i].page) {
+ *index = i;
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index 237a357..92e5097 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -96,5 +96,6 @@ struct amdgpu_buffer_funcs {
struct amdgpu_sdma_instance *
amdgpu_get_sdma_instance(struct amdgpu_ring *ring);
+int amdgpu_get_sdma_index(struct amdgpu_ring *ring, uint32_t *index);
#endif
--
1.9.1
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[PATCH 2/6] drm/amdgpu: report more sdma amdgpu_fence_info
This can help checking MCBP feature on sdma. If preemption occurred in the previous IB the address is adjusted by 2 DWs. Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 5448cf2..aa7415c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -679,7 +679,8 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) seq_printf(m, "Last emitted0x%08x\n", ring->fence_drv.sync_seq); - if (ring->funcs->type != AMDGPU_RING_TYPE_GFX) + if (ring->funcs->type != AMDGPU_RING_TYPE_GFX && + ring->funcs->type != AMDGPU_RING_TYPE_SDMA) continue; /* set in CP_VMID_PREEMPT and preemption occurred */ -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/6] drm/amdgpu: Add fence flag AMDGPU_FENCE_FLAG_CLEAR_PREEMPT
when emit fence with this flag, driver will de-assert IB_PREEMPTION Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index a4b6eff..a9ddb0d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -43,6 +43,7 @@ #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) #define AMDGPU_FENCE_FLAG_INT (1 << 1) #define AMDGPU_FENCE_FLAG_TC_WB_ONLY(1 << 2) +#define AMDGPU_FENCE_FLAG_CLEAR_PREEMPT (1<<3) #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched) -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amd/pp: Print warning if od_sclk/mclk out of range
print warning in dmesg to notify user the setting for
sclk_od/mclk_od out of range that vbios can support
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 3fd68df..8c4db86 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -1333,7 +1333,6 @@ static int vega10_setup_default_dpm_tables(struct
pp_hwmgr *hwmgr)
if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
hwmgr->platform_descriptor.overdriveLimit.memoryClock =
dpm_table->dpm_levels[dpm_table->count-1].value;
-
vega10_init_dpm_state(&(dpm_table->dpm_state));
data->dpm_table.eclk_table.count = 0;
@@ -4560,11 +4559,13 @@ static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr,
uint32_t value)
if (vega10_ps->performance_levels
[vega10_ps->performance_level_count - 1].gfx_clock >
- hwmgr->platform_descriptor.overdriveLimit.engineClock)
+ hwmgr->platform_descriptor.overdriveLimit.engineClock) {
vega10_ps->performance_levels
[vega10_ps->performance_level_count - 1].gfx_clock =
hwmgr->platform_descriptor.overdriveLimit.engineClock;
-
+ pr_warn("max sclk supported by vbios is %d\n",
+
hwmgr->platform_descriptor.overdriveLimit.engineClock);
+ }
return 0;
}
@@ -4612,10 +4613,13 @@ static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr,
uint32_t value)
if (vega10_ps->performance_levels
[vega10_ps->performance_level_count - 1].mem_clock >
- hwmgr->platform_descriptor.overdriveLimit.memoryClock)
+ hwmgr->platform_descriptor.overdriveLimit.memoryClock) {
vega10_ps->performance_levels
[vega10_ps->performance_level_count - 1].mem_clock =
hwmgr->platform_descriptor.overdriveLimit.memoryClock;
+ pr_warn("max mclk supported by vbios is %d\n",
+
hwmgr->platform_descriptor.overdriveLimit.memoryClock);
+ }
return 0;
}
--
1.9.1
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[PATCH 1/2] drm/amd/pp: Fix pp_sclk/mclk_od not work on Vega10
not update dpm table with user's setting.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 31 ++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 419a1d7..3fd68df 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3249,6 +3249,37 @@ static int vega10_apply_state_adjust_rules(struct
pp_hwmgr *hwmgr,
static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr,
const void *input)
{
struct vega10_hwmgr *data = hwmgr->backend;
+ const struct phm_set_power_state_input *states =
+ (const struct phm_set_power_state_input *)input;
+ const struct vega10_power_state *vega10_ps =
+ cast_const_phw_vega10_power_state(states->pnew_state);
+ struct vega10_single_dpm_table *sclk_table =
&(data->dpm_table.gfx_table);
+ uint32_t sclk = vega10_ps->performance_levels
+ [vega10_ps->performance_level_count - 1].gfx_clock;
+ struct vega10_single_dpm_table *mclk_table =
&(data->dpm_table.mem_table);
+ uint32_t mclk = vega10_ps->performance_levels
+ [vega10_ps->performance_level_count - 1].mem_clock;
+ uint32_t i;
+
+ for (i = 0; i < sclk_table->count; i++) {
+ if (sclk == sclk_table->dpm_levels[i].value)
+ break;
+ }
+
+ if (i >= sclk_table->count) {
+ data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
+ sclk_table->dpm_levels[i-1].value = sclk;
+ }
+
+ for (i = 0; i < mclk_table->count; i++) {
+ if (mclk == mclk_table->dpm_levels[i].value)
+ break;
+ }
+
+ if (i >= mclk_table->count) {
+ data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
+ mclk_table->dpm_levels[i-1].value = mclk;
+ }
if (data->display_timing.num_existing_displays !=
hwmgr->display_config->num_display)
data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
--
1.9.1
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[PATCH 3/3] drm/amdgpu: Patch csa mc address to sdma IB packet
the csa buffer is used by sdma engine to do context
save when preemption happens. if the mc address is zero,
mean the preemtpion feature(MCBP) is disabled.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 1 +
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 11 ---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 11 +--
4 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
index 15b4d39..e4a0837 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
@@ -33,7 +33,9 @@
#define to_amdgpu_job(sched_job) \
container_of((sched_job), struct amdgpu_job, base)
+
#define AMDGPU_JOB_GET_VMID(job) ((job) ? (job)->vmid : 0)
+#define AMDGPU_JOB_GET_CSA_MC_ADDR(job) ((job) ? (job)->csa_mc_addr : 0)
struct amdgpu_fence;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index 479a245..237a357 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -26,6 +26,7 @@
/* max number of IP instances */
#define AMDGPU_MAX_SDMA_INSTANCES 2
+#define AMDGPU_SDMA_CSA_SIZE (1024)
enum amdgpu_sdma_irq {
AMDGPU_SDMA_IRQ_TRAP0 = 0,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 8bfc68d..ae8f5db 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -424,6 +424,12 @@ static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring
*ring,
bool ctx_switch)
{
unsigned vmid = AMDGPU_JOB_GET_VMID(job);
+ uint64_t csa_mc_addr = AMDGPU_JOB_GET_CSA_MC_ADDR(job);
+
+ if (csa_mc_addr == 0 || vmid == 0)
+ csa_mc_addr = 0;
+ else
+ csa_mc_addr += ring->idx * AMDGPU_SDMA_CSA_SIZE;
/* IB packet must end on a 8 DW boundary */
sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7))
% 8);
@@ -434,9 +440,8 @@ static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffe0);
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
amdgpu_ring_write(ring, ib->length_dw);
- amdgpu_ring_write(ring, 0);
- amdgpu_ring_write(ring, 0);
-
+ amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
+ amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 64fa6be..eede68e 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -506,7 +506,14 @@ static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring
*ring,
struct amdgpu_ib *ib,
bool ctx_switch)
{
+
unsigned vmid = AMDGPU_JOB_GET_VMID(job);
+ uint64_t csa_mc_addr = AMDGPU_JOB_GET_CSA_MC_ADDR(job);
+
+ if (csa_mc_addr == 0 || vmid == 0)
+ csa_mc_addr = 0;
+ else
+ csa_mc_addr += ring->idx * AMDGPU_SDMA_CSA_SIZE;
/* IB packet must end on a 8 DW boundary */
sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7))
% 8);
@@ -517,8 +524,8 @@ static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffe0);
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
amdgpu_ring_write(ring, ib->length_dw);
- amdgpu_ring_write(ring, 0);
- amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
+ amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
}
--
1.9.1
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[PATCH 2/3] drm/amdgpu: Add csa mc address into job structure
save csa mc address in the job, so can patch the
address to pm4 when emit_ib even the ctx was freed.
suggested by Christian.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 3 ++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index ad3bbaf..dddfa8f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -230,6 +230,8 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p, union drm_amdgpu_cs
goto free_all_kdata;
}
+ p->job->csa_mc_addr = p->ctx->csa_mc_addr;
+
if (p->uf_entry.tv.bo)
p->job->uf_addr = uf_offset;
kfree(chunk_array);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
index e1b46a6..15b4d39 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
@@ -56,10 +56,11 @@ struct amdgpu_job {
uint32_toa_base, oa_size;
uint32_tvram_lost_counter;
+ /* csa buffer mc address */
+ uint64_tcsa_mc_addr;
/* user fence handling */
uint64_tuf_addr;
uint64_tuf_sequence;
-
};
int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
--
1.9.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/3] drm/amdgpu: Create csa per ctx
create csa for gfx/sdma engine to save the
middle command buffer when gpu preemption triggered.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 12 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 48 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 5
3 files changed, 59 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 8836186..ad3bbaf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -824,8 +824,9 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
struct amdgpu_device *adev = p->adev;
struct amdgpu_vm *vm = >vm;
struct amdgpu_bo_list_entry *e;
- struct amdgpu_bo_va *bo_va;
+ struct amdgpu_bo_va *bo_va = NULL;
struct amdgpu_bo *bo;
+ struct amdgpu_ctx *ctx = p->ctx;
int r;
/* Only for UVD/VCE VM emulation */
@@ -907,10 +908,15 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser
*p)
return r;
if (amdgpu_sriov_vf(adev)) {
- struct dma_fence *f;
-
bo_va = fpriv->csa_va;
BUG_ON(!bo_va);
+ } else if (adev->gpu_preemption) {
+ bo_va = ctx->csa_va;
+ BUG_ON(!bo_va);
+ }
+ if (bo_va) {
+ struct dma_fence *f;
+
r = amdgpu_vm_bo_update(adev, bo_va, false);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 8802ff2..6fc3cbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -68,9 +68,10 @@ static int amdgpu_ctx_priority_permit(struct drm_file *filp,
}
static int amdgpu_ctx_init(struct amdgpu_device *adev,
+ struct amdgpu_fpriv *fpriv,
enum drm_sched_priority priority,
struct drm_file *filp,
- struct amdgpu_ctx *ctx)
+ struct amdgpu_ctx *ctx, uint32_t id)
{
unsigned num_entities = amdgput_ctx_total_num_entities();
unsigned i, j;
@@ -85,6 +86,25 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
memset(ctx, 0, sizeof(*ctx));
ctx->adev = adev;
+ ctx->resv_space_id = id;
+
+ if (!amdgpu_sriov_vf(adev) && adev->gpu_preemption) {
+ ctx->csa_mc_addr = amdgpu_csa_vaddr(adev, ctx->resv_space_id);
+ r = amdgpu_allocate_static_csa(adev, >csa_bo,
+ AMDGPU_GEM_DOMAIN_GTT,
+ AMDGPU_CSA_SIZE);
+ if (!r) {
+ r = amdgpu_map_static_csa(adev, >vm, ctx->csa_bo,
+ >csa_va,
ctx->csa_mc_addr,
+ AMDGPU_CSA_SIZE);
+ if (r) {
+ amdgpu_free_static_csa(>csa_bo);
+ return -EINVAL;
+ }
+ } else {
+ return -ENOMEM;
+ }
+ }
ctx->fences = kcalloc(amdgpu_sched_jobs * num_entities,
sizeof(struct dma_fence*), GFP_KERNEL);
@@ -204,6 +224,16 @@ static void amdgpu_ctx_fini(struct kref *ref)
kfree(ctx->fences);
kfree(ctx->entities[0]);
+ if (!amdgpu_sriov_vf(adev) && adev->gpu_preemption && ctx->csa_bo) {
+ BUG_ON(amdgpu_bo_reserve(ctx->csa_bo, true));
+ amdgpu_vm_bo_rmv(adev, ctx->csa_va);
+ ctx->csa_va = NULL;
+ amdgpu_bo_unreserve(ctx->csa_bo);
+ amdgpu_free_static_csa(>csa_bo);
+ if (ctx->ctx_mgr)
+ __clear_bit(ctx->resv_space_id - 1,
ctx->ctx_mgr->resv_vm_bitmap);
+ }
+
mutex_destroy(>lock);
kfree(ctx);
@@ -241,6 +271,7 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
struct amdgpu_ctx_mgr *mgr = >ctx_mgr;
struct amdgpu_ctx *ctx;
int r;
+ u32 resv_space_id = 0;
ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
if (!ctx)
@@ -253,14 +284,25 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
kfree(ctx);
return r;
}
-
*id = (uint32_t)r;
- r = amdgpu_ctx_init(adev, priority, filp, ctx);
+ if (!amdgpu_sriov_vf(adev) && adev->gpu_preemption) {
+ resv_space_id = find_first_zero_bit(mgr->resv_vm_bitmap,
AMDGPU_VM_MAX_NUM_CTX);
+ if (resv_space_id < AMDGPU_VM_MAX_NUM_CTX)
+ __set_bit(resv_space_id,
[PATCH 3/3] drm/amdgpu: Use dynamical reserved vm size
Use dynamical reserved vm size instand of hardcode.
driver always reserve AMDGPU_VA_RESERVED_SIZE at the
bottom of VM space.
when gpu_preemption enabled, reserve
AMDGPU_VA_RESERVED_SIZ * AMDGPU_VM_MAX_NUM_CTX at
the top of VM space. if disabled,
reserve AMDGPU_VA_RESERVED_SIZE at the top.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 8
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 10 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
10 files changed, 27 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 3ef5c3e..abd0f8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1026,6 +1026,8 @@ struct amdgpu_device {
unsigned long last_mm_index;
boolin_gpu_reset;
struct mutex lock_reset;
+ /* gpu_preemption */
+ boolgpu_preemption;
};
static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
index 44b046f..fea4555 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
@@ -24,6 +24,14 @@
#include "amdgpu.h"
+uint64_t amdgpu_get_reserved_csa_size(struct amdgpu_device *adev)
+{
+ if (adev->gpu_preemption)
+ return AMDGPU_VA_RESERVED_SIZE * AMDGPU_VM_MAX_NUM_CTX;
+ else
+ return AMDGPU_VA_RESERVED_SIZE;
+}
+
uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id)
{
uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
index aaf1fba..7159d6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
@@ -27,6 +27,7 @@
#define AMDGPU_CSA_SIZE(128 * 1024)
+uint64_t amdgpu_get_reserved_csa_size(struct amdgpu_device *adev);
uint32_t amdgpu_get_total_csa_size(struct amdgpu_device *adev);
uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id);
int amdgpu_allocate_static_csa(struct amdgpu_device *adev, struct amdgpu_bo
**bo,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 7b3d1eb..4c12de8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -557,6 +557,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
struct ww_acquire_ctx ticket;
struct list_head list, duplicates;
uint64_t va_flags;
+ uint64_t va_reserved, va_top;
int r = 0;
if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
@@ -565,6 +566,15 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
args->va_address, AMDGPU_VA_RESERVED_SIZE);
return -EINVAL;
}
+ va_top = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
+ va_reserved = va_top - adev->vm_manager.reserved_vm_size;
+
+ if (args->va_address > va_reserved && args->va_address < va_top) {
+ dev_dbg(>pdev->dev,
+ "va_address 0x%LX is in reserved area 0x%LX\n",
+ args->va_address, adev->vm_manager.reserved_vm_size);
+ return -EINVAL;
+ }
if (args->va_address >= AMDGPU_GMC_HOLE_START &&
args->va_address < AMDGPU_GMC_HOLE_END) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 808d6d1..2cd9a0e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -702,7 +702,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file
dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
- vm_size -= AMDGPU_VA_RESERVED_SIZE;
+ vm_size -= adev->vm_manager.reserved_vm_size;
/* Older VCE FW versions are buggy and can handle only 40bits */
if (adev->vce.fw_version &&
@@ -977,7 +977,6 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
goto error_vm;
}
-
if (amdgpu_sriov_vf(adev)) {
uint64_t csa_addr = amdgpu_csa_vaddr(adev, 1) &
AMD
[PATCH 2/3] drm/amdgpu: Refine function amdgpu_csa_vaddr
Add a function argument: ctx_id,
so can find the vaddr via ctx_id.
In Sriov, the id always is 1.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
index 0c590dd..44b046f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
@@ -24,11 +24,12 @@
#include "amdgpu.h"
-uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
+uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id)
{
uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
- addr -= AMDGPU_VA_RESERVED_SIZE;
+ addr -= AMDGPU_VA_RESERVED_SIZE * id;
+
addr = amdgpu_gmc_sign_extend(addr);
return addr;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
index 524b443..aaf1fba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
@@ -28,7 +28,7 @@
#define AMDGPU_CSA_SIZE(128 * 1024)
uint32_t amdgpu_get_total_csa_size(struct amdgpu_device *adev);
-uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev);
+uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id);
int amdgpu_allocate_static_csa(struct amdgpu_device *adev, struct amdgpu_bo
**bo,
u32 domain, uint32_t size);
int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 19d01fe..808d6d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -977,9 +977,9 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
goto error_vm;
}
- if (amdgpu_sriov_vf(adev)) {
- uint64_t csa_addr = amdgpu_csa_vaddr(adev) &
AMDGPU_GMC_HOLE_MASK;
+ if (amdgpu_sriov_vf(adev)) {
+ uint64_t csa_addr = amdgpu_csa_vaddr(adev, 1) &
AMDGPU_GMC_HOLE_MASK;
r = amdgpu_map_static_csa(adev, >vm, adev->virt.csa_obj,
>csa_va, csa_addr,
AMDGPU_CSA_SIZE);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 31d2b01..0b2a3c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -7214,11 +7214,11 @@ static void gfx_v8_0_ring_emit_ce_meta(struct
amdgpu_ring *ring)
} ce_payload = {};
if (ring->adev->virt.chained_ib_support) {
- ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
+ ce_payload_addr = amdgpu_csa_vaddr(ring->adev, 1) +
offsetof(struct vi_gfx_meta_data_chained_ib,
ce_payload);
cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
} else {
- ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
+ ce_payload_addr = amdgpu_csa_vaddr(ring->adev, 1) +
offsetof(struct vi_gfx_meta_data, ce_payload);
cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2;
}
@@ -7242,7 +7242,7 @@ static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring
*ring)
struct vi_de_ib_state_chained_ib chained;
} de_payload = {};
- csa_addr = amdgpu_csa_vaddr(ring->adev);
+ csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
gds_addr = csa_addr + 4096;
if (ring->adev->virt.chained_ib_support) {
de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 93f7f5a..747fe03 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4350,7 +4350,7 @@ static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring
*ring)
int cnt;
cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
- csa_addr = amdgpu_csa_vaddr(ring->adev);
+ csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
@@ -4368,7 +4368,7 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring
*ring)
uint64_t csa_addr, gds_addr;
int cnt;
- csa_addr = amdgpu_csa_vaddr(ring->adev);
+ csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
gds_addr = csa_addr + 4096;
de_payload.gds_backup_addrlo = lo
[PATCH 1/3] drm/amdgpu: Limit vm max ctx number to 4096
driver need to reserve resource for each ctx for
some hw features. so add this limitation.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 33f5f2c..3ef5c3e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -161,6 +161,7 @@ struct amdgpu_mgpu_info
extern int amdgpu_cik_support;
#endif
+#define AMDGPU_VM_MAX_NUM_CTX 4096
#define AMDGPU_SG_THRESHOLD(256*1024*1024)
#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index f9b5423..8edf54b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -247,7 +247,7 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
return -ENOMEM;
mutex_lock(>lock);
- r = idr_alloc(>ctx_handles, ctx, 1, 0, GFP_KERNEL);
+ r = idr_alloc(>ctx_handles, ctx, 1, AMDGPU_VM_MAX_NUM_CTX,
GFP_KERNEL);
if (r < 0) {
mutex_unlock(>lock);
kfree(ctx);
--
1.9.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2] drm/amdgpu: Implement cond_exec for sdma3/4
the cond_exec is needed by sdma mid command buffer
preemption
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 31 +++
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 28
2 files changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 9a892f8..8bfc68d 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -500,6 +500,34 @@ static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring
*ring, u64 addr, u64 se
amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
}
+static unsigned sdma_v3_0_ring_init_cond_exec(struct amdgpu_ring *ring)
+{
+ unsigned ret;
+
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
+ amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
+ amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
+ amdgpu_ring_write(ring, 1);
+ ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch
later */
+ amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it
later */
+ return ret;
+}
+
+static void sdma_v3_0_ring_patch_cond_exec(struct amdgpu_ring *ring, unsigned
offset)
+{
+ unsigned cur;
+
+ BUG_ON(offset > ring->buf_mask);
+ BUG_ON(ring->ring[offset] != 0x55aa55aa);
+
+ cur = ring->wptr - 1;
+ if (likely(cur > offset))
+ ring->ring[offset] = cur - offset;
+ else
+ ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
+}
+
+
/**
* sdma_v3_0_gfx_stop - stop the gfx async dma engines
*
@@ -1597,6 +1625,7 @@ static void sdma_v3_0_get_clockgating_state(void *handle,
u32 *flags)
.get_wptr = sdma_v3_0_ring_get_wptr,
.set_wptr = sdma_v3_0_ring_set_wptr,
.emit_frame_size =
+ 5 + /* sdma_v3_0_ring_init_cond_exec */
6 + /* sdma_v3_0_ring_emit_hdp_flush */
3 + /* hdp invalidate */
6 + /* sdma_v3_0_ring_emit_pipeline_sync */
@@ -1613,6 +1642,8 @@ static void sdma_v3_0_get_clockgating_state(void *handle,
u32 *flags)
.insert_nop = sdma_v3_0_ring_insert_nop,
.pad_ib = sdma_v3_0_ring_pad_ib,
.emit_wreg = sdma_v3_0_ring_emit_wreg,
+ .init_cond_exec = sdma_v3_0_ring_init_cond_exec,
+ .patch_cond_exec = sdma_v3_0_ring_patch_cond_exec,
};
static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 51e1d1a..64fa6be 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -609,6 +609,31 @@ static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring
*ring, u64 addr, u64 se
amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
}
+static unsigned sdma_v4_0_ring_init_cond_exec(struct amdgpu_ring *ring)
+{
+ unsigned ret;
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
+ amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
+ amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
+ amdgpu_ring_write(ring, 1);
+ ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch
later */
+ amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it
later */
+ return ret;
+}
+
+static void sdma_v4_0_ring_patch_cond_exec(struct amdgpu_ring *ring, unsigned
offset)
+{
+ unsigned cur;
+
+ BUG_ON(offset > ring->buf_mask);
+ BUG_ON(ring->ring[offset] != 0x55aa55aa);
+
+ cur = ring->wptr - 1;
+ if (likely(cur > offset))
+ ring->ring[offset] = cur - offset;
+ else
+ ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
+}
/**
* sdma_v4_0_gfx_stop - stop the gfx async dma engines
@@ -1933,6 +1958,7 @@ static void sdma_v4_0_get_clockgating_state(void *handle,
u32 *flags)
.get_wptr = sdma_v4_0_ring_get_wptr,
.set_wptr = sdma_v4_0_ring_set_wptr,
.emit_frame_size =
+ 5 + /* sdma_v4_0_ring_init_cond_exec */
6 + /* sdma_v4_0_ring_emit_hdp_flush */
3 + /* hdp invalidate */
6 + /* sdma_v4_0_ring_emit_pipeline_sync */
@@ -1953,6 +1979,8 @@ static void sdma_v4_0_get_clockgating_state(void *handle,
u32 *flags)
.emit_wreg = sdma_v4_0_ring_emit_wreg,
.emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ .init_cond_exec = sdma_v4_0_ring_init_cond_exec,
+ .patch_cond_exec = sdma_v4_0_ring_patch_cond_exec,
};
static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
--
1.9.1
[PATCH 2/2] drm/amdgpu: Add helper function amdgpu_ring_set_preempt_cond_exec
can preempt the ring by setting cond_exec to false
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index ef7252a..54ca8a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -266,6 +266,12 @@ void amdgpu_ring_emit_reg_write_reg_wait_helper(struct
amdgpu_ring *ring,
bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
struct dma_fence *fence);
+static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring,
+ bool cond_exec)
+{
+ *ring->cond_exe_cpu_addr = cond_exec;
+}
+
static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
{
int i = 0;
--
1.9.1
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[PATCH v3] drm/amdgpu: Modify the argument of emit_ib interface
use the point of struct amdgpu_job as the function
argument instand of vmid, so the other members of
struct amdgpu_job can be visit in emit_ib function.
v2: add a wrapper for getting the VMID
add the job before the ib on the parameter list.
v3: refine the wrapper name
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 6 --
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 4 ++--
drivers/gpu/drm/amd/amdgpu/cik_sdma.c| 4 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c| 4 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c| 10 +++---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 10 +++---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 26 +++---
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 5 -
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 -
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 7 +--
drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c| 11 +--
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c| 10 --
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c| 6 +-
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c| 6 --
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c| 18 +-
21 files changed, 106 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index b8963b7..ba277cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -221,8 +221,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
!amdgpu_sriov_vf(adev)) /* for SRIOV preemption,
Preamble CE ib must be inserted anyway */
continue;
- amdgpu_ring_emit_ib(ring, ib, job ? job->vmid : 0,
- need_ctx_switch);
+ amdgpu_ring_emit_ib(ring, job, ib, need_ctx_switch);
need_ctx_switch = false;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
index 57cfe78..e1b46a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
@@ -33,6 +33,8 @@
#define to_amdgpu_job(sched_job) \
container_of((sched_job), struct amdgpu_job, base)
+#define AMDGPU_JOB_GET_VMID(job) ((job) ? (job)->vmid : 0)
+
struct amdgpu_fence;
struct amdgpu_job {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 4caa301..ef7252a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -129,8 +129,9 @@ struct amdgpu_ring_funcs {
unsigned emit_ib_size;
/* command emit functions */
void (*emit_ib)(struct amdgpu_ring *ring,
+ struct amdgpu_job *job,
struct amdgpu_ib *ib,
- unsigned vmid, bool ctx_switch);
+ bool ctx_switch);
void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
uint64_t seq, unsigned flags);
void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
@@ -229,7 +230,7 @@ struct amdgpu_ring {
#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
-#define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib),
(vmid), (c))
+#define amdgpu_ring_emit_ib(r, job, ib, c) ((r)->funcs->emit_ib((r), (job),
(ib), (c)))
#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
#define amdgpu_ring_emit_vm_flush(r, vmid, addr)
(r)->funcs->emit_vm_flush((r), (vmid), (addr))
#define amdgpu_ring_emit_fence(r, addr, seq, flags)
(r)->funcs->emit_fence((r), (addr), (seq), (flags))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 5f3f540..56675ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -1032,8 +1032,10 @@ int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser
*p, uint32_t ib_idx)
* @ib: the IB to execute
*
*/
-void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
-unsigned vmid, bool ctx_switch)
+void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring,
+ struct amdgpu_job *job,
+ struct amdgpu_ib *ib,
+ bool ctx_switch)
{
amdgpu_ring_write(ring, VCE_CMD_IB);
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_add
[PATCH] drm/amd/pp: Fix pp_sclk/mclk_od not work on smu7
not update the dpm table with user's setting
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 6c99cbf..71cfbd4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3588,9 +3588,10 @@ static int
smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
break;
}
- if (i >= sclk_table->count)
+ if (i >= sclk_table->count) {
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
- else {
+ sclk_table->dpm_levels[i].value = sclk;
+ } else {
/* TODO: Check SCLK in DAL's minimum clocks
* in case DeepSleep divider update is required.
*/
@@ -3605,9 +3606,10 @@ static int
smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
break;
}
- if (i >= mclk_table->count)
+ if (i >= mclk_table->count) {
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
-
+ mclk_table->dpm_levels[i-1].value = mclk;
+ }
if (data->display_timing.num_existing_displays !=
hwmgr->display_config->num_display)
data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
--
1.9.1
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[PATCH] drm/amdgpu: Change AMDGPU_CSA_SIZE to 128K
In order to support new asics and MCBP feature enablement on baremetal. Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h index ef2dfb0..524b443 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h @@ -25,7 +25,7 @@ #ifndef AMDGPU_CSA_MANAGER_H #define AMDGPU_CSA_MANAGER_H -#define AMDGPU_CSA_SIZE(8 * 1024) +#define AMDGPU_CSA_SIZE(128 * 1024) uint32_t amdgpu_get_total_csa_size(struct amdgpu_device *adev); uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev); -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: Limit vm max ctx number to 4096
driver need to reserve resource for each ctx for
some hw features. so add this limitation.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 33f5f2c..26f11eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -161,6 +161,7 @@ struct amdgpu_mgpu_info
extern int amdgpu_cik_support;
#endif
+#define VM_MAX_NUM_CTX 4096
#define AMDGPU_SG_THRESHOLD(256*1024*1024)
#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index f9b5423..08b47dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -247,7 +247,7 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
return -ENOMEM;
mutex_lock(>lock);
- r = idr_alloc(>ctx_handles, ctx, 1, 0, GFP_KERNEL);
+ r = idr_alloc(>ctx_handles, ctx, 1, VM_MAX_NUM_CTX, GFP_KERNEL);
if (r < 0) {
mutex_unlock(>lock);
kfree(ctx);
--
1.9.1
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[PATCH v2] drm/amdgpu: Modify the argument of emit_ib interface
use the point of struct amdgpu_job as the function
argument instand of vmid, so the other members of
struct amdgpu_job can be visit in emit_ib function.
v2: add a wrapper for getting the VMID
add the job before the ib on the parameter list.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 6 --
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 4 ++--
drivers/gpu/drm/amd/amdgpu/cik_sdma.c| 4 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c| 4 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c| 10 +++---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 10 +++---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 26 +++---
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 5 -
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 -
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 7 +--
drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c| 11 +--
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c| 10 --
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c| 6 +-
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c| 6 --
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c| 18 +-
21 files changed, 106 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index b8963b7..ba277cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -221,8 +221,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
!amdgpu_sriov_vf(adev)) /* for SRIOV preemption,
Preamble CE ib must be inserted anyway */
continue;
- amdgpu_ring_emit_ib(ring, ib, job ? job->vmid : 0,
- need_ctx_switch);
+ amdgpu_ring_emit_ib(ring, job, ib, need_ctx_switch);
need_ctx_switch = false;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
index 57cfe78..a71fe22 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
@@ -33,6 +33,8 @@
#define to_amdgpu_job(sched_job) \
container_of((sched_job), struct amdgpu_job, base)
+#define GET_VMID(job) ((job) ? (job)->vmid : 0)
+
struct amdgpu_fence;
struct amdgpu_job {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 4caa301..ef7252a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -129,8 +129,9 @@ struct amdgpu_ring_funcs {
unsigned emit_ib_size;
/* command emit functions */
void (*emit_ib)(struct amdgpu_ring *ring,
+ struct amdgpu_job *job,
struct amdgpu_ib *ib,
- unsigned vmid, bool ctx_switch);
+ bool ctx_switch);
void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
uint64_t seq, unsigned flags);
void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
@@ -229,7 +230,7 @@ struct amdgpu_ring {
#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
-#define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib),
(vmid), (c))
+#define amdgpu_ring_emit_ib(r, job, ib, c) ((r)->funcs->emit_ib((r), (job),
(ib), (c)))
#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
#define amdgpu_ring_emit_vm_flush(r, vmid, addr)
(r)->funcs->emit_vm_flush((r), (vmid), (addr))
#define amdgpu_ring_emit_fence(r, addr, seq, flags)
(r)->funcs->emit_fence((r), (addr), (seq), (flags))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 5f3f540..56675ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -1032,8 +1032,10 @@ int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser
*p, uint32_t ib_idx)
* @ib: the IB to execute
*
*/
-void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
-unsigned vmid, bool ctx_switch)
+void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring,
+ struct amdgpu_job *job,
+ struct amdgpu_ib *ib,
+ bool ctx_switch)
{
amdgpu_ring_write(ring, VCE_CMD_IB);
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
diff --git a/drivers/gpu/
[PATCH v2] drm/amdgpu: Patch csa mc address in IB packet
the csa buffer is used by sdma engine to do context
save when preemption happens. it the mc address is zero,
mean the preemtpion feature(MCBP) is disabled.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 2 ++
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 8 ++--
4 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index 0fb9907..24b80bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -40,3 +40,16 @@ struct amdgpu_sdma_instance *
amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
return NULL;
}
+
+int amdgpu_get_sdma_index(struct amdgpu_ring *ring, uint32_t *index)
+{
+ struct amdgpu_device *adev = ring->adev;
+ int i;
+
+ for (i = 0; i < adev->sdma.num_instances; i++)
+ if (ring == >sdma.instance[i].ring ||
+ ring == >sdma.instance[i].page)
+ return i;
+
+ return -EINVAL;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index 479a245..314078a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -26,6 +26,7 @@
/* max number of IP instances */
#define AMDGPU_MAX_SDMA_INSTANCES 2
+#define AMDGPU_SDMA_CSA_SIZE (1024)
enum amdgpu_sdma_irq {
AMDGPU_SDMA_IRQ_TRAP0 = 0,
@@ -96,4 +97,5 @@ struct amdgpu_buffer_funcs {
struct amdgpu_sdma_instance *
amdgpu_get_sdma_instance(struct amdgpu_ring *ring);
+int amdgpu_get_sdma_index(struct amdgpu_ring *ring, uint32_t *index);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index f5e6aa2..fdc5d75 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -424,7 +424,11 @@ static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring
*ring,
bool ctx_switch)
{
unsigned vmid = GET_VMID(job);
+ uint64_t csa_mc_addr = job ? job->csa_mc_addr : 0;
+ uint32_t i = 0;
+ if (amdgpu_get_sdma_index(ring, ))
+ return -EINVAL;
/* IB packet must end on a 8 DW boundary */
sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7))
% 8);
@@ -434,8 +438,8 @@ static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffe0);
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
amdgpu_ring_write(ring, ib->length_dw);
- amdgpu_ring_write(ring, 0);
- amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr + i *
AMDGPU_SDMA_CSA_SIZE));
+ amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr + i *
AMDGPU_SDMA_CSA_SIZE));
}
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 2282ac1..e69a584 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -507,7 +507,11 @@ static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring
*ring,
bool ctx_switch)
{
unsigned vmid = GET_VMID(job);
+ uint64_t csa_mc_addr = job ? job->csa_mc_addr : 0;
+ uint32_t i = 0;
+ if (amdgpu_get_sdma_index(ring, ))
+ return -EINVAL;
/* IB packet must end on a 8 DW boundary */
sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7))
% 8);
@@ -517,8 +521,8 @@ static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffe0);
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
amdgpu_ring_write(ring, ib->length_dw);
- amdgpu_ring_write(ring, 0);
- amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr + i *
AMDGPU_SDMA_CSA_SIZE));
+ amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr + i *
AMDGPU_SDMA_CSA_SIZE));
}
--
1.9.1
___
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[PATCH] drm/amdgpu: Modify the argument of emit_ib interface
use the point of struct amdgpu_job as the function
argument instand of vmid, so the other members of
struct amdgpu_job can be visit in emit_ib function.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 2 +-
drivers/gpu/drm/amd/amdgpu/cik_sdma.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c| 6 --
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 6 --
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 24 +---
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/si_dma.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c| 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c| 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c| 8 ++--
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c| 7 +--
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c| 4 +++-
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c| 4 +++-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c| 10 +++---
20 files changed, 66 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index b8963b7..0b227ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -221,8 +221,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
!amdgpu_sriov_vf(adev)) /* for SRIOV preemption,
Preamble CE ib must be inserted anyway */
continue;
- amdgpu_ring_emit_ib(ring, ib, job ? job->vmid : 0,
- need_ctx_switch);
+ amdgpu_ring_emit_ib(ring, ib, job, need_ctx_switch);
need_ctx_switch = false;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 3cb7fb8..0f0f8fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -229,7 +229,7 @@ struct amdgpu_ring {
#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
-#define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib),
(vmid), (c))
+#define amdgpu_ring_emit_ib(r, ib, job, c) ((r)->funcs->emit_ib((r), (ib),
(job), (c)))
#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
#define amdgpu_ring_emit_vm_flush(r, vmid, addr)
(r)->funcs->emit_vm_flush((r), (vmid), (addr))
#define amdgpu_ring_emit_fence(r, addr, seq, flags)
(r)->funcs->emit_fence((r), (addr), (seq), (flags))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 84dd550..8f98641 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -1032,7 +1032,7 @@ int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser
*p, uint32_t ib_idx)
*
*/
void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
-unsigned vmid, bool ctx_switch)
+ struct amdgpu_job *job, bool ctx_switch)
{
amdgpu_ring_write(ring, VCE_CMD_IB);
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
index a1f209e..06d6d87 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
@@ -66,7 +66,7 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring,
uint32_t handle,
int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx);
int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx);
void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
-unsigned vmid, bool ctx_switch);
+ struct amdgpu_job *job, bool ctx_switch);
void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
unsigned flags);
int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 32eb43d..70d4419 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -219,8 +219,9 @@ static void cik_sdma_ring_insert_nop(struct amdgpu_ring
*ring, uint32_t count)
*/
static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
struct amdgpu_ib *ib,
- unsigned vmid, bool ctx_switch)
+
[PATCH] drm/amdgpu: Fix amdgpu_vm_alloc_pts failed
when the VA address located in the last PD entries,
the alloc_pts will faile.
Use the right PD mask instand of hardcode, suggested
by jerry.zhang.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 054633b..3939013 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -202,8 +202,11 @@ static unsigned amdgpu_vm_num_entries(struct amdgpu_device
*adev,
static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
unsigned int level)
{
+ unsigned shift = amdgpu_vm_level_shift(adev,
+ adev->vm_manager.root_level);
+
if (level <= adev->vm_manager.root_level)
- return 0x;
+ return (round_up(adev->vm_manager.max_pfn, 1 << shift) >>
shift) - 1;
else if (level != AMDGPU_VM_PTB)
return 0x1ff;
else
--
1.9.1
___
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[PATCH] drm/amdgpu: Fix amdgpu_vm_alloc_pts failed
When the va address located in the last pd entry,
the alloc_pts will failed.
caused by
"drm/amdgpu: add amdgpu_vm_entries_mask v2"
commit 72af632549b97ead9251bb155f08fefd1fb6f5c3.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 +++---
1 file changed, 7 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 054633b..1a3af72 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -191,26 +191,6 @@ static unsigned amdgpu_vm_num_entries(struct amdgpu_device
*adev,
}
/**
- * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
- *
- * @adev: amdgpu_device pointer
- * @level: VMPT level
- *
- * Returns:
- * The mask to extract the entry number of a PD/PT from an address.
- */
-static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
- unsigned int level)
-{
- if (level <= adev->vm_manager.root_level)
- return 0x;
- else if (level != AMDGPU_VM_PTB)
- return 0x1ff;
- else
- return AMDGPU_VM_PTE_COUNT(adev) - 1;
-}
-
-/**
* amdgpu_vm_bo_size - returns the size of the BOs in bytes
*
* @adev: amdgpu_device pointer
@@ -419,17 +399,17 @@ static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
struct amdgpu_vm_pt_cursor *cursor)
{
- unsigned mask, shift, idx;
+ unsigned num_entries, shift, idx;
if (!cursor->entry->entries)
return false;
BUG_ON(!cursor->entry->base.bo);
- mask = amdgpu_vm_entries_mask(adev, cursor->level);
+ num_entries = amdgpu_vm_num_entries(adev, cursor->level);
shift = amdgpu_vm_level_shift(adev, cursor->level);
++cursor->level;
- idx = (cursor->pfn >> shift) & mask;
+ idx = (cursor->pfn >> shift) % num_entries;
cursor->parent = cursor->entry;
cursor->entry = >entry->entries[idx];
return true;
@@ -1618,7 +1598,7 @@ static int amdgpu_vm_update_ptes(struct
amdgpu_pte_update_params *params,
amdgpu_vm_pt_start(adev, params->vm, start, );
while (cursor.pfn < end) {
struct amdgpu_bo *pt = cursor.entry->base.bo;
- unsigned shift, parent_shift, mask;
+ unsigned shift, parent_shift, num_entries;
uint64_t incr, entry_end, pe_start;
if (!pt)
@@ -1673,9 +1653,9 @@ static int amdgpu_vm_update_ptes(struct
amdgpu_pte_update_params *params,
/* Looks good so far, calculate parameters for the update */
incr = AMDGPU_GPU_PAGE_SIZE << shift;
- mask = amdgpu_vm_entries_mask(adev, cursor.level);
- pe_start = ((cursor.pfn >> shift) & mask) * 8;
- entry_end = (mask + 1) << shift;
+ num_entries = amdgpu_vm_num_entries(adev, cursor.level);
+ pe_start = ((cursor.pfn >> shift) & (num_entries - 1)) * 8;
+ entry_end = num_entries << shift;
entry_end += cursor.pfn & ~(entry_end - 1);
entry_end = min(entry_end, end);
--
1.9.1
___
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[PATCH] drm/amdgpu: Reverse the sequence of ctx_mgr_fini and vm_fini in amdgpu_driver_postclose_kms
csa buffer will be created per ctx, when ctx fini, the csa buffer and va will be released. so need to do ctx_mgr fin before vm fini. Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 27de848..f2ef9a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1054,8 +1054,8 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, pasid = fpriv->vm.pasid; pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); - amdgpu_vm_fini(adev, >vm); amdgpu_ctx_mgr_fini(>ctx_mgr); + amdgpu_vm_fini(adev, >vm); if (pasid) amdgpu_pasid_free_delayed(pd->tbo.resv, pasid); -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amdgpu: Fix null point errro
need to check adev->powerplay.pp_funcs first, becasue from
AI, the smu ip may be disabled by user, and the pp_handle
is null in this case.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c| 6 --
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 2 +-
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c| 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 --
5 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 297a549..0a4fba1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -135,7 +135,8 @@ static int acp_poweroff(struct generic_pm_domain *genpd)
* 2. power off the acp tiles
* 3. check and enter ulv state
*/
- if (adev->powerplay.pp_funcs->set_powergating_by_smu)
+ if (adev->powerplay.pp_funcs &&
+ adev->powerplay.pp_funcs->set_powergating_by_smu)
amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_ACP, true);
}
return 0;
@@ -517,7 +518,8 @@ static int acp_set_powergating_state(void *handle,
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
bool enable = state == AMD_PG_STATE_GATE ? true : false;
- if (adev->powerplay.pp_funcs->set_powergating_by_smu)
+ if (adev->powerplay.pp_funcs &&
+ adev->powerplay.pp_funcs->set_powergating_by_smu)
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP,
enable);
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 4fca67a..7dad682 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1783,6 +1783,7 @@ static int amdgpu_device_set_pg_state(struct
amdgpu_device *adev, enum amd_power
adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCE ||
adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN ||
adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP)
&&
+ adev->powerplay.pp_funcs &&
adev->powerplay.pp_funcs->set_powergating_by_smu) {
if (!adev->ip_blocks[i].status.valid) {
amdgpu_dpm_set_powergating_by_smu(adev,
adev->ip_blocks[i].version->type, state == AMD_PG_STATE_GATE ?
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 790fd54..1a656b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -392,7 +392,7 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool
enable)
if (!(adev->powerplay.pp_feature & PP_GFXOFF_MASK))
return;
- if (!adev->powerplay.pp_funcs->set_powergating_by_smu)
+ if (!adev->powerplay.pp_funcs ||
!adev->powerplay.pp_funcs->set_powergating_by_smu)
return;
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 14649f8..fd23ba1 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -280,7 +280,7 @@ void mmhub_v1_0_update_power_gating(struct amdgpu_device
*adev,
return;
if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) {
- if (adev->powerplay.pp_funcs->set_powergating_by_smu)
+ if (adev->powerplay.pp_funcs &&
adev->powerplay.pp_funcs->set_powergating_by_smu)
amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GMC, true);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 2e8365d..d97e6a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1595,7 +1595,8 @@ static int sdma_v4_0_hw_init(void *handle)
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- if (adev->asic_type == CHIP_RAVEN &&
adev->powerplay.pp_funcs->set_powergating_by_smu)
+ if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs &&
+ adev->powerplay.pp_funcs->set_powergating_by_smu)
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA,
false);
sdma_v4_0_init_golden_registers(adev);
@@ -1615,7 +1616,8 @@ static int sdma_v4_0_hw_fini(void *handle)
sdma_v4_0_ctx_switch_enable(adev, false);
sdma_v4_0_enable(adev, false);
- if (adev->asic_type == C
[PATCH 1/2] drm/amd/display: Fix Null point error if smu ip was disabled
from AI, SMU Ip is not indispensable to driver and can be
disabled by user via module parameter ip_block_mask.
so the pp_handle may be NULL.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 0fab64a..12001a0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -101,7 +101,7 @@ bool dm_pp_apply_display_requirements(
adev->pm.pm_display_cfg.displays[i].controller_id =
dc_cfg->pipe_idx + 1;
}
- if (adev->powerplay.pp_funcs->display_configuration_change)
+ if (adev->powerplay.pp_funcs &&
adev->powerplay.pp_funcs->display_configuration_change)
adev->powerplay.pp_funcs->display_configuration_change(
adev->powerplay.pp_handle,
>pm.pm_display_cfg);
@@ -304,7 +304,7 @@ bool dm_pp_get_clock_levels_by_type(
struct amd_pp_simple_clock_info validation_clks = { 0 };
uint32_t i;
- if (adev->powerplay.pp_funcs->get_clock_by_type) {
+ if (adev->powerplay.pp_funcs &&
adev->powerplay.pp_funcs->get_clock_by_type) {
if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle,
dc_to_pp_clock_type(clk_type), _clks)) {
/* Error in pplib. Provide default values. */
@@ -315,7 +315,7 @@ bool dm_pp_get_clock_levels_by_type(
pp_to_dc_clock_levels(_clks, dc_clks, clk_type);
- if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks) {
+ if (adev->powerplay.pp_funcs &&
adev->powerplay.pp_funcs->get_display_mode_validation_clocks) {
if
(adev->powerplay.pp_funcs->get_display_mode_validation_clocks(
pp_handle, _clks)) {
/* Error in pplib. Provide default values. */
@@ -398,6 +398,9 @@ bool dm_pp_get_clock_levels_by_type_with_voltage(
struct pp_clock_levels_with_voltage pp_clk_info = {0};
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+ if (!pp_funcs || !pp_funcs->get_clock_by_type_with_voltage)
+ return false;
+
if (pp_funcs->get_clock_by_type_with_voltage(pp_handle,
dc_to_pp_clock_type(clk_type),
_clk_info))
@@ -438,7 +441,7 @@ bool dm_pp_apply_clock_for_voltage_request(
if (!pp_clock_request.clock_type)
return false;
- if (adev->powerplay.pp_funcs->display_clock_voltage_request)
+ if (adev->powerplay.pp_funcs &&
adev->powerplay.pp_funcs->display_clock_voltage_request)
ret = adev->powerplay.pp_funcs->display_clock_voltage_request(
adev->powerplay.pp_handle,
_clock_request);
@@ -455,7 +458,7 @@ bool dm_pp_get_static_clocks(
struct amd_pp_clock_info pp_clk_info = {0};
int ret = 0;
- if (adev->powerplay.pp_funcs->get_current_clocks)
+ if (adev->powerplay.pp_funcs &&
adev->powerplay.pp_funcs->get_current_clocks)
ret = adev->powerplay.pp_funcs->get_current_clocks(
adev->powerplay.pp_handle,
_clk_info);
@@ -505,6 +508,9 @@ void pp_rv_set_wm_ranges(struct pp_smu *pp,
wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;
+ if (!pp_funcs || !pp_funcs->set_watermarks_for_clocks_ranges)
+ return;
+
for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {
if (ranges->reader_wm_sets[i].wm_inst > 3)
wm_dce_clocks[i].wm_set_id = WM_SET_A;
--
1.9.1
___
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[PATCH v2] drm/amdgpu: Poweroff uvd/vce/vcn/acp block if they were disabled by user
If user disable uvd/vce/vcn/acp blocks via module
parameter ip_block_mask,
driver power off thoser blocks to save power.
v2: power off uvd/vce/vcn/acp via smu.
Reviewed-by: Alex Deucher
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 6fe6ea9..ef9fe50 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1776,6 +1776,24 @@ static int amdgpu_device_set_pg_state(struct
amdgpu_device *adev, enum amd_power
for (j = 0; j < adev->num_ip_blocks; j++) {
i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j -
1;
+
+ /* try to power off VCE/UVD/VCN/ACP if they were disabled by
user */
+ if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_UVD
||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCE ||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN ||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP)
&&
+ adev->powerplay.pp_funcs->set_powergating_by_smu) {
+ if (!adev->ip_blocks[i].status.valid) {
+ amdgpu_dpm_set_powergating_by_smu(adev,
adev->ip_blocks[i].version->type, state == AMD_PG_STATE_GATE ?
+
true : false);
+ if (r) {
+ DRM_ERROR("set_powergating_state(gate)
of IP block <%s> failed %d\n",
+
adev->ip_blocks[i].version->funcs->name, r);
+ return r;
+ }
+ }
+ }
+
if (!adev->ip_blocks[i].status.late_initialized)
continue;
/* skip CG for VCE/UVD, it's handled specially */
@@ -1793,6 +1811,7 @@ static int amdgpu_device_set_pg_state(struct
amdgpu_device *adev, enum amd_power
}
}
}
+
return 0;
}
--
1.9.1
___
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[PATCH 3/3] drm/amdgpu: Move csa related functions to separate file
Those functions can be shared between SRIOV and baremetal
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_csa_manager.c | 117
drivers/gpu/drm/amd/amdgpu/amdgpu_csa_manager.h | 40
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c| 92 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h| 7 --
6 files changed, 159 insertions(+), 100 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_csa_manager.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_csa_manager.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 138cb78..0533d69 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -53,7 +53,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
- amdgpu_gmc.o amdgpu_xgmi.o
+ amdgpu_gmc.o amdgpu_xgmi.o amdgpu_csa_manager.o
# add asic specific block
amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8cd301f..eb2afe4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -75,6 +75,7 @@
#include "amdgpu_sdma.h"
#include "amdgpu_dm.h"
#include "amdgpu_virt.h"
+#include "amdgpu_csa_manager.h"
#include "amdgpu_gart.h"
#include "amdgpu_debugfs.h"
#include "amdgpu_job.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa_manager.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa_manager.c
new file mode 100644
index 000..7d0cc19
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa_manager.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+
+ * * Author: monk@amd.com
+ */
+
+#include "amdgpu.h"
+
+uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
+{
+ uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
+
+ addr -= AMDGPU_VA_RESERVED_SIZE;
+ addr = amdgpu_gmc_sign_extend(addr);
+
+ return addr;
+}
+
+int amdgpu_allocate_static_csa(struct amdgpu_device *adev, struct amdgpu_bo
*bo,
+ uint32_t size)
+{
+ int r;
+ void *ptr;
+
+ r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM, ,
+ NULL, );
+ if (!bo)
+ return -ENOMEM;
+
+ memset(ptr, 0, size);
+ return 0;
+}
+
+void amdgpu_free_static_csa(struct amdgpu_bo *bo)
+{
+ amdgpu_bo_free_kernel(, NULL, NULL);
+}
+
+/*
+ * amdgpu_map_static_csa should be called during amdgpu_vm_init
+ * it maps virtual address amdgpu_csa_vaddr() to this VM, and each command
+ * submission of GFX should use this virtual address within META_DATA init
+ * package to support SRIOV gfx preemption.
+ */
+int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ struct amdgpu_bo *bo, struct amdgpu_bo_va **bo_va,
+ uint64_t csa_addr)
+{
+ struct ww_acquire_ctx ticket;
+ struct list_head list;
+ struct amdgpu_bo_list_entry pd;
+ struct ttm_validate_buffer csa_tv;
+ int r;
+
+ INIT_LIST_HEAD();
+ INIT_LIST_HEAD(_tv.head);
+ csa_tv.bo = >tbo;
+ csa_tv.shared = true;
+
+ list_add(_tv.head, );
+ amdgpu_vm_get_pd_bo(vm, , );
+
+ r = ttm_eu_reserve_buffers(, , true, NULL);
+
[PATCH 2/3] drm/amdgpu: Refine CSA related functions
There is no functional changes,
Use function arguments for SRIOV special variables which
is hardcode in those functions.
so we can share those functions with os preemption in
baremetal.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 5 -
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 28 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 8 +---
4 files changed, 26 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3ffee08..20f36fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1658,7 +1658,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
/* right after GMC hw init, we create CSA */
if (amdgpu_sriov_vf(adev)) {
- r = amdgpu_allocate_static_csa(adev);
+ r = amdgpu_allocate_static_csa(adev,
adev->virt.csa_obj,
+
AMDGPU_CSA_SIZE);
if (r) {
DRM_ERROR("allocate CSA failed %d\n",
r);
return r;
@@ -1911,7 +1912,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device
*adev)
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
amdgpu_ucode_free_bo(adev);
- amdgpu_free_static_csa(adev);
+ amdgpu_free_static_csa(adev->virt.csa_obj);
amdgpu_device_wb_fini(adev);
amdgpu_device_vram_scratch_fini(adev);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 46e9d74..f5063ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -980,7 +980,10 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
}
if (amdgpu_sriov_vf(adev)) {
- r = amdgpu_map_static_csa(adev, >vm, >csa_va);
+ uint64_t csa_addr = amdgpu_csa_vaddr(adev) &
AMDGPU_GMC_HOLE_MASK;
+
+ r = amdgpu_map_static_csa(adev, >vm, adev->virt.csa_obj,
+ >csa_va, csa_addr);
if (r)
goto error_vm;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 9ff16b7..e4f2901 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -41,25 +41,25 @@ bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
return RREG32_NO_KIQ(0xc040) == 0x;
}
-int amdgpu_allocate_static_csa(struct amdgpu_device *adev)
+int amdgpu_allocate_static_csa(struct amdgpu_device *adev, struct amdgpu_bo
*bo,
+ uint32_t size)
{
int r;
void *ptr;
- r = amdgpu_bo_create_kernel(adev, AMDGPU_CSA_SIZE, PAGE_SIZE,
- AMDGPU_GEM_DOMAIN_VRAM, >virt.csa_obj,
+ r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM, ,
NULL, );
- if (r)
- return r;
+ if (!bo)
+ return -ENOMEM;
- memset(ptr, 0, AMDGPU_CSA_SIZE);
+ memset(ptr, 0, size);
return 0;
}
-void amdgpu_free_static_csa(struct amdgpu_device *adev) {
- amdgpu_bo_free_kernel(>virt.csa_obj,
- NULL,
- NULL);
+void amdgpu_free_static_csa(struct amdgpu_bo *bo)
+{
+ amdgpu_bo_free_kernel(, NULL, NULL);
}
/*
@@ -69,9 +69,9 @@ void amdgpu_free_static_csa(struct amdgpu_device *adev) {
* package to support SRIOV gfx preemption.
*/
int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- struct amdgpu_bo_va **bo_va)
+ struct amdgpu_bo *bo, struct amdgpu_bo_va **bo_va,
+ uint64_t csa_addr)
{
- uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
struct ww_acquire_ctx ticket;
struct list_head list;
struct amdgpu_bo_list_entry pd;
@@ -80,7 +80,7 @@ int amdgpu_map_static_csa(struct amdgpu_device *adev, struct
amdgpu_vm *vm,
INIT_LIST_HEAD();
INIT_LIST_HEAD(_tv.head);
- csa_tv.bo = >virt.csa_obj->tbo;
+ csa_tv.bo = >tbo;
csa_tv.shared = true;
list_add(_tv.head, );
@@ -92,7 +92,7 @@ int amdgpu_map_static_csa(struct amdgpu_device *adev, struct
amdgpu_vm *vm,
retu
[PATCH 1/3] drm/amdgpu: Remove useless csa gpu address in vmid0
driver didn't use this address so far.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 1 -
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index f2f358a..9ff16b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -48,7 +48,7 @@ int amdgpu_allocate_static_csa(struct amdgpu_device *adev)
r = amdgpu_bo_create_kernel(adev, AMDGPU_CSA_SIZE, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM, >virt.csa_obj,
- >virt.csa_vmid0_addr, );
+ NULL, );
if (r)
return r;
@@ -58,7 +58,7 @@ int amdgpu_allocate_static_csa(struct amdgpu_device *adev)
void amdgpu_free_static_csa(struct amdgpu_device *adev) {
amdgpu_bo_free_kernel(>virt.csa_obj,
- >virt.csa_vmid0_addr,
+ NULL,
NULL);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 880ac11..f1a6a50 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -238,7 +238,6 @@ struct amdgim_vf2pf_info_v2 {
struct amdgpu_virt {
uint32_tcaps;
struct amdgpu_bo*csa_obj;
- uint64_tcsa_vmid0_addr;
bool chained_ib_support;
uint32_treg_val_offs;
struct amdgpu_irq_src ack_irq;
--
1.9.1
___
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[PATCH] drm/amdgpu: Poweroff uvd/vce/vcn/acp block if they were disabled by user
If user disable uvd/vce/vcn/acp blocks via module
parameter ip_block_mask,
driver power off thoser blocks to save power.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1e4dd09..3ffee08 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1774,6 +1774,24 @@ static int amdgpu_device_set_pg_state(struct
amdgpu_device *adev, enum amd_power
for (j = 0; j < adev->num_ip_blocks; j++) {
i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j -
1;
+
+ /* try to power off VCE/UVD/VCN/ACP if they were disabled by
user */
+ if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_UVD
||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCE ||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN ||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP)
&&
+ adev->ip_blocks[i].version->funcs->set_powergating_state) {
+ if (!adev->ip_blocks[i].status.valid) {
+ r =
adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
+
state);
+ if (r) {
+ DRM_ERROR("set_powergating_state(gate)
of IP block <%s> failed %d\n",
+
adev->ip_blocks[i].version->funcs->name, r);
+ return r;
+ }
+ }
+ }
+
if (!adev->ip_blocks[i].status.late_initialized)
continue;
/* skip CG for VCE/UVD, it's handled specially */
@@ -1791,6 +1809,7 @@ static int amdgpu_device_set_pg_state(struct
amdgpu_device *adev, enum amd_power
}
}
}
+
return 0;
}
--
1.9.1
___
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[PATCH] drm/amdgpu: Fix typo in amdgpu_vmid_mgr_init
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index 3a072a7..df9b173 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -574,7 +574,7 @@ void amdgpu_vmid_mgr_init(struct amdgpu_device *adev)
/* skip over VMID 0, since it is the system VM */
for (j = 1; j < id_mgr->num_ids; ++j) {
amdgpu_vmid_reset(adev, i, j);
- amdgpu_sync_create(_mgr->ids[i].active);
+ amdgpu_sync_create(_mgr->ids[j].active);
list_add_tail(_mgr->ids[j].list, _mgr->ids_lru);
}
}
--
1.9.1
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[PATCH 2/3] drm/amdgpu: Load fw between hw_init/resume_phase1 and phase2
Extract the function of fw loading out of powerplay.
Do fw loading between hw_init/resuem_phase1 and phase2
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 61 +-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 ---
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 20 ---
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 -
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 8 +--
drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 5 --
7 files changed, 62 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 372574a..1e4dd09 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1570,6 +1570,47 @@ static int amdgpu_device_ip_hw_init_phase2(struct
amdgpu_device *adev)
return 0;
}
+static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
+{
+ int r = 0;
+ int i;
+
+ if (adev->asic_type >= CHIP_VEGA10) {
+ for (i = 0; i < adev->num_ip_blocks; i++) {
+ if (adev->ip_blocks[i].version->type ==
AMD_IP_BLOCK_TYPE_PSP) {
+ if (adev->in_gpu_reset || adev->in_suspend) {
+ if (amdgpu_sriov_vf(adev) &&
adev->in_gpu_reset)
+ break; /* sriov gpu reset, psp
need to do hw_init before IH because of hw limit */
+ r =
adev->ip_blocks[i].version->funcs->resume(adev);
+ if (r) {
+ DRM_ERROR("resume of IP block
<%s> failed %d\n",
+
adev->ip_blocks[i].version->funcs->name, r);
+ return r;
+ }
+ } else {
+ r =
adev->ip_blocks[i].version->funcs->hw_init(adev);
+ if (r) {
+ DRM_ERROR("hw_init of IP block
<%s> failed %d\n",
+
adev->ip_blocks[i].version->funcs->name, r);
+ return r;
+ }
+ }
+ adev->ip_blocks[i].status.hw = true;
+ }
+ }
+ }
+
+ if (adev->powerplay.pp_funcs->load_firmware) {
+ r =
adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
+ if (r) {
+ pr_err("firmware loading failed\n");
+ return r;
+ }
+ }
+
+ return 0;
+}
+
/**
* amdgpu_device_ip_init - run init for hardware IPs
*
@@ -1634,6 +1675,10 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
if (r)
return r;
+ r = amdgpu_device_fw_loading(adev);
+ if (r)
+ return r;
+
r = amdgpu_device_ip_hw_init_phase2(adev);
if (r)
return r;
@@ -2167,7 +2212,8 @@ static int amdgpu_device_ip_resume_phase2(struct
amdgpu_device *adev)
continue;
if (adev->ip_blocks[i].version->type ==
AMD_IP_BLOCK_TYPE_COMMON ||
adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
- adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
continue;
r = adev->ip_blocks[i].version->funcs->resume(adev);
if (r) {
@@ -2199,6 +2245,11 @@ static int amdgpu_device_ip_resume(struct amdgpu_device
*adev)
r = amdgpu_device_ip_resume_phase1(adev);
if (r)
return r;
+
+ r = amdgpu_device_fw_loading(adev);
+ if (r)
+ return r;
+
r = amdgpu_device_ip_resume_phase2(adev);
return r;
@@ -3149,6 +3200,10 @@ static int amdgpu_device_reset(struct amdgpu_device
*adev)
if (r)
goto out;
+ r = amdgpu_device_fw_loading(adev);
+ if (r)
+ return r;
+
r = amdgpu_device_ip_resume_phase2(adev);
if (r)
goto out;
@@ -3205,6 +3260,10 @@ static int amdgpu_
[PATCH 3/3] drm/amdgpu: Remove wrong fw loading type warning
Remove the warning message:
"-1 is not supported on VI"
the -1 is the default fw load type, mean auto.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 971549f..d91f378 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -297,8 +297,6 @@ enum amdgpu_firmware_load_type
case CHIP_POLARIS11:
case CHIP_POLARIS12:
case CHIP_VEGAM:
- if (load_type != AMDGPU_FW_LOAD_SMU)
- pr_warning("%d is not supported on VI\n", load_type);
return AMDGPU_FW_LOAD_SMU;
case CHIP_VEGA10:
case CHIP_RAVEN:
--
1.9.1
___
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[PATCH 1/3] drm/amdgpu: split ip hw_init into 2 phases
We need to do some IPs earlier to deal with ordering issues
similar to how resume is split into two phases.
Do fw loading via smu/psp between the two phases.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 66 --
1 file changed, 53 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 680df05..372574a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1525,6 +1525,51 @@ static int amdgpu_device_ip_early_init(struct
amdgpu_device *adev)
return 0;
}
+static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
+{
+ int i, r;
+
+ for (i = 0; i < adev->num_ip_blocks; i++) {
+ if (!adev->ip_blocks[i].status.sw)
+ continue;
+ if (adev->ip_blocks[i].status.hw)
+ continue;
+ if (adev->ip_blocks[i].version->type ==
AMD_IP_BLOCK_TYPE_COMMON ||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
+ r = adev->ip_blocks[i].version->funcs->hw_init(adev);
+ if (r) {
+ DRM_ERROR("hw_init of IP block <%s> failed
%d\n",
+
adev->ip_blocks[i].version->funcs->name, r);
+ return r;
+ }
+ adev->ip_blocks[i].status.hw = true;
+ }
+ }
+
+ return 0;
+}
+
+static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
+{
+ int i, r;
+
+ for (i = 0; i < adev->num_ip_blocks; i++) {
+ if (!adev->ip_blocks[i].status.sw)
+ continue;
+ if (adev->ip_blocks[i].status.hw)
+ continue;
+ r = adev->ip_blocks[i].version->funcs->hw_init(adev);
+ if (r) {
+ DRM_ERROR("hw_init of IP block <%s> failed %d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
+ return r;
+ }
+ adev->ip_blocks[i].status.hw = true;
+ }
+
+ return 0;
+}
+
/**
* amdgpu_device_ip_init - run init for hardware IPs
*
@@ -1584,19 +1629,14 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init
complete*/
if (r)
return r;
- for (i = 0; i < adev->num_ip_blocks; i++) {
- if (!adev->ip_blocks[i].status.sw)
- continue;
- if (adev->ip_blocks[i].status.hw)
- continue;
- r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
- if (r) {
- DRM_ERROR("hw_init of IP block <%s> failed %d\n",
- adev->ip_blocks[i].version->funcs->name, r);
- return r;
- }
- adev->ip_blocks[i].status.hw = true;
- }
+
+ r = amdgpu_device_ip_hw_init_phase1(adev);
+ if (r)
+ return r;
+
+ r = amdgpu_device_ip_hw_init_phase2(adev);
+ if (r)
+ return r;
amdgpu_xgmi_add_device(adev);
amdgpu_amdkfd_device_init(adev);
--
1.9.1
___
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[PATCH v2 4/5] drm/amdgpu: Fix unnecessary warning in dmesg
Fix the warning message:
"-1 is not supported on VI"
the -1 is the default fw load type, mean auto.
v2: fix typo
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 971549f..01d794d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -297,7 +297,7 @@ enum amdgpu_firmware_load_type
case CHIP_POLARIS11:
case CHIP_POLARIS12:
case CHIP_VEGAM:
- if (load_type != AMDGPU_FW_LOAD_SMU)
+ if (load_type == AMDGPU_FW_LOAD_DIRECT || load_type ==
AMDGPU_FW_LOAD_PSP)
pr_warning("%d is not supported on VI\n", load_type);
return AMDGPU_FW_LOAD_SMU;
case CHIP_VEGA10:
--
1.9.1
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[PATCH v2 1/5] drm/amdgpu: Split amdgpu_ucode_init/fini_bo into two functions
1. one is for create/free bo when init/fini
2. one is for fill the bo before fw loading
the ucode bo only need to be created when load driver
and free when driver unload.
when resume/reset, driver only need to re-fill the bo
if the bo is allocated in vram.
Suggested by Christian.
v2: Return error when bo create failed.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 58 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 ++
3 files changed, 36 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 94c92f5..680df05 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1581,6 +1581,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
}
}
+ r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init
complete*/
+ if (r)
+ return r;
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.sw)
continue;
@@ -1803,6 +1806,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device
*adev)
continue;
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
+ amdgpu_ucode_free_bo(adev);
amdgpu_free_static_csa(adev);
amdgpu_device_wb_fini(adev);
amdgpu_device_vram_scratch_fini(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index adfeb93..57ed384 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -422,32 +422,42 @@ static int amdgpu_ucode_patch_jt(struct
amdgpu_firmware_info *ucode,
return 0;
}
+int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
+{
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
+ amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
+ amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM :
AMDGPU_GEM_DOMAIN_GTT,
+ >firmware.fw_buf,
+ >firmware.fw_buf_mc,
+ >firmware.fw_buf_ptr);
+ if (!adev->firmware.fw_buf) {
+ dev_err(adev->dev, "failed to create kernel buffer for
firmware.fw_buf\n");
+ return -ENOMEM;
+ } else if (amdgpu_sriov_vf(adev)) {
+ memset(adev->firmware.fw_buf_ptr, 0,
adev->firmware.fw_size);
+ }
+ }
+ return 0;
+}
+
+void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
+{
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT)
+ amdgpu_bo_free_kernel(>firmware.fw_buf,
+ >firmware.fw_buf_mc,
+ >firmware.fw_buf_ptr);
+}
+
int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
{
uint64_t fw_offset = 0;
- int i, err;
+ int i;
struct amdgpu_firmware_info *ucode = NULL;
const struct common_firmware_header *header = NULL;
- if (!adev->firmware.fw_size) {
- dev_warn(adev->dev, "No ip firmware need to load\n");
+ /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo
when reset/suspend */
+ if (!amdgpu_sriov_vf(adev) && (adev->in_gpu_reset || adev->in_suspend))
return 0;
- }
-
- if (!adev->in_gpu_reset && !adev->in_suspend) {
- err = amdgpu_bo_create_kernel(adev, adev->firmware.fw_size,
PAGE_SIZE,
- amdgpu_sriov_vf(adev) ?
AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
- >firmware.fw_buf,
- >firmware.fw_buf_mc,
- >firmware.fw_buf_ptr);
- if (err) {
- dev_err(adev->dev, "failed to create kernel buffer for
firmware.fw_buf\n");
- goto failed;
- }
- }
-
- memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
-
/*
* if SMU loaded firmware, it needn't add SMC, UVD, and VCE
* ucode info here
@@ -479,12 +489,6 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
}
}
return 0;
-
-failed:
- if (err)
- adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
-
- return err;
}
int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
@@ -503,9 +507,5 @@ int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
}
}
- amdgpu_bo_free_kernel(>firmwar
[PATCH 5/5] drm/amdgpu: Remove the direct fw loading support for sdma2.4
sdma2.4 is only for iceland. For Vi, we don't maintain the
direct fw loading.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 42 --
1 file changed, 42 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index cd781ab..2d4770e 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -504,41 +504,6 @@ static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
return 0;
}
-/**
- * sdma_v2_4_load_microcode - load the sDMA ME ucode
- *
- * @adev: amdgpu_device pointer
- *
- * Loads the sDMA0/1 ucode.
- * Returns 0 for success, -EINVAL if the ucode is not available.
- */
-static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
-{
- const struct sdma_firmware_header_v1_0 *hdr;
- const __le32 *fw_data;
- u32 fw_size;
- int i, j;
-
- /* halt the MEs */
- sdma_v2_4_enable(adev, false);
-
- for (i = 0; i < adev->sdma.num_instances; i++) {
- if (!adev->sdma.instance[i].fw)
- return -EINVAL;
- hdr = (const struct sdma_firmware_header_v1_0
*)adev->sdma.instance[i].fw->data;
- amdgpu_ucode_print_sdma_hdr(>header);
- fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
- fw_data = (const __le32 *)
- (adev->sdma.instance[i].fw->data +
-le32_to_cpu(hdr->header.ucode_array_offset_bytes));
- WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
- for (j = 0; j < fw_size; j++)
- WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i],
le32_to_cpup(fw_data++));
- WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i],
adev->sdma.instance[i].fw_version);
- }
-
- return 0;
-}
/**
* sdma_v2_4_start - setup and start the async dma engines
@@ -552,13 +517,6 @@ static int sdma_v2_4_start(struct amdgpu_device *adev)
{
int r;
-
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
- r = sdma_v2_4_load_microcode(adev);
- if (r)
- return r;
- }
-
/* halt the engine before programing */
sdma_v2_4_enable(adev, false);
--
1.9.1
___
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[PATCH 4/5] drm/amdgpu: Fix unnecessary warning in dmesg
Fix the warning message:
"-1 is not supported on VI"
the -1 is the default fw load type, mean auto.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index f2604ac..e5b13b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -297,7 +297,7 @@ enum amdgpu_firmware_load_type
case CHIP_POLARIS11:
case CHIP_POLARIS12:
case CHIP_VEGAM:
- if (load_type != AMDGPU_FW_LOAD_SMU)
+ if (load_type != AMDGPU_FW_LOAD_DIRECT || load_type ==
AMDGPU_FW_LOAD_PSP)
pr_warning("%d is not supported on VI\n", load_type);
return AMDGPU_FW_LOAD_SMU;
case CHIP_VEGA10:
--
1.9.1
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[PATCH 3/5] drm/amdgpu: Extract the function of fw loading out of powerplay
So there is no dependence between gfx/sdma/smu.
and for Vi, after IH hw_init, driver load all the smu/gfx/sdma
fw. for AI, fw loading is controlled by PSP, after psp hw init,
we call the function to check smu fw version.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 30 ++
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 --
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 20 ---
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 -
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 8 ++
drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 5
7 files changed, 32 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 4787571..a6766b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1525,6 +1525,24 @@ static int amdgpu_device_ip_early_init(struct
amdgpu_device *adev)
return 0;
}
+static int amdgpu_device_fw_loading(struct amdgpu_device *adev, uint32_t index)
+{
+ int r = 0;
+
+ if ((adev->asic_type < CHIP_VEGA10
+&& (adev->ip_blocks[index].version->type == AMD_IP_BLOCK_TYPE_IH))
+|| (adev->asic_type >= CHIP_VEGA10
+&& (adev->ip_blocks[index].version->type ==
AMD_IP_BLOCK_TYPE_PSP))) {
+ if (adev->powerplay.pp_funcs->load_firmware) {
+ r =
adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
+ if (r) {
+ pr_err("firmware loading failed\n");
+ return r;
+ }
+ }
+ }
+ return 0;
+}
/**
* amdgpu_device_ip_init - run init for hardware IPs
*
@@ -1595,6 +1613,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
return r;
}
adev->ip_blocks[i].status.hw = true;
+ r = amdgpu_device_fw_loading(adev, i);
+ if (r)
+ return r;
}
amdgpu_xgmi_add_device(adev);
@@ -2030,6 +2051,9 @@ static int amdgpu_device_ip_reinit_early_sriov(struct
amdgpu_device *adev)
DRM_INFO("RE-INIT: %s %s\n",
block->version->funcs->name, r?"failed":"succeeded");
if (r)
return r;
+ r = amdgpu_device_fw_loading(adev, i);
+ if (r)
+ return r;
}
}
@@ -2098,6 +2122,9 @@ static int amdgpu_device_ip_resume_phase1(struct
amdgpu_device *adev)
adev->ip_blocks[i].version->funcs->name, r);
return r;
}
+ r = amdgpu_device_fw_loading(adev, i);
+ if (r)
+ return r;
}
}
@@ -2134,6 +2161,9 @@ static int amdgpu_device_ip_resume_phase2(struct
amdgpu_device *adev)
adev->ip_blocks[i].version->funcs->name, r);
return r;
}
+ r = amdgpu_device_fw_loading(adev, i);
+ if (r)
+ return r;
}
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 8439f9a..3d0f277 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4175,20 +4175,9 @@ static void gfx_v8_0_rlc_start(struct amdgpu_device
*adev)
static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
{
- int r;
-
gfx_v8_0_rlc_stop(adev);
gfx_v8_0_rlc_reset(adev);
gfx_v8_0_init_pg(adev);
-
- if (adev->powerplay.pp_funcs->load_firmware) {
- r =
adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
- if (r) {
- pr_err("firmware loading failed\n");
- return r;
- }
- }
-
gfx_v8_0_rlc_start(adev);
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 0bdde7f..6fb3eda 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -788,14 +788,6 @@ static int sdma_v3_0_start(struct amdgpu_device *adev)
{
int r;
- if (adev->powerplay.pp_funcs->load_firmware) {
- r =
adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
- if (r) {
-
[PATCH 1/5] drm/amdgpu: Split amdgpu_ucode_init/fini_bo into two functions
1. one is for create/free bo when init/fini
2. one is for fill the bo before fw loading
the ucode bo only need to be created when load driver
and free when driver unload.
when resume/reset, driver only need to re-fill the bo
if the bo is allocated in vram.
Suggested by Christian.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 57 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 ++
3 files changed, 34 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 94c92f5..4787571 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1581,6 +1581,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
}
}
+ amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
+
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.sw)
continue;
@@ -1803,6 +1805,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device
*adev)
continue;
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
+ amdgpu_ucode_free_bo(adev);
amdgpu_free_static_csa(adev);
amdgpu_device_wb_fini(adev);
amdgpu_device_vram_scratch_fini(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index adfeb93..7b6b2f4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -422,32 +422,41 @@ static int amdgpu_ucode_patch_jt(struct
amdgpu_firmware_info *ucode,
return 0;
}
+void amdgpu_ucode_create_bo(struct amdgpu_device *adev)
+{
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
+ amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
+ amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM :
AMDGPU_GEM_DOMAIN_GTT,
+ >firmware.fw_buf,
+ >firmware.fw_buf_mc,
+ >firmware.fw_buf_ptr);
+ if (!adev->firmware.fw_buf) {
+ dev_err(adev->dev, "failed to create kernel buffer for
firmware.fw_buf\n");
+ adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
+ } else if (amdgpu_sriov_vf(adev)) {
+ memset(adev->firmware.fw_buf_ptr, 0,
adev->firmware.fw_size);
+ }
+ }
+}
+
+void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
+{
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT)
+ amdgpu_bo_free_kernel(>firmware.fw_buf,
+ >firmware.fw_buf_mc,
+ >firmware.fw_buf_ptr);
+}
+
int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
{
uint64_t fw_offset = 0;
- int i, err;
+ int i;
struct amdgpu_firmware_info *ucode = NULL;
const struct common_firmware_header *header = NULL;
- if (!adev->firmware.fw_size) {
- dev_warn(adev->dev, "No ip firmware need to load\n");
+ /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo
when reset/suspend */
+ if (!amdgpu_sriov_vf(adev) && (adev->in_gpu_reset || adev->in_suspend))
return 0;
- }
-
- if (!adev->in_gpu_reset && !adev->in_suspend) {
- err = amdgpu_bo_create_kernel(adev, adev->firmware.fw_size,
PAGE_SIZE,
- amdgpu_sriov_vf(adev) ?
AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
- >firmware.fw_buf,
- >firmware.fw_buf_mc,
- >firmware.fw_buf_ptr);
- if (err) {
- dev_err(adev->dev, "failed to create kernel buffer for
firmware.fw_buf\n");
- goto failed;
- }
- }
-
- memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
-
/*
* if SMU loaded firmware, it needn't add SMC, UVD, and VCE
* ucode info here
@@ -479,12 +488,6 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
}
}
return 0;
-
-failed:
- if (err)
- adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
-
- return err;
}
int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
@@ -503,9 +506,5 @@ int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
}
}
- amdgpu_bo_free_kernel(>firmware.fw_buf,
- >firmware.fw_buf_mc,
[PATCH 2/5] drm/amdgpu: Remove amdgpu_ucode_fini_bo
The variable clean is unnecessary.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 --
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 19 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 +--
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 ---
4 files changed, 1 insertion(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index bd397d2..25d2f3e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -452,8 +452,6 @@ static int psp_hw_fini(void *handle)
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
return 0;
- amdgpu_ucode_fini_bo(adev);
-
psp_ring_destroy(psp, PSP_RING_TYPE__KM);
amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, >tmr_buf);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 7b6b2f4c..f2604ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -489,22 +489,3 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
}
return 0;
}
-
-int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
-{
- int i;
- struct amdgpu_firmware_info *ucode = NULL;
-
- if (!adev->firmware.fw_size)
- return 0;
-
- for (i = 0; i < adev->firmware.max_ucodes; i++) {
- ucode = >firmware.ucode[i];
- if (ucode->fw) {
- ucode->mc_addr = 0;
- ucode->kaddr = NULL;
- }
- }
-
- return 0;
-}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index 4c0e5be..05a2c46 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -276,9 +276,8 @@ struct amdgpu_firmware {
int amdgpu_ucode_validate(const struct firmware *fw);
bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
uint16_t hdr_major, uint16_t hdr_minor);
-int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
-int amdgpu_ucode_fini_bo(struct amdgpu_device *adev);
+int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
void amdgpu_ucode_create_bo(struct amdgpu_device *adev);
void amdgpu_ucode_free_bo(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 6bc8e9c..75b56ae 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -109,9 +109,6 @@ static int pp_sw_fini(void *handle)
hwmgr_sw_fini(hwmgr);
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
- amdgpu_ucode_fini_bo(adev);
-
release_firmware(adev->pm.fw);
adev->pm.fw = NULL;
--
1.9.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: Always enable fan sensors for read
don't need to set fan1_enable to read fan sensors. Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 10 -- 1 file changed, 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 68548fb..94055a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -1179,11 +1179,6 @@ static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, struct amdgpu_device *adev = dev_get_drvdata(dev); int err; u32 speed = 0; - u32 pwm_mode; - - pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); - if (pwm_mode != AMD_FAN_CTRL_MANUAL) - return -ENODATA; /* Can't adjust fan when the card is off */ if ((adev->flags & AMD_IS_PX) && @@ -1246,11 +1241,6 @@ static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev, struct amdgpu_device *adev = dev_get_drvdata(dev); int err; u32 rpm = 0; - u32 pwm_mode; - - pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); - if (pwm_mode != AMD_FAN_CTRL_MANUAL) - return -ENODATA; /* Can't adjust fan when the card is off */ if ((adev->flags & AMD_IS_PX) && -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2] drm/amdgpu: Change SI/CI gfx/sdma/smu init sequence
initialize gfx/sdma before dpm features enabled. Acked-by: Alex Deucher Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/amdgpu/cik.c | 17 + drivers/gpu/drm/amd/amdgpu/si.c | 13 +++-- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 78ab939..f41f5f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -2002,6 +2002,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _common_ip_block); amdgpu_device_ip_block_add(adev, _v7_0_ip_block); amdgpu_device_ip_block_add(adev, _ih_ip_block); + amdgpu_device_ip_block_add(adev, _v7_2_ip_block); + amdgpu_device_ip_block_add(adev, _sdma_ip_block); if (amdgpu_dpm == -1) amdgpu_device_ip_block_add(adev, _smu_ip_block); else @@ -2014,8 +2016,6 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) #endif else amdgpu_device_ip_block_add(adev, _v8_2_ip_block); - amdgpu_device_ip_block_add(adev, _v7_2_ip_block); - amdgpu_device_ip_block_add(adev, _sdma_ip_block); amdgpu_device_ip_block_add(adev, _v4_2_ip_block); amdgpu_device_ip_block_add(adev, _v2_0_ip_block); break; @@ -2023,6 +2023,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _common_ip_block); amdgpu_device_ip_block_add(adev, _v7_0_ip_block); amdgpu_device_ip_block_add(adev, _ih_ip_block); + amdgpu_device_ip_block_add(adev, _v7_3_ip_block); + amdgpu_device_ip_block_add(adev, _sdma_ip_block); if (amdgpu_dpm == -1) amdgpu_device_ip_block_add(adev, _smu_ip_block); else @@ -2035,8 +2037,6 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) #endif else amdgpu_device_ip_block_add(adev, _v8_5_ip_block); - amdgpu_device_ip_block_add(adev, _v7_3_ip_block); - amdgpu_device_ip_block_add(adev, _sdma_ip_block); amdgpu_device_ip_block_add(adev, _v4_2_ip_block); amdgpu_device_ip_block_add(adev, _v2_0_ip_block); break; @@ -2044,6 +2044,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _common_ip_block); amdgpu_device_ip_block_add(adev, _v7_0_ip_block); amdgpu_device_ip_block_add(adev, _ih_ip_block); + amdgpu_device_ip_block_add(adev, _v7_1_ip_block); + amdgpu_device_ip_block_add(adev, _sdma_ip_block); amdgpu_device_ip_block_add(adev, _smu_ip_block); if (adev->enable_virtual_display) amdgpu_device_ip_block_add(adev, _virtual_ip_block); @@ -2053,8 +2055,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) #endif else amdgpu_device_ip_block_add(adev, _v8_1_ip_block); - amdgpu_device_ip_block_add(adev, _v7_1_ip_block); - amdgpu_device_ip_block_add(adev, _sdma_ip_block); + amdgpu_device_ip_block_add(adev, _v4_2_ip_block); amdgpu_device_ip_block_add(adev, _v2_0_ip_block); break; @@ -2063,6 +2064,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _common_ip_block); amdgpu_device_ip_block_add(adev, _v7_0_ip_block); amdgpu_device_ip_block_add(adev, _ih_ip_block); + amdgpu_device_ip_block_add(adev, _v7_2_ip_block); + amdgpu_device_ip_block_add(adev, _sdma_ip_block); amdgpu_device_ip_block_add(adev, _smu_ip_block); if (adev->enable_virtual_display) amdgpu_device_ip_block_add(adev, _virtual_ip_block); @@ -2072,8 +2075,6 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) #endif else amdgpu_device_ip_block_add(adev, _v8_3_ip_block); - amdgpu_device_ip_block_add(adev, _v7_2_ip_block); - amdgpu_device_ip_block_add(adev, _sdma_ip_block); amdgpu_device_ip_block_add(adev, _v4_2_ip_block); amdgpu_device_ip_block_add(adev, _v2_0_ip_block); break; diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index c364ef9..f8408f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -2057,13 +2057,13 @@ int si_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _common_ip_block); amdgpu_device_ip_block_add(adev, _v6_0_ip_block); amdgpu_device_ip_blo
[PATCH 2/2] drm/amdgpu: Change AI gfx/sdma/smu init sequence
initialize gfx/sdma before dpm features enabled.
Acked-by: Alex Deucher
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index fb26039..bf5e6a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -529,6 +529,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _v11_0_ip_block);
else
amdgpu_device_ip_block_add(adev, _v3_1_ip_block);
+ amdgpu_device_ip_block_add(adev, _v9_0_ip_block);
+ amdgpu_device_ip_block_add(adev, _v4_0_ip_block);
if (!amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
@@ -539,8 +541,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
#else
# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
#endif
- amdgpu_device_ip_block_add(adev, _v9_0_ip_block);
- amdgpu_device_ip_block_add(adev, _v4_0_ip_block);
if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
{
amdgpu_device_ip_block_add(adev, _v7_0_ip_block);
amdgpu_device_ip_block_add(adev, _v4_0_ip_block);
@@ -551,6 +551,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _v9_0_ip_block);
amdgpu_device_ip_block_add(adev, _ih_ip_block);
amdgpu_device_ip_block_add(adev, _v10_0_ip_block);
+ amdgpu_device_ip_block_add(adev, _v9_0_ip_block);
+ amdgpu_device_ip_block_add(adev, _v4_0_ip_block);
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
@@ -560,8 +562,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
#else
# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
#endif
- amdgpu_device_ip_block_add(adev, _v9_0_ip_block);
- amdgpu_device_ip_block_add(adev, _v4_0_ip_block);
amdgpu_device_ip_block_add(adev, _v1_0_ip_block);
break;
default:
--
1.9.1
___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 5/5] drm/amdgpu: Change VI gfx/sdma/smu init sequence
initialize gfx/sdma before dpm features enabled.
Acked-by: Alex Deucher
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/vi.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 88b57a5..07880d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1596,16 +1596,18 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _common_ip_block);
amdgpu_device_ip_block_add(adev, _v7_4_ip_block);
amdgpu_device_ip_block_add(adev, _ih_ip_block);
+ amdgpu_device_ip_block_add(adev, _v8_0_ip_block);
+ amdgpu_device_ip_block_add(adev, _v2_4_ip_block);
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
- amdgpu_device_ip_block_add(adev, _v8_0_ip_block);
- amdgpu_device_ip_block_add(adev, _v2_4_ip_block);
break;
case CHIP_FIJI:
amdgpu_device_ip_block_add(adev, _common_ip_block);
amdgpu_device_ip_block_add(adev, _v8_5_ip_block);
amdgpu_device_ip_block_add(adev, _ih_ip_block);
+ amdgpu_device_ip_block_add(adev, _v8_0_ip_block);
+ amdgpu_device_ip_block_add(adev, _v3_0_ip_block);
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
@@ -1615,8 +1617,6 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
#endif
else
amdgpu_device_ip_block_add(adev, _v10_1_ip_block);
- amdgpu_device_ip_block_add(adev, _v8_0_ip_block);
- amdgpu_device_ip_block_add(adev, _v3_0_ip_block);
if (!amdgpu_sriov_vf(adev)) {
amdgpu_device_ip_block_add(adev, _v6_0_ip_block);
amdgpu_device_ip_block_add(adev, _v3_0_ip_block);
@@ -1626,6 +1626,8 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _common_ip_block);
amdgpu_device_ip_block_add(adev, _v8_0_ip_block);
amdgpu_device_ip_block_add(adev, _ih_ip_block);
+ amdgpu_device_ip_block_add(adev, _v8_0_ip_block);
+ amdgpu_device_ip_block_add(adev, _v3_0_ip_block);
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
@@ -1635,8 +1637,6 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
#endif
else
amdgpu_device_ip_block_add(adev, _v10_0_ip_block);
- amdgpu_device_ip_block_add(adev, _v8_0_ip_block);
- amdgpu_device_ip_block_add(adev, _v3_0_ip_block);
if (!amdgpu_sriov_vf(adev)) {
amdgpu_device_ip_block_add(adev, _v5_0_ip_block);
amdgpu_device_ip_block_add(adev, _v3_0_ip_block);
@@ -1649,6 +1649,8 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _common_ip_block);
amdgpu_device_ip_block_add(adev, _v8_1_ip_block);
amdgpu_device_ip_block_add(adev, _ih_ip_block);
+ amdgpu_device_ip_block_add(adev, _v8_0_ip_block);
+ amdgpu_device_ip_block_add(adev, _v3_1_ip_block);
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
@@ -1658,8 +1660,6 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
#endif
else
amdgpu_device_ip_block_add(adev, _v11_2_ip_block);
- amdgpu_device_ip_block_add(adev, _v8_0_ip_block);
- amdgpu_device_ip_block_add(adev, _v3_1_ip_block);
amdgpu_device_ip_block_add(adev, _v6_3_ip_block);
amdgpu_device_ip_block_add(adev, _v3_4_ip_block);
break;
@@ -1667,6 +1667,8 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _common_ip_block);
amdgpu_device_ip_block_add(adev, _v8_0_ip_block);
amdgpu_device_ip_block_add(adev, _ih_ip_block);
+ amdgpu_device_ip_block_add(adev, _v8_0_ip_block);
+ amdgpu_device_ip_block_add(adev, _v3_0_ip_block);
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, _v
[PATCH 4/5] drm/amdgpu: Add fw load in gfx_v8 and sdma_v3
gfx and sdma can be initialized before smu.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 +++
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8
2 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 6b1954e..77e05c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4180,9 +4180,20 @@ static void gfx_v8_0_rlc_start(struct amdgpu_device
*adev)
static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
{
+ int r;
+
gfx_v8_0_rlc_stop(adev);
gfx_v8_0_rlc_reset(adev);
gfx_v8_0_init_pg(adev);
+
+ if (adev->powerplay.pp_funcs->load_firmware) {
+ r =
adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
+ if (r) {
+ pr_err("firmware loading failed\n");
+ return r;
+ }
+ }
+
gfx_v8_0_rlc_start(adev);
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 6fb3eda..0bdde7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -788,6 +788,14 @@ static int sdma_v3_0_start(struct amdgpu_device *adev)
{
int r;
+ if (adev->powerplay.pp_funcs->load_firmware) {
+ r =
adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
+ if (r) {
+ pr_err("firmware loading failed\n");
+ return r;
+ }
+ }
+
/* disable sdma engine before programing it */
sdma_v3_0_ctx_switch_enable(adev, false);
sdma_v3_0_enable(adev, false);
--
1.9.1
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[PATCH 3/5] drm/amd/pp: Implement load_firmware interface
with this interface, gfx/sdma can be initialized
before smu.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index b2ebcb1..6bc8e9c 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -270,8 +270,23 @@ static int pp_set_clockgating_state(void *handle,
.funcs = _ip_funcs,
};
+/* This interface only be supported On Vi,
+ * because only smu7/8 can help to load gfx/sdma fw,
+ * smu need to be enabled before load other ip's fw.
+ * so call start smu to load smu7 fw and other ip's fw
+ */
static int pp_dpm_load_fw(void *handle)
{
+ struct pp_hwmgr *hwmgr = handle;
+
+ if (!hwmgr || !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->start_smu)
+ return -EINVAL;
+
+ if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
+ pr_err("fw load failed\n");
+ return -EINVAL;
+ }
+
return 0;
}
--
1.9.1
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[PATCH 2/5] drm/amd/pp: Allocate ucode bo in request_smu_load_fw
ucode bo is needed by request_smu_load_fw, the request_smu_load_fw maybe called by gfx/sdma before smu hw init. so move amdgpu_ucode_bo_init to request_smu_lowd_fw from smu hw init. Reviewed-by: Evan Quan Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 --- drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 2 ++ drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 2 ++ 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index e51d961..b2ebcb1 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -124,9 +124,6 @@ static int pp_hw_init(void *handle) struct amdgpu_device *adev = handle; struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; - if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) - amdgpu_ucode_init_bo(adev); - ret = hwmgr_hw_init(hwmgr); if (ret) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c index 794a165..99b4e4f 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c @@ -346,6 +346,8 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr) if (!hwmgr->reload_fw) return 0; + amdgpu_ucode_init_bo(hwmgr->adev); + if (smu_data->soft_regs_start) cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->soft_regs_start + smum_get_offsetof(hwmgr, diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c index 7b3b66d..abbf2f2 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c @@ -664,6 +664,8 @@ static int smu8_request_smu_load_fw(struct pp_hwmgr *hwmgr) if (!hwmgr->reload_fw) return 0; + amdgpu_ucode_init_bo(hwmgr->adev); + smu8_smu_populate_firmware_entries(hwmgr); smu8_smu_construct_toc(hwmgr); -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/5] drm/amdgpu: Don't reallocate ucode bo when suspend
driver don't release the ucode memory when suspend. so don't
need to allocate bo when resume back.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 9878212..adfeb93 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -434,7 +434,7 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
return 0;
}
- if (!adev->in_gpu_reset) {
+ if (!adev->in_gpu_reset && !adev->in_suspend) {
err = amdgpu_bo_create_kernel(adev, adev->firmware.fw_size,
PAGE_SIZE,
amdgpu_sriov_vf(adev) ?
AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
>firmware.fw_buf,
--
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[PATCH 0/5] Change the hw ip initialize sequence
we are suggested to initialize gfx/sdma before power feature enabled. and On Vi, the gfx/sdma fw will be loaded by smu, Export load_firmware interface to gfx/sdma, so gfx/sdma can trigger fw loading if they were initialized before smu. Rex Zhu (5): drm/amdgpu: Don't reallocate ucode bo when suspend drm/amd/pp: Allocate ucode bo in request_smu_load_fw drm/amd/pp: Implement load_firmware interface drm/amdgpu: Add fw load in gfx_v8 and sdma_v3 drm/amdgpu: Change VI gfx/sdma/smu init sequence drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 ++ drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 drivers/gpu/drm/amd/amdgpu/vi.c| 24 +++--- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 18 +--- drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 2 ++ drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 2 ++ 7 files changed, 51 insertions(+), 16 deletions(-) -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2] drm/amdgpu: Remove FW_LOAD_DIRECT type support on VI
AMDGPU_FW_LOAD_DIRECT is used for bring up.
Now it don't work any more. so remove the support.
v2: Add warning message if user select
AMDGPU_FW_LOAD_DIRECT/AMDGPU_FW_LOAD_PSP on VI.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 7 +-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 249 ++
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c| 57 +--
3 files changed, 59 insertions(+), 254 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 1fa8bc3..9878212 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -297,10 +297,9 @@ enum amdgpu_firmware_load_type
case CHIP_POLARIS11:
case CHIP_POLARIS12:
case CHIP_VEGAM:
- if (!load_type)
- return AMDGPU_FW_LOAD_DIRECT;
- else
- return AMDGPU_FW_LOAD_SMU;
+ if (load_type != AMDGPU_FW_LOAD_SMU)
+ pr_warning("%d is not supported on VI\n", load_type);
+ return AMDGPU_FW_LOAD_SMU;
case CHIP_VEGA10:
case CHIP_RAVEN:
case CHIP_VEGA12:
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index f9e0a21..6b1954e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1173,64 +1173,61 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device
*adev)
}
}
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
- info = >firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
- info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
- info->fw = adev->gfx.pfp_fw;
- header = (const struct common_firmware_header *)info->fw->data;
- adev->firmware.fw_size +=
- ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
-
- info = >firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
- info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
- info->fw = adev->gfx.me_fw;
- header = (const struct common_firmware_header *)info->fw->data;
- adev->firmware.fw_size +=
- ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
-
- info = >firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
- info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
- info->fw = adev->gfx.ce_fw;
- header = (const struct common_firmware_header *)info->fw->data;
- adev->firmware.fw_size +=
- ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+ info = >firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
+ info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
+ info->fw = adev->gfx.pfp_fw;
+ header = (const struct common_firmware_header *)info->fw->data;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+
+ info = >firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
+ info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
+ info->fw = adev->gfx.me_fw;
+ header = (const struct common_firmware_header *)info->fw->data;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+
+ info = >firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
+ info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
+ info->fw = adev->gfx.ce_fw;
+ header = (const struct common_firmware_header *)info->fw->data;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+
+ info = >firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
+ info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
+ info->fw = adev->gfx.rlc_fw;
+ header = (const struct common_firmware_header *)info->fw->data;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+
+ info = >firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
+ info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
+ info->fw = adev->gfx.mec_fw;
+ header = (const struct common_firmware_header *)info->fw->data;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+
+ /* we need account JT in */
+ cp_hdr = (const struct gfx_firmware_header_v1_0
*)adev->gfx.mec_fw->data;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
- info = >firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
- info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
- info->fw = adev->gfx.rlc_fw;
- header = (const stru
[PATCH 1/2] drm/amdgpu: Refine function amdgpu_device_ip_late_init
1. only call late_init when hw_init successful,
so check status.hw instand of status.valid in late_init.
2. set status.late_initialized true if late_init was not implemented.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 95095a8..eda3d1e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1723,7 +1723,7 @@ static int amdgpu_device_ip_late_init(struct
amdgpu_device *adev)
int i = 0, r;
for (i = 0; i < adev->num_ip_blocks; i++) {
- if (!adev->ip_blocks[i].status.valid)
+ if (!adev->ip_blocks[i].status.hw)
continue;
if (adev->ip_blocks[i].version->funcs->late_init) {
r = adev->ip_blocks[i].version->funcs->late_init((void
*)adev);
@@ -1732,8 +1732,8 @@ static int amdgpu_device_ip_late_init(struct
amdgpu_device *adev)
adev->ip_blocks[i].version->funcs->name, r);
return r;
}
- adev->ip_blocks[i].status.late_initialized = true;
}
+ adev->ip_blocks[i].status.late_initialized = true;
}
amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
--
1.9.1
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[PATCH 2/2] drm/amdgpu: Check late_init status before set cg/pg state
Fix cg/pg unexpected set in hw init failed case.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index eda3d1e..94c92f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1656,7 +1656,7 @@ static int amdgpu_device_set_cg_state(struct
amdgpu_device *adev,
for (j = 0; j < adev->num_ip_blocks; j++) {
i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j -
1;
- if (!adev->ip_blocks[i].status.valid)
+ if (!adev->ip_blocks[i].status.late_initialized)
continue;
/* skip CG for VCE/UVD, it's handled specially */
if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
@@ -1686,7 +1686,7 @@ static int amdgpu_device_set_pg_state(struct
amdgpu_device *adev, enum amd_power
for (j = 0; j < adev->num_ip_blocks; j++) {
i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j -
1;
- if (!adev->ip_blocks[i].status.valid)
+ if (!adev->ip_blocks[i].status.late_initialized)
continue;
/* skip CG for VCE/UVD, it's handled specially */
if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
--
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[PATCH 5/5] drm/amdgpu: Disable sysfs pwm1 if not in manual fan control
Following lm-sensors 3.0.0,
Only enable pwm1 sysfs when fan control mode(pwm1_enable)
in manual
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 1d85706..d6bd5ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1120,12 +1120,19 @@ static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
struct amdgpu_device *adev = dev_get_drvdata(dev);
int err;
u32 value;
+ u32 pwm_mode;
/* Can't adjust fan when the card is off */
if ((adev->flags & AMD_IS_PX) &&
(adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
return -EINVAL;
+ pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
+ if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
+ pr_info("manual fan speed control should be enabled first\n");
+ return -EINVAL;
+ }
+
err = kstrtou32(buf, 10, );
if (err)
return err;
--
1.9.1
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[PATCH 4/5] drm/amdgpu: Add fan RPM setting via sysfs
Add fan1_target for get/set fan speed in RPM unit
Add fan1_min/fan1_max for get min, max fan speed in RPM unit
Add fan1_enable to enable/disable the fan1 sensor
v2: query the min/max rpm gpu support instand of hardcode.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h| 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 190 -
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 19 +++
4 files changed, 210 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 42568ae..f972cd1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -278,6 +278,9 @@ enum amdgpu_pcie_gen {
#define amdgpu_dpm_get_fan_speed_rpm(adev, s) \
((adev)->powerplay.pp_funcs->get_fan_speed_rpm)((adev)->powerplay.pp_handle,
(s))
+#define amdgpu_dpm_set_fan_speed_rpm(adev, s) \
+
((adev)->powerplay.pp_funcs->set_fan_speed_rpm)((adev)->powerplay.pp_handle,
(s))
+
#define amdgpu_dpm_get_sclk(adev, l) \
((adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 18d989e..1d85706 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1172,6 +1172,11 @@ static ssize_t amdgpu_hwmon_get_fan1_input(struct device
*dev,
struct amdgpu_device *adev = dev_get_drvdata(dev);
int err;
u32 speed = 0;
+ u32 pwm_mode;
+
+ pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
+ if (pwm_mode != AMD_FAN_CTRL_MANUAL)
+ return -ENODATA;
/* Can't adjust fan when the card is off */
if ((adev->flags & AMD_IS_PX) &&
@@ -1187,6 +1192,153 @@ static ssize_t amdgpu_hwmon_get_fan1_input(struct
device *dev,
return sprintf(buf, "%i\n", speed);
}
+static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
+struct device_attribute *attr,
+char *buf)
+{
+ struct amdgpu_device *adev = dev_get_drvdata(dev);
+ u32 min_rpm = 0;
+ u32 size = sizeof(min_rpm);
+ int r;
+
+ if (!adev->powerplay.pp_funcs->read_sensor)
+ return -EINVAL;
+
+ r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
+ (void *)_rpm, );
+ if (r)
+ return r;
+
+ return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
+}
+
+static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
+struct device_attribute *attr,
+char *buf)
+{
+ struct amdgpu_device *adev = dev_get_drvdata(dev);
+ u32 max_rpm = 0;
+ u32 size = sizeof(max_rpm);
+ int r;
+
+ if (!adev->powerplay.pp_funcs->read_sensor)
+ return -EINVAL;
+
+ r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
+ (void *)_rpm, );
+ if (r)
+ return r;
+
+ return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
+}
+
+static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct amdgpu_device *adev = dev_get_drvdata(dev);
+ int err;
+ u32 rpm = 0;
+ u32 pwm_mode;
+
+ pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
+ if (pwm_mode != AMD_FAN_CTRL_MANUAL)
+ return -ENODATA;
+
+ /* Can't adjust fan when the card is off */
+ if ((adev->flags & AMD_IS_PX) &&
+(adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+ return -EINVAL;
+
+ if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
+ err = amdgpu_dpm_get_fan_speed_rpm(adev, );
+ if (err)
+ return err;
+ }
+
+ return sprintf(buf, "%i\n", rpm);
+}
+
+static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
+struct device_attribute *attr,
+const char *buf, size_t count)
+{
+ struct amdgpu_device *adev = dev_get_drvdata(dev);
+ int err;
+ u32 value;
+ u32 pwm_mode;
+
+ pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
+ if (pwm_mode != AMD_FAN_CTRL_MANUAL)
+ return -ENODATA;
+
+ /* Can't adjust fan when the card is off */
+ if ((adev->flags & AMD_IS_PX) &&
+(adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+
[PATCH 2/5] drm/amdgpu: Add new AMDGPU_PP_SENSOR_MIN/MAX_FAN_RPM sensor
For getting the min/max fan speed in RPM units.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 8593850..97001a6 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -114,6 +114,8 @@ enum amd_pp_sensors {
AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
+ AMDGPU_PP_SENSOR_MIN_FAN_RPM,
+ AMDGPU_PP_SENSOR_MAX_FAN_RPM,
};
enum amd_pp_task {
--
1.9.1
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[PATCH 1/5] drm/amdgpu: Refine uvd_v6/7_0_enc_get_destroy_msg
1. make uvd_v7_0_enc_get_destroy_msg static
2. drop a function variable that always true
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 10 +++---
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 12
2 files changed, 7 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 8ef4a53..7a5b402 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -274,7 +274,7 @@ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring
*ring, uint32_t handle
*/
static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
uint32_t handle,
- bool direct, struct dma_fence **fence)
+ struct dma_fence **fence)
{
const unsigned ib_size_dw = 16;
struct amdgpu_job *job;
@@ -310,11 +310,7 @@ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring
*ring,
for (i = ib->length_dw; i < ib_size_dw; ++i)
ib->ptr[i] = 0x0;
- if (direct)
- r = amdgpu_job_submit_direct(job, ring, );
- else
- r = amdgpu_job_submit(job, >adev->vce.entity,
- AMDGPU_FENCE_OWNER_UNDEFINED, );
+ r = amdgpu_job_submit_direct(job, ring, );
if (r)
goto err;
@@ -345,7 +341,7 @@ static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring
*ring, long timeout)
goto error;
}
- r = uvd_v6_0_enc_get_destroy_msg(ring, 1, true, );
+ r = uvd_v6_0_enc_get_destroy_msg(ring, 1, );
if (r) {
DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
goto error;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index a289f6a..58b39af 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -280,8 +280,8 @@ static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring
*ring, uint32_t handle
*
* Close up a stream for HW test or if userspace failed to do so
*/
-int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
-bool direct, struct dma_fence **fence)
+static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t
handle,
+ struct dma_fence **fence)
{
const unsigned ib_size_dw = 16;
struct amdgpu_job *job;
@@ -317,11 +317,7 @@ int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
uint32_t handle,
for (i = ib->length_dw; i < ib_size_dw; ++i)
ib->ptr[i] = 0x0;
- if (direct)
- r = amdgpu_job_submit_direct(job, ring, );
- else
- r = amdgpu_job_submit(job, >adev->vce.entity,
- AMDGPU_FENCE_OWNER_UNDEFINED, );
+ r = amdgpu_job_submit_direct(job, ring, );
if (r)
goto err;
@@ -352,7 +348,7 @@ static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring
*ring, long timeout)
goto error;
}
- r = uvd_v7_0_enc_get_destroy_msg(ring, 1, true, );
+ r = uvd_v7_0_enc_get_destroy_msg(ring, 1, );
if (r) {
DRM_ERROR("amdgpu: (%d)failed to get destroy ib (%ld).\n",
ring->me, r);
goto error;
--
1.9.1
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[PATCH 3/5] drm/amd/pp: Implement AMDGPU_PP_SENSOR_MIN/MAX_FAN_RPM
so user can query the RPM range Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c| 6 ++ drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index 32f475e..053c485 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -813,6 +813,12 @@ static int pp_dpm_read_sensor(void *handle, int idx, case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: *((uint32_t *)value) = hwmgr->pstate_mclk; return 0; + case AMDGPU_PP_SENSOR_MIN_FAN_RPM: + *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMinRPM; + return 0; + case AMDGPU_PP_SENSOR_MAX_FAN_RPM: + *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMaxRPM; + return 0; default: mutex_lock(>smu_lock); ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size); diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c index 5f1f7a3..c9b93e6 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c @@ -834,6 +834,8 @@ static int init_powerplay_table_information( hwmgr->thermal_controller.ucType = powerplay_table->ucThermalControllerType; pptable_information->uc_thermal_controller_type = powerplay_table->ucThermalControllerType; + hwmgr->thermal_controller.fanInfo.ulMinRPM = 0; + hwmgr->thermal_controller.fanInfo.ulMaxRPM = powerplay_table->smcPPTable.FanMaximumRpm; set_hw_cap(hwmgr, ATOM_VEGA20_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType, -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 4/4] drm/amdgpu: Change the gfx/sdma init/fini sequence
initialize gfx/sdma before dpm features enabled. and disable dpm features before gfx/sdma fini. Acked-by: Alex Deucher Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/amdgpu/cik.c | 17 + drivers/gpu/drm/amd/amdgpu/si.c| 13 +++-- drivers/gpu/drm/amd/amdgpu/soc15.c | 8 drivers/gpu/drm/amd/amdgpu/vi.c| 24 4 files changed, 32 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 78ab939..f41f5f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -2002,6 +2002,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _common_ip_block); amdgpu_device_ip_block_add(adev, _v7_0_ip_block); amdgpu_device_ip_block_add(adev, _ih_ip_block); + amdgpu_device_ip_block_add(adev, _v7_2_ip_block); + amdgpu_device_ip_block_add(adev, _sdma_ip_block); if (amdgpu_dpm == -1) amdgpu_device_ip_block_add(adev, _smu_ip_block); else @@ -2014,8 +2016,6 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) #endif else amdgpu_device_ip_block_add(adev, _v8_2_ip_block); - amdgpu_device_ip_block_add(adev, _v7_2_ip_block); - amdgpu_device_ip_block_add(adev, _sdma_ip_block); amdgpu_device_ip_block_add(adev, _v4_2_ip_block); amdgpu_device_ip_block_add(adev, _v2_0_ip_block); break; @@ -2023,6 +2023,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _common_ip_block); amdgpu_device_ip_block_add(adev, _v7_0_ip_block); amdgpu_device_ip_block_add(adev, _ih_ip_block); + amdgpu_device_ip_block_add(adev, _v7_3_ip_block); + amdgpu_device_ip_block_add(adev, _sdma_ip_block); if (amdgpu_dpm == -1) amdgpu_device_ip_block_add(adev, _smu_ip_block); else @@ -2035,8 +2037,6 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) #endif else amdgpu_device_ip_block_add(adev, _v8_5_ip_block); - amdgpu_device_ip_block_add(adev, _v7_3_ip_block); - amdgpu_device_ip_block_add(adev, _sdma_ip_block); amdgpu_device_ip_block_add(adev, _v4_2_ip_block); amdgpu_device_ip_block_add(adev, _v2_0_ip_block); break; @@ -2044,6 +2044,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _common_ip_block); amdgpu_device_ip_block_add(adev, _v7_0_ip_block); amdgpu_device_ip_block_add(adev, _ih_ip_block); + amdgpu_device_ip_block_add(adev, _v7_1_ip_block); + amdgpu_device_ip_block_add(adev, _sdma_ip_block); amdgpu_device_ip_block_add(adev, _smu_ip_block); if (adev->enable_virtual_display) amdgpu_device_ip_block_add(adev, _virtual_ip_block); @@ -2053,8 +2055,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) #endif else amdgpu_device_ip_block_add(adev, _v8_1_ip_block); - amdgpu_device_ip_block_add(adev, _v7_1_ip_block); - amdgpu_device_ip_block_add(adev, _sdma_ip_block); + amdgpu_device_ip_block_add(adev, _v4_2_ip_block); amdgpu_device_ip_block_add(adev, _v2_0_ip_block); break; @@ -2063,6 +2064,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _common_ip_block); amdgpu_device_ip_block_add(adev, _v7_0_ip_block); amdgpu_device_ip_block_add(adev, _ih_ip_block); + amdgpu_device_ip_block_add(adev, _v7_2_ip_block); + amdgpu_device_ip_block_add(adev, _sdma_ip_block); amdgpu_device_ip_block_add(adev, _smu_ip_block); if (adev->enable_virtual_display) amdgpu_device_ip_block_add(adev, _virtual_ip_block); @@ -2072,8 +2075,6 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) #endif else amdgpu_device_ip_block_add(adev, _v8_3_ip_block); - amdgpu_device_ip_block_add(adev, _v7_2_ip_block); - amdgpu_device_ip_block_add(adev, _sdma_ip_block); amdgpu_device_ip_block_add(adev, _v4_2_ip_block); amdgpu_device_ip_block_add(adev, _v2_0_ip_block); break; diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index c364ef9..f8408f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -2057,13 +2057,13 @@ int si_set_ip_blocks(struct amdgpu_device
[PATCH 1/4] drm/amd/pp: Not allocate ucode bo in smu hw init
ucode bo is needed by request_smu_load_fw, the request_smu_load_fw maybe called by gfx/sdma before smu hw init. so move amdgpu_ucode_bo_init to request_smu_lowd_fw. Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 --- drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 2 ++ drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 2 ++ 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index d3eaf5d..a267f9e 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -124,9 +124,6 @@ static int pp_hw_init(void *handle) struct amdgpu_device *adev = handle; struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; - if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) - amdgpu_ucode_init_bo(adev); - ret = hwmgr_hw_init(hwmgr); if (ret) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c index 794a165..99b4e4f 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c @@ -346,6 +346,8 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr) if (!hwmgr->reload_fw) return 0; + amdgpu_ucode_init_bo(hwmgr->adev); + if (smu_data->soft_regs_start) cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->soft_regs_start + smum_get_offsetof(hwmgr, diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c index 7b3b66d..abbf2f2 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c @@ -664,6 +664,8 @@ static int smu8_request_smu_load_fw(struct pp_hwmgr *hwmgr) if (!hwmgr->reload_fw) return 0; + amdgpu_ucode_init_bo(hwmgr->adev); + smu8_smu_populate_firmware_entries(hwmgr); smu8_smu_construct_toc(hwmgr); -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/4] drm/amd/pp: Implement load_firmware interface
with this interface, gfx/sdma can be initialized
before smu.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index a267f9e..ace88e2 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -270,8 +270,23 @@ static int pp_set_clockgating_state(void *handle,
.funcs = _ip_funcs,
};
+/* This interface only be supported On Vi,
+ * because only smu7/8 can help to load gfx/sdma fw,
+ * smu need to be enabled before load other ip's fw.
+ * so call start smu to load smu7 fw and other ip's fw
+ */
static int pp_dpm_load_fw(void *handle)
{
+ struct pp_hwmgr *hwmgr = handle;
+
+ if (!hwmgr || !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->start_smu)
+ return -EINVAL;
+
+ if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
+ pr_err("fw load failed\n");
+ return -EINVAL;
+ }
+
return 0;
}
--
1.9.1
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[PATCH 3/4] drm/amdgpu: Add fw load in gfx_v8 and sdma_v3.
gfx and sdma can be initialized before smu.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 +++
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8
2 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 6b1954e..77e05c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4180,9 +4180,20 @@ static void gfx_v8_0_rlc_start(struct amdgpu_device
*adev)
static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
{
+ int r;
+
gfx_v8_0_rlc_stop(adev);
gfx_v8_0_rlc_reset(adev);
gfx_v8_0_init_pg(adev);
+
+ if (adev->powerplay.pp_funcs->load_firmware) {
+ r =
adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
+ if (r) {
+ pr_err("firmware loading failed\n");
+ return r;
+ }
+ }
+
gfx_v8_0_rlc_start(adev);
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 6fb3eda..0bdde7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -788,6 +788,14 @@ static int sdma_v3_0_start(struct amdgpu_device *adev)
{
int r;
+ if (adev->powerplay.pp_funcs->load_firmware) {
+ r =
adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
+ if (r) {
+ pr_err("firmware loading failed\n");
+ return r;
+ }
+ }
+
/* disable sdma engine before programing it */
sdma_v3_0_ctx_switch_enable(adev, false);
sdma_v3_0_enable(adev, false);
--
1.9.1
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[PATCH 3/3] drm/amd/pp: Refine smu7/8 request_smu_load_fw callback function
The request_smu_load_fw of VI is used to load gfx/sdma
ip's firmware.
Check whether the gfx/sdma firmware have been loaded successfully
in this callback function.
if failed, driver can exit to avoid gpu hard hung.
if successful, clean the flag reload_fw to avoid duplicated fw load.
when suspend/resume, driver need to reload fw.
so in suspend, reset the reload_fw flag to true to enable load fw when
resume.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 1 +
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 55 -
drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 56 +++---
3 files changed, 39 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 7500a3e..d552af2 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -301,6 +301,7 @@ int hwmgr_suspend(struct pp_hwmgr *hwmgr)
if (!hwmgr || !hwmgr->pm_en)
return 0;
+ hwmgr->reload_fw = true;
phm_disable_smc_firmware_ctf(hwmgr);
ret = psm_set_boot_states(hwmgr);
if (ret)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index 186dafc..794a165 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -302,44 +302,6 @@ int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr,
uint32_t smc_addr, uint32_
return 0;
}
-/* Convert the firmware type to SMU type mask. For MEC, we need to check all
MEC related type */
-
-static uint32_t smu7_get_mask_for_firmware_type(uint32_t fw_type)
-{
- uint32_t result = 0;
-
- switch (fw_type) {
- case UCODE_ID_SDMA0:
- result = UCODE_ID_SDMA0_MASK;
- break;
- case UCODE_ID_SDMA1:
- result = UCODE_ID_SDMA1_MASK;
- break;
- case UCODE_ID_CP_CE:
- result = UCODE_ID_CP_CE_MASK;
- break;
- case UCODE_ID_CP_PFP:
- result = UCODE_ID_CP_PFP_MASK;
- break;
- case UCODE_ID_CP_ME:
- result = UCODE_ID_CP_ME_MASK;
- break;
- case UCODE_ID_CP_MEC:
- case UCODE_ID_CP_MEC_JT1:
- case UCODE_ID_CP_MEC_JT2:
- result = UCODE_ID_CP_MEC_MASK;
- break;
- case UCODE_ID_RLC_G:
- result = UCODE_ID_RLC_G_MASK;
- break;
- default:
- pr_info("UCode type is out of range! \n");
- result = 0;
- }
-
- return result;
-}
-
static int smu7_populate_single_firmware_entry(struct pp_hwmgr *hwmgr,
uint32_t fw_type,
struct SMU_Entry *entry)
@@ -381,10 +343,8 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
uint32_t fw_to_load;
int r = 0;
- if (!hwmgr->reload_fw) {
- pr_info("skip reloading...\n");
+ if (!hwmgr->reload_fw)
return 0;
- }
if (smu_data->soft_regs_start)
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
@@ -467,10 +427,14 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI,
upper_32_bits(smu_data->header_buffer.mc_addr));
smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO,
lower_32_bits(smu_data->header_buffer.mc_addr));
- if (smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_LoadUcodes,
fw_to_load))
- pr_err("Fail to Request SMU Load uCode");
+ smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_LoadUcodes,
fw_to_load);
- return r;
+ r = smu7_check_fw_load_finish(hwmgr, fw_to_load);
+ if (!r) {
+ hwmgr->reload_fw = 0;
+ return 0;
+ }
+ pr_err("SMU load firmware failed\n");
failed:
kfree(smu_data->toc);
@@ -482,13 +446,12 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type)
{
struct smu7_smumgr *smu_data = (struct smu7_smumgr
*)(hwmgr->smu_backend);
- uint32_t fw_mask = smu7_get_mask_for_firmware_type(fw_type);
uint32_t ret;
ret = phm_wait_on_indirect_register(hwmgr, mmSMC_IND_INDEX_11,
smu_data->soft_regs_start +
smum_get_offsetof(hwmgr,
SMU_SoftRegisters, UcodeLoadStatus),
- fw_mask, fw_mask);
+ fw_type, fw_type);
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_
[PATCH 2/3] drm/amd/pp: Setup SoftRegsStart before request smu load fw
need to know SoftRegsStart value to visit the register
UcodeLoadStatus to check fw loading state.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 11 ++-
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 9 +
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
index c712d93..374aa4a 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
@@ -232,6 +232,7 @@ static int iceland_request_smu_load_specific_fw(struct
pp_hwmgr *hwmgr,
static int iceland_start_smu(struct pp_hwmgr *hwmgr)
{
+ struct iceland_smumgr *priv = hwmgr->smu_backend;
int result;
if (!smu7_is_smc_ram_running(hwmgr)) {
@@ -242,6 +243,14 @@ static int iceland_start_smu(struct pp_hwmgr *hwmgr)
iceland_smu_start_smc(hwmgr);
}
+ /* Setup SoftRegsStart here to visit the register UcodeLoadStatus
+* to check fw loading state
+*/
+ smu7_read_smc_sram_dword(hwmgr,
+ SMU71_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU71_Firmware_Header, SoftRegisters),
+ &(priv->smu7_data.soft_regs_start), 0x4);
+
result = smu7_request_smu_load_fw(hwmgr);
return result;
@@ -2652,7 +2661,7 @@ static bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr)
.smu_fini = _smu_fini,
.start_smu = _start_smu,
.check_fw_load_finish = _check_fw_load_finish,
- .request_smu_load_fw = _reload_firmware,
+ .request_smu_load_fw = _request_smu_load_fw,
.request_smu_load_specific_fw = _request_smu_load_specific_fw,
.send_msg_to_smc = _send_msg_to_smc,
.send_msg_to_smc_with_parameter = _send_msg_to_smc_with_parameter,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index ae8378e..1f366c0 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -192,6 +192,7 @@ static int tonga_start_in_non_protection_mode(struct
pp_hwmgr *hwmgr)
static int tonga_start_smu(struct pp_hwmgr *hwmgr)
{
+ struct tonga_smumgr *priv = hwmgr->smu_backend;
int result;
/* Only start SMC if SMC RAM is not running */
@@ -209,6 +210,14 @@ static int tonga_start_smu(struct pp_hwmgr *hwmgr)
}
}
+ /* Setup SoftRegsStart here to visit the register UcodeLoadStatus
+* to check fw loading state
+*/
+ smu7_read_smc_sram_dword(hwmgr,
+ SMU72_FIRMWARE_HEADER_LOCATION +
+ offsetof(SMU72_Firmware_Header, SoftRegisters),
+ &(priv->smu7_data.soft_regs_start), 0x4);
+
result = smu7_request_smu_load_fw(hwmgr);
return result;
--
1.9.1
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[PATCH 1/3] drm/amd/pp: Refine function iceland_start_smu
if upload firmware failed, no matter how many times
the function runs again, the same error will be encountered.
so remove the duplicated code.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
index 73aa368..c712d93 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
@@ -234,22 +234,12 @@ static int iceland_start_smu(struct pp_hwmgr *hwmgr)
{
int result;
- result = iceland_smu_upload_firmware_image(hwmgr);
- if (result)
- return result;
- result = iceland_smu_start_smc(hwmgr);
- if (result)
- return result;
-
if (!smu7_is_smc_ram_running(hwmgr)) {
- pr_info("smu not running, upload firmware again \n");
result = iceland_smu_upload_firmware_image(hwmgr);
if (result)
return result;
- result = iceland_smu_start_smc(hwmgr);
- if (result)
- return result;
+ iceland_smu_start_smc(hwmgr);
}
result = smu7_request_smu_load_fw(hwmgr);
--
1.9.1
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[PATCH 3/6] drm/amdgpu: Fix cg/pg unexpected disabled when hw init failed
Check the ip blocks late_initialized state before enable/disable
cg/pg, so if hw init failed, cg/pg function will not be executed.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 95095a8..94c92f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1656,7 +1656,7 @@ static int amdgpu_device_set_cg_state(struct
amdgpu_device *adev,
for (j = 0; j < adev->num_ip_blocks; j++) {
i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j -
1;
- if (!adev->ip_blocks[i].status.valid)
+ if (!adev->ip_blocks[i].status.late_initialized)
continue;
/* skip CG for VCE/UVD, it's handled specially */
if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
@@ -1686,7 +1686,7 @@ static int amdgpu_device_set_pg_state(struct
amdgpu_device *adev, enum amd_power
for (j = 0; j < adev->num_ip_blocks; j++) {
i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j -
1;
- if (!adev->ip_blocks[i].status.valid)
+ if (!adev->ip_blocks[i].status.late_initialized)
continue;
/* skip CG for VCE/UVD, it's handled specially */
if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
@@ -1723,7 +1723,7 @@ static int amdgpu_device_ip_late_init(struct
amdgpu_device *adev)
int i = 0, r;
for (i = 0; i < adev->num_ip_blocks; i++) {
- if (!adev->ip_blocks[i].status.valid)
+ if (!adev->ip_blocks[i].status.hw)
continue;
if (adev->ip_blocks[i].version->funcs->late_init) {
r = adev->ip_blocks[i].version->funcs->late_init((void
*)adev);
@@ -1732,8 +1732,8 @@ static int amdgpu_device_ip_late_init(struct
amdgpu_device *adev)
adev->ip_blocks[i].version->funcs->name, r);
return r;
}
- adev->ip_blocks[i].status.late_initialized = true;
}
+ adev->ip_blocks[i].status.late_initialized = true;
}
amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
--
1.9.1
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[PATCH 1/6] drm/amdgpu: Remove FW_LOAD_DIRECT type support on VI
AMDGPU_FW_LOAD_DIRECT is used for bring up.
Now it don't work any more. so remove the support.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 3 -
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 249 ++
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c| 57 +--
3 files changed, 56 insertions(+), 253 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 1fa8bc3..fb2bdf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -297,9 +297,6 @@ enum amdgpu_firmware_load_type
case CHIP_POLARIS11:
case CHIP_POLARIS12:
case CHIP_VEGAM:
- if (!load_type)
- return AMDGPU_FW_LOAD_DIRECT;
- else
return AMDGPU_FW_LOAD_SMU;
case CHIP_VEGA10:
case CHIP_RAVEN:
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 2aeef2b..c63ede1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1173,64 +1173,61 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device
*adev)
}
}
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
- info = >firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
- info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
- info->fw = adev->gfx.pfp_fw;
- header = (const struct common_firmware_header *)info->fw->data;
- adev->firmware.fw_size +=
- ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
-
- info = >firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
- info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
- info->fw = adev->gfx.me_fw;
- header = (const struct common_firmware_header *)info->fw->data;
- adev->firmware.fw_size +=
- ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
-
- info = >firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
- info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
- info->fw = adev->gfx.ce_fw;
- header = (const struct common_firmware_header *)info->fw->data;
- adev->firmware.fw_size +=
- ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+ info = >firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
+ info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
+ info->fw = adev->gfx.pfp_fw;
+ header = (const struct common_firmware_header *)info->fw->data;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+
+ info = >firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
+ info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
+ info->fw = adev->gfx.me_fw;
+ header = (const struct common_firmware_header *)info->fw->data;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+
+ info = >firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
+ info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
+ info->fw = adev->gfx.ce_fw;
+ header = (const struct common_firmware_header *)info->fw->data;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+
+ info = >firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
+ info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
+ info->fw = adev->gfx.rlc_fw;
+ header = (const struct common_firmware_header *)info->fw->data;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+
+ info = >firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
+ info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
+ info->fw = adev->gfx.mec_fw;
+ header = (const struct common_firmware_header *)info->fw->data;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+
+ /* we need account JT in */
+ cp_hdr = (const struct gfx_firmware_header_v1_0
*)adev->gfx.mec_fw->data;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
- info = >firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
- info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
- info->fw = adev->gfx.rlc_fw;
- header = (const struct common_firmware_header *)info->fw->data;
+ if (amdgpu_sriov_vf(adev)) {
+ info = >firmware.ucode[AMDGPU_UCODE_ID_STORAGE];
+ info->ucode_id = AMDGPU_UCODE_ID_STORAGE;
+ info->fw = adev->gfx.mec_fw;
adev->
[PATCH 6/6] drm/amdgpu: Drop dead define in amdgpu.h
the struct was not in use any more.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 28
1 file changed, 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 7c44871..c21d9b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -616,31 +616,6 @@ struct amdgpu_wb {
*/
void amdgpu_test_moves(struct amdgpu_device *adev);
-
-/*
- * amdgpu smumgr functions
- */
-struct amdgpu_smumgr_funcs {
- int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t
fwtype);
- int (*request_smu_load_fw)(struct amdgpu_device *adev);
- int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t
fwtype);
-};
-
-/*
- * amdgpu smumgr
- */
-struct amdgpu_smumgr {
- struct amdgpu_bo *toc_buf;
- struct amdgpu_bo *smu_buf;
- /* asic priv smu data */
- void *priv;
- spinlock_t smu_lock;
- /* smumgr functions */
- const struct amdgpu_smumgr_funcs *smumgr_funcs;
- /* ucode loading complete flag */
- uint32_t fw_flags;
-};
-
/*
* ASIC specific register table accessible by UMD
*/
@@ -979,9 +954,6 @@ struct amdgpu_device {
u32 cg_flags;
u32 pg_flags;
- /* amdgpu smumgr */
- struct amdgpu_smumgr smu;
-
/* gfx */
struct amdgpu_gfx gfx;
--
1.9.1
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[PATCH 4/6] drm/amdgpu: Don't allocate memory for ucode when suspend
driver don't release the ucode memory when suspend. so don't
need to allocate bo when resume back.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index fb2bdf3..e7dafa1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -432,7 +432,7 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
return 0;
}
- if (!adev->in_gpu_reset) {
+ if (!adev->in_gpu_reset && !adev->in_suspend) {
err = amdgpu_bo_create_kernel(adev, adev->firmware.fw_size,
PAGE_SIZE,
amdgpu_sriov_vf(adev) ?
AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
>firmware.fw_buf,
--
1.9.1
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[PATCH 2/6] drm/amdgpu: Move gfx flag in_suspend to adev
Move in_suspend flag to adev from gfx, so
can be used in other ip blocks, also keep
consistent with gpu_in_reset flag.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h| 3 +--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 13 +++--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 16
5 files changed, 14 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 6583a68..7c44871 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1046,6 +1046,9 @@ struct amdgpu_device {
bool has_hw_reset;
u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
+ /* s3/s4 mask */
+ boolin_suspend;
+
/* record last mm index being written through WREG32*/
unsigned long last_mm_index;
boolin_gpu_reset;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a1d8d97..95095a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2649,6 +2649,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool
suspend, bool fbcon)
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
return 0;
+ adev->in_suspend = true;
drm_kms_helper_poll_disable(dev);
if (fbcon)
@@ -2834,6 +2835,8 @@ int amdgpu_device_resume(struct drm_device *dev, bool
resume, bool fbcon)
#ifdef CONFIG_PM
dev->dev->power.disable_depth--;
#endif
+ adev->in_suspend = false;
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index f172e92..b61b5c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -297,8 +297,7 @@ struct amdgpu_gfx {
/* reset mask */
uint32_tgrbm_soft_reset;
uint32_tsrbm_soft_reset;
- /* s3/s4 mask */
- boolin_suspend;
+
/* NGG */
struct amdgpu_ngg ngg;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index c63ede1..6b1954e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4732,7 +4732,7 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring
*ring)
struct vi_mqd *mqd = ring->mqd_ptr;
int mqd_idx = ring - >gfx.compute_ring[0];
- if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
+ if (!adev->in_gpu_reset && !adev->in_suspend) {
memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0x;
((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0x;
@@ -4991,19 +4991,12 @@ static int gfx_v8_0_hw_fini(void *handle)
static int gfx_v8_0_suspend(void *handle)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- adev->gfx.in_suspend = true;
- return gfx_v8_0_hw_fini(adev);
+ return gfx_v8_0_hw_fini(handle);
}
static int gfx_v8_0_resume(void *handle)
{
- int r;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- r = gfx_v8_0_hw_init(adev);
- adev->gfx.in_suspend = false;
- return r;
+ return gfx_v8_0_hw_init(handle);
}
static bool gfx_v8_0_check_soft_reset(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 7a6a814..4b020cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3198,7 +3198,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring
*ring)
struct v9_mqd *mqd = ring->mqd_ptr;
int mqd_idx = ring - >gfx.compute_ring[0];
- if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
+ if (!adev->in_gpu_reset && !adev->in_suspend) {
memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0x;
((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0x;
@@ -3417,7 +3417,7 @@ static int gfx_v9_0_hw_fini(void *handle)
/* Use deinitialize sequence from CAIL when unbinding device from
driver,
* otherwise KIQ is hanging when binding back
*/
- if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
+ if (!adev->in_gpu_reset && !adev->in_suspend) {
mutex_lock(>srbm_mutex);
soc15_
