From: Aric Cyr
This DC version brings along:
- FW Release 0.0.162.0
- Enable FPO+Vactivate
- Support for VESA SCR on OLED
- Refactor DMUB commands
- Fixes in secure display, modeset, memleak and more
- Picked up missed patches in history
Acked-by: Qingqing Zhuo
Signed-off-by: Aric Cyr
| uint32_t otg_inst = pipe_ctx->stream_res.tg->inst;
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hwseq.c:226:27: warning:
unused variable ‘cmd’ [-Wunused-variable]
226 | union dmub_rb_cmd cmd;
Reviewed-by: Qingqing Zhuo
Reviewed-b
From: Po-Ting Chen
Base on PSRSU specification, every seletive update frame need to use two
SDP to indicate the frame active range. So we occupy another GSP1 for
PSRSU execution.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Po-Ting Chen
---
.../display/dc/dcn30/dcn30_dio_stream_encoder.c |
From: Nicholas Kazlauskas
[Why]
The bit for flip addr is being set causing the determination for
FAST vs MEDIUM to always return MEDIUM when plane info is provided
as a surface update. This causes extreme stuttering for the typical
atomic update path on Linux.
[How]
Don't use update_flags->raw
From: Aurabindo Pillai
DCN31 supports FAMS, but this was not correctly set to the hardware
setup sequence. This commit fixes this issue by setting the MCLK switch
capability based on the feature capability retrieved from the DMUB.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
From: Aurabindo Pillai
[Why]
Add Enum and documenation related to FAMS (Firmware Assisted Memclk
Switching) and CAB (Cache As Buffer)
Reviewed-by: Qingqing Zhuo
Reviewed-by: Leo Li
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 17 +++--
1
From: Zhongwei
[Why]
disable_vbios_mode_if_required() will set dpms_off to false during boot
when pixel clk dismatches with driver requires. This will cause extra
backlight on and off if OS call 2 times setmode.
[How]
Set dpms_off to true to keep power_off and let OS control backlight by
From: Igor Kravchenko
Add min_width, min_height fields to dc_plane_cap structure. Set values
to 16x16 for discrete ASICs, and 64x64 for others.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Igor Kravchenko
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 4 +++-
1 file changed, 3
From: Meenakshikumar Somasundaram
[Why]
Currently driver enables dmub outbox notification before oubox ISR is
registered. During boot scenario, sometimes dmub issues hpd outbox
message before driver registers ISR and those messages are missed.
[How]
Enable dmub outbox notification after outbox
From: Dmytro Laktyushkin
Dst_y can become negative in extreme odm 4to1 cases. While not strictly
invalid, this should be limited to 0 for rq/dlg/ttu calculation.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Dmytro Laktyushkin
---
.../gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
From: Aurabindo Pillai
DCN30 is missing a check for the pixel format 444 when using 16bits
before setting the flag that Viewport exceeds the surface.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 2 +-
1
From: Krunoslav Kovac
Enable 3-planes MPO for DCN321 by reporting max_slave_planes in DC caps
for each ASIC.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Krunoslav Kovac
---
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
From: Sherry Wang
[Why]
DML calculation is different from HW formula.
[How]
Correct the bug to keep it same as HW formula.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Sherry Wang
---
.../gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c| 4 ++--
From: Jasdeep Dhillon
[Why]
DCN32 resource contains code that uses FPU.
[How]
Moved code into DCN32 FPU
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Jasdeep Dhillon
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 6 ++
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h | 2
From: Aurabindo Pillai
Drop duplicate check for DET Swath in DCN32.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 1 -
1 file changed, 1 deletion(-)
diff --git
From: Aurabindo Pillai
Set DRAM clock change state if retraining is required.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Aurabindo Pillai
For pstate change, allow DML to loop through
all possible prefetch combinations so as to
support more display configurations. Set the max
and min prefetch modes to enable the sequence.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
---
From: Aurabindo Pillai
[Why]
Update bounding box values as per hardware spec
Fixes: 1951340bd31a ("drm/amd/display: Create dcn321_fpu file")
Acked-by: Leo Li
Signed-off-by: Aurabindo Pillai
---
.../amd/display/dc/dml/dcn321/dcn321_fpu.c| 24 +--
1 file changed, 12
From: Aurabindo Pillai
[WHY]
Low bpc timings are failing validation, port a patch to allow them to pass.
Signed-off-by: Dillon Varone
Acked-by: Aurabindo Pillai
---
.../dc/dml/dcn32/display_mode_vba_util_32.c| 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff
From: Aurabindo Pillai
[Why & How]
There's no need to clear GPINT register for DMUB
when releasing it from reset. Fix that.
Fixes: ac2e555e0a7f ("drm/amd/display: Add DMCUB source files and changes for
DCN32/321")
Reviewed-by: Leo Li
Signed-off-by: Aurabindo Pillai
---
From: Samson Tam
[Why]
Workaround for DMCUB front door load
[How]
Clear GPINT after reset so its consistent
Signed-off-by: Samson Tam
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
From: Aurabindo Pillai
[Why]
Fix CLK MGR early initialization and add logging.
Fixes: 265280b99822 ("drm/amd/display: add CLKMGR changes for DCN32/321")
Reviewed-by: Leo Li
Reviewed-by: Qingqing Zhuo
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/clk
From: Cruise Hung
[Why & How]
We missed resetting OUTBOX0 mailbox r/w pointer on DMUB reset.
Fix it.
Fixes: 6ecf9773a503 ("drm/amd/display: Fix DMUB outbox trace in S4")
Signed-off-by: Cruise Hung
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 2 ++
1 file
From: Alvin Lee
[Why]
- Implement interface to program DTBCLK DTO’s
according to reference DTBCLK returned by PMFW
- This is required because DTO programming
requires exact DTBCLK reference freq or it could
result in underflow
Acked-by: Aurabindo Pillai
Signed-off-by: Alvin Lee
---
From: Tianci Yin
[why]
Since the variable fpu_recursion_depth is per-CPU type, it has one copy
on each CPU, thread migration causes data consistency issue, then the
call trace shows up. And preemption disabling can't prevent migration.
[how]
Disable migration to ensure consistency of
From: Wesley Chalmers
[WHY]
Add log entry for when display refresh from MALL
settings are sent to SMU.
Fixes: 1664641ea946 ("drm/amd/display: Add logger for SMU msg")
Signed-off-by: Wesley Chalmers
Acked-by: Aurabindo Pillai
---
.../drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
From: Mikita Lipski
Extract edid's checksum and send it back for verification if EDID_TEST
is requested.
Signed-off-by: Mikita Lipski
Acked-by: Aurabindo Pillai
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 30 +--
1 file changed, 27 insertions(+), 3 deletions(-)
diff
From: hersen wu
[Why]
We were not returning -EINVAL on DSC atomic check fail. Add it.
Fixes: 71be4b16d39a ("drm/amd/display: dsc validate fail not pass to atomic
check")
Reviewed-by: Aurabindo Pillai
Signed-off-by: Hersen Wu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |
From: Aurabindo Pillai
[Why]
Remove incorrect early return in a device specific fifo reset workaround
Reviewed-by: Leo Li
Reviewed-by: Qingqing Zhuo
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 1 -
1 file changed, 1 deletion(-)
diff --git
term, filter out in dc bandwidth validation.
[How]
Force 2K@240Hz+8K@24Hz timing validation false in dc.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Daniel Miess
---
.../amd/display/dc/dcn314/dcn314_resource.c | 20 +++
1 file changed, 20
From: Eric Yang
[Why]
If optimized init is done in FW. DCN init can be skipped in driver. This
need to be communicated between driver and fw and maintain backwards
compatibility.
[How]
Use DMUB scratch 0 bit 2 to indicate optimized init done in fw and
use DMUB scatch 4 bit 0 to indicate drive
From: Dmytro Laktyushkin
[Why & How]
Fix a typo for dcn315 line buffer bpp.
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Dmytro Laktyushkin
---
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
From: Dmytro Laktyushkin
[Why & How]
Add options for dc odm debug.
Reviewed-by: Ariel Bernstein
Acked-by: Qingqing Zhuo
Signed-off-by: Dmytro Laktyushkin
---
drivers/gpu/drm/amd/display/dc/dc.h| 2 ++
drivers/gpu/drm/amd/display/dc/dc_stream.h | 5 +
2 files change
From: Alex Hung
[Why & How]
timing.dsc_cfg.num_slices_v can be zero and it is necessary to check
before using it.
This fixes the error "divide error: [#1] PREEMPT SMP NOPTI".
Reviewed-by: Aurabindo Pillai
Acked-by: Qingqing Zhuo
Signed-off-by: Alex Hung
---
drive
and
disable_link_dp once.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Jingwen Zhu
---
.../display/dc/dce110/dce110_hw_sequencer.c | 19 +++
.../gpu/drm/amd/display/dc/link/link_dpms.c | 5 +
2 files changed, 16 insertions(+), 8 deletions(-)
diff
mode. Do not reset panel mode to default while performing link
training if previously used panel mode = eDP.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Michael Mityushkin
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../gpu/drm/amd
From: Anthony Koo
- Add DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command
- Remove d3 entry event and instead check for stream mask
- dmu: Enable timeout recovery and detection for p-state
Acked-by: Qingqing Zhuo
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 9
From: Alvin Lee
[Description]
- Enable FPO + Vactive
Reviewed-by: George Shen
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 2 +-
2 files changed, 2 insertions
at least two horizontal slices are used for DSC when
ODM combine is forced.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Nasir Osman
---
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 1 +
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 10 +-
2 files changed, 10
-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 23a972f2885f..2f7723053042 100644
of
core_link_disable_stream or set_dpms_off.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Michael Mityushkin
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 1 +
drivers/gpu/drm/amd/display/dc
From: Rodrigo Siqueira
To ensure that FAMS can be used, DC must check if there is VRR support.
This commit adds the required configuration to ensure FAMS can be executed in
the target system.
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm
From: Iswara Nagulendran
[HOW]
Write DPCD 721 bit 7 to high, and
the appropriate luminance level
to DPCD 734-736 if bit 4 from DPCD register
734 is high, indicating that the panel
luminance control is enabled from the panel side.
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
Signed-off
From: Josip Pavic
[Why & How]
Consolidate dmub access to a single interface. This makes it easier to
add code in the future that needs to run every time a dmub command is
requested (e.g. instrumentation, locking etc).
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed
From: Alvin Lee
[Description]
- Previous bug fix for audio issue included dtbclk and p-state
on the optimized boot path which is incorarect
- We only care about DISPCLK in the optimized vs. non-optimized
boot path to avoid audio issues
Reviewed-by: Saaem Rizvi
Acked-by: Qingqing Zhuo
Acked-by: Qingqing Zhuo
Signed-off-by: Hersen Wu
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c| 6 ++
.../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 16 ++--
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 181a3408cc61..25284006019c 100644
--- a/drivers
From: Josip Pavic
[Why & How]
If dmub command queuing fails due to the inbox being full, flush the
inbox and resubmit the comamnd. This was previously the default behavior
but was lost in a refactor.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Josip P
From: Dmytro Laktyushkin
Increse to 6 as that is the max surfaces supported asics can have.
The is no practical use case yet, but this is valuable for pre-si
validation.
Reviewed-by: Ariel Bernstein
Acked-by: Qingqing Zhuo
Signed-off-by: Dmytro Laktyushkin
---
drivers/gpu/drm/amd/display/dc
From: Alex Hung
[Why]
When IGT's kms_hdmi_inject forces EDID for HDMI audio, dc rejects the
request because virtual signal is not in dc_is_audio_capable_signal
function.
[How]
Includes SIGNAL_TYPE_VIRTUAL as audio capable.
Reviewed-by: Chao-kai Wang
Acked-by: Qingqing Zhuo
Signed-off
s null.
Reviewed-by: Qingqing Zhuo
Acked-by: Qingqing Zhuo
Signed-off-by: Hersen Wu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amd
display was enabled or not before stopping it in dmub.
Reviewed-by: Wayne Lin
Acked-by: Qingqing Zhuo
Signed-off-by: Alan Liu
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 31 ---
1 file changed, 13 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display
From: Aurabindo Pillai
[Why]
When skipping full modeset since the only state change was a front porch
change, the DC commit sequence requires extra checks to handle non
existant plane states being asked to be removed from context.
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off
From: Rodrigo Siqueira
When the commit a983d2631869 (drm/amd/display: Don't set dram clock
change requirement for SubVP) was merged, we missed some parts
associated with the MCLK switch. This commit adds all the missing parts.
Fixes: a983d2631869 (drm/amd/display: Don't set dram clock change
From: Josip Pavic
[Why & How]
Add code path to copy dmub caps to dc, which is missing on dcn31
Acked-by: Qingqing Zhuo
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/displa
From: Leon Huang
[Why]
set ABM pipe/backlight gets some issues when abm callback func pointers
are NULL. For some usecase, driver would like to control PWM level before
ABM resource is ready. However, recent flow refactor of ABM didn't
consider that use case.
[How]
Rollback flow that sending
From: Wesley Chalmers
[WHY]
It is possible to commit state multiple times in rapid succession with
FAMS enabled; if each of these commits were to set optimized_required,
then the user may see latency.
[HOW]
fw_based_mclk_switching is currently not used in dc->clk_mgr; use it
to track whether
From: Leon Huang
[Why]
Refactor ABM feature and implement inbox command for DMUB.
[How]
Implement the ioctl to send inbox command to DMUB.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Leon Huang
---
drivers/gpu/drm/amd/display/dc/dce/Makefile | 2 +-
From: Wesley Chalmers
[WHY]
Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
pipe commit can cause underflow.
[HOW]
Move DMUB p-state delegate into optimze_bandwidth; enabling FAMS sets
optimized_required.
This change expects that Freesync requests are blocked when
From: Rodrigo Siqueira
This commit replaces spaces with tabs in multiple functions and adjusts
the indentation in some other parts of the code to improve readability.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 44 ++---
From: Rodrigo Siqueira
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
From: Rodrigo Siqueira
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
From: Rodrigo Siqueira
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
From: Rodrigo Siqueira
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
From: Rodrigo Siqueira
When using FPO, there is some misconfiguration that happens for the lack
of configuration of the MCLK switch in some circumstances. This commit
adds the required field update when using the MCLK switch.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
From: Rodrigo Siqueira
All clock values came from firmware, but bounding box values can be
helpful in some debug situations. This commit updates some of the values
associated with clock speed and memory channels.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- FW Release 0.0.162.0
- Enable FPO+Vactivate
- Support for VESA SCR on OLED
- Refactor DMUB commands
- Fixes in secure display, modeset, memleak and more
- Picked up missed patches in history
Cc: Daniel Wheeler
From: Aric Cyr
This DC version brings along:
- FW Release 0.0.161.0
- Improvements on FPO/FAMS
- Correction to DML calculation
- Fix to multiple clock related issues
Acked-by: Qingqing Zhuo
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion
From: Anthony Koo
- Add command to idle opt.
- Rename d3 entry event and add idle trigger param on
notify event.
- Add bit to fw boot status to notify status when hardware
is powered up.
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
Signed-off-by: Anthony Koo
---
.../gpu/drm/amd
From: Michael Strauss
[WHY]
New sequence for transparent mode DP1.x link training was provided by LTTPR
vendor
[HOW]
Implement new FIXED_VS sequence, increase LT retry count to minimize
any potential intermittent lightup failures
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off
From: Charlene Liu
[why]
based on dscclk instance offset check conditiona program dscclk
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Charlene Liu
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 8
.../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 18
the same value to ensure
the timing is valid and unchanged
- However, add option to do a full pipe power down (including link)
which will also avoid audio related issues
- Disabled for the time being on dcn32
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
-by: Nicholas Kazlauskas
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Paul Hsieh
---
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 2 +-
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 2 +-
.../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
From: Alvin Lee
[Description]
- When determining FPO support, include FPO + VActive support
- Support FPO + VActive if one display meets regular requirements
for FPO and the second display is able to switch in VACTIVE with
a given amount of margin
Reviewed-by: Jun Lei
Acked-by: Qingqing
is mostly in alignment with dccg31_init() but
accounts for the new DPSTREAMCLK sequence.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Hamza Mahfooz
---
.../drm/amd/display/dc/dcn314/dcn314_dccg.c | 28 ++-
.../drm/amd/display/dc/dcn314/dcn314_dccg.h
From: Zhikai Zhai
[WHY]
It will introduce the extra warnning log on some asic
that doesn't register
[HOW]
Add the register on dcn32
Reviewed-by: Dmytro Laktyushkin
Acked-by: Qingqing Zhuo
Signed-off-by: Zhikai Zhai
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h | 1 +
1 file
From: Alvin Lee
[Description]
- If we find that applying FAMS doesn't reduce the voltage level,
we will not use it
- Ensure to clear the stream flags indicating FAMS if we hit this
case
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- FW Release 0.0.161.0
- Improvements on FPO/FAMS
- Correction to DML calculation
- Fix to multiple clock related issues
Cc: Daniel Wheeler
---
Alvin Lee (3):
drm/amd/display: Clear FAMS flag if FAMS doesn't
From: Aric Cyr
This DC version brings along:
- Enable FPO optimization
- Support for 6.75 GBps link rate
- Fixes to underflow, black screen and more
Acked-by: Qingqing Zhuo
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion
From: Anthony Koo
- New parameter to define extra vblank stretch required when
doing FPO + Vactive
- Pass in pipe index for FPO
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 14 +++---
1 file changed
From: Alvin Lee
[Description]
Assign the correct info now that FW headers are promoted
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display
From: Peichen Huang
[Why]
Some dock and mst monitor don't like to receive ClearPayloadIdTable
when mst_en is set to 0. And it doesn't make sense to do so in source
side, either.
[How]
Not send ClearyPayloadIdTable if mst_en is 0
Reviewed-by: George Shen
Acked-by: Qingqing Zhuo
Signed-off
From: Alvin Lee
[Description]
Enable optimization for preferring FPO if it achieves
a lower voltage level
Reviewed-by: George Shen
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn321
From: Alvin Lee
[Description]
If transitioning from an FPO config -> FPO config, we want
to keep cursor P-State force disallowed. Any other transition
from FPO config -> non FPO config should unforce the cursor
P-State disallow
Reviewed-by: Wesley Chalmers
Acked-by: Qingqing Zhuo
Sign
this feature until we can validate it with real hardware.
[How]
- Add boolean flag support_eDP1_5 in struct dc_debug_options.
- Enable the 6.75 link rate in reduce_link_rate(...) only when
the flag is true.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Artem Grishin
---
drivers/gpu
for P-State disallow,
use per pipe p-state force instead
- This is in preparation to enable FPO + VActive
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 46 +++
drivers/gpu/drm/amd/display/dc/dc_stream.h
From: Artem Grishin
[Why]
The latest eDP spec version 1.5 defines a new generic link
rate of 6.75 Gbps/Lane, which needs to be supported in the driver.
[How]
Added new element to the dc_link_rate enum
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Artem Grishin
which enables P-state switching.
Just added a conditional check to avoid setting hardmax on init.
Reviewed-by: Alvin Lee
Reviewed-by: Martin Leung
Acked-by: Qingqing Zhuo
Signed-off-by: Ayush Gupta
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 3 ++-
drivers/gpu/drm/amd/display/dc
As part of the FAMS work, we need code infrastructure in DC.
dcn30_fpu.c changes went missing during previous upstream
activity.
Reviewed-by: Rodrigo Siqueira
Acked-by: Qingqing Zhuo
Signed-off-by: Qingqing Zhuo
---
.../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 53 ---
1
From: Taimur Hassan
[Why & How]
Needed to get certain EDID to light up during TMDS compliance.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Taimur Hassan
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/dri
From: Dmytro Laktyushkin
[Why & How]
w/a for dcn315 inconsistent smu clock.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Dmytro Laktyushkin
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 5 +
1 file changed, 5 insertions(+)
diff -
From: Charlene Liu
[why]
HW delta follow up
Reviewed-by: Chris Park
Reviewed-by: Jun Lei
Reviewed-by: Jerry Zuo
Acked-by: Qingqing Zhuo
Signed-off-by: Charlene Liu
---
.../amd/display/dc/dcn32/dcn32_dio_stream_encoder.c | 10 +-
.../amd/display/dc/dcn32
sta...@vger.kernel.org
Cc: Mario Limonciello
Reviewed-by: Leo Ma
Acked-by: Qingqing Zhuo
Signed-off-by: Martin Leung
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm
From: Alvin Lee
[Descrtipion]
- Driver hardcoded FCLK P-State latency was incorrect
- Use the value provided by PMFW header instead
Reviewed-by: Nevenko Stupar
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2
DOMAIN.
The new sequence should be:
Power down: PG enabled -> RCO on
Power up: RCO off -> PG disabled
Rename power_on_plane to power_on_plane_resources to reflect the
actual operation that's occurring.
Cc: sta...@vger.kernel.org
Cc: Mario Limonciello
Reviewed-by: Jun Lei
Acked-by: Qingqin
, have debug option to enable
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 1 +
.../amd/display/dc/dcn321/dcn321_resource.c | 1 +
.../drm/amd/display/dc/dml/dcn32
...@vger.kernel.org
Cc: Mario Limonciello
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10
disable logic
drm/amd/display: Fix 4to1 MPC black screen with DPP RCO
Peichen Huang (1):
drm/amd/display: skip ClearPayloadIdTable if device mst_en is 0
Qingqing Zhuo (1):
drm/amd/display: Add infrastructure for enabling FAMS for DCN30
Taimur Hassan (1):
drm/amd/display: Add 90Mhz
Siqueira
Acked-by: Qingqing Zhuo
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index
From: Aric Cyr
This DC version brings along:
- Power down eDP if eDP not present
- Set MPC_SPLIT_DYNAMIC for DCN10 and DCN301
- Initialize link_srv in virtual env
- Code cleanup and alignment
Acked-by: Qingqing Zhuo
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
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