On Tue, Jan 17, 2017 at 12:14:24AM +0200, Laurent Pinchart wrote:
> Hi Harry,
>
> On Monday 16 Jan 2017 16:13:39 Harry Wentland wrote:
> > On 2017-01-16 03:39 PM, Laurent Pinchart wrote:
> > > On Monday 16 Jan 2017 10:44:54 Andrey Grodzovsky wrote:
> > >> This series is a folow-up on
> > >> https:
On Mon, Jan 16, 2017 at 10:44:55AM -0500, Andrey Grodzovsky wrote:
> Allows using atomic flip helpers for drivers
> using ASYNC flip.
> Remove ASYNC_FLIP restriction in helpers and
> caches the page flip flags in drm_plane_state
> to be used in the low level drivers.
>
> Signed-off-by: Andrey Grod
Change-Id: Ic32eb032eacb5eaa08ba23a83e834472774fb5c3
Signed-off-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 3 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
drivers/gpu/drm
Am 23.01.2017 um 09:37 schrieb Junwei Zhang:
Change-Id: Ic32eb032eacb5eaa08ba23a83e834472774fb5c3
Signed-off-by: Junwei Zhang
Oh, yeah good catch. That was removed quite a while ago.
Patch is Reviewed-by: Christian König .
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++--
drivers/gpu
Am 23.01.2017 um 03:46 schrieb Michel Dänzer:
On 23/01/17 04:15 AM, Nils Holland wrote:
From d44ac1157fdb86e67822b6538ae6113c8d620412 Mon Sep 17 00:00:00 2001
From: Nils Holland
Date: Sun, 22 Jan 2017 13:24:52 +0100
Subject: [PATCH] drm/amdgpu: Bring bo creation in line with radeon driver
Add
we fixed this issue on Kv as uvd pg was enabled on APU.
We need to change the uvd cg mode.
When idle, use hw cg. And encode, use sw cg.
So
WREG32(mmUVD_CGC_GATE, 0); // ture off cg.
Then
uvd_v4_2_set_dcm(adev, true); // set sw cg.
The first patch can fix this issue.
The second dpm patch can
On Mon, Jan 23, 2017 at 10:55:49AM +, Zhu, Rex wrote:
> we fixed this issue on Kv as uvd pg was enabled on APU.
>
> We need to change the uvd cg mode.
> When idle, use hw cg. And encode, use sw cg.
>
> So
> WREG32(mmUVD_CGC_GATE, 0); // ture off cg.
> Then
> uvd_v4_2_set_dcm(adev, true);
Am 22.01.2017 um 04:55 schrieb Monk Liu:
previously we always insert 128nops behind vm_flush, which
may lead to DAMframe size above 256 dw and automatially aligned
to 512 dw.
now we calculate how many DWs already inserted after vm_flush
and make up for the reset to pad up to 128dws before emit_i
From: Tony Cheng
- these are moved to color module
Change-Id: I2131991772553893b91ba9b927d20306e846141b
Signed-off-by: Tony Cheng
Acked-by: Harry Wentland
Reviewed-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/basics/conversion.c | 118 -
drivers/gpu/drm/amd/display/dc/
From: Amy Zhang
- Made sure dest color space is updated in stream and info frame
- Optimized segment distribution algorithm for regamma mapping
Change-Id: Ia9bb4e56719e23a9827080194d89f715ee5fde29
Signed-off-by: Amy Zhang
Acked-by: Harry Wentland
Reviewed-by: Aric Cyr
---
drivers/gpu/drm/amd
From: Andrey Grodzovsky
Use new functions so flip failures can be gracefully handled
v2:
Avoid -EINVAL returned from amdgpu_crtc_prepare_flip in some
error cases, it is not allowed according to expected
return values for atomic_commit hook.
Change-Id: Ie04af6f0c56ee822ddb9f24fb77f367b4e31c620
S
From: Tony Cheng
Change-Id: Id5c632c474a1643825c0bedbaf8be9c12bb36dca
Signed-off-by: Tony Cheng
Reviewed-by: Harry Wentland
---
.../drm/amd/display/dc/dce/dce_stream_encoder.c| 2 +-
.../amd/display/dc/dce110/dce110_hw_sequencer.c| 2 +-
.../gpu/drm/amd/display/dc/inc/hw/stream_encod
From: Tony Cheng
- include clock constraint logic in validate
- in dc_commit_streams, include surfaces of unaffected streams
Change-Id: I43488ffa9002bd00740a4edb39c362b0257bdb11
Signed-off-by: Yongqiang Sun
Acked-by: Harry Wentland
Reviewed-by: Dmytro Laktyushkin
---
drivers/gpu/drm/amd/disp
From: Tony Cheng
Change-Id: I8d7266d9542132b2a4406eb7591a75769998e984
Signed-off-by: Tony Cheng
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 76 --
.../gpu/drm/amd/display/dc/bios/command_table.c| 114 -
.../gpu/drm/a
From: Anthony Koo
Add NULL check in modules
Change-Id: I3e668c93b16795c539ac790638694c2b4c4dab28
Signed-off-by: Anthony Koo
Acked-by: Harry Wentland
Reviewed-by: Tony Cheng
---
.../drm/amd/display/modules/freesync/freesync.c| 94 +++---
.../gpu/drm/amd/display/modules/inc
From: Andrey Grodzovsky
Change-Id: Iaf1b717863c59810657e66835468628acf3aee4c
Signed-off-by: Andrey Grodzovsky
Acked-by: Harry Wentland
Reviewed-by: Tony Cheng
Reviewed-by: Jordan Lazare
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ---
1 file changed, 4 insertions(+), 3 dele
From: Leon Elazar
Also avoid allocating memory dce110_set_output_transfer_func
if not needed
Change-Id: Ica29ab36d1bb47451550e2f6ee0cdf8617c44a48
Signed-off-by: Leon Elazar
Acked-by: Harry Wentland
Reviewed-by: Tony Cheng
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c| 6 +++--
dri
From: Leon Elazar
This will fix the memory Input programing with MST tiled display.
This Fix should fix connectivity problems with MST tiled Display
Change-Id: I2cf36a325a44edd4198e30f9fc801208399e1a83
Signed-off-by: Leon Elazar
Acked-by: Harry Wentland
Reviewed-by: Tony Cheng
---
drivers/gp
From: Amy Zhang
Change-Id: I572a114be92e8d1e92780793ffdc0644c805c36e
Signed-off-by: Amy Zhang
Acked-by: Harry Wentland
Reviewed-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/
From: Tony Cheng
- not all DCE has PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE bit defined.
Change-Id: I4bf25deb134637c713ac5ee1eac786bafdc9eb4a
Signed-off-by: Tony Cheng
Acked-by: Harry Wentland
Reviewed-by: Yongqiang Sun
---
.../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 57 ---
From: Dmytro Laktyushkin
Change-Id: I4eb19bf87e3cee5fb51f572fc866f2e641021884
Signed-off-by: Dmytro Laktyushkin
Acked-by: Harry Wentland
Reviewed-by: Tony Cheng
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/co
From: Tony Cheng
- construct using encoder_info_frame directly
Change-Id: I95a2cdb6cdeaccea8c87c9c3ff6be9673ba65afe
Signed-off-by: Tony Cheng
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 124 +++--
.../drm/amd/display/include/hw_sequence
From: Andrey Grodzovsky
Change-Id: Ia59c22ea5a78d5eecca6c62c7f50e651f29ef5f7
Signed-off-by: Andrey Grodzovsky
Acked-by: Harry Wentland
Reviewed-by: Tony Cheng
---
.../amd/display/dc/irq/dce110/irq_service_dce110.c | 42 ++
.../amd/display/dc/irq/dce80/irq_service_dce80.c
From: Amy Zhang
- Create translation function to translate logical format to hw format
- Refactor to use transfer function in dc instead of input gamma
Change-Id: If7ea756ea206c3776ab328f3b351ce546ae080a0
Signed-off-by: Amy Zhang
Acked-by: Harry Wentland
Reviewed-by: Anthony Koo
---
drivers/
From: Tony Cheng
Change-Id: Ib32be9d265062d862557568b19160d7a866bb454
Signed-off-by: Tony Cheng
Reviewed-by: Harry Wentland
---
.../gpu/drm/amd/display/dc/basics/signal_types.c | 35 ---
.../gpu/drm/amd/display/dc/bios/command_table.c| 55 --
.../gpu/drm/amd/display/dc/bios
From: Tony Cheng
DC actually support ABGR instead of BGRA (R/B swap rather than endian
swap) ,
rename to avoid confusion
Change-Id: Ib0e30df605268b2d4567dd21e3e6a9db48471f92
Signed-off-by: Tony Cheng
Acked-by: Harry Wentland
Reviewed-by: Yongqiang Sun
---
drivers/gpu/drm/amd/display
From: Zeyu Fan
Change-Id: I621c2356319229c5e455d2fd6ccbedc4a74077ae
Signed-off-by: Zeyu Fan
Acked-by: Harry Wentland
Reviewed-by: Tony Cheng
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc
From: Tony Cheng
- mask = 0 means something is wrong in caller and no register field will be
updated
Change-Id: Ib30c28ca30f574c703cd3b6acc42e5a401a9aff0
Signed-off-by: Tony Cheng
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dm_services.h | 1 +
1 file changed, 1 insertion
From: Yongqiang Sun
Change-Id: Ifcec8c22d0df9434a470e2abc1bc77f503d9c0f7
Signed-off-by: Yongqiang Sun
Acked-by: Harry Wentland
Reviewed-by: Tony Cheng
---
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/a
From: Andrey Grodzovsky
Switch from VUPDATE to VBLANK.
Change-Id: I8652e01091efe91c3c7ad71004d170af412da9f5
Signed-off-by: Andrey Grodzovsky
Acked-by: Harry Wentland
Reviewed-by: Tony Cheng
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +++--
drivers/gpu/drm/amd/disp
From: Hersen Wu
Change-Id: I36ffd7bb121067d85d43ab90c9abf62981d50ed7
Signed-off-by: Hersen Wu
Acked-by: Harry Wentland
Reviewed-by: Eagle Yeh
---
drivers/gpu/drm/amd/display/dc/dce/dce_audio.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/
From: Dmytro Laktyushkin
Change-Id: I2e7e1531259f1d58c2d4dc02817f0ad6e8104f19
Signed-off-by: Dmytro Laktyushkin
Acked-by: Harry Wentland
Reviewed-by: Tony Cheng
---
drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 8 ++--
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 4
2 files ch
From: Tony Cheng
Change-Id: I67199dfb44db442aee25ebc73dea50e5c935bb84
Signed-off-by: Tony Cheng
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/basics/log_helpers.c | 1 -
drivers/gpu/drm/amd/display/dc/basics/signal_types.c | 3 +--
drivers/gpu/drm/amd/display/dc/core/dc_lin
* Use VBLANK instead of VUPDATE for VBLANK notification
* Cleanup pflip code a bit more
* Bunch of bug fixes all over the place
* Removing some more dead code
Amy Zhang (3):
drm/amd/display: Output Transfer Function Regamma Refactor
drm/amd/display: Set default degamma to sRGB instead of bypa
I don't think is correct. The incoming handle is in shared_handle, not
in handle. Once the code block around line 310 has executed,
shared_handle is the handle produced by drmPrimeFDToHandle, and closing
it on error (as the code currently does) should be the correct thing to do.
The only possi
On 22.01.2017 19:48, Emil Velikov wrote:
Cc: amd-gfx@lists.freedesktop.org
Signed-off-by: Emil Velikov
Reviewed-by: Nicolai Hähnle
---
amdgpu/amdgpu_bo.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index d30fd1e7..c9f31587 100644
--- a/amdgpu
On Mon, Jan 23, 2017 at 9:36 AM, Harry Wentland wrote:
> From: Andrey Grodzovsky
>
> Change-Id: Ia59c22ea5a78d5eecca6c62c7f50e651f29ef5f7
> Signed-off-by: Andrey Grodzovsky
> Acked-by: Harry Wentland
> Reviewed-by: Tony Cheng
> ---
> .../amd/display/dc/irq/dce110/irq_service_dce110.c | 42
>
> -Original Message-
> From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf
> Of Daniel Vetter
> Sent: Monday, January 23, 2017 3:55 AM
> To: Grodzovsky, Andrey
> Cc: Deucher, Alexander ;
> nouv...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; dri-
> de...@l
On Sun, Jan 22, 2017 at 8:47 AM, Nicolas Iooss
wrote:
> In smu7_clockpowergating.h, the #ifndef statement which prevents
> multiple inclusions of the header file uses _SMU7_CLOCK_POWER_GATING_H_
> but the following #define statement uses _SMU7_CLOCK__POWER_GATING_H_.
>
> Signed-off-by: Nicolas Ioo
On Mon, Jan 23, 2017 at 5:29 AM, Christian König
wrote:
> Am 23.01.2017 um 03:46 schrieb Michel Dänzer:
>>
>> On 23/01/17 04:15 AM, Nils Holland wrote:
>>>
>>> From d44ac1157fdb86e67822b6538ae6113c8d620412 Mon Sep 17 00:00:00 2001
>>> From: Nils Holland
>>> Date: Sun, 22 Jan 2017 13:24:52 +0100
On Tue, Jan 24, 2017 at 06:37:58AM +0800, kbuild test robot wrote:
>
>drivers/gpu/drm/amd/amdgpu/amdgpu_object.c: In function
> 'amdgpu_bo_create_restricted':
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:377:2: warning: #warning Please
> >> enable CONFIG_MTRR and CONFIG_X86_PAT for better
So I decided to fix this with the following follow-up patch. I hope
this is the right approach (vs. reverting the commit and instead using
a fixed v2 of the original patch).
From 41775d2c8a14873f522667a57b66cfbe119e28a4 Mon Sep 17 00:00:00 2001
From: Nils Holland
Date: Tue, 24 Jan 2017 01:36:45 +
On 24/01/17 09:55 AM, Nils Holland wrote:
> So I decided to fix this with the following follow-up patch. I hope
> this is the right approach (vs. reverting the commit and instead using
> a fixed v2 of the original patch).
>
> From 41775d2c8a14873f522667a57b66cfbe119e28a4 Mon Sep 17 00:00:00 2001
>
On 23 January 2017 at 16:14, Nicolai Hähnle wrote:
> I don't think is correct. The incoming handle is in shared_handle, not in
> handle. Once the code block around line 310 has executed, shared_handle is
> the handle produced by drmPrimeFDToHandle, and closing it on error (as the
> code currently
On Tue, Jan 24, 2017 at 10:35:16AM +0900, Michel Dänzer wrote:
> On 24/01/17 09:55 AM, Nils Holland wrote:
> > So I decided to fix this with the following follow-up patch. I hope
> > this is the right approach (vs. reverting the commit and instead using
> > a fixed v2 of the original patch).
> >
>
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