[PATCH 6/6] drm/amdgpu: enable foreign DMA-buf objects v2

From: Christian König We should be able to handle BOs from other instances as well. v2: * Add a module option that is off-by-default * Use new DRM helper function to check the exporting driver Signed-off-by: Christian König Signed-off-by:

[PATCH 1/6] drm: Add helper to check exporting driver of a DMA-buf

This allows drivers to check if a DMA-buf contains a GEM object and whether it comes from the same driver. It may be from the same or a different device. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/drm_prime.c | 24 include/drm/drmP.h

Re: [PATCH 1/6] drm: Add helper to check exporting driver of a DMA-buf

Am 06.07.2017 um 22:16 schrieb Felix Kuehling: This allows drivers to check if a DMA-buf contains a GEM object and whether it comes from the same driver. It may be from the same or a different device. Signed-off-by: Felix Kuehling I think Daniel/Dave hadmore a

[PATCH 0/6] Experimental P2P buffer sharing

This patch series adds experimental P2P buffer sharing. It's disabled by default and can be enabled with amdgpu.p2p_sharing=1. TODO: * Add a whitelist of chipsets that support P2P access * Refine UVD/VCE handling on newer IP versions with GPUVM support * Handle foreign BOs in DC path * Test for

Re: [PATCH 00/12] Patches from amd-kfd-staging

I split the P2P patches into a separate series for review. Patches 1-6 from this series should still be valid. I still need Reviewed-by's for patches 1 and 4. Patches 2 and 5 are by other authors and reviewed by me. But I'd feel better to get at least an Acked-by from some amdgpu folks. Thanks,

Re: [PATCH 03/12] drm/amdgpu: Enable SDMA context switching for CIK

On Mon, Jul 3, 2017 at 5:11 PM, Felix Kuehling wrote: > Enable SDMA context switching on CIK (copied from sdma_v3_0.c). > > Signed-off-by: Felix Kuehling Reviewed-by: Alex Deucher > --- >

Re: [PATCH 04/12] drm/amdgpu: Make SDMA phase quantum configurable

On Mon, Jul 3, 2017 at 5:11 PM, Felix Kuehling wrote: > Set a configurable SDMA phase quantum when enabling SDMA context > switching. The default value significantly reduces SDMA latency > in page table updates when user-mode SDMA queues have concurrent > activity,

Re: [PATCH 09/12] drm/amdgpu: disallow foreign BOs in the display path

On Mon, Jul 3, 2017 at 5:11 PM, Felix Kuehling wrote: > From: Christian König > > Pinning them in other devices VRAM would obviously not work. > > Signed-off-by: Christian König > Reviewed-by: Felix Kuehling

Re: [PATCH libdrm] libdrm_amdgpu: add kernel semaphore support

Chrstian, you are probably the best person to ack this, I'd like to get the radv code landed and allow the GL code to get going. Dave. > This adds kernel semaphore support to the command submission > interface in what should be a backwards compatible manner, > it adds a new command submission

Re: [PATCH 02/12] drm/amdgpu: Enable SDMA_CNTL.ATC_L1_ENABLE for SDMA on CZ

On Mon, Jul 3, 2017 at 5:11 PM, Felix Kuehling wrote: > From: shaoyunl > > For GFX context, the ATC bit in SDMA*_GFX_VIRTUAL_ADDRESS can be cleared > to perform in VM mode. For RLC context, to support ATC mode , ATC bit in >

Re: [PATCH 06/12] drm/amdgpu: Correctly establish the suspend/resume hook for amdkfd

On Thu, Jul 6, 2017 at 5:33 PM, Yong Zhao wrote: > Hi Alex, > > As far as I know, we never tested suspend/resume on the setting you > mentioned. Theoretically it should work. Are the kfd s/r entry points global or per GPU? If you have two GPUs and you suspend one, will it

[PATCH 2/6] drm/amdgpu: disallow foreign BOs for UVD/VCE

From: Christian König They don't support VM mode yet. Signed-off-by: Christian König Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

[PATCH 4/6] drm/amdgpu: separate BO from GEM object

From: Christian König This allows us to have multiple GEM objects for one BO. Signed-off-by: Christian König Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 12 +++--

[PATCH 5/6] drm/amdgpu: handle foreign BOs in the VM mapping

From: Amber Lin Set the system bit for foreign BO mappings and use the remote VRAM BAR address as the VRAM base offset. Signed-off-by: Amber Lin Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17

[PATCH 3/6] drm/amdgpu: disallow foreign BOs in the display path

From: Christian König Pinning them in other devices VRAM would obviously not work. Signed-off-by: Christian König Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 ++ 1 file

Re: [PATCH 06/12] drm/amdgpu: Correctly establish the suspend/resume hook for amdkfd

On Mon, Jul 3, 2017 at 5:11 PM, Felix Kuehling wrote: > From: Yong Zhao > > Signed-off-by: Yong Zhao > Reviewed-by: Felix Kuehling Does this work properly for multiple GPUs? E.g., if one is suspended and

Re: [PATCH 09/12] drm/amdgpu: disallow foreign BOs in the display path

On 17-07-06 05:13 PM, Alex Deucher wrote: > On Mon, Jul 3, 2017 at 5:11 PM, Felix Kuehling wrote: >> From: Christian König >> >> Pinning them in other devices VRAM would obviously not work. >> >> Signed-off-by: Christian König

Re: [PATCH 06/12] drm/amdgpu: Correctly establish the suspend/resume hook for amdkfd

On 2017-07-06 05:44 PM, Alex Deucher wrote: On Thu, Jul 6, 2017 at 5:33 PM, Yong Zhao wrote: Hi Alex, As far as I know, we never tested suspend/resume on the setting you mentioned. Theoretically it should work. Are the kfd s/r entry points global or per GPU? If you have

Re: [PATCH 1/3] drm/amdgpu/atom: fix atom_fw check

Am 05.07.2017 um 21:51 schrieb Alex Deucher: Not all vbios images seem to set the version appropriately. Switch the check based on asic type instead. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 15 +-- 1 file changed, 1

Re: [PATCH 4/5] drm/amdgpu: check scratch registers to see if we need post

On 07/01/2017 05:32 AM, Alex Deucher wrote: Rather than checking the CONGIG_MEMSIZE register as that may not be reliable on some APUs. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +- 1 file changed, 1 insertion(+), 9

Re: [PATCH] drm/amd/powerplay: fixed wrong data type declaration for ppfeaturemask

Reviewed-by: Christian König . Am 06.07.2017 um 04:38 schrieb Zhu, Rex: Reviewed-by: Rex Zhu Best Regards Rex -Original Message- From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Evan Quan Sent: Thursday, July 06,

Re: [PATCH libdrm 2/2] radeon: use asic id table to get chipset name

On 5 July 2017 at 22:31, Li, Samuel wrote: >> - above all, as-is make check will fail > Right, I did not check that. > >> - keeping the radeon API symmetrical to the amdgpu one would a good idea > The issue is Radeon does not have a struct similar to amdgpu_device_handle.

Re: [PATCH v3 2/5] drm/amdgpu: Throttle visible VRAM moves separately

Am 06.07.2017 um 12:51 schrieb Michel Dänzer: From: John Brooks The BO move throttling code is designed to allow VRAM to fill quickly if it is relatively empty. However, this does not take into account situations where the visible VRAM is smaller than total VRAM, and total

[PATCH 4/5] drm/amdgpu: Don't force BOs into visible VRAM for page faults

From: John Brooks There is no need for page faults to force BOs into visible VRAM if it's full, and the time it takes to do so is great enough to cause noticeable stuttering. Add GTT as a possible placement so that if visible VRAM is full, page faults move BOs to GTT instead

[PATCH 0/5] amdgpu: Visible VRAM Management Improvements, next take

From: Michel Dänzer This is a rearrangement of some patches of John's, with some improvements of mine, and a patch of mine, rebased on current amd-staging-4.11. Details about changes in the individual patches. John Brooks (4): drm/amdgpu: Add vis_vramlimit module

[PATCH v3 3/5] drm/amdgpu: Set/clear CPU_ACCESS flag on page fault and move to VRAM

From: John Brooks When a BO is moved to VRAM, clear AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED. This allows it to potentially later move to invisible VRAM if the CPU does not access it again. Setting the CPU_ACCESS flag in amdgpu_bo_fault_reserve_notify() also means that we can

[PATCH v2 1/5] drm/amdgpu: Add vis_vramlimit module parameter

From: John Brooks Allow specifying a limit on visible VRAM via a module parameter. This is helpful for testing performance under visible VRAM pressure. v2: Add cast to 64-bit (Christian König) Signed-off-by: John Brooks Reviewed-by: Michel Dänzer

[PATCH v2 5/5] drm/amdgpu: Try evicting from CPU visible to invisible VRAM first

From: Michel Dänzer This gives BOs which haven't been accessed by the CPU since they were moved to visible VRAM another chance to stay in VRAM when another BO needs to go to visible VRAM. This should allow BOs to stay in VRAM longer in some cases. v2: * Only do this for

Re: [PATCH v3 3/5] drm/amdgpu: Set/clear CPU_ACCESS flag on page fault and move to VRAM

Am 06.07.2017 um 12:51 schrieb Michel Dänzer: From: John Brooks When a BO is moved to VRAM, clear AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED. This allows it to potentially later move to invisible VRAM if the CPU does not access it again. Setting the CPU_ACCESS flag in

Re: [PATCH 4/5] drm/amdgpu: Don't force BOs into visible VRAM for page faults

Am 06.07.2017 um 12:51 schrieb Michel Dänzer: From: John Brooks There is no need for page faults to force BOs into visible VRAM if it's full, and the time it takes to do so is great enough to cause noticeable stuttering. Add GTT as a possible placement so that if visible

RE: [PATCH 4/5] drm/amdgpu: check scratch registers to see if we need post

> -Original Message- > From: Zhang, Jerry > Sent: Thursday, July 06, 2017 2:08 AM > To: Alex Deucher; amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander > Subject: Re: [PATCH 4/5] drm/amdgpu: check scratch registers to see if we > need post > > On 07/01/2017 05:32 AM, Alex Deucher

RE: [PATCH libdrm 2/2] radeon: use asic id table to get chipset name

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Emil Velikov > Sent: Thursday, July 06, 2017 5:21 AM > To: Li, Samuel > Cc: ML dri-devel; amd-gfx mailing list > Subject: Re: [PATCH libdrm 2/2] radeon: use asic id table to get chipset name

[PATCH umr] Add ability to import new asic from script file (v2)

This is meant for NPI support only as publicly released designs can simply add to the static definitions. This is used by using the --force (-f) option with a filename that has a @ prefixed on, e.g. umr -O bits -f @demo/npi/newchip -lr gfx10 Will read the file 'newchip' and import the

[PATCH umr] Add ability to import new asic from script file

This is meant for NPI support only as publicly released designs can simply add to the static definitions. This is used by using the --force (-f) option with a filename that has a @ prefixed on, e.g. umr -O bits -f @demo/npi/newchip -lr gfx10 Will read the file 'newchip' and import the

[PATCH v4 04/14] drm: amd: remove dead code and pointless local lut storage

The redundant fb helpers .load_lut, .gamma_set and .gamma_get are no longer used. Remove the dead code and hook up the crtc .gamma_set to use the crtc gamma_store directly instead of duplicating that info locally. Signed-off-by: Peter Rosin ---

[PATCH v4 12/14] drm: radeon: remove dead code and pointless local lut storage

The redundant fb helpers .load_lut, .gamma_set and .gamma_get are no longer used. Remove the dead code and hook up the crtc .gamma_set to use the crtc gamma_store directly instead of duplicating that info locally. Signed-off-by: Peter Rosin ---

[PATCH v4 00/14] improve the fb_setcmap helper

Hi! While trying to get CLUT support for the atmel_hlcdc driver, and specifically for the emulated fbdev interface, I received some push-back that my feeble in-driver attempts should be solved by the core. This is my attempt to do it right. I have obviously not tested all of this with more than

[PATCH][drm-next] drm/amdgpu: make arrays pctl0_data and pctl1_data static

From: Colin Ian King The arrays pctl0_data and pctl1_data do not need to be in global scope, so them both static. Cleans up sparse warnings: symbol 'pctl0_data' was not declared. Should it be static? symbol 'pctl1_data' was not declared. Should it be static?

Re: [PATCH][drm-next] drm/amdgpu: make arrays pctl0_data and pctl1_data static

On Thu, Jul 6, 2017 at 5:58 AM, Colin King wrote: > From: Colin Ian King > > The arrays pctl0_data and pctl1_data do not need to be in global scope, > so them both static. > > Cleans up sparse warnings: > symbol 'pctl0_data' was not declared.

Re: [PATCH v2 5/5] drm/amdgpu: Try evicting from CPU visible to invisible VRAM first

Am 06.07.2017 um 12:51 schrieb Michel Dänzer: From: Michel Dänzer This gives BOs which haven't been accessed by the CPU since they were moved to visible VRAM another chance to stay in VRAM when another BO needs to go to visible VRAM. This should allow BOs to stay in

Re: [PATCH 01/11] drm/amdgpu: reserve the first 2x512 of GART

On Mon, Jul 3, 2017 at 5:44 AM, Christian König wrote: > From: Christian König > > We want to use them as remap address space. > > Signed-off-by: Christian König 2x512 pages. With that updated: Reviewed-by: Alex

Re: [PATCH 02/11] drm/amdgpu: add amdgpu_gart_map function v2

On Mon, Jul 3, 2017 at 5:44 AM, Christian König wrote: > From: Christian König > > This allows us to write the mapped PTEs into > an IB instead of the table directly. > > v2: fix build with debugfs enabled, remove unused assignment > >

Re: [PATCH 03/11] drm/amdgpu: use the GTT windows for BO moves v2

On Mon, Jul 3, 2017 at 5:44 AM, Christian König wrote: > From: Christian König > > This way we don't need to map the full BO at a time any more. > > v2: use fixed windows for src/dst > > Signed-off-by: Christian König

Re: [PATCH 04/11] drm/amdgpu: stop mapping BOs to GTT

On Mon, Jul 3, 2017 at 5:44 AM, Christian König wrote: > From: Christian König > > No need to map BOs to GTT on eviction and intermediate transfers any more. > > Signed-off-by: Christian König Reviewed-by: Alex

Re: [PATCH 05/11] drm/amdgpu: remove maximum BO size limitation v2

On Mon, Jul 3, 2017 at 5:44 AM, Christian König wrote: > From: Christian König > > We can finally remove this now. > > v2: remove now unused max_size variable as well. > > Signed-off-by: Christian König Reviewed-by:

Re: [PATCH 06/11] drm/amdgpu: use TTM values instead of MC values for the info queries

On Mon, Jul 3, 2017 at 5:44 AM, Christian König wrote: > From: Christian König > > Use the TTM values instead of the hardware config here. > > Signed-off-by: Christian König Reviewed-by: Alex Deucher

Re: [PATCH 08/11] drm/amdgpu: move SYSVM struct and function into amdgpu_sysvm.h

On Mon, Jul 3, 2017 at 5:44 AM, Christian König wrote: > From: Christian König > > No functional change. > > Signed-off-by: Christian König I agree with what the patch does, but I'd prefer gart to sysvm for the

Re: [PATCH 10/11] drm/amdgpu: setup GTT size directly from module parameter

On Mon, Jul 3, 2017 at 5:44 AM, Christian König wrote: > From: Christian König > > Instead of relying on the sysvm_size to be the same as the module parameter. > > Signed-off-by: Christian König Reviewed-by: Alex

Re: [PATCH 09/11] drm/amdgpu: move amdgpu_sysvm_location into amdgpu_sysvm.c as well

On Mon, Jul 3, 2017 at 5:44 AM, Christian König wrote: > From: Christian König > > No intended functional change. > > Signed-off-by: Christian König I think I'd prefer to keep this together with the vram_location

Re: [PATCH 11/11] drm/amdgpu: add sysvm_size

On Mon, Jul 3, 2017 at 5:44 AM, Christian König wrote: > From: Christian König > > Limit the size of the SYSVM. This saves us a bunch of visible VRAM, > but also limitates the maximum BO size we can swap out. Update the description. The

[PATCH 2/2] drm/amdgpu/soc15: init nbio registers for vega10

Call nbio init registers on hw_init to set up any nbio registers that need initialization at hw init time. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c

[PATCH 1/2] drm/amdgpu: add nbio 6.1 register init function

Used for nbio registers that need to be initialized. Currently only used for a golden setting that got missed on some boards. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 13 + drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h | 1 + 2

[PATCH 4/6] drm/amd/powerplay: added support for new se_cac_idx APIs to cgs

Change-Id: If2ac93808d1922fe3dbec64a58f674a9c342088d Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 4 drivers/gpu/drm/amd/include/cgs_common.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

[PATCH 1/6] drm/amd/powerplay: added index gc cac read/write apis for vega10

Change-Id: I1a62db8c764d368e6ba08440ad1761adb55d85fd Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/soc15.c | 24 1 file changed, 24 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index

[PATCH] drm/radeon: Fix eDP for single-display iMac10,1 (v2)

The late 2009, 27 inch Apple iMac10,1 has an internal eDP display and an external Mini- Displayport output, driven by a DCE-3.2, RV730 Radeon Mobility HD-4670. The machine worked fine in a dual-display setup with eDP panel + externally connected HDMI or DVI-D digital display sink, connected via

RE: [PATCH 6/6] drm/amd/powerplay: added didt support for vega10

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Evan Quan > Sent: Thursday, July 06, 2017 9:59 PM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander; Quan, Evan > Subject: [PATCH 6/6] drm/amd/powerplay: added didt support for

Re: [PATCH 06/12] drm/amdgpu: Correctly establish the suspend/resume hook for amdkfd

Hi Alex, As far as I know, we never tested suspend/resume on the setting you mentioned. Theoretically it should work. When I read the code now, I was wondering whether we should stop kfd before amdgpu_bo_evict_vram() and amdgpu_fence_driver_suspend(). If that's not needed, it may make more

[PATCH 5/6] drm/amd/powerplay: added grbm_idx_mutex lock/unlock to cgs v2 - v2: rename param 'en' as 'lock'

Change-Id: If7088d6046c84355b8f1308d584ab6524ceab724 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 12 drivers/gpu/drm/amd/include/cgs_common.h | 5 + 2 files changed, 17 insertions(+) diff --git

Re: [PATCH 0/5] amdgpu: Visible VRAM Management Improvements, next take

On Thu, Jul 06, 2017 at 07:51:25PM +0900, Michel Dänzer wrote: > From: Michel Dänzer > > This is a rearrangement of some patches of John's, with some improvements > of mine, and a patch of mine, rebased on current amd-staging-4.11. > Details about changes in the

[PATCH 2/6] drm/amd/powerplay: added new se_cac_idx r/w APIs v2 - v2: added missing spinlock init

Change-Id: I9f16ec9f5bab9abe83e9df01609893b38bb691fe Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 6 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h

[PATCH 3/6] drm/amd/powerplay: added soc15 support for new se_cac_idx APIs

Change-Id: I9b925397d7ac61bcf9f0e8850f2d8b3dabd4a105 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/soc15.c | 24 1 file changed, 24 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index

Re: [PATCH] drm/amdgpu: check scratch registers to see if we need post (v2)

Thanks for update. That's fine for me. Feel free to add my RB. Reviewed-by: Junwei Zhang On 07/04/2017 04:20 AM, Alex Deucher wrote: Rather than checking the CONGIG_MEMSIZE register as that may not be reliable on some APUs. v2: The scratch register is only used on CIK+