Re: [PATCH 12/13] drm/amd/powerplay: correct vega12 thermal support as true

On Tue, Jun 19, 2018 at 3:39 AM, Evan Quan wrote: > Thermal support is enabled on vega12. > > Change-Id: I7069a65c6b289dbfe4a12f81ff96e943e878e6fa > Signed-off-by: Evan Quan Acked-by: Alex Deucher > --- > drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 1 + > 1 file changed, 1

Re: [PATCH 2/5] dma-buf: remove kmap_atomic interface

On Tue, Jun 19, 2018 at 4:47 PM, Christian König wrote: > Am 18.06.2018 um 10:18 schrieb Daniel Vetter: >> >> On Fri, Jun 01, 2018 at 02:00:17PM +0200, Christian König wrote: >>> >>> Neither used nor correctly implemented anywhere. Just completely remove >>> the interface. >>> >>> Signed-off-by:

Re: [PATCH 10/13] drm/amd/powerplay: apply clocks adjust rules on power state change

Hi Evan, did we need to check the following flags on vega12?will driver set those flags when user select the umd_pstate? PHM_PlatformCaps_UMDPState/PHM_PlatformCaps_PState. Best Regards Rex ?? Outlook for Android From: amd-gfx on

Re: [PATCH 10/13] drm/amd/powerplay: apply clocks adjust rules on power state change

On Tue, Jun 19, 2018 at 3:39 AM, Evan Quan wrote: > The clocks hard/soft min/max clock levels will be adjusted > correspondingly. Also note that this add the apply_clocks_adjust_rules callback which is used to validate the clock settings on a power state change. One other comment below. > >

Re: [PATCH 13/13] drm/amd/powerplay: cosmetic fix

On Tue, Jun 19, 2018 at 3:39 AM, Evan Quan wrote: > Fix coding style and drop unused variable. > > Change-Id: I9630f39154ec6bc30115e75924b35bcbe028a1a4 > Signed-off-by: Evan Quan Acked-by: Alex Deucher > --- > drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 10 +++--- >

[PATCH 1/2] drm/amdgpu: Polish SQ IH.

Switch to using reg fields defines istead of magic values. Add SH_ID and PRIV fields reading for instr. and err cases. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 36 +++ 1 file changed, 20 insertions(+), 16 deletions(-) diff

[PATCH 2/2] drm/amdgpu: Add parsing SQ_EDC_INFO to SQ IH.

Access to SQ_EDC_INFO requires selecting register instance and hence mutex lock when accessing GRBM_GFX_INDEX for which a work is schedueled from IH. But SQ interrupt can be raised on many instances at once which means queuing work will usually succeed for the first one but fail for the reset

Re: [PATCH 11/13] drm/amd/powerplay: set vega12 pre display configurations

On Tue, Jun 19, 2018 at 3:39 AM, Evan Quan wrote: > PPSMC_MSG_NumOfDisplays is set as 0 and uclk is forced as > highest. Adjust the commit message to make it clear that you set num_displays to 0 and force uclk high as part of the mode set dequence. With that fixed: Acked-by: Alex Deucher > >

Re: [PATCH] drm/amdgpu: Use correct enum to set powergating state

On Tue, Jun 19, 2018 at 5:16 AM, Stefan Agner wrote: > Use enum amd_powergating_state instead of enum amd_clockgating_state. > The underlying value stays the same, so there is no functional change > in practise. This fixes a warning seen with clang: >

Re: [PATCH] drm/amdgpu:All UVD instances share one idle_work handle

On 18.06.2018 20:00, James Zhu wrote: > All UVD instanses have only one dpm control, so it is better > to share one idle_work handle. Compiles fine with clang here. Tested-by: Stefan Agner > > Signed-off-by: James Zhu > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 14 +++--- >

[PATCH 14/51] drm/amd/display: get rid of cur_clks from dcn_bw_output

From: Dmytro Laktyushkin Cleans up dcn_bw_output to only contain calculated info, actual programmed values will now be stored in respective blocks. Change-Id: I8d5139ba4bea9e6738bd6d8bd8e45ec82477c276 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Nikola Cornij Acked-by: Harry Wentland ---

[PATCH 01/51] drm/amd/display: replace clocks_value struct with dc_clocks

From: Dmytro Laktyushkin This will avoid structs with duplicate information. Also removes pixel clock voltage request. This has no effect since pixel clock does not affect dcn voltage and this function only matters for dcn. Change-Id: I62e8906e8f250602ccc8e8a61e9585df13a00a0f Signed-off-by:

[PATCH 13/51] drm/amd/display: Add clock types to applying clk for voltage

From: Mikita Lipski Add DCF and FCLK clock case statements for changing raven's clocks for voltage request. Also maintain DCEF clock for DCE120 calls. Change-Id: I33018a752485b107c4127d4655d5e976855b6917 Signed-off-by: Mikita Lipski Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 07/51] drm/amd/display: Adding Get static clocks for dm_pp interface

From: Mikita Lipski Adding a call to powerplay to get system clocks and translate to dm structure Change-Id: Ic6892857a16cce24d9ac9485b5507d97a67fca37 Signed-off-by: Mikita Lipski Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- .../amd/display/amdgpu_dm/amdgpu_dm_services.c | 18

[PATCH 11/51] drm/amd/display: Use tg count for opp init.

From: Yongqiang Sun In case of tg count not equal to FE pipe count, if use pipe count to iterate the tgs, it will cause BSOD. Change-Id: I83a3e1b5a1fdbf004fa43cdc6943f69e436ac49d Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 12/51] drm/amd/display: Use local structs instead of struct pointers

From: Mikita Lipski Change struct pointers to creating structs on a stack. Thats fixing a mistake in a previous patch introducing dm_pplib functions Change-Id: Ibd7960f5ccfcc8a9377ad8dbc8bd2f81e75d30d7 Signed-off-by: Mikita Lipski Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 15/51] drm/amd/display: move dcn1 dispclk programming to dccg

From: Dmytro Laktyushkin No functional change. Change-Id: Ia774240b5a2410df6bee9c6c912b5b1315d8989f Signed-off-by: Dmytro Laktyushkin Reviewed-by: Nikola Cornij Acked-by: Harry Wentland --- .../gpu/drm/amd/display/dc/dce/dce_clocks.c | 95 ++--

[PATCH 08/51] drm/amd/display: dal 3.1.48

From: Tony Cheng Change-Id: I74a0ddcba313f0e51d38c6cad058063b9586d936 Signed-off-by: Tony Cheng Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h

[PATCH 09/51] drm/amd/display: Introduce pp-smu raven functions

From: Mikita Lipski DM powerplay calls for DCN10 allowing to bypass PPLib and call directly to the SMU functions. Change-Id: I55952aca19299c7c61747ec15695c026f29dbbc8 Signed-off-by: Mikita Lipski Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- .../display/amdgpu_dm/amdgpu_dm_services.c

[PATCH 23/51] drm/amd/display: fix pplib voltage request

From: Dmytro Laktyushkin This fixes incorrect clock caching and by extension fixes the clock reporting. Change-Id: I47ec8d78da4f7938ed79c86a9ab475a8e1e47819 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Eric Yang Acked-by: Harry Wentland --- .../gpu/drm/amd/display/dc/dce/dce_clocks.c |

[PATCH 19/51] drm/amd/display: remove unnecessary pplib volage requests that are asserting

From: Dmytro Laktyushkin Change-Id: Ifb3b0175987d6e5d2d203896818b82742f125fe4 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 8 1 file changed, 8 deletions(-) diff --git

[PATCH 03/51] drm/amd/display: rename display clock block to dccg

From: Dmytro Laktyushkin Change-Id: I73b4dd52de0b5988fcb9013f01c65512070cc26f Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- .../gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- .../gpu/drm/amd/display/dc/dce/dce_clocks.c | 78 +--

[PATCH 10/51] drm/amd/display: remove invalid assert when no max_pixel_clk is found

From: Dmytro Laktyushkin Change-Id: If7c3c7a1dc754eef3fa60cc9d4f56a4779a10ece Signed-off-by: Dmytro Laktyushkin Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 --- 1 file changed, 3 deletions(-) diff --git

[PATCH 27/51] drm/amd/display: support ACrYCb2101010

From: "Zheng, XueLai(Eric)" Change-Id: I291b94fa4db12f42ae38bb9b9e3a78c24a63c423 Signed-off-by: XueLai(Eric), Zheng Reviewed-by: Charlene Liu Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 1 + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 2 +- 2

[PATCH 43/51] drm/amd/display: separate out wm change request dcn workaround

From: Dmytro Laktyushkin Change-Id: I4546eaa268498b5ca0a4b5f18c5f4c4446be8d76 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c | 11 ++- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h |

[PATCH 32/51] drm/amd/display: clean rq/dlg/ttu reg structs before calculations

From: Dmytro Laktyushkin Change-Id: I7b6c3f223cbb383c9c041a18a7f7b00e0a5be89b Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 4 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c |

[PATCH 31/51] drm/amd/display: dal 3.1.50

From: Tony Cheng Change-Id: I5a44c0d4289122f7738efa674dc079cfedb258b9 Signed-off-by: Tony Cheng Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h

[PATCH 36/51] drm/amd/display: Add dmpp clks types for conversion

From: Mikita Lipski Add more cases for dm_pp clks translator into pp clks so we can pass the right structures to the powerplay. Use clks translator instead of massive switch statement. Change-Id: Ic757734d9e708f81bd72cfe00c55a627a51f8d7a Signed-off-by: Mikita Lipski Reviewed-by: Tony Cheng

[PATCH 30/51] drm/amd/display: Add front end for dp debugfs files

From: David Francis As part of hardware certification, read-write access to the link rate, lane count, voltage swing, pre-emphasis, and PHY test pattern of DP connectors is required. This commit adds debugfs files that will correspond to these values. The file operations are not yet

[PATCH 37/51] drm/amd/display: Convert 10kHz clks from PPLib into kHz

From: Mikita Lipski The driver is expecting clock frequency in kHz, while SMU returns the values in 10kHz, which causes the bandwidth validation to fail Change-Id: I7b79af18d200fd2157193ee9041c675fe66c391c Signed-off-by: Mikita Lipski Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 48/51] drm/amd/display: add valid regoffset and NULL pointer check

From: Charlene Liu Change-Id: I31c377a4ab1c428d260cf311b7e28c6137159cf7 Signed-off-by: Charlene Liu Reviewed-by: Dmytro Laktyushkin Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 +++--- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 9 ---

[PATCH 41/51] drm/amd/display: fix dcn1 watermark range reporting

From: Dmytro Laktyushkin Change-Id: I984632d3eda21200e3911be5ec197801c3b855fb Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 102 -- 1 file changed, 18 insertions(+), 84 deletions(-) diff

[PATCH 28/51] drm/amd/display: fix use of uninitialized memory

From: Wesley Chalmers DML does not calculate chroma values for RQ when surface is not YUV, but DC will unconditionally use the uninitialized values for HW programming. This does not cause visual corruption since HW will ignore garbage chroma values when surface is not YUV, but causes

[PATCH 51/51] drm/amd/display: Program vsc_infopacket in commit_planes_for_stream

From: Alvin lee Change-Id: I0867e7e8d85a64cf35d9de2c319699ae027091d2 Signed-off-by: Alvin lee Reviewed-by: Jun Lei Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++- drivers/gpu/drm/amd/display/dc/dc_stream.h | 1 + 2 files changed, 3 insertions(+), 1

[PATCH 50/51] drm/amd/display: Allow option to use worst-case watermark

From: Tony Cheng use worse case watermark (consider both DCC and VM) to keep golden consistent regardless of DCC Change-Id: Ibc7ef72099dcd0a514a600ceae2e3ddc19f47a48 Signed-off-by: Tony Cheng Reviewed-by: Aric Cyr Acked-by: Harry Wentland --- .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c |

[PATCH 38/51] drm/amd/display: move dml defaults to respective dcn resource files

From: Dmytro Laktyushkin Change-Id: I77cb3bca09bd2939e66c538bf1c317d0639711c0 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- .../drm/amd/display/dc/dcn10/dcn10_resource.c | 62 ++ .../drm/amd/display/dc/dml/display_mode_lib.c | 63

[PATCH 49/51] drm/amd/display: get board layout for edid emulation

From: Samson Tam Change-Id: I74999e1a164c027d74fafb8be32321377fcadb9e Signed-off-by: Samson Tam Reviewed-by: Aric Cyr Acked-by: Harry Wentland --- .../gpu/drm/amd/display/dc/bios/bios_parser.c | 196 .../drm/amd/display/dc/bios/bios_parser2.c| 218 +-

[PATCH 47/51] drm/amd/display: dal 3.1.52

From: Tony Cheng Change-Id: I247a15ddaa6ed8b94f8ebe23bdebd5a475549f4f Signed-off-by: Tony Cheng Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h

[PATCH 44/51] drm/amd/display: move dcn watermark programming to set_bandwidth

From: Dmytro Laktyushkin Change-Id: If70a4124cf898c7561b8f3c8aa7960901f8b6dcc Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 107 +++--- .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 +-

[PATCH 21/51] drm/amd/display: Define dp_alt_mode

From: Charlene Liu Also cleanup command_table2.c. No need for a lot of forward declarations. Change-Id: Ia8668e9142556d9f7d865480afc64bc00444a578 Signed-off-by: Charlene Liu Reviewed-by: Krunoslav Kovac Acked-by: Harry Wentland --- .../drm/amd/display/dc/bios/command_table2.c | 46

[PATCH 24/51] drm/amd/display: add CHG_DONE mash/sh defines for dentist

From: Dmytro Laktyushkin Change-Id: Ib6de55162c46b5f3858c528ec80905fdef1371c6 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Charlene Liu Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git

[PATCH 06/51] drm/amd/display: Apply clock for voltage request

From: Mikita Lipski Translate dm_pp tructure to pp type Call PP lib to apply clock voltage request for display Change-Id: I9aa732073fda7b2d7f911849a35572ef5db6ae48 Signed-off-by: Mikita Lipski Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- .../display/amdgpu_dm/amdgpu_dm_services.c

[PATCH 04/51] drm/amd/display: move clock programming from set_bandwidth to dccg

From: Dmytro Laktyushkin This change moves dcn clock programming(with exception of dispclk) into dccg. This should have no functional effect. Change-Id: I5f857f620e6649cdafcf519569e07c36716bf47b Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 18/51] drm/amd/display: clean up set_bandwidth usage

From: Dmytro Laktyushkin This removes redundant set_bandwidth calls as well as fixes a bug in post_set_address_update where dcn1 would never get to lower clocks. Change-Id: I6ad9fe8179b7281b5bd3b58665a1efdf1ec5b8a0 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Nikola Cornij Acked-by: Harry

[PATCH 00/51] DC Patches Jun 19, 2018

Been pretty busy and haven't been able to get these out as regularly as I'd like. We're working on improving our process. I hope to be able to give an update next week. Changes here are: * RV powerplay integration * Retry link-training if it fails initially * Stubbing out a DP debugfs to

[PATCH 05/51] drm/amd/display: Adding dm-pp clocks getting by voltage

From: Mikita Lipski Function to get clock levels by voltage from PPLib Change-Id: I0723e59ac21e69a90497382fce348be95bea4ed9 Signed-off-by: Mikita Lipski Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- .../display/amdgpu_dm/amdgpu_dm_services.c| 43 ++- 1 file

[PATCH 16/51] drm/amd/display: clean up dccg divider calc and dcn constructor

From: Dmytro Laktyushkin No functional change. Change-Id: Ia108aff1f2e1def6d69cbda13d90b9a818fbecc4 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- .../gpu/drm/amd/display/dc/dce/dce_clocks.c | 197 ++

[PATCH 02/51] drm/amd/display: redesign dce/dcn clock voltage update request

From: Dmytro Laktyushkin The goal of this change is to move clock programming and voltage requests to a single function. As of this change only dce is affected. Change-Id: If2fdb76f2760533fbd701db9855a611d9569fd54 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry

[PATCH 20/51] drm/amd/display: Temporarily remove Chroma logs

From: Wesley Chalmers To ensure tests continue to pass Change-Id: I03e78245b679889786730897306a6e572c5e89d0 Signed-off-by: Wesley Chalmers Reviewed-by: Shahin Khayyer Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 8 ++-- 1 file changed, 2

[PATCH 42/51] drm/amd/display: remove dcn1 watermark sets b, c and d

From: Dmytro Laktyushkin Currently dcn1 will not switch between watermark sets so we can save time by not calculating 3 extra sets. Change-Id: If0282c383df30d3698ab90cc41b4a8c52624ceb8 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 40/51] drm/amd/display: Enable Stereo in Dal3

From: Alvin lee - program infoframe for Stereo - program stereo flip control registers properly Change-Id: If547e2677b72709359b3a8602357b80961f1bfce Signed-off-by: Alvin lee Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/Makefile | 3 +-

[PATCH 26/51] drm/amd/display: add safe_to_lower support to dcn wm programming

From: Dmytro Laktyushkin This will prevent watermarks from lowering when unsafe to do so. Change-Id: I848dcf3dfbdab9c64e365857c98a7efdc65410cb Signed-off-by: Dmytro Laktyushkin Reviewed-by: Charlene Liu Acked-by: Harry Wentland --- .../drm/amd/display/dc/dcn10/dcn10_hubbub.c | 346

[PATCH 22/51] drm/amd/display: fix dccg dcn1 ifdef

From: Dmytro Laktyushkin Change-Id: I49bedf2d8bad4d8405375007270e3702bdd6523c Signed-off-by: Dmytro Laktyushkin Reviewed-by: Eric Yang Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 10 ++ drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 2 ++ 2

[PATCH 29/51] drm/amd/display: dal 3.1.49

From: Tony Cheng Change-Id: I411ec7317d612caff8ffb7c830a9857d0e81d586 Signed-off-by: Tony Cheng Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h

[PATCH 34/51] drm/amd/display: fix potential infinite loop in fbc path

From: Roman Li - Fixing integer overflow bug in wait_for_fbc_state_changed() - Correct the max value of retries for the corresponding warning Change-Id: I67e3e5dd7762d3a2d73711840fc1754f8e8a4dfb Signed-off-by: Roman Li Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 35/51] drm/amd/display: Enable PPLib calls from DC on linux

From: Mikita Lipski Set the powerplay debug flag to false for both Windows and Linux to allow the calls to pplib. So we can retrieve the clock values from powerplay instead of using default hardcoded values. Change-Id: I529f6fab41a88d88a5447d24e857656049e061ec Signed-off-by: Mikita Lipski

[PATCH 3/5] drm/amd/pp: Memory Latency is always 25us on Vega10

From: Rex Zhu Also use the tolerable latency defined in Display to find lowest MCLK frequency when disable mclk switch Signed-off-by: Rex Zhu Acked-by: Alex Deucher --- .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 24 ++- 1 file changed, 2 insertions(+), 22 deletions(-)

[PATCH 1/5] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency

From: Rex Zhu Display component can get tru max_displ_clk_in_khz instand of hardcode Signed-off-by: Rex Zhu Acked-by: Alex Deucher --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 16 +--- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git

[PATCH 4/5] drm/amd/display: Delete old implementation of bw_calcs_data_update_from_pplib

From: Rex Zhu this function is copied from dce112. it is not for AI/RV. driver need to re-implement this function. Signed-off-by: Rex Zhu --- .../amd/display/dc/dce120/dce120_resource.c | 123 +- 1 file changed, 1 insertion(+), 122 deletions(-) diff --git

[PATCH 5/5] drm/amd/display: Refine the interface dm_pp_notify_wm_clock_changes

From: Rex Zhu change function parameter type from dm_pp_wm_sets_with_clock_ranges * to void *. so this interface can be supported on AI/RV. Signed-off-by: Rex Zhu Acked-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 2 +-

[PATCH 0/5] Rex's pplib/dc changes rebased on latest DC

Sending Rex's pplib changes rebased on the latest DC as that had some work Mikita did in the same area. Patch 1 is Reviewed-by: Harry Wentland Patches 2-3 are Acked-by: Harry Wentland Not sure yet about 4-5. Will need to get someone with more expertise to eyeball those. Harry Rex Zhu (5):

[PATCH 2/5] drm/amd/pp: Fix wrong clock-unit exported to Display

From: Rex Zhu Transfer 10KHz (requested by smu) to KHz needed by Display component. This can fix the issue 4k Monitor can't be lit up on Vega/Raven. Signed-off-by: Rex Zhu Acked-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 4 ++--

Re: [PATCH 05/13] drm/amd/powerplay: retrieve all clock ranges on startup

On Tue, Jun 19, 2018 at 3:38 AM, Evan Quan wrote: > So that we do not need to use PPSMC_MSG_GetMin/MaxDpmFreq to > get the clock ranges on runtime. Since that causes some problems. > > Change-Id: Ia0d6390c976749538b35c8ffde5d1e661b4944c0 > Signed-off-by: Evan Quan > --- >

Re: [PATCH 08/13] drm/amd/powerplay: correct smc display config setting

On Tue, Jun 19, 2018 at 3:39 AM, Evan Quan wrote: > Multi monitor situation should be taked into consideration. > Also, there is no need to setup UCLK hard min clock level. This looks like it should be two patches since there are two distinct changes. Also please extend the commit messages a

Re: [PATCH 09/13] drm/amd/powerplay: correct vega12 max num of dpm level

On Tue, Jun 19, 2018 at 3:39 AM, Evan Quan wrote: > Use MAX_NUM_CLOCKS instead of VG12_PSUEDO* macros for > the max number of dpm levels. > > Change-Id: Ida49f51777663a8d68d05ddcd41f4df0d8e61481 > Signed-off-by: Evan Quan Acked-by: Alex Deucher > --- >

Re: [PATCH 04/13] drm/amd/powerplay: revise default dpm tables setup

On Tue, Jun 19, 2018 at 3:38 AM, Evan Quan wrote: > Initialize the soft/hard min/max level correctly and > handle the dpm disabled situation. > > Change-Id: I9a1d303ee54ac4c9687f72c86097b008ae398c05 > Signed-off-by: Evan Quan Acked-by: Alex Deucher > --- >

Re: [PATCH 07/13] drm/amd/powerplay: initialize uvd/vce powergate status

On Tue, Jun 19, 2018 at 3:38 AM, Evan Quan wrote: > On UVD/VCE dpm disabled, the powergate status should be > set as true. Can you explain this patch a bit? Why is power gate state set to true when dpm is disabled? Alex > > Change-Id: I569a5aa216b5e7d64a2b504f2ff98cc83ca802d5 > Signed-off-by:

[PATCH] drm/amdgpu: band aid validating VM PTs

Always validating the VM PTs takes to much time. Only always validate the per VM BOs for now. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

Re: [PATCH 2/5] dma-buf: remove kmap_atomic interface

Am 18.06.2018 um 10:18 schrieb Daniel Vetter: On Fri, Jun 01, 2018 at 02:00:17PM +0200, Christian König wrote: Neither used nor correctly implemented anywhere. Just completely remove the interface. Signed-off-by: Christian König I wonder whether we can nuke the normal kmap stuff too ...

Re: [PATCH 02/13] drm/amd/powerplay: smc_dpm_info structure change

On Tue, Jun 19, 2018 at 3:38 AM, Evan Quan wrote: > A new member Vr2_I2C_address is added. > > Change-Id: I9821365721c9d73e1d2df2f65dfa97f39f0425c6 > Signed-off-by: Evan Quan Acked-by: Alex Deucher > --- > drivers/gpu/drm/amd/include/atomfirmware.h | 5 - >

Re: [PATCH 03/13] drm/amd/powerplay: drop the acg fix

On Tue, Jun 19, 2018 at 3:38 AM, Evan Quan wrote: > This workaround is not needed any more. > > Change-Id: I81cb20ecd52d242af26ca32860baacdb5ec126c9 > Signed-off-by: Evan Quan Acked-by: Alex Deucher > --- > drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c | 6 -- > 1 file

Re: [PATCH 06/13] drm/amd/powerplay: revise clock level setup

On Tue, Jun 19, 2018 at 3:38 AM, Evan Quan wrote: > Make sure the clock level set only on dpm enabled. Also uvd/vce/soc > clock also changed correspondingly. > > Change-Id: I1db2e2ac355fd5aea1c0a25c2b140d039a590089 > Signed-off-by: Evan Quan Acked-by: Alex Deucher > --- >

[PATCH 1/2] drm/amd/pp: Remove duplicate code in vega12_hwmgr.c

use smu_helper function smu_set_watermarks_for_clocks_ranges in vega12_set_watermarks_for_clocks_ranges. Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 43 +- 1 file changed, 1 insertion(+), 42 deletions(-) diff --git

RE: [PATCH 1/7] drm/amdgpu: Rename set_mmhub_powergating_by_smu to powergate_mmhub

Reviewed-by: Evan Quan > -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Rex Zhu > Sent: Wednesday, June 13, 2018 7:18 PM > To: amd-gfx@lists.freedesktop.org > Cc: Zhu, Rex > Subject: [PATCH 1/7] drm/amdgpu: Rename >

RE: [PATCH 2/7] drm/amd/pp: Rename enable_per_cu_power_gating to powergate_gfx

Reviewed-by: Evan Quan > -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Rex Zhu > Sent: Wednesday, June 13, 2018 7:18 PM > To: amd-gfx@lists.freedesktop.org > Cc: Zhu, Rex > Subject: [PATCH 2/7] drm/amd/pp: Rename

Re: [PATCH 40/51] drm/amd/display: Enable Stereo in Dal3

On Tue, Jun 19, 2018 at 5:10 PM, Harry Wentland wrote: > From: Alvin lee > > - program infoframe for Stereo > - program stereo flip control registers properly > > Change-Id: If547e2677b72709359b3a8602357b80961f1bfce > Signed-off-by: Alvin lee > Reviewed-by: Tony Cheng > Acked-by: Harry

Re: [PATCH 2/5] drm/amd/pp: Fix wrong clock-unit exported to Display

On Tue, Jun 19, 2018 at 5:17 PM, Harry Wentland wrote: > From: Rex Zhu > > Transfer 10KHz (requested by smu) to KHz needed by Display > component. > > This can fix the issue 4k Monitor can't be lit up on Vega/Raven. > > Signed-off-by: Rex Zhu > Acked-by: Alex Deucher Need to make sure we drop

RE: [PATCH v2 6/7] drm/amdgpu: Make gfx_off control by GFX ip

Reviewed-by: Evan Quan > -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Rex Zhu > Sent: Wednesday, June 13, 2018 7:37 PM > To: amd-gfx@lists.freedesktop.org > Cc: Zhu, Rex > Subject: [PATCH v2 6/7] drm/amdgpu: Make gfx_off control by GFX

RE: [PATCH v2 7/7] drm/amdgpu: Change PG enable sequence

Reviewed-by: Evan Quan > -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Rex Zhu > Sent: Wednesday, June 13, 2018 7:39 PM > To: amd-gfx@lists.freedesktop.org > Cc: Zhu, Rex > Subject: [PATCH v2 7/7] drm/amdgpu: Change PG enable sequence >

[PATCH] drm/amd/display: Fix a typo

change wm_min_memg_clk_in_khz -> wm_min_mem_clk_in_khz Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 8 drivers/gpu/drm/amd/display/dc/dm_services_types.h | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git

Re: [PATCH] drm/amdgpu: correct GART location info

We need a commit message, something like "Avoid confusing the GART with the GTT domain.". Am 19.06.2018 um 06:41 schrieb Junwei Zhang: Signed-off-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git

[PATCH 08/13] drm/amd/powerplay: correct smc display config setting

Multi monitor situation should be taked into consideration. Also, there is no need to setup UCLK hard min clock level. Change-Id: Icf1bc9b420a4048d9071e386308d30999491 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 13 ++--- 1 file changed, 2

[PATCH 13/13] drm/amd/powerplay: cosmetic fix

Fix coding style and drop unused variable. Change-Id: I9630f39154ec6bc30115e75924b35bcbe028a1a4 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 10 +++--- .../gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h | 18 +- 2 files changed,

[PATCH 12/13] drm/amd/powerplay: correct vega12 thermal support as true

Thermal support is enabled on vega12. Change-Id: I7069a65c6b289dbfe4a12f81ff96e943e878e6fa Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

[PATCH 11/13] drm/amd/powerplay: set vega12 pre display configurations

PPSMC_MSG_NumOfDisplays is set as 0 and uclk is forced as highest. Change-Id: I2400279d3c979d99f4dd4b8d53f051cd8f8e0c33 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 41 ++ 1 file changed, 41 insertions(+) diff --git

Re: [PATCH] drm/amdgpu: correct GART location info

On 06/19/2018 03:04 PM, Christian König wrote: We need a commit message, something like "Avoid confusing the GART with the GTT domain.". Yeah, will add such kind of info. Am 19.06.2018 um 06:41 schrieb Junwei Zhang: Signed-off-by: Junwei Zhang ---

[PATCH 04/13] drm/amd/powerplay: revise default dpm tables setup

Initialize the soft/hard min/max level correctly and handle the dpm disabled situation. Change-Id: I9a1d303ee54ac4c9687f72c86097b008ae398c05 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 334 - 1 file changed, 132 insertions(+), 202

[PATCH 05/13] drm/amd/powerplay: retrieve all clock ranges on startup

So that we do not need to use PPSMC_MSG_GetMin/MaxDpmFreq to get the clock ranges on runtime. Since that causes some problems. Change-Id: Ia0d6390c976749538b35c8ffde5d1e661b4944c0 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 69 +-

[PATCH 06/13] drm/amd/powerplay: revise clock level setup

Make sure the clock level set only on dpm enabled. Also uvd/vce/soc clock also changed correspondingly. Change-Id: I1db2e2ac355fd5aea1c0a25c2b140d039a590089 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 318 ++--- 1 file changed, 211

[PATCH 10/13] drm/amd/powerplay: apply clocks adjust rules on power state change

The clocks hard/soft min/max clock levels will be adjusted correspondingly. Change-Id: I2c4b6cd6756d40a28933f0c26b9e1a3d5078bab8 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 162 + drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h | 2

[PATCH 09/13] drm/amd/powerplay: correct vega12 max num of dpm level

Use MAX_NUM_CLOCKS instead of VG12_PSUEDO* macros for the max number of dpm levels. Change-Id: Ida49f51777663a8d68d05ddcd41f4df0d8e61481 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 17 + 1 file changed, 9 insertions(+), 8 deletions(-) diff

[PATCH 01/13] drm/amd/powerplay: correct vega12 bootup values settings

The vbios firmware structure changed between v3_1 and v3_2. So, the code to setup bootup values needs different paths based on header version. Change-Id: I15140c4d80a91022f66a5052f4b9303fdab4ed9d Signed-off-by: Evan Quan Acked-by: Alex Deucher ---

[PATCH 02/13] drm/amd/powerplay: smc_dpm_info structure change

A new member Vr2_I2C_address is added. Change-Id: I9821365721c9d73e1d2df2f65dfa97f39f0425c6 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/include/atomfirmware.h | 5 - drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 2 ++

[PATCH 03/13] drm/amd/powerplay: drop the acg fix

This workaround is not needed any more. Change-Id: I81cb20ecd52d242af26ca32860baacdb5ec126c9 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c | 6 -- 1 file changed, 6 deletions(-) diff --git

[PATCH 07/13] drm/amd/powerplay: initialize uvd/vce powergate status

On UVD/VCE dpm disabled, the powergate status should be set as true. Change-Id: I569a5aa216b5e7d64a2b504f2ff98cc83ca802d5 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 17 + 1 file changed, 17 insertions(+) diff --git

Re: [PATCH] drm/amdgpu:All UVD instances share one idle_work handle

Am 18.06.2018 um 20:00 schrieb James Zhu: All UVD instanses have only one dpm control, so it is better to share one idle_work handle. Signed-off-by: James Zhu Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 14 +++---

[PATCH] drm/amdgpu: Use correct enum to set powergating state

Use enum amd_powergating_state instead of enum amd_clockgating_state. The underlying value stays the same, so there is no functional change in practise. This fixes a warning seen with clang: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1930:14: warning: implicit conversion from enumeration