To avoid the tlb flush not interrupted by world switch, use kiq and one
command to do tlb invalidate.
SWDEV-161497
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git
Cleanup coding style in sched_entity.c
Signed-off-by: Christian König
---
drivers/gpu/drm/scheduler/sched_entity.c | 167 ---
1 file changed, 110 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/scheduler/sched_entity.c
>-Original Message-
>From: Christian König
>Sent: Tuesday, August 14, 2018 3:54 PM
>To: Deng, Emily ; amd-gfx@lists.freedesktop.org
>Subject: Re: [PATCH] drm/amdgpu/sriov: For sriov runtime, use kiq to do
>invalidate tlb
>
>Am 14.08.2018 um 09:46 schrieb Emily Deng:
>> To avoid the tlb
Better match the naming of the other components.
Signed-off-by: Christian König
---
drivers/gpu/drm/scheduler/Makefile | 2 +-
drivers/gpu/drm/scheduler/{gpu_scheduler.c => sched_main.c} | 0
2 files changed, 1 insertion(+), 1 deletion(-)
rename
Return -ENOMEM when allocating the rq_list fails.
Signed-off-by: Christian König
---
drivers/gpu/drm/scheduler/gpu_scheduler.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/scheduler/gpu_scheduler.c
b/drivers/gpu/drm/scheduler/gpu_scheduler.c
index
On Tue, Aug 14, 2018 at 09:35:50AM +0200, Christian König wrote:
> Am 14.08.2018 um 09:24 schrieb Huang Rui:
> >On Tue, Aug 14, 2018 at 02:45:22PM +0800, Koenig, Christian wrote:
> >>Am 14.08.2018 um 05:05 schrieb Huang Rui:
> >>>On Tue, Aug 14, 2018 at 10:26:43AM +0800, Zhang, Jerry wrote:
>
Am 14.08.2018 um 05:05 schrieb Huang Rui:
On Tue, Aug 14, 2018 at 10:26:43AM +0800, Zhang, Jerry wrote:
On 08/13/2018 05:58 PM, Huang Rui wrote:
I continue to work for bulk moving that based on the proposal by Christian.
Background:
amdgpu driver will move all PD/PT and PerVM BOs into idle
Hi all,
Please ignore this patch, will send another patch.
Best wishes
Emily Deng
-Original Message-
From: amd-gfx On Behalf Of Emily Deng
Sent: Tuesday, August 14, 2018 2:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily
Subject: [PATCH] drm/amdgpu/sriov: For sriov runtime,
Am 14.08.2018 um 09:24 schrieb Huang Rui:
On Tue, Aug 14, 2018 at 02:45:22PM +0800, Koenig, Christian wrote:
Am 14.08.2018 um 05:05 schrieb Huang Rui:
On Tue, Aug 14, 2018 at 10:26:43AM +0800, Zhang, Jerry wrote:
On 08/13/2018 05:58 PM, Huang Rui wrote:
I continue to work for bulk moving
Am 14.08.2018 um 09:46 schrieb Emily Deng:
To avoid the tlb flush not interrupted by world switch, use kiq and one
command to do tlb invalidate.
Well NAK, this just duplicates the TLB handling and moves it outside of
the GMC code.
Instead just lower the timeout and suppress the warning when
This is complex enough on it's own. Move it into a separate C file.
Signed-off-by: Christian König
---
drivers/gpu/drm/scheduler/Makefile| 2 +-
drivers/gpu/drm/scheduler/gpu_scheduler.c | 441 +---
drivers/gpu/drm/scheduler/sched_entity.c | 459
On Tue, Aug 14, 2018 at 02:45:22PM +0800, Koenig, Christian wrote:
> Am 14.08.2018 um 05:05 schrieb Huang Rui:
> > On Tue, Aug 14, 2018 at 10:26:43AM +0800, Zhang, Jerry wrote:
> >> On 08/13/2018 05:58 PM, Huang Rui wrote:
> >>> I continue to work for bulk moving that based on the proposal by
>
That is fixed by "drm/scheduler: bind job earlier to scheduler".
Christian.
Am 13.08.2018 um 16:33 schrieb Andres Rodriguez:
Any updates on this issue?
Regards,
Andres
On 2018-08-08 03:10 AM, Christian König wrote:
Yeah that is a known issue, but this solution is not correct either.
See
Fix quite a number of bugs here. Unfortunately only compile tested.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 103 ++-
1 file changed, 46 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
To avoid the tlb flush not interrupted by world switch, use kiq and one
command to do tlb invalidate.
SWDEV-161497
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 50
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 2 ++
Am 14.08.2018 um 10:13 schrieb Deng, Emily:
-Original Message-
From: Christian König
Sent: Tuesday, August 14, 2018 3:54 PM
To: Deng, Emily ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu/sriov: For sriov runtime, use kiq to do
invalidate tlb
Am 14.08.2018 um 09:46
From: Evan Quan
1. The min/max level is determined by soft_min_level/soft_max_level.
2. Vega20 comes with pptable v3 which has no vdd related
table(vdd_dep_on_socclk, vdd_dep_on_mclk) support.
3. Vega20 does not support separate fan feature control(enable or
disable).
v2: squash in fixes:
- bug
From: Evan Quan
Support the power profile API.
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 193 -
1 file changed, 192 insertions(+), 1 deletion(-)
diff --git
From: Evan Quan
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
Revert this to add proper nbio 7.4 support.
This reverts commit f5b2e1fa321eff20a9418ebd497d8a466f024a85.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 18 +-
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 --
2 files changed, 1 insertion(+), 19
From: Evan Quan
v2: use thm 11.0.2 headers
Signed-off-by: Evan Quan
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_inc.h | 35
1 file changed, 35 insertions(+)
create mode 100644
From: Evan Quan
v2: squash in table size fixes
Signed-off-by: Evan Quan
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/powerplay/hwmgr/vega20_pptable.h | 140 +
1 file changed, 140 insertions(+)
create mode 100644
From: Evan Quan
v2: switch to SOC15 register access macros
reserve space for ActivityMonitor table
enable SMU fw loading
Drop dead code from bringup
Signed-off-by: Evan Quan
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/smumgr/Makefile
From: Evan Quan
Add struct atom_smc_dpm_info_v4_3
Signed-off-by: Evan Quan
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/include/atomfirmware.h | 86 ++
1 file changed, 86 insertions(+)
diff --git
From: Feifei Xu
Some register offset in nbio v7.4 are different with v7.0.
We need a seperate nbio_v7_4.c for vega20.
v2: fix doorbell range for sdma (Alex)
Signed-off-by: Feifei Xu
Reviewed-by: Hawking Zhang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
This patch set implements SMU and PSP support for vega20. Patches
1-4 are huge register headers updates so I didn't send them to the
list. The whole series can be viewed here:
https://cgit.freedesktop.org/~agd5f/linux/log/?h=vega20_psp_smu
Thanks,
Alex
Alex Deucher (2):
Revert "drm/amdgpu:
From: Evan Quan
Vega20 has a new activity monitor table that is stored in memory. Add
API to get and set the new table.
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c | 57 ++
From: Evan Quan
fix possible handshake hang and video playback crash
Corner cases:
- Handshake between SMU and DCE causes hangs when CRTC is not
enabled
- System crash occurs when starting 4K playback with Movies and TV
in an SLS configuration
Signed-off-by: Evan Quan
Reviewed-by:
From: Evan Quan
Add support for the new SMU firmware interface for clock adjustment.
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 169 +
1 file changed, 169 insertions(+)
diff
From: Evan Quan
Powerplay uses 10KHz units.
Signed-off-by: Evan Quan
Reviewed-by: Rex Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
From: Evan Quan
Signed-off-by: Evan Quan
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index
From: Evan Quan
UVD, VCE and SOC clocks need to be taken into consideration. Also, the
thresholds need be updated correspondingly when stable power state is selected.
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
From: Evan Quan
UVD, VCE and Socclk also need to be taken into consideration when
setting PPSMC_MSG_SetSoftMinByFreq and PPSMC_MSG_SetSoftMaxByFreq.
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 109
From: Evan Quan
This is essentially necessary when uvd/vce dpm is not enabled yet.
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 18 ++
1 file changed, 18 insertions(+)
diff --git
From: Evan Quan
v2: update to latest.
Signed-off-by: Evan Quan
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h | 127 +++
1 file changed, 127 insertions(+)
create mode 100644
Now that PSP and SMU support is in place.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index
From: Evan Quan
Run AFLL BTC after upload pptable and before enabling
all smu features.
Signed-off-by: Evan Quan
Reviewed-by: Rex Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 10 ++
1 file changed, 10 insertions(+)
diff --git
From: Evan Quan
The argument was set wrongly. Fast/slow switch was asked when there is
actually a slow/fast switch needed.
Signed-off-by: Evan Quan
Reviewed-by: Rex Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 2 +-
1 file changed, 1 insertion(+),
From: Evan Quan
Otherwise there may be potential SMU performance issues.
Signed-off-by: Evan Quan
Reviewed-by: Rex Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Evan Quan
SOC voltage is not able to switch and forced to low 0.8V when running HEVC.
Thus the test failed.
Signed-off-by: Evan Quan
Reviewed-by: Rex Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 9 +
From: Evan Quan
The latest SMU fw removes the limitation that required
UCLK >= DCEFCLK.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 3 ---
1 file changed, 3 deletions(-)
diff --git
From: Evan Quan
Set fclk ss as enabled on default.
Signed-off-by: Evan Quan
Reviewed-by: Rex Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Feifei Xu
Update the goldensettings for vega20.
Signed-off-by: Feifei Xu
Signed-off-by: Evan Quan
Reviewed-by: Hawking Zhang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Evan Quan
For vega20, there are two UVD rings which share one powerplay instance.
Under some case(two rings used parallel), the uvd dpm is disabled twice
which causes the SMC hang.
Signed-off-by: Evan Quan
Reviewed-by: Rex Zhu
Signed-off-by: Alex Deucher
---
From: Likun Gao
Modified the vega20 load type to psp now that psp
support is implemented.
v2: squash in fixes history (Alex)
Signed-off-by: Likun Gao
Reviewed-by: Feifei Xu
Reviewed-by: Hawking Zhang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
From: Feifei Xu
Add psp 11.0 code for vega20 and enable it. PSP is the
security processor for the GPU. It handles firmware
loading and GPU resets among other things.
v2: whitespace fix, enable support, adjust reg includes (Alex)
Signed-off-by: Feifei Xu
Reviewed-by: Alex Deucher
From: Evan Quan
The initialized overdrive settings are taken from vbios and SMU(
by PPSMC_MSG_TransferTableSmu2Dram).
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 293 +++--
From: Feifei Xu
Enlarge the PSP TMR SIZE to 4M for dual UVD fw front-door loading.
Signed-off-by: Feifei Xu
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 --
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
2 files changed, 5
From: Evan Quan
Updated vega20 SDMA0 and SDMA1 golden settings.
Signed-off-by: Evan Quan
Signed-off-by: Feifei Xu
Reviewed-by: Hawking Zhang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 68 --
1 file
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of likun Gao
Sent: Tuesday, August 14, 2018 7:10:10 AM
To: amd-gfx@lists.freedesktop.org
Cc: Gao, Likun
Subject: [PATCH libdrm] amdgpu: Disable deadlock test suite for RV/RV2/PCO
From: Likun Gao
disable
On Tue, Aug 14, 2018 at 5:58 AM Rex Zhu wrote:
>
> After set power ungate state, set clock ungate state
> before driver suspend or fini.
>
> Signed-off-by: Rex Zhu
Nice cleanup! Series is:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 56
>
Reviewed-by: Andrey Grodzovsky
Andrey
On 08/14/2018 04:23 AM, Huang Rui wrote:
On Tue, Aug 14, 2018 at 10:12:23AM +0200, Christian König wrote:
Return -ENOMEM when allocating the rq_list fails.
Signed-off-by: Christian König
Reviewed-by: Huang Rui
---
On Tue, Aug 14, 2018 at 3:11 PM James Zhu wrote:
>
> From: Feifei Xu
>
> With PSP firmware loading, TMR mc address is supposed to be used.
>
> Signed-off-by: James Zhu
Series is:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 13 +
> 1 file changed, 9
From: Feifei Xu
With PSP firmware loading, TMR mc address is supposed to be used.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
From: Evan Quan
Added psp fw loading support for vega20 2nd UVD instance.
Change-Id: Ib1eeeb1308641c0d64ca2f8f465f17c567434c68
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 1 +
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 3 ++-
With PSP firmware loading, TMR mc address is supposed to be used.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
[+Harish]
I think this looks good for the most part. See one comment inline below.
But bear with me while I'm trying to understand what was wrong with the
old code. Please correct me if I get this wrong or point out anything
I'm missing.
The reservation_object_list looks to be protected by a
On 2018-08-13 05:23 PM, Arnd Bergmann wrote:
> On Mon, Aug 13, 2018 at 4:49 PM Alex Deucher wrote:
>>
>> On Sun, Aug 12, 2018 at 3:55 AM Christian König
>> wrote:
>>> Adding Harry as well.
>>> Am 11.08.2018 um 17:54 schrieb Arnd Bergmann:
Fixes: bf2e2e2e0ea9 ("drm/amd/display: Limit
The if statement isn't indented and it makes static checkers complain.
Signed-off-by: Dan Carpenter
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 4ca41d6e3bcf..d82ba58c720f 100644
---
On Tue, Aug 14, 2018 at 10:12:24AM +0200, Christian König wrote:
> This is complex enough on it's own. Move it into a separate C file.
>
> Signed-off-by: Christian König
For series:
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/scheduler/Makefile| 2 +-
>
Am 14.08.2018 um 05:00 schrieb Junwei Zhang:
Fix potential memory leak when handle flink bo in bo import.
Free the flink bo after bo import and in error handling.
Signed-off-by: Junwei Zhang
Reviewed-by: Christian König for the series.
I assume you don't have commit rights to the upstream
>-Original Message-
>From: Christian König
>Sent: Tuesday, August 14, 2018 4:20 PM
>To: Deng, Emily ; Koenig, Christian
>; amd-gfx@lists.freedesktop.org
>Subject: Re: [PATCH] drm/amdgpu/sriov: For sriov runtime, use kiq to do
>invalidate tlb
>
>Am 14.08.2018 um 10:13 schrieb Deng, Emily:
From: Likun Gao
disable deadlock test suite for RV/RV2/PCO
Signed-off-by: Likun Gao
---
tests/amdgpu/deadlock_tests.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c
index 1eb5761..304482d 100644
---
On 08/14/2018 04:26 PM, Christian König wrote:
Am 14.08.2018 um 05:00 schrieb Junwei Zhang:
Fix potential memory leak when handle flink bo in bo import.
Free the flink bo after bo import and in error handling.
Signed-off-by: Junwei Zhang
Reviewed-by: Christian König for the series.
I
Am 14.08.2018 um 10:35 schrieb Deng, Emily:
-Original Message-
From: amd-gfx On Behalf Of
Christian König
Sent: Tuesday, August 14, 2018 4:32 PM
To: Deng, Emily ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu/sriov: For sriov runtime, use kiq to do
invalidate tlb
Am
>-Original Message-
>From: Koenig, Christian
>Sent: Tuesday, August 14, 2018 4:38 PM
>To: Deng, Emily ; amd-gfx@lists.freedesktop.org
>Subject: Re: [PATCH] drm/amdgpu/sriov: For sriov runtime, use kiq to do
>invalidate tlb
>
>Am 14.08.2018 um 10:35 schrieb Deng, Emily:
>>> -Original
Am 14.08.2018 um 11:15 schrieb Arnd Bergmann:
On Tue, Aug 14, 2018 at 10:54 AM Michel Dänzer wrote:
On 2018-08-13 05:23 PM, Arnd Bergmann wrote:
On Mon, Aug 13, 2018 at 4:49 PM Alex Deucher wrote:
On Sun, Aug 12, 2018 at 3:55 AM Christian König
wrote:
Adding Harry as well.
Am 11.08.2018
From: Michel Dänzer
Arithmetic using void* pointers isn't defined by the C standard, only as
a GCC extension. Avoids compiler warnings:
../../amdgpu/amdgpu_bo.c: In function ‘amdgpu_find_bo_by_cpu_mapping’:
../../amdgpu/amdgpu_bo.c:554:48: warning: pointer of type ‘void *’ used in
arithmetic
Am 14.08.2018 um 11:36 schrieb Rex Zhu:
Cancel the delay work to avoid the corner case that
ib test was not running when suspend
Signed-off-by: Rex Zhu
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Michel Dänzer
The compiler points out that an int doesn't work as intended if
dev->bo_handles.max_key > INT_MAX:
../../amdgpu/amdgpu_bo.c: In function ‘amdgpu_find_bo_by_cpu_mapping’:
../../amdgpu/amdgpu_bo.c:550:16: warning: comparison of integer expressions of
different signedness:
>-Original Message-
>From: amd-gfx On Behalf Of
>Christian König
>Sent: Tuesday, August 14, 2018 4:32 PM
>To: Deng, Emily ; amd-gfx@lists.freedesktop.org
>Subject: Re: [PATCH] drm/amdgpu/sriov: For sriov runtime, use kiq to do
>invalidate tlb
>
>Am 14.08.2018 um 10:26 schrieb Deng, Emily:
Cancel the delay work to avoid the corner case that
ib test was not running when suspend
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
there is no logical change in this patch.
1. change function names:
amdgpu_device_ip_late_set_pg/cg_state to
amdgpu_device_set_pg/cg_state.
2. add a function argument cg/pg_state, so
we can enable/disable cg/pg through those functions
Signed-off-by: Rex Zhu
---
Unify to set power ungate state before suspend/fini.
Remove the workaround code for gfx off feature in
amdgpu_device.c.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 11 +--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4
After set power ungate state, set clock ungate state
before driver suspend or fini.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 56 +++---
1 file changed, 5 insertions(+), 51 deletions(-)
diff --git
To avoid the tlb flush not interrupted by world switch, use kiq and one
command to do tlb invalidate.
v2:
Add firmware version checking.
SWDEV-161497
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 63
On Tue, Aug 14, 2018 at 10:12:23AM +0200, Christian König wrote:
> Return -ENOMEM when allocating the rq_list fails.
>
> Signed-off-by: Christian König
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/scheduler/gpu_scheduler.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git
Am 14.08.2018 um 10:26 schrieb Deng, Emily:
-Original Message-
From: Christian König
Sent: Tuesday, August 14, 2018 4:20 PM
To: Deng, Emily ; Koenig, Christian
; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu/sriov: For sriov runtime, use kiq to do
invalidate tlb
Am
From: David Francis
[Why]
I2C code did not match dc resource model and was generally
unpleasant
[How]
Move code into new svelte dce_i2c files, replacing various i2c
objects with two structs: dce_i2c_sw and dce_i2c_hw. Fully split
sw and hw code paths. Remove all redundant declarations. Use
From: Samson Tam
[Why]
Implement full mode enumeration using emulated sink and nothing
connected on link
[How]
Do not retrain link settings if lane count and link rate are both
unknown. Causes driver to be stuck reading VBIOS register after
removing emulated connection.
Change-Id:
From: Anthony Koo
[Why]
During S4/S3 stress test it is possible to resume from S4 without
calling mode set on eDP, meaning high level optimization flag is not
reset. If this is followed by an S3 resume call, driver will see
optimization flag is set and consume it and think backend is powered
on
From: Dmytro Laktyushkin
dp_ss_control = 0 means ss is off, we had a typo where
we would double not dp_ss_control while setting dp_ss_off
flag
Change-Id: Ied5cd2132bdc269b9692ecb643798057524d380c
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Bhawanpreet Lakha
---
Summary of Changes:
* i2c refactor
* Implement EDID emulation
Anthony Koo (1):
drm/amd/display: move edp fast boot optimization flag to stream
David Francis (2):
drm/amd/display: Create new i2c resource
drm/amd/display: Combine dce80 and dce100 i2c hw functions
Dmytro Laktyushkin (3):
From: SivapiriyanKumarasamy
Add csc_transform struct to dc_stream_update, and program if set when
updating streams
Change-Id: Ib98486736002327a67f60fa2e24879e3b8e765fd
Signed-off-by: SivapiriyanKumarasamy
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
---
From: David Francis
[Why]
There are two versions of the hw function pointers: one for dce80
and one for all other versions. These paired functions are
nearly identical. dce80 and dce100 should not require
different i2c access functions.
[How]
Combine each pair of functions into a single
From: Nikola Cornij
Define register for dcn10 for future changes
Change-Id: Ia2d33f451c6464cd26345d1e56c5676bbc7cac1e
Signed-off-by: Nikola Cornij
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h | 2 ++
1 file changed, 2
From: Jun Lei
[why]
Existing DTN infrastructure in driver is hacky. It uses implicit log
names, and also incorrect escape ID.
[how]
- Implement using generic DTN escape ID.
- Move file logging functionality from driver to to script; driver now outputs
to string/buffer
- Move HWSS debug
From: Dmytro Laktyushkin
dp_ss_off flag doesn't need to be set, so we create a link_init
function if it is needed by an asic
Change-Id: Ieb58532895bd01f1317ca13913211e63007ae9d8
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Bhawanpreet Lakha
---
On 08/14/2018 05:58 PM, Michel Dänzer wrote:
From: Michel Dänzer
Arithmetic using void* pointers isn't defined by the C standard, only as
a GCC extension. Avoids compiler warnings:
../../amdgpu/amdgpu_bo.c: In function ‘amdgpu_find_bo_by_cpu_mapping’:
../../amdgpu/amdgpu_bo.c:554:48: warning:
Thanks for your review, will send a patch to review again as your suggestion. I
think it will be better to use the amdgpu_sriov_vf(adev).
As need to let somebody to test all your bare metal test cases, such as vega10,
and other asics, as I don't have those environments, and only could test
On 08/14/2018 05:58 PM, Michel Dänzer wrote:
From: Michel Dänzer
The compiler points out that an int doesn't work as intended if
dev->bo_handles.max_key > INT_MAX:
../../amdgpu/amdgpu_bo.c: In function ‘amdgpu_find_bo_by_cpu_mapping’:
../../amdgpu/amdgpu_bo.c:550:16: warning: comparison of
On Tue, Aug 14, 2018 at 02:53:51PM -0400, James Zhu wrote:
> With PSP firmware loading, TMR mc address is supposed to be used.
> Signed-off-by: James Zhu
Series are
Acked-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 13 +
> 1 file changed, 9 insertions(+), 4
The status field must be 0 after FW is loaded.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 9f1a5bd..44bcd03 100644
---
Am 14.08.2018 um 12:56 schrieb Emily Deng:
To avoid the tlb flush not interrupted by world switch, use kiq and one
command to do tlb invalidate.
v2:
Add firmware version checking.
SWDEV-161497
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 63
Hi folks,
I was trying to play around with NGG on Vega using the open source AMDVLK stack.
After fetching all the code, I disabled an override in PAL, under
gfx9SettingsLoader.cpp
that disables the NGG setting. I've put a new option in my
amdPalSettings.cfg: `NggMode,7` and that was enough to
On Tue, Aug 14, 2018 at 10:54 AM Michel Dänzer wrote:
>
> On 2018-08-13 05:23 PM, Arnd Bergmann wrote:
> > On Mon, Aug 13, 2018 at 4:49 PM Alex Deucher wrote:
> >>
> >> On Sun, Aug 12, 2018 at 3:55 AM Christian König
> >> wrote:
> >>> Adding Harry as well.
> >>> Am 11.08.2018 um 17:54 schrieb
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